1 //===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits a target specifier matcher for converting parsed
11 // assembly operands in the MCInst structures. It also emits a matcher for
12 // custom operand parsing.
14 // Converting assembly operands into MCInst structures
15 // ---------------------------------------------------
17 // The input to the target specific matcher is a list of literal tokens and
18 // operands. The target specific parser should generally eliminate any syntax
19 // which is not relevant for matching; for example, comma tokens should have
20 // already been consumed and eliminated by the parser. Most instructions will
21 // end up with a single literal token (the instruction name) and some number of
24 // Some example inputs, for X86:
25 // 'addl' (immediate ...) (register ...)
26 // 'add' (immediate ...) (memory ...)
29 // The assembly matcher is responsible for converting this input into a precise
30 // machine instruction (i.e., an instruction with a well defined encoding). This
31 // mapping has several properties which complicate matching:
33 // - It may be ambiguous; many architectures can legally encode particular
34 // variants of an instruction in different ways (for example, using a smaller
35 // encoding for small immediates). Such ambiguities should never be
36 // arbitrarily resolved by the assembler, the assembler is always responsible
37 // for choosing the "best" available instruction.
39 // - It may depend on the subtarget or the assembler context. Instructions
40 // which are invalid for the current mode, but otherwise unambiguous (e.g.,
41 // an SSE instruction in a file being assembled for i486) should be accepted
42 // and rejected by the assembler front end. However, if the proper encoding
43 // for an instruction is dependent on the assembler context then the matcher
44 // is responsible for selecting the correct machine instruction for the
47 // The core matching algorithm attempts to exploit the regularity in most
48 // instruction sets to quickly determine the set of possibly matching
49 // instructions, and the simplify the generated code. Additionally, this helps
50 // to ensure that the ambiguities are intentionally resolved by the user.
52 // The matching is divided into two distinct phases:
54 // 1. Classification: Each operand is mapped to the unique set which (a)
55 // contains it, and (b) is the largest such subset for which a single
56 // instruction could match all members.
58 // For register classes, we can generate these subgroups automatically. For
59 // arbitrary operands, we expect the user to define the classes and their
60 // relations to one another (for example, 8-bit signed immediates as a
61 // subset of 32-bit immediates).
63 // By partitioning the operands in this way, we guarantee that for any
64 // tuple of classes, any single instruction must match either all or none
65 // of the sets of operands which could classify to that tuple.
67 // In addition, the subset relation amongst classes induces a partial order
68 // on such tuples, which we use to resolve ambiguities.
70 // 2. The input can now be treated as a tuple of classes (static tokens are
71 // simple singleton sets). Each such tuple should generally map to a single
72 // instruction (we currently ignore cases where this isn't true, whee!!!),
73 // which we can emit a simple matcher for.
75 // Custom Operand Parsing
76 // ----------------------
78 // Some targets need a custom way to parse operands, some specific instructions
79 // can contain arguments that can represent processor flags and other kinds of
80 // identifiers that need to be mapped to specific values in the final encoded
81 // instructions. The target specific custom operand parsing works in the
84 // 1. A operand match table is built, each entry contains a mnemonic, an
85 // operand class, a mask for all operand positions for that same
86 // class/mnemonic and target features to be checked while trying to match.
88 // 2. The operand matcher will try every possible entry with the same
89 // mnemonic and will check if the target feature for this mnemonic also
90 // matches. After that, if the operand to be matched has its index
91 // present in the mask, a successful match occurs. Otherwise, fallback
92 // to the regular operand parsing.
94 // 3. For a match success, each operand class that has a 'ParserMethod'
95 // becomes part of a switch from where the custom method is called.
97 //===----------------------------------------------------------------------===//
99 #include "CodeGenTarget.h"
100 #include "llvm/ADT/PointerUnion.h"
101 #include "llvm/ADT/STLExtras.h"
102 #include "llvm/ADT/SmallPtrSet.h"
103 #include "llvm/ADT/SmallVector.h"
104 #include "llvm/ADT/StringExtras.h"
105 #include "llvm/Support/CommandLine.h"
106 #include "llvm/Support/Debug.h"
107 #include "llvm/Support/ErrorHandling.h"
108 #include "llvm/TableGen/Error.h"
109 #include "llvm/TableGen/Record.h"
110 #include "llvm/TableGen/StringMatcher.h"
111 #include "llvm/TableGen/StringToOffsetTable.h"
112 #include "llvm/TableGen/TableGenBackend.h"
118 #include <forward_list>
119 using namespace llvm;
121 #define DEBUG_TYPE "asm-matcher-emitter"
123 static cl::opt<std::string>
124 MatchPrefix("match-prefix", cl::init(""),
125 cl::desc("Only match instructions with the given prefix"));
128 class AsmMatcherInfo;
129 struct SubtargetFeatureInfo;
131 // Register sets are used as keys in some second-order sets TableGen creates
132 // when generating its data structures. This means that the order of two
133 // RegisterSets can be seen in the outputted AsmMatcher tables occasionally, and
134 // can even affect compiler output (at least seen in diagnostics produced when
135 // all matches fail). So we use a type that sorts them consistently.
136 typedef std::set<Record*, LessRecordByID> RegisterSet;
138 class AsmMatcherEmitter {
139 RecordKeeper &Records;
141 AsmMatcherEmitter(RecordKeeper &R) : Records(R) {}
143 void run(raw_ostream &o);
146 /// ClassInfo - Helper class for storing the information about a particular
147 /// class of operands which can be matched.
150 /// Invalid kind, for use as a sentinel value.
153 /// The class for a particular token.
156 /// The (first) register class, subsequent register classes are
157 /// RegisterClass0+1, and so on.
160 /// The (first) user defined class, subsequent user defined classes are
161 /// UserClass0+1, and so on.
165 /// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
166 /// N) for the Nth user defined class.
169 /// SuperClasses - The super classes of this class. Note that for simplicities
170 /// sake user operands only record their immediate super class, while register
171 /// operands include all superclasses.
172 std::vector<ClassInfo*> SuperClasses;
174 /// Name - The full class name, suitable for use in an enum.
177 /// ClassName - The unadorned generic name for this class (e.g., Token).
178 std::string ClassName;
180 /// ValueName - The name of the value this class represents; for a token this
181 /// is the literal token string, for an operand it is the TableGen class (or
182 /// empty if this is a derived class).
183 std::string ValueName;
185 /// PredicateMethod - The name of the operand method to test whether the
186 /// operand matches this class; this is not valid for Token or register kinds.
187 std::string PredicateMethod;
189 /// RenderMethod - The name of the operand method to add this operand to an
190 /// MCInst; this is not valid for Token or register kinds.
191 std::string RenderMethod;
193 /// ParserMethod - The name of the operand method to do a target specific
194 /// parsing on the operand.
195 std::string ParserMethod;
197 /// For register classes: the records for all the registers in this class.
198 RegisterSet Registers;
200 /// For custom match classes: the diagnostic kind for when the predicate fails.
201 std::string DiagnosticType;
203 /// isRegisterClass() - Check if this is a register class.
204 bool isRegisterClass() const {
205 return Kind >= RegisterClass0 && Kind < UserClass0;
208 /// isUserClass() - Check if this is a user defined class.
209 bool isUserClass() const {
210 return Kind >= UserClass0;
213 /// isRelatedTo - Check whether this class is "related" to \p RHS. Classes
214 /// are related if they are in the same class hierarchy.
215 bool isRelatedTo(const ClassInfo &RHS) const {
216 // Tokens are only related to tokens.
217 if (Kind == Token || RHS.Kind == Token)
218 return Kind == Token && RHS.Kind == Token;
220 // Registers classes are only related to registers classes, and only if
221 // their intersection is non-empty.
222 if (isRegisterClass() || RHS.isRegisterClass()) {
223 if (!isRegisterClass() || !RHS.isRegisterClass())
227 std::insert_iterator<RegisterSet> II(Tmp, Tmp.begin());
228 std::set_intersection(Registers.begin(), Registers.end(),
229 RHS.Registers.begin(), RHS.Registers.end(),
230 II, LessRecordByID());
235 // Otherwise we have two users operands; they are related if they are in the
236 // same class hierarchy.
238 // FIXME: This is an oversimplification, they should only be related if they
239 // intersect, however we don't have that information.
240 assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");
241 const ClassInfo *Root = this;
242 while (!Root->SuperClasses.empty())
243 Root = Root->SuperClasses.front();
245 const ClassInfo *RHSRoot = &RHS;
246 while (!RHSRoot->SuperClasses.empty())
247 RHSRoot = RHSRoot->SuperClasses.front();
249 return Root == RHSRoot;
252 /// isSubsetOf - Test whether this class is a subset of \p RHS.
253 bool isSubsetOf(const ClassInfo &RHS) const {
254 // This is a subset of RHS if it is the same class...
258 // ... or if any of its super classes are a subset of RHS.
259 for (const ClassInfo *CI : SuperClasses)
260 if (CI->isSubsetOf(RHS))
266 /// operator< - Compare two classes.
267 // FIXME: This ordering seems to be broken. For example:
268 // u64 < i64, i64 < s8, s8 < u64, forming a cycle
269 // u64 is a subset of i64
270 // i64 and s8 are not subsets of each other, so are ordered by name
271 // s8 and u64 are not subsets of each other, so are ordered by name
272 bool operator<(const ClassInfo &RHS) const {
276 // Unrelated classes can be ordered by kind.
277 if (!isRelatedTo(RHS))
278 return Kind < RHS.Kind;
282 llvm_unreachable("Invalid kind!");
285 // This class precedes the RHS if it is a proper subset of the RHS.
288 if (RHS.isSubsetOf(*this))
291 // Otherwise, order by name to ensure we have a total ordering.
292 return ValueName < RHS.ValueName;
297 class AsmVariantInfo {
299 std::string RegisterPrefix;
300 std::string TokenizingCharacters;
301 std::string SeparatorCharacters;
302 std::string BreakCharacters;
306 /// MatchableInfo - Helper class for storing the necessary information for an
307 /// instruction or alias which is capable of being matched.
308 struct MatchableInfo {
310 /// Token - This is the token that the operand came from.
313 /// The unique class instance this operand should match.
316 /// The operand name this is, if anything.
319 /// The suboperand index within SrcOpName, or -1 for the entire operand.
322 /// Whether the token is "isolated", i.e., it is preceded and followed
324 bool IsIsolatedToken;
326 /// Register record if this token is singleton register.
327 Record *SingletonReg;
329 explicit AsmOperand(bool IsIsolatedToken, StringRef T)
330 : Token(T), Class(nullptr), SubOpIdx(-1),
331 IsIsolatedToken(IsIsolatedToken), SingletonReg(nullptr) {}
334 /// ResOperand - This represents a single operand in the result instruction
335 /// generated by the match. In cases (like addressing modes) where a single
336 /// assembler operand expands to multiple MCOperands, this represents the
337 /// single assembler operand, not the MCOperand.
340 /// RenderAsmOperand - This represents an operand result that is
341 /// generated by calling the render method on the assembly operand. The
342 /// corresponding AsmOperand is specified by AsmOperandNum.
345 /// TiedOperand - This represents a result operand that is a duplicate of
346 /// a previous result operand.
349 /// ImmOperand - This represents an immediate value that is dumped into
353 /// RegOperand - This represents a fixed register that is dumped in.
358 /// This is the operand # in the AsmOperands list that this should be
360 unsigned AsmOperandNum;
362 /// TiedOperandNum - This is the (earlier) result operand that should be
364 unsigned TiedOperandNum;
366 /// ImmVal - This is the immediate value added to the instruction.
369 /// Register - This is the register record.
373 /// MINumOperands - The number of MCInst operands populated by this
375 unsigned MINumOperands;
377 static ResOperand getRenderedOp(unsigned AsmOpNum, unsigned NumOperands) {
379 X.Kind = RenderAsmOperand;
380 X.AsmOperandNum = AsmOpNum;
381 X.MINumOperands = NumOperands;
385 static ResOperand getTiedOp(unsigned TiedOperandNum) {
387 X.Kind = TiedOperand;
388 X.TiedOperandNum = TiedOperandNum;
393 static ResOperand getImmOp(int64_t Val) {
401 static ResOperand getRegOp(Record *Reg) {
410 /// AsmVariantID - Target's assembly syntax variant no.
413 /// AsmString - The assembly string for this instruction (with variants
414 /// removed), e.g. "movsx $src, $dst".
415 std::string AsmString;
417 /// TheDef - This is the definition of the instruction or InstAlias that this
418 /// matchable came from.
419 Record *const TheDef;
421 /// DefRec - This is the definition that it came from.
422 PointerUnion<const CodeGenInstruction*, const CodeGenInstAlias*> DefRec;
424 const CodeGenInstruction *getResultInst() const {
425 if (DefRec.is<const CodeGenInstruction*>())
426 return DefRec.get<const CodeGenInstruction*>();
427 return DefRec.get<const CodeGenInstAlias*>()->ResultInst;
430 /// ResOperands - This is the operand list that should be built for the result
432 SmallVector<ResOperand, 8> ResOperands;
434 /// Mnemonic - This is the first token of the matched instruction, its
438 /// AsmOperands - The textual operands that this instruction matches,
439 /// annotated with a class and where in the OperandList they were defined.
440 /// This directly corresponds to the tokenized AsmString after the mnemonic is
442 SmallVector<AsmOperand, 8> AsmOperands;
444 /// Predicates - The required subtarget features to match this instruction.
445 SmallVector<const SubtargetFeatureInfo *, 4> RequiredFeatures;
447 /// ConversionFnKind - The enum value which is passed to the generated
448 /// convertToMCInst to convert parsed operands into an MCInst for this
450 std::string ConversionFnKind;
452 /// If this instruction is deprecated in some form.
455 /// If this is an alias, this is use to determine whether or not to using
456 /// the conversion function defined by the instruction's AsmMatchConverter
457 /// or to use the function generated by the alias.
458 bool UseInstAsmMatchConverter;
460 MatchableInfo(const CodeGenInstruction &CGI)
461 : AsmVariantID(0), AsmString(CGI.AsmString), TheDef(CGI.TheDef), DefRec(&CGI),
462 UseInstAsmMatchConverter(true) {
465 MatchableInfo(std::unique_ptr<const CodeGenInstAlias> Alias)
466 : AsmVariantID(0), AsmString(Alias->AsmString), TheDef(Alias->TheDef),
467 DefRec(Alias.release()),
468 UseInstAsmMatchConverter(
469 TheDef->getValueAsBit("UseInstAsmMatchConverter")) {
472 // Could remove this and the dtor if PointerUnion supported unique_ptr
473 // elements with a dynamic failure/assertion (like the one below) in the case
474 // where it was copied while being in an owning state.
475 MatchableInfo(const MatchableInfo &RHS)
476 : AsmVariantID(RHS.AsmVariantID), AsmString(RHS.AsmString),
477 TheDef(RHS.TheDef), DefRec(RHS.DefRec), ResOperands(RHS.ResOperands),
478 Mnemonic(RHS.Mnemonic), AsmOperands(RHS.AsmOperands),
479 RequiredFeatures(RHS.RequiredFeatures),
480 ConversionFnKind(RHS.ConversionFnKind),
481 HasDeprecation(RHS.HasDeprecation),
482 UseInstAsmMatchConverter(RHS.UseInstAsmMatchConverter) {
483 assert(!DefRec.is<const CodeGenInstAlias *>());
487 delete DefRec.dyn_cast<const CodeGenInstAlias*>();
490 // Two-operand aliases clone from the main matchable, but mark the second
491 // operand as a tied operand of the first for purposes of the assembler.
492 void formTwoOperandAlias(StringRef Constraint);
494 void initialize(const AsmMatcherInfo &Info,
495 SmallPtrSetImpl<Record*> &SingletonRegisters,
496 AsmVariantInfo const &Variant,
497 bool HasMnemonicFirst);
499 /// validate - Return true if this matchable is a valid thing to match against
500 /// and perform a bunch of validity checking.
501 bool validate(StringRef CommentDelimiter, bool Hack) const;
503 /// findAsmOperand - Find the AsmOperand with the specified name and
504 /// suboperand index.
505 int findAsmOperand(StringRef N, int SubOpIdx) const {
506 auto I = std::find_if(AsmOperands.begin(), AsmOperands.end(),
507 [&](const AsmOperand &Op) {
508 return Op.SrcOpName == N && Op.SubOpIdx == SubOpIdx;
510 return (I != AsmOperands.end()) ? I - AsmOperands.begin() : -1;
513 /// findAsmOperandNamed - Find the first AsmOperand with the specified name.
514 /// This does not check the suboperand index.
515 int findAsmOperandNamed(StringRef N) const {
516 auto I = std::find_if(AsmOperands.begin(), AsmOperands.end(),
517 [&](const AsmOperand &Op) {
518 return Op.SrcOpName == N;
520 return (I != AsmOperands.end()) ? I - AsmOperands.begin() : -1;
523 void buildInstructionResultOperands();
524 void buildAliasResultOperands();
526 /// operator< - Compare two matchables.
527 bool operator<(const MatchableInfo &RHS) const {
528 // The primary comparator is the instruction mnemonic.
529 if (Mnemonic != RHS.Mnemonic)
530 return Mnemonic < RHS.Mnemonic;
532 if (AsmOperands.size() != RHS.AsmOperands.size())
533 return AsmOperands.size() < RHS.AsmOperands.size();
535 // Compare lexicographically by operand. The matcher validates that other
536 // orderings wouldn't be ambiguous using \see couldMatchAmbiguouslyWith().
537 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
538 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
540 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
544 // Give matches that require more features higher precedence. This is useful
545 // because we cannot define AssemblerPredicates with the negation of
546 // processor features. For example, ARM v6 "nop" may be either a HINT or
547 // MOV. With v6, we want to match HINT. The assembler has no way to
548 // predicate MOV under "NoV6", but HINT will always match first because it
549 // requires V6 while MOV does not.
550 if (RequiredFeatures.size() != RHS.RequiredFeatures.size())
551 return RequiredFeatures.size() > RHS.RequiredFeatures.size();
556 /// couldMatchAmbiguouslyWith - Check whether this matchable could
557 /// ambiguously match the same set of operands as \p RHS (without being a
558 /// strictly superior match).
559 bool couldMatchAmbiguouslyWith(const MatchableInfo &RHS) const {
560 // The primary comparator is the instruction mnemonic.
561 if (Mnemonic != RHS.Mnemonic)
564 // The number of operands is unambiguous.
565 if (AsmOperands.size() != RHS.AsmOperands.size())
568 // Otherwise, make sure the ordering of the two instructions is unambiguous
569 // by checking that either (a) a token or operand kind discriminates them,
570 // or (b) the ordering among equivalent kinds is consistent.
572 // Tokens and operand kinds are unambiguous (assuming a correct target
574 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
575 if (AsmOperands[i].Class->Kind != RHS.AsmOperands[i].Class->Kind ||
576 AsmOperands[i].Class->Kind == ClassInfo::Token)
577 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class ||
578 *RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
581 // Otherwise, this operand could commute if all operands are equivalent, or
582 // there is a pair of operands that compare less than and a pair that
583 // compare greater than.
584 bool HasLT = false, HasGT = false;
585 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
586 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
588 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
592 return HasLT == HasGT;
598 void tokenizeAsmString(AsmMatcherInfo const &Info,
599 AsmVariantInfo const &Variant);
600 void addAsmOperand(StringRef Token, bool IsIsolatedToken = false);
603 /// SubtargetFeatureInfo - Helper class for storing information on a subtarget
604 /// feature which participates in instruction matching.
605 struct SubtargetFeatureInfo {
606 /// \brief The predicate record for this feature.
609 /// \brief An unique index assigned to represent this feature.
612 SubtargetFeatureInfo(Record *D, uint64_t Idx) : TheDef(D), Index(Idx) {}
614 /// \brief The name of the enumerated constant identifying this feature.
615 std::string getEnumName() const {
616 return "Feature_" + TheDef->getName();
620 errs() << getEnumName() << " " << Index << "\n";
625 struct OperandMatchEntry {
626 unsigned OperandMask;
627 const MatchableInfo* MI;
630 static OperandMatchEntry create(const MatchableInfo *mi, ClassInfo *ci,
633 X.OperandMask = opMask;
641 class AsmMatcherInfo {
644 RecordKeeper &Records;
646 /// The tablegen AsmParser record.
649 /// Target - The target information.
650 CodeGenTarget &Target;
652 /// The classes which are needed for matching.
653 std::forward_list<ClassInfo> Classes;
655 /// The information on the matchables to match.
656 std::vector<std::unique_ptr<MatchableInfo>> Matchables;
658 /// Info for custom matching operands by user defined methods.
659 std::vector<OperandMatchEntry> OperandMatchInfo;
661 /// Map of Register records to their class information.
662 typedef std::map<Record*, ClassInfo*, LessRecordByID> RegisterClassesTy;
663 RegisterClassesTy RegisterClasses;
665 /// Map of Predicate records to their subtarget information.
666 std::map<Record *, SubtargetFeatureInfo, LessRecordByID> SubtargetFeatures;
668 /// Map of AsmOperandClass records to their class information.
669 std::map<Record*, ClassInfo*> AsmOperandClasses;
672 /// Map of token to class information which has already been constructed.
673 std::map<std::string, ClassInfo*> TokenClasses;
675 /// Map of RegisterClass records to their class information.
676 std::map<Record*, ClassInfo*> RegisterClassClasses;
679 /// getTokenClass - Lookup or create the class for the given token.
680 ClassInfo *getTokenClass(StringRef Token);
682 /// getOperandClass - Lookup or create the class for the given operand.
683 ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI,
685 ClassInfo *getOperandClass(Record *Rec, int SubOpIdx);
687 /// buildRegisterClasses - Build the ClassInfo* instances for register
689 void buildRegisterClasses(SmallPtrSetImpl<Record*> &SingletonRegisters);
691 /// buildOperandClasses - Build the ClassInfo* instances for user defined
693 void buildOperandClasses();
695 void buildInstructionOperandReference(MatchableInfo *II, StringRef OpName,
697 void buildAliasOperandReference(MatchableInfo *II, StringRef OpName,
698 MatchableInfo::AsmOperand &Op);
701 AsmMatcherInfo(Record *AsmParser,
702 CodeGenTarget &Target,
703 RecordKeeper &Records);
705 /// buildInfo - Construct the various tables used during matching.
708 /// buildOperandMatchInfo - Build the necessary information to handle user
709 /// defined operand parsing methods.
710 void buildOperandMatchInfo();
712 /// getSubtargetFeature - Lookup or create the subtarget feature info for the
714 const SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const {
715 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
716 const auto &I = SubtargetFeatures.find(Def);
717 return I == SubtargetFeatures.end() ? nullptr : &I->second;
720 RecordKeeper &getRecords() const {
725 } // End anonymous namespace
727 void MatchableInfo::dump() const {
728 errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n";
730 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
731 const AsmOperand &Op = AsmOperands[i];
732 errs() << " op[" << i << "] = " << Op.Class->ClassName << " - ";
733 errs() << '\"' << Op.Token << "\"\n";
737 static std::pair<StringRef, StringRef>
738 parseTwoOperandConstraint(StringRef S, ArrayRef<SMLoc> Loc) {
739 // Split via the '='.
740 std::pair<StringRef, StringRef> Ops = S.split('=');
741 if (Ops.second == "")
742 PrintFatalError(Loc, "missing '=' in two-operand alias constraint");
743 // Trim whitespace and the leading '$' on the operand names.
744 size_t start = Ops.first.find_first_of('$');
745 if (start == std::string::npos)
746 PrintFatalError(Loc, "expected '$' prefix on asm operand name");
747 Ops.first = Ops.first.slice(start + 1, std::string::npos);
748 size_t end = Ops.first.find_last_of(" \t");
749 Ops.first = Ops.first.slice(0, end);
750 // Now the second operand.
751 start = Ops.second.find_first_of('$');
752 if (start == std::string::npos)
753 PrintFatalError(Loc, "expected '$' prefix on asm operand name");
754 Ops.second = Ops.second.slice(start + 1, std::string::npos);
755 end = Ops.second.find_last_of(" \t");
756 Ops.first = Ops.first.slice(0, end);
760 void MatchableInfo::formTwoOperandAlias(StringRef Constraint) {
761 // Figure out which operands are aliased and mark them as tied.
762 std::pair<StringRef, StringRef> Ops =
763 parseTwoOperandConstraint(Constraint, TheDef->getLoc());
765 // Find the AsmOperands that refer to the operands we're aliasing.
766 int SrcAsmOperand = findAsmOperandNamed(Ops.first);
767 int DstAsmOperand = findAsmOperandNamed(Ops.second);
768 if (SrcAsmOperand == -1)
769 PrintFatalError(TheDef->getLoc(),
770 "unknown source two-operand alias operand '" + Ops.first +
772 if (DstAsmOperand == -1)
773 PrintFatalError(TheDef->getLoc(),
774 "unknown destination two-operand alias operand '" +
777 // Find the ResOperand that refers to the operand we're aliasing away
778 // and update it to refer to the combined operand instead.
779 for (ResOperand &Op : ResOperands) {
780 if (Op.Kind == ResOperand::RenderAsmOperand &&
781 Op.AsmOperandNum == (unsigned)SrcAsmOperand) {
782 Op.AsmOperandNum = DstAsmOperand;
786 // Remove the AsmOperand for the alias operand.
787 AsmOperands.erase(AsmOperands.begin() + SrcAsmOperand);
788 // Adjust the ResOperand references to any AsmOperands that followed
789 // the one we just deleted.
790 for (ResOperand &Op : ResOperands) {
793 // Nothing to do for operands that don't reference AsmOperands.
795 case ResOperand::RenderAsmOperand:
796 if (Op.AsmOperandNum > (unsigned)SrcAsmOperand)
799 case ResOperand::TiedOperand:
800 if (Op.TiedOperandNum > (unsigned)SrcAsmOperand)
807 /// extractSingletonRegisterForAsmOperand - Extract singleton register,
808 /// if present, from specified token.
810 extractSingletonRegisterForAsmOperand(MatchableInfo::AsmOperand &Op,
811 const AsmMatcherInfo &Info,
812 StringRef RegisterPrefix) {
813 StringRef Tok = Op.Token;
815 // If this token is not an isolated token, i.e., it isn't separated from
816 // other tokens (e.g. with whitespace), don't interpret it as a register name.
817 if (!Op.IsIsolatedToken)
820 if (RegisterPrefix.empty()) {
821 std::string LoweredTok = Tok.lower();
822 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(LoweredTok))
823 Op.SingletonReg = Reg->TheDef;
827 if (!Tok.startswith(RegisterPrefix))
830 StringRef RegName = Tok.substr(RegisterPrefix.size());
831 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName))
832 Op.SingletonReg = Reg->TheDef;
834 // If there is no register prefix (i.e. "%" in "%eax"), then this may
835 // be some random non-register token, just ignore it.
839 void MatchableInfo::initialize(const AsmMatcherInfo &Info,
840 SmallPtrSetImpl<Record*> &SingletonRegisters,
841 AsmVariantInfo const &Variant,
842 bool HasMnemonicFirst) {
843 AsmVariantID = Variant.AsmVariantNo;
845 CodeGenInstruction::FlattenAsmStringVariants(AsmString,
846 Variant.AsmVariantNo);
848 tokenizeAsmString(Info, Variant);
850 // The first token of the instruction is the mnemonic, which must be a
851 // simple string, not a $foo variable or a singleton register.
852 if (AsmOperands.empty())
853 PrintFatalError(TheDef->getLoc(),
854 "Instruction '" + TheDef->getName() + "' has no tokens");
856 assert(!AsmOperands[0].Token.empty());
857 if (HasMnemonicFirst) {
858 Mnemonic = AsmOperands[0].Token;
859 if (Mnemonic[0] == '$')
860 PrintFatalError(TheDef->getLoc(),
861 "Invalid instruction mnemonic '" + Mnemonic + "'!");
863 // Remove the first operand, it is tracked in the mnemonic field.
864 AsmOperands.erase(AsmOperands.begin());
865 } else if (AsmOperands[0].Token[0] != '$')
866 Mnemonic = AsmOperands[0].Token;
868 // Compute the require features.
869 for (Record *Predicate : TheDef->getValueAsListOfDefs("Predicates"))
870 if (const SubtargetFeatureInfo *Feature =
871 Info.getSubtargetFeature(Predicate))
872 RequiredFeatures.push_back(Feature);
874 // Collect singleton registers, if used.
875 for (MatchableInfo::AsmOperand &Op : AsmOperands) {
876 extractSingletonRegisterForAsmOperand(Op, Info, Variant.RegisterPrefix);
877 if (Record *Reg = Op.SingletonReg)
878 SingletonRegisters.insert(Reg);
881 const RecordVal *DepMask = TheDef->getValue("DeprecatedFeatureMask");
883 DepMask = TheDef->getValue("ComplexDeprecationPredicate");
886 DepMask ? !DepMask->getValue()->getAsUnquotedString().empty() : false;
889 /// Append an AsmOperand for the given substring of AsmString.
890 void MatchableInfo::addAsmOperand(StringRef Token, bool IsIsolatedToken) {
891 AsmOperands.push_back(AsmOperand(IsIsolatedToken, Token));
894 /// tokenizeAsmString - Tokenize a simplified assembly string.
895 void MatchableInfo::tokenizeAsmString(const AsmMatcherInfo &Info,
896 AsmVariantInfo const &Variant) {
897 StringRef String = AsmString;
900 bool IsIsolatedToken = true;
901 for (size_t i = 0, e = String.size(); i != e; ++i) {
902 char Char = String[i];
903 if (Variant.BreakCharacters.find(Char) != std::string::npos) {
905 addAsmOperand(String.slice(Prev, i), false);
907 IsIsolatedToken = false;
912 if (Variant.TokenizingCharacters.find(Char) != std::string::npos) {
914 addAsmOperand(String.slice(Prev, i), IsIsolatedToken);
916 IsIsolatedToken = false;
918 addAsmOperand(String.slice(i, i + 1), IsIsolatedToken);
920 IsIsolatedToken = true;
923 if (Variant.SeparatorCharacters.find(Char) != std::string::npos) {
925 addAsmOperand(String.slice(Prev, i), IsIsolatedToken);
929 IsIsolatedToken = true;
936 addAsmOperand(String.slice(Prev, i), false);
938 IsIsolatedToken = false;
941 assert(i != String.size() && "Invalid quoted character");
942 addAsmOperand(String.slice(i, i + 1), IsIsolatedToken);
944 IsIsolatedToken = false;
949 addAsmOperand(String.slice(Prev, i), false);
951 IsIsolatedToken = false;
954 // If this isn't "${", start new identifier looking like "$xxx"
955 if (i + 1 == String.size() || String[i + 1] != '{') {
960 size_t EndPos = String.find('}', i);
961 assert(EndPos != StringRef::npos &&
962 "Missing brace in operand reference!");
963 addAsmOperand(String.slice(i, EndPos+1), IsIsolatedToken);
966 IsIsolatedToken = false;
975 if (InTok && Prev != String.size())
976 addAsmOperand(String.substr(Prev), IsIsolatedToken);
979 bool MatchableInfo::validate(StringRef CommentDelimiter, bool Hack) const {
980 // Reject matchables with no .s string.
981 if (AsmString.empty())
982 PrintFatalError(TheDef->getLoc(), "instruction with empty asm string");
984 // Reject any matchables with a newline in them, they should be marked
985 // isCodeGenOnly if they are pseudo instructions.
986 if (AsmString.find('\n') != std::string::npos)
987 PrintFatalError(TheDef->getLoc(),
988 "multiline instruction is not valid for the asmparser, "
989 "mark it isCodeGenOnly");
991 // Remove comments from the asm string. We know that the asmstring only
993 if (!CommentDelimiter.empty() &&
994 StringRef(AsmString).find(CommentDelimiter) != StringRef::npos)
995 PrintFatalError(TheDef->getLoc(),
996 "asmstring for instruction has comment character in it, "
997 "mark it isCodeGenOnly");
999 // Reject matchables with operand modifiers, these aren't something we can
1000 // handle, the target should be refactored to use operands instead of
1003 // Also, check for instructions which reference the operand multiple times;
1004 // this implies a constraint we would not honor.
1005 std::set<std::string> OperandNames;
1006 for (const AsmOperand &Op : AsmOperands) {
1007 StringRef Tok = Op.Token;
1008 if (Tok[0] == '$' && Tok.find(':') != StringRef::npos)
1009 PrintFatalError(TheDef->getLoc(),
1010 "matchable with operand modifier '" + Tok +
1011 "' not supported by asm matcher. Mark isCodeGenOnly!");
1013 // Verify that any operand is only mentioned once.
1014 // We reject aliases and ignore instructions for now.
1015 if (Tok[0] == '$' && !OperandNames.insert(Tok).second) {
1017 PrintFatalError(TheDef->getLoc(),
1018 "ERROR: matchable with tied operand '" + Tok +
1019 "' can never be matched!");
1020 // FIXME: Should reject these. The ARM backend hits this with $lane in a
1021 // bunch of instructions. It is unclear what the right answer is.
1023 errs() << "warning: '" << TheDef->getName() << "': "
1024 << "ignoring instruction with tied operand '"
1034 static std::string getEnumNameForToken(StringRef Str) {
1037 for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) {
1039 case '*': Res += "_STAR_"; break;
1040 case '%': Res += "_PCT_"; break;
1041 case ':': Res += "_COLON_"; break;
1042 case '!': Res += "_EXCLAIM_"; break;
1043 case '.': Res += "_DOT_"; break;
1044 case '<': Res += "_LT_"; break;
1045 case '>': Res += "_GT_"; break;
1046 case '-': Res += "_MINUS_"; break;
1048 if ((*it >= 'A' && *it <= 'Z') ||
1049 (*it >= 'a' && *it <= 'z') ||
1050 (*it >= '0' && *it <= '9'))
1053 Res += "_" + utostr((unsigned) *it) + "_";
1060 ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) {
1061 ClassInfo *&Entry = TokenClasses[Token];
1064 Classes.emplace_front();
1065 Entry = &Classes.front();
1066 Entry->Kind = ClassInfo::Token;
1067 Entry->ClassName = "Token";
1068 Entry->Name = "MCK_" + getEnumNameForToken(Token);
1069 Entry->ValueName = Token;
1070 Entry->PredicateMethod = "<invalid>";
1071 Entry->RenderMethod = "<invalid>";
1072 Entry->ParserMethod = "";
1073 Entry->DiagnosticType = "";
1080 AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI,
1082 Record *Rec = OI.Rec;
1084 Rec = cast<DefInit>(OI.MIOperandInfo->getArg(SubOpIdx))->getDef();
1085 return getOperandClass(Rec, SubOpIdx);
1089 AsmMatcherInfo::getOperandClass(Record *Rec, int SubOpIdx) {
1090 if (Rec->isSubClassOf("RegisterOperand")) {
1091 // RegisterOperand may have an associated ParserMatchClass. If it does,
1092 // use it, else just fall back to the underlying register class.
1093 const RecordVal *R = Rec->getValue("ParserMatchClass");
1094 if (!R || !R->getValue())
1095 PrintFatalError("Record `" + Rec->getName() +
1096 "' does not have a ParserMatchClass!\n");
1098 if (DefInit *DI= dyn_cast<DefInit>(R->getValue())) {
1099 Record *MatchClass = DI->getDef();
1100 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1104 // No custom match class. Just use the register class.
1105 Record *ClassRec = Rec->getValueAsDef("RegClass");
1107 PrintFatalError(Rec->getLoc(), "RegisterOperand `" + Rec->getName() +
1108 "' has no associated register class!\n");
1109 if (ClassInfo *CI = RegisterClassClasses[ClassRec])
1111 PrintFatalError(Rec->getLoc(), "register class has no class info!");
1115 if (Rec->isSubClassOf("RegisterClass")) {
1116 if (ClassInfo *CI = RegisterClassClasses[Rec])
1118 PrintFatalError(Rec->getLoc(), "register class has no class info!");
1121 if (!Rec->isSubClassOf("Operand"))
1122 PrintFatalError(Rec->getLoc(), "Operand `" + Rec->getName() +
1123 "' does not derive from class Operand!\n");
1124 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1125 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1128 PrintFatalError(Rec->getLoc(), "operand has no match class!");
1131 struct LessRegisterSet {
1132 bool operator() (const RegisterSet &LHS, const RegisterSet & RHS) const {
1133 // std::set<T> defines its own compariso "operator<", but it
1134 // performs a lexicographical comparison by T's innate comparison
1135 // for some reason. We don't want non-deterministic pointer
1136 // comparisons so use this instead.
1137 return std::lexicographical_compare(LHS.begin(), LHS.end(),
1138 RHS.begin(), RHS.end(),
1143 void AsmMatcherInfo::
1144 buildRegisterClasses(SmallPtrSetImpl<Record*> &SingletonRegisters) {
1145 const auto &Registers = Target.getRegBank().getRegisters();
1146 auto &RegClassList = Target.getRegBank().getRegClasses();
1148 typedef std::set<RegisterSet, LessRegisterSet> RegisterSetSet;
1150 // The register sets used for matching.
1151 RegisterSetSet RegisterSets;
1153 // Gather the defined sets.
1154 for (const CodeGenRegisterClass &RC : RegClassList)
1155 RegisterSets.insert(
1156 RegisterSet(RC.getOrder().begin(), RC.getOrder().end()));
1158 // Add any required singleton sets.
1159 for (Record *Rec : SingletonRegisters) {
1160 RegisterSets.insert(RegisterSet(&Rec, &Rec + 1));
1163 // Introduce derived sets where necessary (when a register does not determine
1164 // a unique register set class), and build the mapping of registers to the set
1165 // they should classify to.
1166 std::map<Record*, RegisterSet> RegisterMap;
1167 for (const CodeGenRegister &CGR : Registers) {
1168 // Compute the intersection of all sets containing this register.
1169 RegisterSet ContainingSet;
1171 for (const RegisterSet &RS : RegisterSets) {
1172 if (!RS.count(CGR.TheDef))
1175 if (ContainingSet.empty()) {
1181 std::swap(Tmp, ContainingSet);
1182 std::insert_iterator<RegisterSet> II(ContainingSet,
1183 ContainingSet.begin());
1184 std::set_intersection(Tmp.begin(), Tmp.end(), RS.begin(), RS.end(), II,
1188 if (!ContainingSet.empty()) {
1189 RegisterSets.insert(ContainingSet);
1190 RegisterMap.insert(std::make_pair(CGR.TheDef, ContainingSet));
1194 // Construct the register classes.
1195 std::map<RegisterSet, ClassInfo*, LessRegisterSet> RegisterSetClasses;
1197 for (const RegisterSet &RS : RegisterSets) {
1198 Classes.emplace_front();
1199 ClassInfo *CI = &Classes.front();
1200 CI->Kind = ClassInfo::RegisterClass0 + Index;
1201 CI->ClassName = "Reg" + utostr(Index);
1202 CI->Name = "MCK_Reg" + utostr(Index);
1204 CI->PredicateMethod = ""; // unused
1205 CI->RenderMethod = "addRegOperands";
1207 // FIXME: diagnostic type.
1208 CI->DiagnosticType = "";
1209 RegisterSetClasses.insert(std::make_pair(RS, CI));
1213 // Find the superclasses; we could compute only the subgroup lattice edges,
1214 // but there isn't really a point.
1215 for (const RegisterSet &RS : RegisterSets) {
1216 ClassInfo *CI = RegisterSetClasses[RS];
1217 for (const RegisterSet &RS2 : RegisterSets)
1219 std::includes(RS2.begin(), RS2.end(), RS.begin(), RS.end(),
1221 CI->SuperClasses.push_back(RegisterSetClasses[RS2]);
1224 // Name the register classes which correspond to a user defined RegisterClass.
1225 for (const CodeGenRegisterClass &RC : RegClassList) {
1226 // Def will be NULL for non-user defined register classes.
1227 Record *Def = RC.getDef();
1230 ClassInfo *CI = RegisterSetClasses[RegisterSet(RC.getOrder().begin(),
1231 RC.getOrder().end())];
1232 if (CI->ValueName.empty()) {
1233 CI->ClassName = RC.getName();
1234 CI->Name = "MCK_" + RC.getName();
1235 CI->ValueName = RC.getName();
1237 CI->ValueName = CI->ValueName + "," + RC.getName();
1239 RegisterClassClasses.insert(std::make_pair(Def, CI));
1242 // Populate the map for individual registers.
1243 for (std::map<Record*, RegisterSet>::iterator it = RegisterMap.begin(),
1244 ie = RegisterMap.end(); it != ie; ++it)
1245 RegisterClasses[it->first] = RegisterSetClasses[it->second];
1247 // Name the register classes which correspond to singleton registers.
1248 for (Record *Rec : SingletonRegisters) {
1249 ClassInfo *CI = RegisterClasses[Rec];
1250 assert(CI && "Missing singleton register class info!");
1252 if (CI->ValueName.empty()) {
1253 CI->ClassName = Rec->getName();
1254 CI->Name = "MCK_" + Rec->getName();
1255 CI->ValueName = Rec->getName();
1257 CI->ValueName = CI->ValueName + "," + Rec->getName();
1261 void AsmMatcherInfo::buildOperandClasses() {
1262 std::vector<Record*> AsmOperands =
1263 Records.getAllDerivedDefinitions("AsmOperandClass");
1265 // Pre-populate AsmOperandClasses map.
1266 for (Record *Rec : AsmOperands) {
1267 Classes.emplace_front();
1268 AsmOperandClasses[Rec] = &Classes.front();
1272 for (Record *Rec : AsmOperands) {
1273 ClassInfo *CI = AsmOperandClasses[Rec];
1274 CI->Kind = ClassInfo::UserClass0 + Index;
1276 ListInit *Supers = Rec->getValueAsListInit("SuperClasses");
1277 for (Init *I : Supers->getValues()) {
1278 DefInit *DI = dyn_cast<DefInit>(I);
1280 PrintError(Rec->getLoc(), "Invalid super class reference!");
1284 ClassInfo *SC = AsmOperandClasses[DI->getDef()];
1286 PrintError(Rec->getLoc(), "Invalid super class reference!");
1288 CI->SuperClasses.push_back(SC);
1290 CI->ClassName = Rec->getValueAsString("Name");
1291 CI->Name = "MCK_" + CI->ClassName;
1292 CI->ValueName = Rec->getName();
1294 // Get or construct the predicate method name.
1295 Init *PMName = Rec->getValueInit("PredicateMethod");
1296 if (StringInit *SI = dyn_cast<StringInit>(PMName)) {
1297 CI->PredicateMethod = SI->getValue();
1299 assert(isa<UnsetInit>(PMName) && "Unexpected PredicateMethod field!");
1300 CI->PredicateMethod = "is" + CI->ClassName;
1303 // Get or construct the render method name.
1304 Init *RMName = Rec->getValueInit("RenderMethod");
1305 if (StringInit *SI = dyn_cast<StringInit>(RMName)) {
1306 CI->RenderMethod = SI->getValue();
1308 assert(isa<UnsetInit>(RMName) && "Unexpected RenderMethod field!");
1309 CI->RenderMethod = "add" + CI->ClassName + "Operands";
1312 // Get the parse method name or leave it as empty.
1313 Init *PRMName = Rec->getValueInit("ParserMethod");
1314 if (StringInit *SI = dyn_cast<StringInit>(PRMName))
1315 CI->ParserMethod = SI->getValue();
1317 // Get the diagnostic type or leave it as empty.
1318 // Get the parse method name or leave it as empty.
1319 Init *DiagnosticType = Rec->getValueInit("DiagnosticType");
1320 if (StringInit *SI = dyn_cast<StringInit>(DiagnosticType))
1321 CI->DiagnosticType = SI->getValue();
1327 AsmMatcherInfo::AsmMatcherInfo(Record *asmParser,
1328 CodeGenTarget &target,
1329 RecordKeeper &records)
1330 : Records(records), AsmParser(asmParser), Target(target) {
1333 /// buildOperandMatchInfo - Build the necessary information to handle user
1334 /// defined operand parsing methods.
1335 void AsmMatcherInfo::buildOperandMatchInfo() {
1337 /// Map containing a mask with all operands indices that can be found for
1338 /// that class inside a instruction.
1339 typedef std::map<ClassInfo *, unsigned, less_ptr<ClassInfo>> OpClassMaskTy;
1340 OpClassMaskTy OpClassMask;
1342 for (const auto &MI : Matchables) {
1343 OpClassMask.clear();
1345 // Keep track of all operands of this instructions which belong to the
1347 for (unsigned i = 0, e = MI->AsmOperands.size(); i != e; ++i) {
1348 const MatchableInfo::AsmOperand &Op = MI->AsmOperands[i];
1349 if (Op.Class->ParserMethod.empty())
1351 unsigned &OperandMask = OpClassMask[Op.Class];
1352 OperandMask |= (1 << i);
1355 // Generate operand match info for each mnemonic/operand class pair.
1356 for (const auto &OCM : OpClassMask) {
1357 unsigned OpMask = OCM.second;
1358 ClassInfo *CI = OCM.first;
1359 OperandMatchInfo.push_back(OperandMatchEntry::create(MI.get(), CI,
1365 void AsmMatcherInfo::buildInfo() {
1366 // Build information about all of the AssemblerPredicates.
1367 std::vector<Record*> AllPredicates =
1368 Records.getAllDerivedDefinitions("Predicate");
1369 for (Record *Pred : AllPredicates) {
1370 // Ignore predicates that are not intended for the assembler.
1371 if (!Pred->getValueAsBit("AssemblerMatcherPredicate"))
1374 if (Pred->getName().empty())
1375 PrintFatalError(Pred->getLoc(), "Predicate has no name!");
1377 SubtargetFeatures.insert(std::make_pair(
1378 Pred, SubtargetFeatureInfo(Pred, SubtargetFeatures.size())));
1379 DEBUG(SubtargetFeatures.find(Pred)->second.dump());
1380 assert(SubtargetFeatures.size() <= 64 && "Too many subtarget features!");
1383 bool HasMnemonicFirst = AsmParser->getValueAsBit("HasMnemonicFirst");
1385 // Parse the instructions; we need to do this first so that we can gather the
1386 // singleton register classes.
1387 SmallPtrSet<Record*, 16> SingletonRegisters;
1388 unsigned VariantCount = Target.getAsmParserVariantCount();
1389 for (unsigned VC = 0; VC != VariantCount; ++VC) {
1390 Record *AsmVariant = Target.getAsmParserVariant(VC);
1391 std::string CommentDelimiter =
1392 AsmVariant->getValueAsString("CommentDelimiter");
1393 AsmVariantInfo Variant;
1394 Variant.RegisterPrefix = AsmVariant->getValueAsString("RegisterPrefix");
1395 Variant.TokenizingCharacters =
1396 AsmVariant->getValueAsString("TokenizingCharacters");
1397 Variant.SeparatorCharacters =
1398 AsmVariant->getValueAsString("SeparatorCharacters");
1399 Variant.BreakCharacters =
1400 AsmVariant->getValueAsString("BreakCharacters");
1401 Variant.AsmVariantNo = AsmVariant->getValueAsInt("Variant");
1403 for (const CodeGenInstruction *CGI : Target.instructions()) {
1405 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1406 // filter the set of instructions we consider.
1407 if (!StringRef(CGI->TheDef->getName()).startswith(MatchPrefix))
1410 // Ignore "codegen only" instructions.
1411 if (CGI->TheDef->getValueAsBit("isCodeGenOnly"))
1414 auto II = llvm::make_unique<MatchableInfo>(*CGI);
1416 II->initialize(*this, SingletonRegisters, Variant, HasMnemonicFirst);
1418 // Ignore instructions which shouldn't be matched and diagnose invalid
1419 // instruction definitions with an error.
1420 if (!II->validate(CommentDelimiter, true))
1423 Matchables.push_back(std::move(II));
1426 // Parse all of the InstAlias definitions and stick them in the list of
1428 std::vector<Record*> AllInstAliases =
1429 Records.getAllDerivedDefinitions("InstAlias");
1430 for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) {
1431 auto Alias = llvm::make_unique<CodeGenInstAlias>(AllInstAliases[i],
1432 Variant.AsmVariantNo,
1435 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1436 // filter the set of instruction aliases we consider, based on the target
1438 if (!StringRef(Alias->ResultInst->TheDef->getName())
1439 .startswith( MatchPrefix))
1442 auto II = llvm::make_unique<MatchableInfo>(std::move(Alias));
1444 II->initialize(*this, SingletonRegisters, Variant, HasMnemonicFirst);
1446 // Validate the alias definitions.
1447 II->validate(CommentDelimiter, false);
1449 Matchables.push_back(std::move(II));
1453 // Build info for the register classes.
1454 buildRegisterClasses(SingletonRegisters);
1456 // Build info for the user defined assembly operand classes.
1457 buildOperandClasses();
1459 // Build the information about matchables, now that we have fully formed
1461 std::vector<std::unique_ptr<MatchableInfo>> NewMatchables;
1462 for (auto &II : Matchables) {
1463 // Parse the tokens after the mnemonic.
1464 // Note: buildInstructionOperandReference may insert new AsmOperands, so
1465 // don't precompute the loop bound.
1466 for (unsigned i = 0; i != II->AsmOperands.size(); ++i) {
1467 MatchableInfo::AsmOperand &Op = II->AsmOperands[i];
1468 StringRef Token = Op.Token;
1470 // Check for singleton registers.
1471 if (Record *RegRecord = Op.SingletonReg) {
1472 Op.Class = RegisterClasses[RegRecord];
1473 assert(Op.Class && Op.Class->Registers.size() == 1 &&
1474 "Unexpected class for singleton register");
1478 // Check for simple tokens.
1479 if (Token[0] != '$') {
1480 Op.Class = getTokenClass(Token);
1484 if (Token.size() > 1 && isdigit(Token[1])) {
1485 Op.Class = getTokenClass(Token);
1489 // Otherwise this is an operand reference.
1490 StringRef OperandName;
1491 if (Token[1] == '{')
1492 OperandName = Token.substr(2, Token.size() - 3);
1494 OperandName = Token.substr(1);
1496 if (II->DefRec.is<const CodeGenInstruction*>())
1497 buildInstructionOperandReference(II.get(), OperandName, i);
1499 buildAliasOperandReference(II.get(), OperandName, Op);
1502 if (II->DefRec.is<const CodeGenInstruction*>()) {
1503 II->buildInstructionResultOperands();
1504 // If the instruction has a two-operand alias, build up the
1505 // matchable here. We'll add them in bulk at the end to avoid
1506 // confusing this loop.
1507 std::string Constraint =
1508 II->TheDef->getValueAsString("TwoOperandAliasConstraint");
1509 if (Constraint != "") {
1510 // Start by making a copy of the original matchable.
1511 auto AliasII = llvm::make_unique<MatchableInfo>(*II);
1513 // Adjust it to be a two-operand alias.
1514 AliasII->formTwoOperandAlias(Constraint);
1516 // Add the alias to the matchables list.
1517 NewMatchables.push_back(std::move(AliasII));
1520 II->buildAliasResultOperands();
1522 if (!NewMatchables.empty())
1523 Matchables.insert(Matchables.end(),
1524 std::make_move_iterator(NewMatchables.begin()),
1525 std::make_move_iterator(NewMatchables.end()));
1527 // Process token alias definitions and set up the associated superclass
1529 std::vector<Record*> AllTokenAliases =
1530 Records.getAllDerivedDefinitions("TokenAlias");
1531 for (Record *Rec : AllTokenAliases) {
1532 ClassInfo *FromClass = getTokenClass(Rec->getValueAsString("FromToken"));
1533 ClassInfo *ToClass = getTokenClass(Rec->getValueAsString("ToToken"));
1534 if (FromClass == ToClass)
1535 PrintFatalError(Rec->getLoc(),
1536 "error: Destination value identical to source value.");
1537 FromClass->SuperClasses.push_back(ToClass);
1540 // Reorder classes so that classes precede super classes.
1544 /// buildInstructionOperandReference - The specified operand is a reference to a
1545 /// named operand such as $src. Resolve the Class and OperandInfo pointers.
1546 void AsmMatcherInfo::
1547 buildInstructionOperandReference(MatchableInfo *II,
1548 StringRef OperandName,
1549 unsigned AsmOpIdx) {
1550 const CodeGenInstruction &CGI = *II->DefRec.get<const CodeGenInstruction*>();
1551 const CGIOperandList &Operands = CGI.Operands;
1552 MatchableInfo::AsmOperand *Op = &II->AsmOperands[AsmOpIdx];
1554 // Map this token to an operand.
1556 if (!Operands.hasOperandNamed(OperandName, Idx))
1557 PrintFatalError(II->TheDef->getLoc(),
1558 "error: unable to find operand: '" + OperandName + "'");
1560 // If the instruction operand has multiple suboperands, but the parser
1561 // match class for the asm operand is still the default "ImmAsmOperand",
1562 // then handle each suboperand separately.
1563 if (Op->SubOpIdx == -1 && Operands[Idx].MINumOperands > 1) {
1564 Record *Rec = Operands[Idx].Rec;
1565 assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
1566 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1567 if (MatchClass && MatchClass->getValueAsString("Name") == "Imm") {
1568 // Insert remaining suboperands after AsmOpIdx in II->AsmOperands.
1569 StringRef Token = Op->Token; // save this in case Op gets moved
1570 for (unsigned SI = 1, SE = Operands[Idx].MINumOperands; SI != SE; ++SI) {
1571 MatchableInfo::AsmOperand NewAsmOp(/*IsIsolatedToken=*/true, Token);
1572 NewAsmOp.SubOpIdx = SI;
1573 II->AsmOperands.insert(II->AsmOperands.begin()+AsmOpIdx+SI, NewAsmOp);
1575 // Replace Op with first suboperand.
1576 Op = &II->AsmOperands[AsmOpIdx]; // update the pointer in case it moved
1581 // Set up the operand class.
1582 Op->Class = getOperandClass(Operands[Idx], Op->SubOpIdx);
1584 // If the named operand is tied, canonicalize it to the untied operand.
1585 // For example, something like:
1586 // (outs GPR:$dst), (ins GPR:$src)
1587 // with an asmstring of
1589 // we want to canonicalize to:
1591 // so that we know how to provide the $dst operand when filling in the result.
1593 if (Operands[Idx].MINumOperands == 1)
1594 OITied = Operands[Idx].getTiedRegister();
1596 // The tied operand index is an MIOperand index, find the operand that
1598 std::pair<unsigned, unsigned> Idx = Operands.getSubOperandNumber(OITied);
1599 OperandName = Operands[Idx.first].Name;
1600 Op->SubOpIdx = Idx.second;
1603 Op->SrcOpName = OperandName;
1606 /// buildAliasOperandReference - When parsing an operand reference out of the
1607 /// matching string (e.g. "movsx $src, $dst"), determine what the class of the
1608 /// operand reference is by looking it up in the result pattern definition.
1609 void AsmMatcherInfo::buildAliasOperandReference(MatchableInfo *II,
1610 StringRef OperandName,
1611 MatchableInfo::AsmOperand &Op) {
1612 const CodeGenInstAlias &CGA = *II->DefRec.get<const CodeGenInstAlias*>();
1614 // Set up the operand class.
1615 for (unsigned i = 0, e = CGA.ResultOperands.size(); i != e; ++i)
1616 if (CGA.ResultOperands[i].isRecord() &&
1617 CGA.ResultOperands[i].getName() == OperandName) {
1618 // It's safe to go with the first one we find, because CodeGenInstAlias
1619 // validates that all operands with the same name have the same record.
1620 Op.SubOpIdx = CGA.ResultInstOperandIndex[i].second;
1621 // Use the match class from the Alias definition, not the
1622 // destination instruction, as we may have an immediate that's
1623 // being munged by the match class.
1624 Op.Class = getOperandClass(CGA.ResultOperands[i].getRecord(),
1626 Op.SrcOpName = OperandName;
1630 PrintFatalError(II->TheDef->getLoc(),
1631 "error: unable to find operand: '" + OperandName + "'");
1634 void MatchableInfo::buildInstructionResultOperands() {
1635 const CodeGenInstruction *ResultInst = getResultInst();
1637 // Loop over all operands of the result instruction, determining how to
1639 for (const CGIOperandList::OperandInfo &OpInfo : ResultInst->Operands) {
1640 // If this is a tied operand, just copy from the previously handled operand.
1642 if (OpInfo.MINumOperands == 1)
1643 TiedOp = OpInfo.getTiedRegister();
1645 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1649 // Find out what operand from the asmparser this MCInst operand comes from.
1650 int SrcOperand = findAsmOperandNamed(OpInfo.Name);
1651 if (OpInfo.Name.empty() || SrcOperand == -1) {
1652 // This may happen for operands that are tied to a suboperand of a
1653 // complex operand. Simply use a dummy value here; nobody should
1654 // use this operand slot.
1655 // FIXME: The long term goal is for the MCOperand list to not contain
1656 // tied operands at all.
1657 ResOperands.push_back(ResOperand::getImmOp(0));
1661 // Check if the one AsmOperand populates the entire operand.
1662 unsigned NumOperands = OpInfo.MINumOperands;
1663 if (AsmOperands[SrcOperand].SubOpIdx == -1) {
1664 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, NumOperands));
1668 // Add a separate ResOperand for each suboperand.
1669 for (unsigned AI = 0; AI < NumOperands; ++AI) {
1670 assert(AsmOperands[SrcOperand+AI].SubOpIdx == (int)AI &&
1671 AsmOperands[SrcOperand+AI].SrcOpName == OpInfo.Name &&
1672 "unexpected AsmOperands for suboperands");
1673 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand + AI, 1));
1678 void MatchableInfo::buildAliasResultOperands() {
1679 const CodeGenInstAlias &CGA = *DefRec.get<const CodeGenInstAlias*>();
1680 const CodeGenInstruction *ResultInst = getResultInst();
1682 // Loop over all operands of the result instruction, determining how to
1684 unsigned AliasOpNo = 0;
1685 unsigned LastOpNo = CGA.ResultInstOperandIndex.size();
1686 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1687 const CGIOperandList::OperandInfo *OpInfo = &ResultInst->Operands[i];
1689 // If this is a tied operand, just copy from the previously handled operand.
1691 if (OpInfo->MINumOperands == 1)
1692 TiedOp = OpInfo->getTiedRegister();
1694 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1698 // Handle all the suboperands for this operand.
1699 const std::string &OpName = OpInfo->Name;
1700 for ( ; AliasOpNo < LastOpNo &&
1701 CGA.ResultInstOperandIndex[AliasOpNo].first == i; ++AliasOpNo) {
1702 int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second;
1704 // Find out what operand from the asmparser that this MCInst operand
1706 switch (CGA.ResultOperands[AliasOpNo].Kind) {
1707 case CodeGenInstAlias::ResultOperand::K_Record: {
1708 StringRef Name = CGA.ResultOperands[AliasOpNo].getName();
1709 int SrcOperand = findAsmOperand(Name, SubIdx);
1710 if (SrcOperand == -1)
1711 PrintFatalError(TheDef->getLoc(), "Instruction '" +
1712 TheDef->getName() + "' has operand '" + OpName +
1713 "' that doesn't appear in asm string!");
1714 unsigned NumOperands = (SubIdx == -1 ? OpInfo->MINumOperands : 1);
1715 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand,
1719 case CodeGenInstAlias::ResultOperand::K_Imm: {
1720 int64_t ImmVal = CGA.ResultOperands[AliasOpNo].getImm();
1721 ResOperands.push_back(ResOperand::getImmOp(ImmVal));
1724 case CodeGenInstAlias::ResultOperand::K_Reg: {
1725 Record *Reg = CGA.ResultOperands[AliasOpNo].getRegister();
1726 ResOperands.push_back(ResOperand::getRegOp(Reg));
1734 static unsigned getConverterOperandID(const std::string &Name,
1735 SmallSetVector<std::string, 16> &Table,
1737 IsNew = Table.insert(Name);
1739 unsigned ID = IsNew ? Table.size() - 1 :
1740 std::find(Table.begin(), Table.end(), Name) - Table.begin();
1742 assert(ID < Table.size());
1748 static void emitConvertFuncs(CodeGenTarget &Target, StringRef ClassName,
1749 std::vector<std::unique_ptr<MatchableInfo>> &Infos,
1750 bool HasMnemonicFirst, raw_ostream &OS) {
1751 SmallSetVector<std::string, 16> OperandConversionKinds;
1752 SmallSetVector<std::string, 16> InstructionConversionKinds;
1753 std::vector<std::vector<uint8_t> > ConversionTable;
1754 size_t MaxRowLength = 2; // minimum is custom converter plus terminator.
1756 // TargetOperandClass - This is the target's operand class, like X86Operand.
1757 std::string TargetOperandClass = Target.getName() + "Operand";
1759 // Write the convert function to a separate stream, so we can drop it after
1760 // the enum. We'll build up the conversion handlers for the individual
1761 // operand types opportunistically as we encounter them.
1762 std::string ConvertFnBody;
1763 raw_string_ostream CvtOS(ConvertFnBody);
1764 // Start the unified conversion function.
1765 CvtOS << "void " << Target.getName() << ClassName << "::\n"
1766 << "convertToMCInst(unsigned Kind, MCInst &Inst, "
1767 << "unsigned Opcode,\n"
1768 << " const OperandVector"
1769 << " &Operands) {\n"
1770 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
1771 << " const uint8_t *Converter = ConversionTable[Kind];\n"
1772 << " Inst.setOpcode(Opcode);\n"
1773 << " for (const uint8_t *p = Converter; *p; p+= 2) {\n"
1774 << " switch (*p) {\n"
1775 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
1776 << " case CVT_Reg:\n"
1777 << " static_cast<" << TargetOperandClass
1778 << "&>(*Operands[*(p + 1)]).addRegOperands(Inst, 1);\n"
1780 << " case CVT_Tied:\n"
1781 << " Inst.addOperand(Inst.getOperand(*(p + 1)));\n"
1784 std::string OperandFnBody;
1785 raw_string_ostream OpOS(OperandFnBody);
1786 // Start the operand number lookup function.
1787 OpOS << "void " << Target.getName() << ClassName << "::\n"
1788 << "convertToMapAndConstraints(unsigned Kind,\n";
1790 OpOS << "const OperandVector &Operands) {\n"
1791 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
1792 << " unsigned NumMCOperands = 0;\n"
1793 << " const uint8_t *Converter = ConversionTable[Kind];\n"
1794 << " for (const uint8_t *p = Converter; *p; p+= 2) {\n"
1795 << " switch (*p) {\n"
1796 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
1797 << " case CVT_Reg:\n"
1798 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1799 << " Operands[*(p + 1)]->setConstraint(\"r\");\n"
1800 << " ++NumMCOperands;\n"
1802 << " case CVT_Tied:\n"
1803 << " ++NumMCOperands;\n"
1806 // Pre-populate the operand conversion kinds with the standard always
1807 // available entries.
1808 OperandConversionKinds.insert("CVT_Done");
1809 OperandConversionKinds.insert("CVT_Reg");
1810 OperandConversionKinds.insert("CVT_Tied");
1811 enum { CVT_Done, CVT_Reg, CVT_Tied };
1813 for (auto &II : Infos) {
1814 // Check if we have a custom match function.
1815 std::string AsmMatchConverter =
1816 II->getResultInst()->TheDef->getValueAsString("AsmMatchConverter");
1817 if (!AsmMatchConverter.empty() && II->UseInstAsmMatchConverter) {
1818 std::string Signature = "ConvertCustom_" + AsmMatchConverter;
1819 II->ConversionFnKind = Signature;
1821 // Check if we have already generated this signature.
1822 if (!InstructionConversionKinds.insert(Signature))
1825 // Remember this converter for the kind enum.
1826 unsigned KindID = OperandConversionKinds.size();
1827 OperandConversionKinds.insert("CVT_" +
1828 getEnumNameForToken(AsmMatchConverter));
1830 // Add the converter row for this instruction.
1831 ConversionTable.emplace_back();
1832 ConversionTable.back().push_back(KindID);
1833 ConversionTable.back().push_back(CVT_Done);
1835 // Add the handler to the conversion driver function.
1836 CvtOS << " case CVT_"
1837 << getEnumNameForToken(AsmMatchConverter) << ":\n"
1838 << " " << AsmMatchConverter << "(Inst, Operands);\n"
1841 // FIXME: Handle the operand number lookup for custom match functions.
1845 // Build the conversion function signature.
1846 std::string Signature = "Convert";
1848 std::vector<uint8_t> ConversionRow;
1850 // Compute the convert enum and the case body.
1851 MaxRowLength = std::max(MaxRowLength, II->ResOperands.size()*2 + 1 );
1853 for (unsigned i = 0, e = II->ResOperands.size(); i != e; ++i) {
1854 const MatchableInfo::ResOperand &OpInfo = II->ResOperands[i];
1856 // Generate code to populate each result operand.
1857 switch (OpInfo.Kind) {
1858 case MatchableInfo::ResOperand::RenderAsmOperand: {
1859 // This comes from something we parsed.
1860 const MatchableInfo::AsmOperand &Op =
1861 II->AsmOperands[OpInfo.AsmOperandNum];
1863 // Registers are always converted the same, don't duplicate the
1864 // conversion function based on them.
1867 Class = Op.Class->isRegisterClass() ? "Reg" : Op.Class->ClassName;
1869 Signature += utostr(OpInfo.MINumOperands);
1870 Signature += "_" + itostr(OpInfo.AsmOperandNum);
1872 // Add the conversion kind, if necessary, and get the associated ID
1873 // the index of its entry in the vector).
1874 std::string Name = "CVT_" + (Op.Class->isRegisterClass() ? "Reg" :
1875 Op.Class->RenderMethod);
1876 Name = getEnumNameForToken(Name);
1878 bool IsNewConverter = false;
1879 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1882 // Add the operand entry to the instruction kind conversion row.
1883 ConversionRow.push_back(ID);
1884 ConversionRow.push_back(OpInfo.AsmOperandNum + HasMnemonicFirst);
1886 if (!IsNewConverter)
1889 // This is a new operand kind. Add a handler for it to the
1890 // converter driver.
1891 CvtOS << " case " << Name << ":\n"
1892 << " static_cast<" << TargetOperandClass
1893 << "&>(*Operands[*(p + 1)])." << Op.Class->RenderMethod
1894 << "(Inst, " << OpInfo.MINumOperands << ");\n"
1897 // Add a handler for the operand number lookup.
1898 OpOS << " case " << Name << ":\n"
1899 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n";
1901 if (Op.Class->isRegisterClass())
1902 OpOS << " Operands[*(p + 1)]->setConstraint(\"r\");\n";
1904 OpOS << " Operands[*(p + 1)]->setConstraint(\"m\");\n";
1905 OpOS << " NumMCOperands += " << OpInfo.MINumOperands << ";\n"
1909 case MatchableInfo::ResOperand::TiedOperand: {
1910 // If this operand is tied to a previous one, just copy the MCInst
1911 // operand from the earlier one.We can only tie single MCOperand values.
1912 assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand");
1913 unsigned TiedOp = OpInfo.TiedOperandNum;
1914 assert(i > TiedOp && "Tied operand precedes its target!");
1915 Signature += "__Tie" + utostr(TiedOp);
1916 ConversionRow.push_back(CVT_Tied);
1917 ConversionRow.push_back(TiedOp);
1920 case MatchableInfo::ResOperand::ImmOperand: {
1921 int64_t Val = OpInfo.ImmVal;
1922 std::string Ty = "imm_" + itostr(Val);
1923 Ty = getEnumNameForToken(Ty);
1924 Signature += "__" + Ty;
1926 std::string Name = "CVT_" + Ty;
1927 bool IsNewConverter = false;
1928 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1930 // Add the operand entry to the instruction kind conversion row.
1931 ConversionRow.push_back(ID);
1932 ConversionRow.push_back(0);
1934 if (!IsNewConverter)
1937 CvtOS << " case " << Name << ":\n"
1938 << " Inst.addOperand(MCOperand::createImm(" << Val << "));\n"
1941 OpOS << " case " << Name << ":\n"
1942 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1943 << " Operands[*(p + 1)]->setConstraint(\"\");\n"
1944 << " ++NumMCOperands;\n"
1948 case MatchableInfo::ResOperand::RegOperand: {
1949 std::string Reg, Name;
1950 if (!OpInfo.Register) {
1954 Reg = getQualifiedName(OpInfo.Register);
1955 Name = "reg" + OpInfo.Register->getName();
1957 Signature += "__" + Name;
1958 Name = "CVT_" + Name;
1959 bool IsNewConverter = false;
1960 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1962 // Add the operand entry to the instruction kind conversion row.
1963 ConversionRow.push_back(ID);
1964 ConversionRow.push_back(0);
1966 if (!IsNewConverter)
1968 CvtOS << " case " << Name << ":\n"
1969 << " Inst.addOperand(MCOperand::createReg(" << Reg << "));\n"
1972 OpOS << " case " << Name << ":\n"
1973 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1974 << " Operands[*(p + 1)]->setConstraint(\"m\");\n"
1975 << " ++NumMCOperands;\n"
1981 // If there were no operands, add to the signature to that effect
1982 if (Signature == "Convert")
1983 Signature += "_NoOperands";
1985 II->ConversionFnKind = Signature;
1987 // Save the signature. If we already have it, don't add a new row
1989 if (!InstructionConversionKinds.insert(Signature))
1992 // Add the row to the table.
1993 ConversionTable.push_back(std::move(ConversionRow));
1996 // Finish up the converter driver function.
1997 CvtOS << " }\n }\n}\n\n";
1999 // Finish up the operand number lookup function.
2000 OpOS << " }\n }\n}\n\n";
2002 OS << "namespace {\n";
2004 // Output the operand conversion kind enum.
2005 OS << "enum OperatorConversionKind {\n";
2006 for (const std::string &Converter : OperandConversionKinds)
2007 OS << " " << Converter << ",\n";
2008 OS << " CVT_NUM_CONVERTERS\n";
2011 // Output the instruction conversion kind enum.
2012 OS << "enum InstructionConversionKind {\n";
2013 for (const std::string &Signature : InstructionConversionKinds)
2014 OS << " " << Signature << ",\n";
2015 OS << " CVT_NUM_SIGNATURES\n";
2019 OS << "} // end anonymous namespace\n\n";
2021 // Output the conversion table.
2022 OS << "static const uint8_t ConversionTable[CVT_NUM_SIGNATURES]["
2023 << MaxRowLength << "] = {\n";
2025 for (unsigned Row = 0, ERow = ConversionTable.size(); Row != ERow; ++Row) {
2026 assert(ConversionTable[Row].size() % 2 == 0 && "bad conversion row!");
2027 OS << " // " << InstructionConversionKinds[Row] << "\n";
2029 for (unsigned i = 0, e = ConversionTable[Row].size(); i != e; i += 2)
2030 OS << OperandConversionKinds[ConversionTable[Row][i]] << ", "
2031 << (unsigned)(ConversionTable[Row][i + 1]) << ", ";
2032 OS << "CVT_Done },\n";
2037 // Spit out the conversion driver function.
2040 // Spit out the operand number lookup function.
2044 /// emitMatchClassEnumeration - Emit the enumeration for match class kinds.
2045 static void emitMatchClassEnumeration(CodeGenTarget &Target,
2046 std::forward_list<ClassInfo> &Infos,
2048 OS << "namespace {\n\n";
2050 OS << "/// MatchClassKind - The kinds of classes which participate in\n"
2051 << "/// instruction matching.\n";
2052 OS << "enum MatchClassKind {\n";
2053 OS << " InvalidMatchClass = 0,\n";
2054 for (const auto &CI : Infos) {
2055 OS << " " << CI.Name << ", // ";
2056 if (CI.Kind == ClassInfo::Token) {
2057 OS << "'" << CI.ValueName << "'\n";
2058 } else if (CI.isRegisterClass()) {
2059 if (!CI.ValueName.empty())
2060 OS << "register class '" << CI.ValueName << "'\n";
2062 OS << "derived register class\n";
2064 OS << "user defined class '" << CI.ValueName << "'\n";
2067 OS << " NumMatchClassKinds\n";
2073 /// emitValidateOperandClass - Emit the function to validate an operand class.
2074 static void emitValidateOperandClass(AsmMatcherInfo &Info,
2076 OS << "static unsigned validateOperandClass(MCParsedAsmOperand &GOp, "
2077 << "MatchClassKind Kind) {\n";
2078 OS << " " << Info.Target.getName() << "Operand &Operand = ("
2079 << Info.Target.getName() << "Operand&)GOp;\n";
2081 // The InvalidMatchClass is not to match any operand.
2082 OS << " if (Kind == InvalidMatchClass)\n";
2083 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n\n";
2085 // Check for Token operands first.
2086 // FIXME: Use a more specific diagnostic type.
2087 OS << " if (Operand.isToken())\n";
2088 OS << " return isSubclass(matchTokenString(Operand.getToken()), Kind) ?\n"
2089 << " MCTargetAsmParser::Match_Success :\n"
2090 << " MCTargetAsmParser::Match_InvalidOperand;\n\n";
2092 // Check the user classes. We don't care what order since we're only
2093 // actually matching against one of them.
2094 for (const auto &CI : Info.Classes) {
2095 if (!CI.isUserClass())
2098 OS << " // '" << CI.ClassName << "' class\n";
2099 OS << " if (Kind == " << CI.Name << ") {\n";
2100 OS << " if (Operand." << CI.PredicateMethod << "())\n";
2101 OS << " return MCTargetAsmParser::Match_Success;\n";
2102 if (!CI.DiagnosticType.empty())
2103 OS << " return " << Info.Target.getName() << "AsmParser::Match_"
2104 << CI.DiagnosticType << ";\n";
2108 // Check for register operands, including sub-classes.
2109 OS << " if (Operand.isReg()) {\n";
2110 OS << " MatchClassKind OpKind;\n";
2111 OS << " switch (Operand.getReg()) {\n";
2112 OS << " default: OpKind = InvalidMatchClass; break;\n";
2113 for (const auto &RC : Info.RegisterClasses)
2114 OS << " case " << Info.Target.getName() << "::"
2115 << RC.first->getName() << ": OpKind = " << RC.second->Name
2118 OS << " return isSubclass(OpKind, Kind) ? "
2119 << "MCTargetAsmParser::Match_Success :\n "
2120 << " MCTargetAsmParser::Match_InvalidOperand;\n }\n\n";
2122 // Generic fallthrough match failure case for operands that don't have
2123 // specialized diagnostic types.
2124 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n";
2128 /// emitIsSubclass - Emit the subclass predicate function.
2129 static void emitIsSubclass(CodeGenTarget &Target,
2130 std::forward_list<ClassInfo> &Infos,
2132 OS << "/// isSubclass - Compute whether \\p A is a subclass of \\p B.\n";
2133 OS << "static bool isSubclass(MatchClassKind A, MatchClassKind B) {\n";
2134 OS << " if (A == B)\n";
2135 OS << " return true;\n\n";
2137 bool EmittedSwitch = false;
2138 for (const auto &A : Infos) {
2139 std::vector<StringRef> SuperClasses;
2140 for (const auto &B : Infos) {
2141 if (&A != &B && A.isSubsetOf(B))
2142 SuperClasses.push_back(B.Name);
2145 if (SuperClasses.empty())
2148 // If this is the first SuperClass, emit the switch header.
2149 if (!EmittedSwitch) {
2150 OS << " switch (A) {\n";
2151 OS << " default:\n";
2152 OS << " return false;\n";
2153 EmittedSwitch = true;
2156 OS << "\n case " << A.Name << ":\n";
2158 if (SuperClasses.size() == 1) {
2159 OS << " return B == " << SuperClasses.back() << ";\n";
2163 if (!SuperClasses.empty()) {
2164 OS << " switch (B) {\n";
2165 OS << " default: return false;\n";
2166 for (StringRef SC : SuperClasses)
2167 OS << " case " << SC << ": return true;\n";
2170 // No case statement to emit
2171 OS << " return false;\n";
2175 // If there were case statements emitted into the string stream write the
2180 OS << " return false;\n";
2185 /// emitMatchTokenString - Emit the function to match a token string to the
2186 /// appropriate match class value.
2187 static void emitMatchTokenString(CodeGenTarget &Target,
2188 std::forward_list<ClassInfo> &Infos,
2190 // Construct the match list.
2191 std::vector<StringMatcher::StringPair> Matches;
2192 for (const auto &CI : Infos) {
2193 if (CI.Kind == ClassInfo::Token)
2194 Matches.emplace_back(CI.ValueName, "return " + CI.Name + ";");
2197 OS << "static MatchClassKind matchTokenString(StringRef Name) {\n";
2199 StringMatcher("Name", Matches, OS).Emit();
2201 OS << " return InvalidMatchClass;\n";
2205 /// emitMatchRegisterName - Emit the function to match a string to the target
2206 /// specific register enum.
2207 static void emitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
2209 // Construct the match list.
2210 std::vector<StringMatcher::StringPair> Matches;
2211 const auto &Regs = Target.getRegBank().getRegisters();
2212 for (const CodeGenRegister &Reg : Regs) {
2213 if (Reg.TheDef->getValueAsString("AsmName").empty())
2216 Matches.emplace_back(Reg.TheDef->getValueAsString("AsmName"),
2217 "return " + utostr(Reg.EnumValue) + ";");
2220 OS << "static unsigned MatchRegisterName(StringRef Name) {\n";
2222 StringMatcher("Name", Matches, OS).Emit();
2224 OS << " return 0;\n";
2228 static const char *getMinimalTypeForRange(uint64_t Range) {
2229 assert(Range <= 0xFFFFFFFFFFFFFFFFULL && "Enum too large");
2230 if (Range > 0xFFFFFFFFULL)
2239 static const char *getMinimalRequiredFeaturesType(const AsmMatcherInfo &Info) {
2240 uint64_t MaxIndex = Info.SubtargetFeatures.size();
2243 return getMinimalTypeForRange(1ULL << MaxIndex);
2246 /// emitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag
2248 static void emitSubtargetFeatureFlagEnumeration(AsmMatcherInfo &Info,
2250 OS << "// Flags for subtarget features that participate in "
2251 << "instruction matching.\n";
2252 OS << "enum SubtargetFeatureFlag : " << getMinimalRequiredFeaturesType(Info)
2254 for (const auto &SF : Info.SubtargetFeatures) {
2255 const SubtargetFeatureInfo &SFI = SF.second;
2256 OS << " " << SFI.getEnumName() << " = (1ULL << " << SFI.Index << "),\n";
2258 OS << " Feature_None = 0\n";
2262 /// emitOperandDiagnosticTypes - Emit the operand matching diagnostic types.
2263 static void emitOperandDiagnosticTypes(AsmMatcherInfo &Info, raw_ostream &OS) {
2264 // Get the set of diagnostic types from all of the operand classes.
2265 std::set<StringRef> Types;
2266 for (const auto &OpClassEntry : Info.AsmOperandClasses) {
2267 if (!OpClassEntry.second->DiagnosticType.empty())
2268 Types.insert(OpClassEntry.second->DiagnosticType);
2271 if (Types.empty()) return;
2273 // Now emit the enum entries.
2274 for (StringRef Type : Types)
2275 OS << " Match_" << Type << ",\n";
2276 OS << " END_OPERAND_DIAGNOSTIC_TYPES\n";
2279 /// emitGetSubtargetFeatureName - Emit the helper function to get the
2280 /// user-level name for a subtarget feature.
2281 static void emitGetSubtargetFeatureName(AsmMatcherInfo &Info, raw_ostream &OS) {
2282 OS << "// User-level names for subtarget features that participate in\n"
2283 << "// instruction matching.\n"
2284 << "static const char *getSubtargetFeatureName(uint64_t Val) {\n";
2285 if (!Info.SubtargetFeatures.empty()) {
2286 OS << " switch(Val) {\n";
2287 for (const auto &SF : Info.SubtargetFeatures) {
2288 const SubtargetFeatureInfo &SFI = SF.second;
2289 // FIXME: Totally just a placeholder name to get the algorithm working.
2290 OS << " case " << SFI.getEnumName() << ": return \""
2291 << SFI.TheDef->getValueAsString("PredicateName") << "\";\n";
2293 OS << " default: return \"(unknown)\";\n";
2296 // Nothing to emit, so skip the switch
2297 OS << " return \"(unknown)\";\n";
2302 /// emitComputeAvailableFeatures - Emit the function to compute the list of
2303 /// available features given a subtarget.
2304 static void emitComputeAvailableFeatures(AsmMatcherInfo &Info,
2306 std::string ClassName =
2307 Info.AsmParser->getValueAsString("AsmParserClassName");
2309 OS << "uint64_t " << Info.Target.getName() << ClassName << "::\n"
2310 << "ComputeAvailableFeatures(const FeatureBitset& FB) const {\n";
2311 OS << " uint64_t Features = 0;\n";
2312 for (const auto &SF : Info.SubtargetFeatures) {
2313 const SubtargetFeatureInfo &SFI = SF.second;
2316 std::string CondStorage =
2317 SFI.TheDef->getValueAsString("AssemblerCondString");
2318 StringRef Conds = CondStorage;
2319 std::pair<StringRef,StringRef> Comma = Conds.split(',');
2326 StringRef Cond = Comma.first;
2327 if (Cond[0] == '!') {
2329 Cond = Cond.substr(1);
2335 OS << "FB[" << Info.Target.getName() << "::" << Cond << "])";
2337 if (Comma.second.empty())
2341 Comma = Comma.second.split(',');
2345 OS << " Features |= " << SFI.getEnumName() << ";\n";
2347 OS << " return Features;\n";
2351 static std::string GetAliasRequiredFeatures(Record *R,
2352 const AsmMatcherInfo &Info) {
2353 std::vector<Record*> ReqFeatures = R->getValueAsListOfDefs("Predicates");
2355 unsigned NumFeatures = 0;
2356 for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) {
2357 const SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]);
2360 PrintFatalError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() +
2361 "' is not marked as an AssemblerPredicate!");
2366 Result += F->getEnumName();
2370 if (NumFeatures > 1)
2371 Result = '(' + Result + ')';
2375 static void emitMnemonicAliasVariant(raw_ostream &OS,const AsmMatcherInfo &Info,
2376 std::vector<Record*> &Aliases,
2377 unsigned Indent = 0,
2378 StringRef AsmParserVariantName = StringRef()){
2379 // Keep track of all the aliases from a mnemonic. Use an std::map so that the
2380 // iteration order of the map is stable.
2381 std::map<std::string, std::vector<Record*> > AliasesFromMnemonic;
2383 for (Record *R : Aliases) {
2384 // FIXME: Allow AssemblerVariantName to be a comma separated list.
2385 std::string AsmVariantName = R->getValueAsString("AsmVariantName");
2386 if (AsmVariantName != AsmParserVariantName)
2388 AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R);
2390 if (AliasesFromMnemonic.empty())
2393 // Process each alias a "from" mnemonic at a time, building the code executed
2394 // by the string remapper.
2395 std::vector<StringMatcher::StringPair> Cases;
2396 for (const auto &AliasEntry : AliasesFromMnemonic) {
2397 const std::vector<Record*> &ToVec = AliasEntry.second;
2399 // Loop through each alias and emit code that handles each case. If there
2400 // are two instructions without predicates, emit an error. If there is one,
2402 std::string MatchCode;
2403 int AliasWithNoPredicate = -1;
2405 for (unsigned i = 0, e = ToVec.size(); i != e; ++i) {
2406 Record *R = ToVec[i];
2407 std::string FeatureMask = GetAliasRequiredFeatures(R, Info);
2409 // If this unconditionally matches, remember it for later and diagnose
2411 if (FeatureMask.empty()) {
2412 if (AliasWithNoPredicate != -1) {
2413 // We can't have two aliases from the same mnemonic with no predicate.
2414 PrintError(ToVec[AliasWithNoPredicate]->getLoc(),
2415 "two MnemonicAliases with the same 'from' mnemonic!");
2416 PrintFatalError(R->getLoc(), "this is the other MnemonicAlias.");
2419 AliasWithNoPredicate = i;
2422 if (R->getValueAsString("ToMnemonic") == AliasEntry.first)
2423 PrintFatalError(R->getLoc(), "MnemonicAlias to the same string");
2425 if (!MatchCode.empty())
2426 MatchCode += "else ";
2427 MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n";
2428 MatchCode += " Mnemonic = \"" +R->getValueAsString("ToMnemonic")+"\";\n";
2431 if (AliasWithNoPredicate != -1) {
2432 Record *R = ToVec[AliasWithNoPredicate];
2433 if (!MatchCode.empty())
2434 MatchCode += "else\n ";
2435 MatchCode += "Mnemonic = \"" + R->getValueAsString("ToMnemonic")+"\";\n";
2438 MatchCode += "return;";
2440 Cases.push_back(std::make_pair(AliasEntry.first, MatchCode));
2442 StringMatcher("Mnemonic", Cases, OS).Emit(Indent);
2445 /// emitMnemonicAliases - If the target has any MnemonicAlias<> definitions,
2446 /// emit a function for them and return true, otherwise return false.
2447 static bool emitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info,
2448 CodeGenTarget &Target) {
2449 // Ignore aliases when match-prefix is set.
2450 if (!MatchPrefix.empty())
2453 std::vector<Record*> Aliases =
2454 Info.getRecords().getAllDerivedDefinitions("MnemonicAlias");
2455 if (Aliases.empty()) return false;
2457 OS << "static void applyMnemonicAliases(StringRef &Mnemonic, "
2458 "uint64_t Features, unsigned VariantID) {\n";
2459 OS << " switch (VariantID) {\n";
2460 unsigned VariantCount = Target.getAsmParserVariantCount();
2461 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2462 Record *AsmVariant = Target.getAsmParserVariant(VC);
2463 int AsmParserVariantNo = AsmVariant->getValueAsInt("Variant");
2464 std::string AsmParserVariantName = AsmVariant->getValueAsString("Name");
2465 OS << " case " << AsmParserVariantNo << ":\n";
2466 emitMnemonicAliasVariant(OS, Info, Aliases, /*Indent=*/2,
2467 AsmParserVariantName);
2472 // Emit aliases that apply to all variants.
2473 emitMnemonicAliasVariant(OS, Info, Aliases);
2480 static void emitCustomOperandParsing(raw_ostream &OS, CodeGenTarget &Target,
2481 const AsmMatcherInfo &Info, StringRef ClassName,
2482 StringToOffsetTable &StringTable,
2483 unsigned MaxMnemonicIndex, bool HasMnemonicFirst) {
2484 unsigned MaxMask = 0;
2485 for (const OperandMatchEntry &OMI : Info.OperandMatchInfo) {
2486 MaxMask |= OMI.OperandMask;
2489 // Emit the static custom operand parsing table;
2490 OS << "namespace {\n";
2491 OS << " struct OperandMatchEntry {\n";
2492 OS << " " << getMinimalRequiredFeaturesType(Info)
2493 << " RequiredFeatures;\n";
2494 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex)
2496 OS << " " << getMinimalTypeForRange(std::distance(
2497 Info.Classes.begin(), Info.Classes.end())) << " Class;\n";
2498 OS << " " << getMinimalTypeForRange(MaxMask)
2499 << " OperandMask;\n\n";
2500 OS << " StringRef getMnemonic() const {\n";
2501 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2502 OS << " MnemonicTable[Mnemonic]);\n";
2506 OS << " // Predicate for searching for an opcode.\n";
2507 OS << " struct LessOpcodeOperand {\n";
2508 OS << " bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {\n";
2509 OS << " return LHS.getMnemonic() < RHS;\n";
2511 OS << " bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {\n";
2512 OS << " return LHS < RHS.getMnemonic();\n";
2514 OS << " bool operator()(const OperandMatchEntry &LHS,";
2515 OS << " const OperandMatchEntry &RHS) {\n";
2516 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2520 OS << "} // end anonymous namespace.\n\n";
2522 OS << "static const OperandMatchEntry OperandMatchTable["
2523 << Info.OperandMatchInfo.size() << "] = {\n";
2525 OS << " /* Operand List Mask, Mnemonic, Operand Class, Features */\n";
2526 for (const OperandMatchEntry &OMI : Info.OperandMatchInfo) {
2527 const MatchableInfo &II = *OMI.MI;
2531 // Write the required features mask.
2532 if (!II.RequiredFeatures.empty()) {
2533 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
2535 OS << II.RequiredFeatures[i]->getEnumName();
2540 // Store a pascal-style length byte in the mnemonic.
2541 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2542 OS << ", " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2543 << " /* " << II.Mnemonic << " */, ";
2547 OS << ", " << OMI.OperandMask;
2549 bool printComma = false;
2550 for (int i = 0, e = 31; i !=e; ++i)
2551 if (OMI.OperandMask & (1 << i)) {
2563 // Emit the operand class switch to call the correct custom parser for
2564 // the found operand class.
2565 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
2566 << Target.getName() << ClassName << "::\n"
2567 << "tryCustomParseOperand(OperandVector"
2568 << " &Operands,\n unsigned MCK) {\n\n"
2569 << " switch(MCK) {\n";
2571 for (const auto &CI : Info.Classes) {
2572 if (CI.ParserMethod.empty())
2574 OS << " case " << CI.Name << ":\n"
2575 << " return " << CI.ParserMethod << "(Operands);\n";
2578 OS << " default:\n";
2579 OS << " return MatchOperand_NoMatch;\n";
2581 OS << " return MatchOperand_NoMatch;\n";
2584 // Emit the static custom operand parser. This code is very similar with
2585 // the other matcher. Also use MatchResultTy here just in case we go for
2586 // a better error handling.
2587 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
2588 << Target.getName() << ClassName << "::\n"
2589 << "MatchOperandParserImpl(OperandVector"
2590 << " &Operands,\n StringRef Mnemonic) {\n";
2592 // Emit code to get the available features.
2593 OS << " // Get the current feature set.\n";
2594 OS << " uint64_t AvailableFeatures = getAvailableFeatures();\n\n";
2596 OS << " // Get the next operand index.\n";
2597 OS << " unsigned NextOpNum = Operands.size()"
2598 << (HasMnemonicFirst ? " - 1" : "") << ";\n";
2600 // Emit code to search the table.
2601 OS << " // Search the table.\n";
2602 if (HasMnemonicFirst) {
2603 OS << " auto MnemonicRange =\n";
2604 OS << " std::equal_range(std::begin(OperandMatchTable), "
2605 "std::end(OperandMatchTable),\n";
2606 OS << " Mnemonic, LessOpcodeOperand());\n\n";
2608 OS << " auto MnemonicRange = std::make_pair(std::begin(OperandMatchTable),"
2609 " std::end(OperandMatchTable));\n";
2610 OS << " if (!Mnemonic.empty())\n";
2611 OS << " MnemonicRange =\n";
2612 OS << " std::equal_range(std::begin(OperandMatchTable), "
2613 "std::end(OperandMatchTable),\n";
2614 OS << " Mnemonic, LessOpcodeOperand());\n\n";
2617 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2618 OS << " return MatchOperand_NoMatch;\n\n";
2620 OS << " for (const OperandMatchEntry *it = MnemonicRange.first,\n"
2621 << " *ie = MnemonicRange.second; it != ie; ++it) {\n";
2623 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2624 OS << " assert(Mnemonic == it->getMnemonic());\n\n";
2626 // Emit check that the required features are available.
2627 OS << " // check if the available features match\n";
2628 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2629 << "!= it->RequiredFeatures) {\n";
2630 OS << " continue;\n";
2633 // Emit check to ensure the operand number matches.
2634 OS << " // check if the operand in question has a custom parser.\n";
2635 OS << " if (!(it->OperandMask & (1 << NextOpNum)))\n";
2636 OS << " continue;\n\n";
2638 // Emit call to the custom parser method
2639 OS << " // call custom parse method to handle the operand\n";
2640 OS << " OperandMatchResultTy Result = ";
2641 OS << "tryCustomParseOperand(Operands, it->Class);\n";
2642 OS << " if (Result != MatchOperand_NoMatch)\n";
2643 OS << " return Result;\n";
2646 OS << " // Okay, we had no match.\n";
2647 OS << " return MatchOperand_NoMatch;\n";
2651 void AsmMatcherEmitter::run(raw_ostream &OS) {
2652 CodeGenTarget Target(Records);
2653 Record *AsmParser = Target.getAsmParser();
2654 std::string ClassName = AsmParser->getValueAsString("AsmParserClassName");
2656 // Compute the information on the instructions to match.
2657 AsmMatcherInfo Info(AsmParser, Target, Records);
2660 // Sort the instruction table using the partial order on classes. We use
2661 // stable_sort to ensure that ambiguous instructions are still
2662 // deterministically ordered.
2663 std::stable_sort(Info.Matchables.begin(), Info.Matchables.end(),
2664 [](const std::unique_ptr<MatchableInfo> &a,
2665 const std::unique_ptr<MatchableInfo> &b){
2668 DEBUG_WITH_TYPE("instruction_info", {
2669 for (const auto &MI : Info.Matchables)
2673 // Check for ambiguous matchables.
2674 DEBUG_WITH_TYPE("ambiguous_instrs", {
2675 unsigned NumAmbiguous = 0;
2676 for (auto I = Info.Matchables.begin(), E = Info.Matchables.end(); I != E;
2678 for (auto J = std::next(I); J != E; ++J) {
2679 const MatchableInfo &A = **I;
2680 const MatchableInfo &B = **J;
2682 if (A.couldMatchAmbiguouslyWith(B)) {
2683 errs() << "warning: ambiguous matchables:\n";
2685 errs() << "\nis incomparable with:\n";
2693 errs() << "warning: " << NumAmbiguous
2694 << " ambiguous matchables!\n";
2697 // Compute the information on the custom operand parsing.
2698 Info.buildOperandMatchInfo();
2700 bool HasMnemonicFirst = AsmParser->getValueAsBit("HasMnemonicFirst");
2702 // Write the output.
2704 // Information for the class declaration.
2705 OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
2706 OS << "#undef GET_ASSEMBLER_HEADER\n";
2707 OS << " // This should be included into the middle of the declaration of\n";
2708 OS << " // your subclasses implementation of MCTargetAsmParser.\n";
2709 OS << " uint64_t ComputeAvailableFeatures(const FeatureBitset& FB) const;\n";
2710 OS << " void convertToMCInst(unsigned Kind, MCInst &Inst, "
2711 << "unsigned Opcode,\n"
2712 << " const OperandVector "
2714 OS << " void convertToMapAndConstraints(unsigned Kind,\n ";
2715 OS << " const OperandVector &Operands) override;\n";
2716 if (HasMnemonicFirst)
2717 OS << " bool mnemonicIsValid(StringRef Mnemonic, unsigned VariantID);\n";
2718 OS << " unsigned MatchInstructionImpl(const OperandVector &Operands,\n"
2719 << " MCInst &Inst,\n"
2720 << " uint64_t &ErrorInfo,"
2721 << " bool matchingInlineAsm,\n"
2722 << " unsigned VariantID = 0);\n";
2724 if (!Info.OperandMatchInfo.empty()) {
2725 OS << "\n enum OperandMatchResultTy {\n";
2726 OS << " MatchOperand_Success, // operand matched successfully\n";
2727 OS << " MatchOperand_NoMatch, // operand did not match\n";
2728 OS << " MatchOperand_ParseFail // operand matched but had errors\n";
2730 OS << " OperandMatchResultTy MatchOperandParserImpl(\n";
2731 OS << " OperandVector &Operands,\n";
2732 OS << " StringRef Mnemonic);\n";
2734 OS << " OperandMatchResultTy tryCustomParseOperand(\n";
2735 OS << " OperandVector &Operands,\n";
2736 OS << " unsigned MCK);\n\n";
2739 OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n";
2741 // Emit the operand match diagnostic enum names.
2742 OS << "\n#ifdef GET_OPERAND_DIAGNOSTIC_TYPES\n";
2743 OS << "#undef GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
2744 emitOperandDiagnosticTypes(Info, OS);
2745 OS << "#endif // GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
2748 OS << "\n#ifdef GET_REGISTER_MATCHER\n";
2749 OS << "#undef GET_REGISTER_MATCHER\n\n";
2751 // Emit the subtarget feature enumeration.
2752 emitSubtargetFeatureFlagEnumeration(Info, OS);
2754 // Emit the function to match a register name to number.
2755 // This should be omitted for Mips target
2756 if (AsmParser->getValueAsBit("ShouldEmitMatchRegisterName"))
2757 emitMatchRegisterName(Target, AsmParser, OS);
2759 OS << "#endif // GET_REGISTER_MATCHER\n\n";
2761 OS << "\n#ifdef GET_SUBTARGET_FEATURE_NAME\n";
2762 OS << "#undef GET_SUBTARGET_FEATURE_NAME\n\n";
2764 // Generate the helper function to get the names for subtarget features.
2765 emitGetSubtargetFeatureName(Info, OS);
2767 OS << "#endif // GET_SUBTARGET_FEATURE_NAME\n\n";
2769 OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
2770 OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
2772 // Generate the function that remaps for mnemonic aliases.
2773 bool HasMnemonicAliases = emitMnemonicAliases(OS, Info, Target);
2775 // Generate the convertToMCInst function to convert operands into an MCInst.
2776 // Also, generate the convertToMapAndConstraints function for MS-style inline
2777 // assembly. The latter doesn't actually generate a MCInst.
2778 emitConvertFuncs(Target, ClassName, Info.Matchables, HasMnemonicFirst, OS);
2780 // Emit the enumeration for classes which participate in matching.
2781 emitMatchClassEnumeration(Target, Info.Classes, OS);
2783 // Emit the routine to match token strings to their match class.
2784 emitMatchTokenString(Target, Info.Classes, OS);
2786 // Emit the subclass predicate routine.
2787 emitIsSubclass(Target, Info.Classes, OS);
2789 // Emit the routine to validate an operand against a match class.
2790 emitValidateOperandClass(Info, OS);
2792 // Emit the available features compute function.
2793 emitComputeAvailableFeatures(Info, OS);
2796 StringToOffsetTable StringTable;
2798 size_t MaxNumOperands = 0;
2799 unsigned MaxMnemonicIndex = 0;
2800 bool HasDeprecation = false;
2801 for (const auto &MI : Info.Matchables) {
2802 MaxNumOperands = std::max(MaxNumOperands, MI->AsmOperands.size());
2803 HasDeprecation |= MI->HasDeprecation;
2805 // Store a pascal-style length byte in the mnemonic.
2806 std::string LenMnemonic = char(MI->Mnemonic.size()) + MI->Mnemonic.str();
2807 MaxMnemonicIndex = std::max(MaxMnemonicIndex,
2808 StringTable.GetOrAddStringOffset(LenMnemonic, false));
2811 OS << "static const char *const MnemonicTable =\n";
2812 StringTable.EmitString(OS);
2815 // Emit the static match table; unused classes get initalized to 0 which is
2816 // guaranteed to be InvalidMatchClass.
2818 // FIXME: We can reduce the size of this table very easily. First, we change
2819 // it so that store the kinds in separate bit-fields for each index, which
2820 // only needs to be the max width used for classes at that index (we also need
2821 // to reject based on this during classification). If we then make sure to
2822 // order the match kinds appropriately (putting mnemonics last), then we
2823 // should only end up using a few bits for each class, especially the ones
2824 // following the mnemonic.
2825 OS << "namespace {\n";
2826 OS << " struct MatchEntry {\n";
2827 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex)
2829 OS << " uint16_t Opcode;\n";
2830 OS << " " << getMinimalTypeForRange(Info.Matchables.size())
2832 OS << " " << getMinimalRequiredFeaturesType(Info)
2833 << " RequiredFeatures;\n";
2834 OS << " " << getMinimalTypeForRange(
2835 std::distance(Info.Classes.begin(), Info.Classes.end()))
2836 << " Classes[" << MaxNumOperands << "];\n";
2837 OS << " StringRef getMnemonic() const {\n";
2838 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2839 OS << " MnemonicTable[Mnemonic]);\n";
2843 OS << " // Predicate for searching for an opcode.\n";
2844 OS << " struct LessOpcode {\n";
2845 OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n";
2846 OS << " return LHS.getMnemonic() < RHS;\n";
2848 OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n";
2849 OS << " return LHS < RHS.getMnemonic();\n";
2851 OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n";
2852 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2856 OS << "} // end anonymous namespace.\n\n";
2858 unsigned VariantCount = Target.getAsmParserVariantCount();
2859 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2860 Record *AsmVariant = Target.getAsmParserVariant(VC);
2861 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2863 OS << "static const MatchEntry MatchTable" << VC << "[] = {\n";
2865 for (const auto &MI : Info.Matchables) {
2866 if (MI->AsmVariantID != AsmVariantNo)
2869 // Store a pascal-style length byte in the mnemonic.
2870 std::string LenMnemonic = char(MI->Mnemonic.size()) + MI->Mnemonic.str();
2871 OS << " { " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2872 << " /* " << MI->Mnemonic << " */, "
2873 << Target.getName() << "::"
2874 << MI->getResultInst()->TheDef->getName() << ", "
2875 << MI->ConversionFnKind << ", ";
2877 // Write the required features mask.
2878 if (!MI->RequiredFeatures.empty()) {
2879 for (unsigned i = 0, e = MI->RequiredFeatures.size(); i != e; ++i) {
2881 OS << MI->RequiredFeatures[i]->getEnumName();
2887 for (unsigned i = 0, e = MI->AsmOperands.size(); i != e; ++i) {
2888 const MatchableInfo::AsmOperand &Op = MI->AsmOperands[i];
2891 OS << Op.Class->Name;
2899 // A method to determine if a mnemonic is in the list.
2900 if (HasMnemonicFirst) {
2901 OS << "bool " << Target.getName() << ClassName << "::\n"
2902 << "mnemonicIsValid(StringRef Mnemonic, unsigned VariantID) {\n";
2903 OS << " // Find the appropriate table for this asm variant.\n";
2904 OS << " const MatchEntry *Start, *End;\n";
2905 OS << " switch (VariantID) {\n";
2906 OS << " default: llvm_unreachable(\"invalid variant!\");\n";
2907 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2908 Record *AsmVariant = Target.getAsmParserVariant(VC);
2909 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2910 OS << " case " << AsmVariantNo << ": Start = std::begin(MatchTable" << VC
2911 << "); End = std::end(MatchTable" << VC << "); break;\n";
2914 OS << " // Search the table.\n";
2915 OS << " auto MnemonicRange = ";
2916 OS << "std::equal_range(Start, End, Mnemonic, LessOpcode());\n";
2917 OS << " return MnemonicRange.first != MnemonicRange.second;\n";
2921 // Finally, build the match function.
2922 OS << "unsigned " << Target.getName() << ClassName << "::\n"
2923 << "MatchInstructionImpl(const OperandVector &Operands,\n";
2924 OS << " MCInst &Inst, uint64_t &ErrorInfo,\n"
2925 << " bool matchingInlineAsm, unsigned VariantID) {\n";
2927 OS << " // Eliminate obvious mismatches.\n";
2928 OS << " if (Operands.size() > "
2929 << (MaxNumOperands + HasMnemonicFirst) << ") {\n";
2930 OS << " ErrorInfo = "
2931 << (MaxNumOperands + HasMnemonicFirst) << ";\n";
2932 OS << " return Match_InvalidOperand;\n";
2935 // Emit code to get the available features.
2936 OS << " // Get the current feature set.\n";
2937 OS << " uint64_t AvailableFeatures = getAvailableFeatures();\n\n";
2939 OS << " // Get the instruction mnemonic, which is the first token.\n";
2940 if (HasMnemonicFirst) {
2941 OS << " StringRef Mnemonic = ((" << Target.getName()
2942 << "Operand&)*Operands[0]).getToken();\n\n";
2944 OS << " StringRef Mnemonic;\n";
2945 OS << " if (Operands[0]->isToken())\n";
2946 OS << " Mnemonic = ((" << Target.getName()
2947 << "Operand&)*Operands[0]).getToken();\n\n";
2950 if (HasMnemonicAliases) {
2951 OS << " // Process all MnemonicAliases to remap the mnemonic.\n";
2952 OS << " applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);\n\n";
2955 // Emit code to compute the class list for this operand vector.
2956 OS << " // Some state to try to produce better error messages.\n";
2957 OS << " bool HadMatchOtherThanFeatures = false;\n";
2958 OS << " bool HadMatchOtherThanPredicate = false;\n";
2959 OS << " unsigned RetCode = Match_InvalidOperand;\n";
2960 OS << " uint64_t MissingFeatures = ~0ULL;\n";
2961 OS << " // Set ErrorInfo to the operand that mismatches if it is\n";
2962 OS << " // wrong for all instances of the instruction.\n";
2963 OS << " ErrorInfo = ~0ULL;\n";
2965 // Emit code to search the table.
2966 OS << " // Find the appropriate table for this asm variant.\n";
2967 OS << " const MatchEntry *Start, *End;\n";
2968 OS << " switch (VariantID) {\n";
2969 OS << " default: llvm_unreachable(\"invalid variant!\");\n";
2970 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2971 Record *AsmVariant = Target.getAsmParserVariant(VC);
2972 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2973 OS << " case " << AsmVariantNo << ": Start = std::begin(MatchTable" << VC
2974 << "); End = std::end(MatchTable" << VC << "); break;\n";
2978 OS << " // Search the table.\n";
2979 if (HasMnemonicFirst) {
2980 OS << " auto MnemonicRange = "
2981 "std::equal_range(Start, End, Mnemonic, LessOpcode());\n\n";
2983 OS << " auto MnemonicRange = std::make_pair(Start, End);\n";
2984 OS << " unsigned SIndex = Mnemonic.empty() ? 0 : 1;\n";
2985 OS << " if (!Mnemonic.empty())\n";
2986 OS << " MnemonicRange = "
2987 "std::equal_range(Start, End, Mnemonic.lower(), LessOpcode());\n\n";
2990 OS << " // Return a more specific error code if no mnemonics match.\n";
2991 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2992 OS << " return Match_MnemonicFail;\n\n";
2994 OS << " for (const MatchEntry *it = MnemonicRange.first, "
2995 << "*ie = MnemonicRange.second;\n";
2996 OS << " it != ie; ++it) {\n";
2998 if (HasMnemonicFirst) {
2999 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
3000 OS << " assert(Mnemonic == it->getMnemonic());\n";
3003 // Emit check that the subclasses match.
3004 OS << " bool OperandsValid = true;\n";
3005 OS << " for (unsigned i = " << (HasMnemonicFirst ? "0" : "SIndex")
3006 << "; i != " << MaxNumOperands << "; ++i) {\n";
3007 OS << " auto Formal = static_cast<MatchClassKind>(it->Classes[i]);\n";
3008 OS << " if (i" << (HasMnemonicFirst ? "+1" : "")
3009 << " >= Operands.size()) {\n";
3010 OS << " OperandsValid = (Formal == " <<"InvalidMatchClass);\n";
3011 OS << " if (!OperandsValid) ErrorInfo = i"
3012 << (HasMnemonicFirst ? "+1" : "") << ";\n";
3015 OS << " MCParsedAsmOperand &Actual = *Operands[i"
3016 << (HasMnemonicFirst ? "+1" : "") << "];\n";
3017 OS << " unsigned Diag = validateOperandClass(Actual, Formal);\n";
3018 OS << " if (Diag == Match_Success)\n";
3019 OS << " continue;\n";
3020 OS << " // If the generic handler indicates an invalid operand\n";
3021 OS << " // failure, check for a special case.\n";
3022 OS << " if (Diag == Match_InvalidOperand) {\n";
3023 OS << " Diag = validateTargetOperandClass(Actual, Formal);\n";
3024 OS << " if (Diag == Match_Success)\n";
3025 OS << " continue;\n";
3027 OS << " // If this operand is broken for all of the instances of this\n";
3028 OS << " // mnemonic, keep track of it so we can report loc info.\n";
3029 OS << " // If we already had a match that only failed due to a\n";
3030 OS << " // target predicate, that diagnostic is preferred.\n";
3031 OS << " if (!HadMatchOtherThanPredicate &&\n";
3032 OS << " (it == MnemonicRange.first || ErrorInfo <= i"
3033 << (HasMnemonicFirst ? "+1" : "") << ")) {\n";
3034 OS << " ErrorInfo = i" << (HasMnemonicFirst ? "+1" : "") << ";\n";
3035 OS << " // InvalidOperand is the default. Prefer specificity.\n";
3036 OS << " if (Diag != Match_InvalidOperand)\n";
3037 OS << " RetCode = Diag;\n";
3039 OS << " // Otherwise, just reject this instance of the mnemonic.\n";
3040 OS << " OperandsValid = false;\n";
3044 OS << " if (!OperandsValid) continue;\n";
3046 // Emit check that the required features are available.
3047 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
3048 << "!= it->RequiredFeatures) {\n";
3049 OS << " HadMatchOtherThanFeatures = true;\n";
3050 OS << " uint64_t NewMissingFeatures = it->RequiredFeatures & "
3051 "~AvailableFeatures;\n";
3052 OS << " if (countPopulation(NewMissingFeatures) <=\n"
3053 " countPopulation(MissingFeatures))\n";
3054 OS << " MissingFeatures = NewMissingFeatures;\n";
3055 OS << " continue;\n";
3058 OS << " Inst.clear();\n\n";
3059 OS << " if (matchingInlineAsm) {\n";
3060 OS << " Inst.setOpcode(it->Opcode);\n";
3061 OS << " convertToMapAndConstraints(it->ConvertFn, Operands);\n";
3062 OS << " return Match_Success;\n";
3064 OS << " // We have selected a definite instruction, convert the parsed\n"
3065 << " // operands into the appropriate MCInst.\n";
3066 OS << " convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n";
3069 // Verify the instruction with the target-specific match predicate function.
3070 OS << " // We have a potential match. Check the target predicate to\n"
3071 << " // handle any context sensitive constraints.\n"
3072 << " unsigned MatchResult;\n"
3073 << " if ((MatchResult = checkTargetMatchPredicate(Inst)) !="
3074 << " Match_Success) {\n"
3075 << " Inst.clear();\n"
3076 << " RetCode = MatchResult;\n"
3077 << " HadMatchOtherThanPredicate = true;\n"
3081 // Call the post-processing function, if used.
3082 std::string InsnCleanupFn =
3083 AsmParser->getValueAsString("AsmParserInstCleanup");
3084 if (!InsnCleanupFn.empty())
3085 OS << " " << InsnCleanupFn << "(Inst);\n";
3087 if (HasDeprecation) {
3088 OS << " std::string Info;\n";
3089 OS << " if (MII.get(Inst.getOpcode()).getDeprecatedInfo(Inst, getSTI(), Info)) {\n";
3090 OS << " SMLoc Loc = ((" << Target.getName()
3091 << "Operand&)*Operands[0]).getStartLoc();\n";
3092 OS << " getParser().Warning(Loc, Info, None);\n";
3096 OS << " return Match_Success;\n";
3099 OS << " // Okay, we had no match. Try to return a useful error code.\n";
3100 OS << " if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)\n";
3101 OS << " return RetCode;\n\n";
3102 OS << " // Missing feature matches return which features were missing\n";
3103 OS << " ErrorInfo = MissingFeatures;\n";
3104 OS << " return Match_MissingFeature;\n";
3107 if (!Info.OperandMatchInfo.empty())
3108 emitCustomOperandParsing(OS, Target, Info, ClassName, StringTable,
3109 MaxMnemonicIndex, HasMnemonicFirst);
3111 OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";
3116 void EmitAsmMatcher(RecordKeeper &RK, raw_ostream &OS) {
3117 emitSourceFileHeader("Assembly Matcher Source Fragment", OS);
3118 AsmMatcherEmitter(RK).run(OS);
3121 } // End llvm namespace