1 //===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits a target specifier matcher for converting parsed
11 // assembly operands in the MCInst structures.
13 // The input to the target specific matcher is a list of literal tokens and
14 // operands. The target specific parser should generally eliminate any syntax
15 // which is not relevant for matching; for example, comma tokens should have
16 // already been consumed and eliminated by the parser. Most instructions will
17 // end up with a single literal token (the instruction name) and some number of
20 // Some example inputs, for X86:
21 // 'addl' (immediate ...) (register ...)
22 // 'add' (immediate ...) (memory ...)
25 // The assembly matcher is responsible for converting this input into a precise
26 // machine instruction (i.e., an instruction with a well defined encoding). This
27 // mapping has several properties which complicate matching:
29 // - It may be ambiguous; many architectures can legally encode particular
30 // variants of an instruction in different ways (for example, using a smaller
31 // encoding for small immediates). Such ambiguities should never be
32 // arbitrarily resolved by the assembler, the assembler is always responsible
33 // for choosing the "best" available instruction.
35 // - It may depend on the subtarget or the assembler context. Instructions
36 // which are invalid for the current mode, but otherwise unambiguous (e.g.,
37 // an SSE instruction in a file being assembled for i486) should be accepted
38 // and rejected by the assembler front end. However, if the proper encoding
39 // for an instruction is dependent on the assembler context then the matcher
40 // is responsible for selecting the correct machine instruction for the
43 // The core matching algorithm attempts to exploit the regularity in most
44 // instruction sets to quickly determine the set of possibly matching
45 // instructions, and the simplify the generated code. Additionally, this helps
46 // to ensure that the ambiguities are intentionally resolved by the user.
48 // The matching is divided into two distinct phases:
50 // 1. Classification: Each operand is mapped to the unique set which (a)
51 // contains it, and (b) is the largest such subset for which a single
52 // instruction could match all members.
54 // For register classes, we can generate these subgroups automatically. For
55 // arbitrary operands, we expect the user to define the classes and their
56 // relations to one another (for example, 8-bit signed immediates as a
57 // subset of 32-bit immediates).
59 // By partitioning the operands in this way, we guarantee that for any
60 // tuple of classes, any single instruction must match either all or none
61 // of the sets of operands which could classify to that tuple.
63 // In addition, the subset relation amongst classes induces a partial order
64 // on such tuples, which we use to resolve ambiguities.
66 // 2. The input can now be treated as a tuple of classes (static tokens are
67 // simple singleton sets). Each such tuple should generally map to a single
68 // instruction (we currently ignore cases where this isn't true, whee!!!),
69 // which we can emit a simple matcher for.
71 //===----------------------------------------------------------------------===//
73 #include "AsmMatcherEmitter.h"
74 #include "CodeGenTarget.h"
76 #include "StringMatcher.h"
77 #include "llvm/ADT/OwningPtr.h"
78 #include "llvm/ADT/PointerUnion.h"
79 #include "llvm/ADT/SmallPtrSet.h"
80 #include "llvm/ADT/SmallVector.h"
81 #include "llvm/ADT/STLExtras.h"
82 #include "llvm/ADT/StringExtras.h"
83 #include "llvm/Support/CommandLine.h"
84 #include "llvm/Support/Debug.h"
89 static cl::opt<std::string>
90 MatchPrefix("match-prefix", cl::init(""),
91 cl::desc("Only match instructions with the given prefix"));
95 struct SubtargetFeatureInfo;
97 /// ClassInfo - Helper class for storing the information about a particular
98 /// class of operands which can be matched.
101 /// Invalid kind, for use as a sentinel value.
104 /// The class for a particular token.
107 /// The (first) register class, subsequent register classes are
108 /// RegisterClass0+1, and so on.
111 /// The (first) user defined class, subsequent user defined classes are
112 /// UserClass0+1, and so on.
116 /// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
117 /// N) for the Nth user defined class.
120 /// SuperClasses - The super classes of this class. Note that for simplicities
121 /// sake user operands only record their immediate super class, while register
122 /// operands include all superclasses.
123 std::vector<ClassInfo*> SuperClasses;
125 /// Name - The full class name, suitable for use in an enum.
128 /// ClassName - The unadorned generic name for this class (e.g., Token).
129 std::string ClassName;
131 /// ValueName - The name of the value this class represents; for a token this
132 /// is the literal token string, for an operand it is the TableGen class (or
133 /// empty if this is a derived class).
134 std::string ValueName;
136 /// PredicateMethod - The name of the operand method to test whether the
137 /// operand matches this class; this is not valid for Token or register kinds.
138 std::string PredicateMethod;
140 /// RenderMethod - The name of the operand method to add this operand to an
141 /// MCInst; this is not valid for Token or register kinds.
142 std::string RenderMethod;
144 /// For register classes, the records for all the registers in this class.
145 std::set<Record*> Registers;
148 /// isRegisterClass() - Check if this is a register class.
149 bool isRegisterClass() const {
150 return Kind >= RegisterClass0 && Kind < UserClass0;
153 /// isUserClass() - Check if this is a user defined class.
154 bool isUserClass() const {
155 return Kind >= UserClass0;
158 /// isRelatedTo - Check whether this class is "related" to \arg RHS. Classes
159 /// are related if they are in the same class hierarchy.
160 bool isRelatedTo(const ClassInfo &RHS) const {
161 // Tokens are only related to tokens.
162 if (Kind == Token || RHS.Kind == Token)
163 return Kind == Token && RHS.Kind == Token;
165 // Registers classes are only related to registers classes, and only if
166 // their intersection is non-empty.
167 if (isRegisterClass() || RHS.isRegisterClass()) {
168 if (!isRegisterClass() || !RHS.isRegisterClass())
171 std::set<Record*> Tmp;
172 std::insert_iterator< std::set<Record*> > II(Tmp, Tmp.begin());
173 std::set_intersection(Registers.begin(), Registers.end(),
174 RHS.Registers.begin(), RHS.Registers.end(),
180 // Otherwise we have two users operands; they are related if they are in the
181 // same class hierarchy.
183 // FIXME: This is an oversimplification, they should only be related if they
184 // intersect, however we don't have that information.
185 assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");
186 const ClassInfo *Root = this;
187 while (!Root->SuperClasses.empty())
188 Root = Root->SuperClasses.front();
190 const ClassInfo *RHSRoot = &RHS;
191 while (!RHSRoot->SuperClasses.empty())
192 RHSRoot = RHSRoot->SuperClasses.front();
194 return Root == RHSRoot;
197 /// isSubsetOf - Test whether this class is a subset of \arg RHS;
198 bool isSubsetOf(const ClassInfo &RHS) const {
199 // This is a subset of RHS if it is the same class...
203 // ... or if any of its super classes are a subset of RHS.
204 for (std::vector<ClassInfo*>::const_iterator it = SuperClasses.begin(),
205 ie = SuperClasses.end(); it != ie; ++it)
206 if ((*it)->isSubsetOf(RHS))
212 /// operator< - Compare two classes.
213 bool operator<(const ClassInfo &RHS) const {
217 // Unrelated classes can be ordered by kind.
218 if (!isRelatedTo(RHS))
219 return Kind < RHS.Kind;
223 assert(0 && "Invalid kind!");
225 // Tokens are comparable by value.
227 // FIXME: Compare by enum value.
228 return ValueName < RHS.ValueName;
231 // This class preceeds the RHS if it is a proper subset of the RHS.
234 if (RHS.isSubsetOf(*this))
237 // Otherwise, order by name to ensure we have a total ordering.
238 return ValueName < RHS.ValueName;
243 /// MatchableInfo - Helper class for storing the necessary information for an
244 /// instruction or alias which is capable of being matched.
245 struct MatchableInfo {
247 /// Token - This is the token that the operand came from.
250 /// The unique class instance this operand should match.
253 /// The operand name this is, if anything.
256 /// The suboperand index within SrcOpName, or -1 for the entire operand.
259 explicit AsmOperand(StringRef T) : Token(T), Class(0), SubOpIdx(-1) {}
262 /// ResOperand - This represents a single operand in the result instruction
263 /// generated by the match. In cases (like addressing modes) where a single
264 /// assembler operand expands to multiple MCOperands, this represents the
265 /// single assembler operand, not the MCOperand.
268 /// RenderAsmOperand - This represents an operand result that is
269 /// generated by calling the render method on the assembly operand. The
270 /// corresponding AsmOperand is specified by AsmOperandNum.
273 /// TiedOperand - This represents a result operand that is a duplicate of
274 /// a previous result operand.
277 /// ImmOperand - This represents an immediate value that is dumped into
281 /// RegOperand - This represents a fixed register that is dumped in.
286 /// This is the operand # in the AsmOperands list that this should be
288 unsigned AsmOperandNum;
290 /// TiedOperandNum - This is the (earlier) result operand that should be
292 unsigned TiedOperandNum;
294 /// ImmVal - This is the immediate value added to the instruction.
297 /// Register - This is the register record.
301 /// MINumOperands - The number of MCInst operands populated by this
303 unsigned MINumOperands;
305 static ResOperand getRenderedOp(unsigned AsmOpNum, unsigned NumOperands) {
307 X.Kind = RenderAsmOperand;
308 X.AsmOperandNum = AsmOpNum;
309 X.MINumOperands = NumOperands;
313 static ResOperand getTiedOp(unsigned TiedOperandNum) {
315 X.Kind = TiedOperand;
316 X.TiedOperandNum = TiedOperandNum;
321 static ResOperand getImmOp(int64_t Val) {
329 static ResOperand getRegOp(Record *Reg) {
338 /// TheDef - This is the definition of the instruction or InstAlias that this
339 /// matchable came from.
340 Record *const TheDef;
342 /// DefRec - This is the definition that it came from.
343 PointerUnion<const CodeGenInstruction*, const CodeGenInstAlias*> DefRec;
345 const CodeGenInstruction *getResultInst() const {
346 if (DefRec.is<const CodeGenInstruction*>())
347 return DefRec.get<const CodeGenInstruction*>();
348 return DefRec.get<const CodeGenInstAlias*>()->ResultInst;
351 /// ResOperands - This is the operand list that should be built for the result
353 std::vector<ResOperand> ResOperands;
355 /// AsmString - The assembly string for this instruction (with variants
356 /// removed), e.g. "movsx $src, $dst".
357 std::string AsmString;
359 /// Mnemonic - This is the first token of the matched instruction, its
363 /// AsmOperands - The textual operands that this instruction matches,
364 /// annotated with a class and where in the OperandList they were defined.
365 /// This directly corresponds to the tokenized AsmString after the mnemonic is
367 SmallVector<AsmOperand, 4> AsmOperands;
369 /// Predicates - The required subtarget features to match this instruction.
370 SmallVector<SubtargetFeatureInfo*, 4> RequiredFeatures;
372 /// ConversionFnKind - The enum value which is passed to the generated
373 /// ConvertToMCInst to convert parsed operands into an MCInst for this
375 std::string ConversionFnKind;
377 MatchableInfo(const CodeGenInstruction &CGI)
378 : TheDef(CGI.TheDef), DefRec(&CGI), AsmString(CGI.AsmString) {
381 MatchableInfo(const CodeGenInstAlias *Alias)
382 : TheDef(Alias->TheDef), DefRec(Alias), AsmString(Alias->AsmString) {
385 void Initialize(const AsmMatcherInfo &Info,
386 SmallPtrSet<Record*, 16> &SingletonRegisters);
388 /// Validate - Return true if this matchable is a valid thing to match against
389 /// and perform a bunch of validity checking.
390 bool Validate(StringRef CommentDelimiter, bool Hack) const;
392 /// getSingletonRegisterForAsmOperand - If the specified token is a singleton
393 /// register, return the Record for it, otherwise return null.
394 Record *getSingletonRegisterForAsmOperand(unsigned i,
395 const AsmMatcherInfo &Info) const;
397 /// FindAsmOperand - Find the AsmOperand with the specified name and
398 /// suboperand index.
399 int FindAsmOperand(StringRef N, int SubOpIdx) const {
400 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
401 if (N == AsmOperands[i].SrcOpName &&
402 SubOpIdx == AsmOperands[i].SubOpIdx)
407 /// FindAsmOperandNamed - Find the first AsmOperand with the specified name.
408 /// This does not check the suboperand index.
409 int FindAsmOperandNamed(StringRef N) const {
410 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
411 if (N == AsmOperands[i].SrcOpName)
416 void BuildInstructionResultOperands();
417 void BuildAliasResultOperands();
419 /// operator< - Compare two matchables.
420 bool operator<(const MatchableInfo &RHS) const {
421 // The primary comparator is the instruction mnemonic.
422 if (Mnemonic != RHS.Mnemonic)
423 return Mnemonic < RHS.Mnemonic;
425 if (AsmOperands.size() != RHS.AsmOperands.size())
426 return AsmOperands.size() < RHS.AsmOperands.size();
428 // Compare lexicographically by operand. The matcher validates that other
429 // orderings wouldn't be ambiguous using \see CouldMatchAmbiguouslyWith().
430 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
431 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
433 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
440 /// CouldMatchAmbiguouslyWith - Check whether this matchable could
441 /// ambiguously match the same set of operands as \arg RHS (without being a
442 /// strictly superior match).
443 bool CouldMatchAmbiguouslyWith(const MatchableInfo &RHS) {
444 // The primary comparator is the instruction mnemonic.
445 if (Mnemonic != RHS.Mnemonic)
448 // The number of operands is unambiguous.
449 if (AsmOperands.size() != RHS.AsmOperands.size())
452 // Otherwise, make sure the ordering of the two instructions is unambiguous
453 // by checking that either (a) a token or operand kind discriminates them,
454 // or (b) the ordering among equivalent kinds is consistent.
456 // Tokens and operand kinds are unambiguous (assuming a correct target
458 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
459 if (AsmOperands[i].Class->Kind != RHS.AsmOperands[i].Class->Kind ||
460 AsmOperands[i].Class->Kind == ClassInfo::Token)
461 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class ||
462 *RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
465 // Otherwise, this operand could commute if all operands are equivalent, or
466 // there is a pair of operands that compare less than and a pair that
467 // compare greater than.
468 bool HasLT = false, HasGT = false;
469 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
470 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
472 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
476 return !(HasLT ^ HasGT);
482 void TokenizeAsmString(const AsmMatcherInfo &Info);
485 /// SubtargetFeatureInfo - Helper class for storing information on a subtarget
486 /// feature which participates in instruction matching.
487 struct SubtargetFeatureInfo {
488 /// \brief The predicate record for this feature.
491 /// \brief An unique index assigned to represent this feature.
494 SubtargetFeatureInfo(Record *D, unsigned Idx) : TheDef(D), Index(Idx) {}
496 /// \brief The name of the enumerated constant identifying this feature.
497 std::string getEnumName() const {
498 return "Feature_" + TheDef->getName();
502 class AsmMatcherInfo {
505 RecordKeeper &Records;
507 /// The tablegen AsmParser record.
510 /// Target - The target information.
511 CodeGenTarget &Target;
513 /// The AsmParser "RegisterPrefix" value.
514 std::string RegisterPrefix;
516 /// The classes which are needed for matching.
517 std::vector<ClassInfo*> Classes;
519 /// The information on the matchables to match.
520 std::vector<MatchableInfo*> Matchables;
522 /// Map of Register records to their class information.
523 std::map<Record*, ClassInfo*> RegisterClasses;
525 /// Map of Predicate records to their subtarget information.
526 std::map<Record*, SubtargetFeatureInfo*> SubtargetFeatures;
529 /// Map of token to class information which has already been constructed.
530 std::map<std::string, ClassInfo*> TokenClasses;
532 /// Map of RegisterClass records to their class information.
533 std::map<Record*, ClassInfo*> RegisterClassClasses;
535 /// Map of AsmOperandClass records to their class information.
536 std::map<Record*, ClassInfo*> AsmOperandClasses;
539 /// getTokenClass - Lookup or create the class for the given token.
540 ClassInfo *getTokenClass(StringRef Token);
542 /// getOperandClass - Lookup or create the class for the given operand.
543 ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI,
546 /// BuildRegisterClasses - Build the ClassInfo* instances for register
548 void BuildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters);
550 /// BuildOperandClasses - Build the ClassInfo* instances for user defined
552 void BuildOperandClasses();
554 void BuildInstructionOperandReference(MatchableInfo *II, StringRef OpName,
556 void BuildAliasOperandReference(MatchableInfo *II, StringRef OpName,
557 MatchableInfo::AsmOperand &Op);
560 AsmMatcherInfo(Record *AsmParser,
561 CodeGenTarget &Target,
562 RecordKeeper &Records);
564 /// BuildInfo - Construct the various tables used during matching.
567 /// getSubtargetFeature - Lookup or create the subtarget feature info for the
569 SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const {
570 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
571 std::map<Record*, SubtargetFeatureInfo*>::const_iterator I =
572 SubtargetFeatures.find(Def);
573 return I == SubtargetFeatures.end() ? 0 : I->second;
576 RecordKeeper &getRecords() const {
583 void MatchableInfo::dump() {
584 errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n";
586 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
587 AsmOperand &Op = AsmOperands[i];
588 errs() << " op[" << i << "] = " << Op.Class->ClassName << " - ";
589 errs() << '\"' << Op.Token << "\"\n";
593 void MatchableInfo::Initialize(const AsmMatcherInfo &Info,
594 SmallPtrSet<Record*, 16> &SingletonRegisters) {
595 // TODO: Eventually support asmparser for Variant != 0.
596 AsmString = CodeGenInstruction::FlattenAsmStringVariants(AsmString, 0);
598 TokenizeAsmString(Info);
600 // Compute the require features.
601 std::vector<Record*> Predicates =TheDef->getValueAsListOfDefs("Predicates");
602 for (unsigned i = 0, e = Predicates.size(); i != e; ++i)
603 if (SubtargetFeatureInfo *Feature =
604 Info.getSubtargetFeature(Predicates[i]))
605 RequiredFeatures.push_back(Feature);
607 // Collect singleton registers, if used.
608 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
609 if (Record *Reg = getSingletonRegisterForAsmOperand(i, Info))
610 SingletonRegisters.insert(Reg);
614 /// TokenizeAsmString - Tokenize a simplified assembly string.
615 void MatchableInfo::TokenizeAsmString(const AsmMatcherInfo &Info) {
616 StringRef String = AsmString;
619 for (unsigned i = 0, e = String.size(); i != e; ++i) {
629 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
632 if (!isspace(String[i]) && String[i] != ',')
633 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
639 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
643 assert(i != String.size() && "Invalid quoted character");
644 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
650 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
654 // If this isn't "${", treat like a normal token.
655 if (i + 1 == String.size() || String[i + 1] != '{') {
660 StringRef::iterator End = std::find(String.begin() + i, String.end(),'}');
661 assert(End != String.end() && "Missing brace in operand reference!");
662 size_t EndPos = End - String.begin();
663 AsmOperands.push_back(AsmOperand(String.slice(i, EndPos+1)));
671 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
680 if (InTok && Prev != String.size())
681 AsmOperands.push_back(AsmOperand(String.substr(Prev)));
683 // The first token of the instruction is the mnemonic, which must be a
684 // simple string, not a $foo variable or a singleton register.
685 assert(!AsmOperands.empty() && "Instruction has no tokens?");
686 Mnemonic = AsmOperands[0].Token;
687 if (Mnemonic[0] == '$' || getSingletonRegisterForAsmOperand(0, Info))
688 throw TGError(TheDef->getLoc(),
689 "Invalid instruction mnemonic '" + Mnemonic.str() + "'!");
691 // Remove the first operand, it is tracked in the mnemonic field.
692 AsmOperands.erase(AsmOperands.begin());
695 bool MatchableInfo::Validate(StringRef CommentDelimiter, bool Hack) const {
696 // Reject matchables with no .s string.
697 if (AsmString.empty())
698 throw TGError(TheDef->getLoc(), "instruction with empty asm string");
700 // Reject any matchables with a newline in them, they should be marked
701 // isCodeGenOnly if they are pseudo instructions.
702 if (AsmString.find('\n') != std::string::npos)
703 throw TGError(TheDef->getLoc(),
704 "multiline instruction is not valid for the asmparser, "
705 "mark it isCodeGenOnly");
707 // Remove comments from the asm string. We know that the asmstring only
709 if (!CommentDelimiter.empty() &&
710 StringRef(AsmString).find(CommentDelimiter) != StringRef::npos)
711 throw TGError(TheDef->getLoc(),
712 "asmstring for instruction has comment character in it, "
713 "mark it isCodeGenOnly");
715 // Reject matchables with operand modifiers, these aren't something we can
716 // handle, the target should be refactored to use operands instead of
719 // Also, check for instructions which reference the operand multiple times;
720 // this implies a constraint we would not honor.
721 std::set<std::string> OperandNames;
722 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
723 StringRef Tok = AsmOperands[i].Token;
724 if (Tok[0] == '$' && Tok.find(':') != StringRef::npos)
725 throw TGError(TheDef->getLoc(),
726 "matchable with operand modifier '" + Tok.str() +
727 "' not supported by asm matcher. Mark isCodeGenOnly!");
729 // Verify that any operand is only mentioned once.
730 // We reject aliases and ignore instructions for now.
731 if (Tok[0] == '$' && !OperandNames.insert(Tok).second) {
733 throw TGError(TheDef->getLoc(),
734 "ERROR: matchable with tied operand '" + Tok.str() +
735 "' can never be matched!");
736 // FIXME: Should reject these. The ARM backend hits this with $lane in a
737 // bunch of instructions. It is unclear what the right answer is.
739 errs() << "warning: '" << TheDef->getName() << "': "
740 << "ignoring instruction with tied operand '"
741 << Tok.str() << "'\n";
750 /// getSingletonRegisterForAsmOperand - If the specified token is a singleton
751 /// register, return the register name, otherwise return a null StringRef.
752 Record *MatchableInfo::
753 getSingletonRegisterForAsmOperand(unsigned i, const AsmMatcherInfo &Info) const{
754 StringRef Tok = AsmOperands[i].Token;
755 if (!Tok.startswith(Info.RegisterPrefix))
758 StringRef RegName = Tok.substr(Info.RegisterPrefix.size());
759 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName))
762 // If there is no register prefix (i.e. "%" in "%eax"), then this may
763 // be some random non-register token, just ignore it.
764 if (Info.RegisterPrefix.empty())
767 // Otherwise, we have something invalid prefixed with the register prefix,
769 std::string Err = "unable to find register for '" + RegName.str() +
770 "' (which matches register prefix)";
771 throw TGError(TheDef->getLoc(), Err);
774 static std::string getEnumNameForToken(StringRef Str) {
777 for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) {
779 case '*': Res += "_STAR_"; break;
780 case '%': Res += "_PCT_"; break;
781 case ':': Res += "_COLON_"; break;
782 case '!': Res += "_EXCLAIM_"; break;
783 case '.': Res += "_DOT_"; break;
788 Res += "_" + utostr((unsigned) *it) + "_";
795 ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) {
796 ClassInfo *&Entry = TokenClasses[Token];
799 Entry = new ClassInfo();
800 Entry->Kind = ClassInfo::Token;
801 Entry->ClassName = "Token";
802 Entry->Name = "MCK_" + getEnumNameForToken(Token);
803 Entry->ValueName = Token;
804 Entry->PredicateMethod = "<invalid>";
805 Entry->RenderMethod = "<invalid>";
806 Classes.push_back(Entry);
813 AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI,
815 Record *Rec = OI.Rec;
817 Rec = dynamic_cast<DefInit*>(OI.MIOperandInfo->getArg(SubOpIdx))->getDef();
819 if (Rec->isSubClassOf("RegisterClass")) {
820 if (ClassInfo *CI = RegisterClassClasses[Rec])
822 throw TGError(Rec->getLoc(), "register class has no class info!");
825 assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
826 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
827 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
830 throw TGError(Rec->getLoc(), "operand has no match class!");
833 void AsmMatcherInfo::
834 BuildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters) {
835 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
836 const std::vector<CodeGenRegisterClass> &RegClassList =
837 Target.getRegisterClasses();
839 // The register sets used for matching.
840 std::set< std::set<Record*> > RegisterSets;
842 // Gather the defined sets.
843 for (std::vector<CodeGenRegisterClass>::const_iterator it =
844 RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it)
845 RegisterSets.insert(std::set<Record*>(it->Elements.begin(),
846 it->Elements.end()));
848 // Add any required singleton sets.
849 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
850 ie = SingletonRegisters.end(); it != ie; ++it) {
852 RegisterSets.insert(std::set<Record*>(&Rec, &Rec + 1));
855 // Introduce derived sets where necessary (when a register does not determine
856 // a unique register set class), and build the mapping of registers to the set
857 // they should classify to.
858 std::map<Record*, std::set<Record*> > RegisterMap;
859 for (std::vector<CodeGenRegister>::const_iterator it = Registers.begin(),
860 ie = Registers.end(); it != ie; ++it) {
861 const CodeGenRegister &CGR = *it;
862 // Compute the intersection of all sets containing this register.
863 std::set<Record*> ContainingSet;
865 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
866 ie = RegisterSets.end(); it != ie; ++it) {
867 if (!it->count(CGR.TheDef))
870 if (ContainingSet.empty()) {
875 std::set<Record*> Tmp;
876 std::swap(Tmp, ContainingSet);
877 std::insert_iterator< std::set<Record*> > II(ContainingSet,
878 ContainingSet.begin());
879 std::set_intersection(Tmp.begin(), Tmp.end(), it->begin(), it->end(), II);
882 if (!ContainingSet.empty()) {
883 RegisterSets.insert(ContainingSet);
884 RegisterMap.insert(std::make_pair(CGR.TheDef, ContainingSet));
888 // Construct the register classes.
889 std::map<std::set<Record*>, ClassInfo*> RegisterSetClasses;
891 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
892 ie = RegisterSets.end(); it != ie; ++it, ++Index) {
893 ClassInfo *CI = new ClassInfo();
894 CI->Kind = ClassInfo::RegisterClass0 + Index;
895 CI->ClassName = "Reg" + utostr(Index);
896 CI->Name = "MCK_Reg" + utostr(Index);
898 CI->PredicateMethod = ""; // unused
899 CI->RenderMethod = "addRegOperands";
901 Classes.push_back(CI);
902 RegisterSetClasses.insert(std::make_pair(*it, CI));
905 // Find the superclasses; we could compute only the subgroup lattice edges,
906 // but there isn't really a point.
907 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
908 ie = RegisterSets.end(); it != ie; ++it) {
909 ClassInfo *CI = RegisterSetClasses[*it];
910 for (std::set< std::set<Record*> >::iterator it2 = RegisterSets.begin(),
911 ie2 = RegisterSets.end(); it2 != ie2; ++it2)
913 std::includes(it2->begin(), it2->end(), it->begin(), it->end()))
914 CI->SuperClasses.push_back(RegisterSetClasses[*it2]);
917 // Name the register classes which correspond to a user defined RegisterClass.
918 for (std::vector<CodeGenRegisterClass>::const_iterator
919 it = RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it) {
920 ClassInfo *CI = RegisterSetClasses[std::set<Record*>(it->Elements.begin(),
921 it->Elements.end())];
922 if (CI->ValueName.empty()) {
923 CI->ClassName = it->getName();
924 CI->Name = "MCK_" + it->getName();
925 CI->ValueName = it->getName();
927 CI->ValueName = CI->ValueName + "," + it->getName();
929 RegisterClassClasses.insert(std::make_pair(it->TheDef, CI));
932 // Populate the map for individual registers.
933 for (std::map<Record*, std::set<Record*> >::iterator it = RegisterMap.begin(),
934 ie = RegisterMap.end(); it != ie; ++it)
935 RegisterClasses[it->first] = RegisterSetClasses[it->second];
937 // Name the register classes which correspond to singleton registers.
938 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
939 ie = SingletonRegisters.end(); it != ie; ++it) {
941 ClassInfo *CI = RegisterClasses[Rec];
942 assert(CI && "Missing singleton register class info!");
944 if (CI->ValueName.empty()) {
945 CI->ClassName = Rec->getName();
946 CI->Name = "MCK_" + Rec->getName();
947 CI->ValueName = Rec->getName();
949 CI->ValueName = CI->ValueName + "," + Rec->getName();
953 void AsmMatcherInfo::BuildOperandClasses() {
954 std::vector<Record*> AsmOperands =
955 Records.getAllDerivedDefinitions("AsmOperandClass");
957 // Pre-populate AsmOperandClasses map.
958 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
959 ie = AsmOperands.end(); it != ie; ++it)
960 AsmOperandClasses[*it] = new ClassInfo();
963 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
964 ie = AsmOperands.end(); it != ie; ++it, ++Index) {
965 ClassInfo *CI = AsmOperandClasses[*it];
966 CI->Kind = ClassInfo::UserClass0 + Index;
968 ListInit *Supers = (*it)->getValueAsListInit("SuperClasses");
969 for (unsigned i = 0, e = Supers->getSize(); i != e; ++i) {
970 DefInit *DI = dynamic_cast<DefInit*>(Supers->getElement(i));
972 PrintError((*it)->getLoc(), "Invalid super class reference!");
976 ClassInfo *SC = AsmOperandClasses[DI->getDef()];
978 PrintError((*it)->getLoc(), "Invalid super class reference!");
980 CI->SuperClasses.push_back(SC);
982 CI->ClassName = (*it)->getValueAsString("Name");
983 CI->Name = "MCK_" + CI->ClassName;
984 CI->ValueName = (*it)->getName();
986 // Get or construct the predicate method name.
987 Init *PMName = (*it)->getValueInit("PredicateMethod");
988 if (StringInit *SI = dynamic_cast<StringInit*>(PMName)) {
989 CI->PredicateMethod = SI->getValue();
991 assert(dynamic_cast<UnsetInit*>(PMName) &&
992 "Unexpected PredicateMethod field!");
993 CI->PredicateMethod = "is" + CI->ClassName;
996 // Get or construct the render method name.
997 Init *RMName = (*it)->getValueInit("RenderMethod");
998 if (StringInit *SI = dynamic_cast<StringInit*>(RMName)) {
999 CI->RenderMethod = SI->getValue();
1001 assert(dynamic_cast<UnsetInit*>(RMName) &&
1002 "Unexpected RenderMethod field!");
1003 CI->RenderMethod = "add" + CI->ClassName + "Operands";
1006 AsmOperandClasses[*it] = CI;
1007 Classes.push_back(CI);
1011 AsmMatcherInfo::AsmMatcherInfo(Record *asmParser,
1012 CodeGenTarget &target,
1013 RecordKeeper &records)
1014 : Records(records), AsmParser(asmParser), Target(target),
1015 RegisterPrefix(AsmParser->getValueAsString("RegisterPrefix")) {
1018 void AsmMatcherInfo::BuildInfo() {
1019 // Build information about all of the AssemblerPredicates.
1020 std::vector<Record*> AllPredicates =
1021 Records.getAllDerivedDefinitions("Predicate");
1022 for (unsigned i = 0, e = AllPredicates.size(); i != e; ++i) {
1023 Record *Pred = AllPredicates[i];
1024 // Ignore predicates that are not intended for the assembler.
1025 if (!Pred->getValueAsBit("AssemblerMatcherPredicate"))
1028 if (Pred->getName().empty())
1029 throw TGError(Pred->getLoc(), "Predicate has no name!");
1031 unsigned FeatureNo = SubtargetFeatures.size();
1032 SubtargetFeatures[Pred] = new SubtargetFeatureInfo(Pred, FeatureNo);
1033 assert(FeatureNo < 32 && "Too many subtarget features!");
1036 StringRef CommentDelimiter = AsmParser->getValueAsString("CommentDelimiter");
1038 // Parse the instructions; we need to do this first so that we can gather the
1039 // singleton register classes.
1040 SmallPtrSet<Record*, 16> SingletonRegisters;
1041 for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
1042 E = Target.inst_end(); I != E; ++I) {
1043 const CodeGenInstruction &CGI = **I;
1045 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1046 // filter the set of instructions we consider.
1047 if (!StringRef(CGI.TheDef->getName()).startswith(MatchPrefix))
1050 // Ignore "codegen only" instructions.
1051 if (CGI.TheDef->getValueAsBit("isCodeGenOnly"))
1054 // Validate the operand list to ensure we can handle this instruction.
1055 for (unsigned i = 0, e = CGI.Operands.size(); i != e; ++i) {
1056 const CGIOperandList::OperandInfo &OI = CGI.Operands[i];
1058 // Validate tied operands.
1059 if (OI.getTiedRegister() != -1) {
1060 // If we have a tied operand that consists of multiple MCOperands,
1061 // reject it. We reject aliases and ignore instructions for now.
1062 if (OI.MINumOperands != 1) {
1063 // FIXME: Should reject these. The ARM backend hits this with $lane
1064 // in a bunch of instructions. It is unclear what the right answer is.
1066 errs() << "warning: '" << CGI.TheDef->getName() << "': "
1067 << "ignoring instruction with multi-operand tied operand '"
1068 << OI.Name << "'\n";
1075 OwningPtr<MatchableInfo> II(new MatchableInfo(CGI));
1077 II->Initialize(*this, SingletonRegisters);
1079 // Ignore instructions which shouldn't be matched and diagnose invalid
1080 // instruction definitions with an error.
1081 if (!II->Validate(CommentDelimiter, true))
1084 // Ignore "Int_*" and "*_Int" instructions, which are internal aliases.
1086 // FIXME: This is a total hack.
1087 if (StringRef(II->TheDef->getName()).startswith("Int_") ||
1088 StringRef(II->TheDef->getName()).endswith("_Int"))
1091 Matchables.push_back(II.take());
1094 // Parse all of the InstAlias definitions and stick them in the list of
1096 std::vector<Record*> AllInstAliases =
1097 Records.getAllDerivedDefinitions("InstAlias");
1098 for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) {
1099 CodeGenInstAlias *Alias = new CodeGenInstAlias(AllInstAliases[i], Target);
1101 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1102 // filter the set of instruction aliases we consider, based on the target
1104 if (!StringRef(Alias->ResultInst->TheDef->getName()).startswith(
1108 OwningPtr<MatchableInfo> II(new MatchableInfo(Alias));
1110 II->Initialize(*this, SingletonRegisters);
1112 // Validate the alias definitions.
1113 II->Validate(CommentDelimiter, false);
1115 Matchables.push_back(II.take());
1118 // Build info for the register classes.
1119 BuildRegisterClasses(SingletonRegisters);
1121 // Build info for the user defined assembly operand classes.
1122 BuildOperandClasses();
1124 // Build the information about matchables, now that we have fully formed
1126 for (std::vector<MatchableInfo*>::iterator it = Matchables.begin(),
1127 ie = Matchables.end(); it != ie; ++it) {
1128 MatchableInfo *II = *it;
1130 // Parse the tokens after the mnemonic.
1131 // Note: BuildInstructionOperandReference may insert new AsmOperands, so
1132 // don't precompute the loop bound.
1133 for (unsigned i = 0; i != II->AsmOperands.size(); ++i) {
1134 MatchableInfo::AsmOperand &Op = II->AsmOperands[i];
1135 StringRef Token = Op.Token;
1137 // Check for singleton registers.
1138 if (Record *RegRecord = II->getSingletonRegisterForAsmOperand(i, *this)) {
1139 Op.Class = RegisterClasses[RegRecord];
1140 assert(Op.Class && Op.Class->Registers.size() == 1 &&
1141 "Unexpected class for singleton register");
1145 // Check for simple tokens.
1146 if (Token[0] != '$') {
1147 Op.Class = getTokenClass(Token);
1151 if (Token.size() > 1 && isdigit(Token[1])) {
1152 Op.Class = getTokenClass(Token);
1156 // Otherwise this is an operand reference.
1157 StringRef OperandName;
1158 if (Token[1] == '{')
1159 OperandName = Token.substr(2, Token.size() - 3);
1161 OperandName = Token.substr(1);
1163 if (II->DefRec.is<const CodeGenInstruction*>())
1164 BuildInstructionOperandReference(II, OperandName, i);
1166 BuildAliasOperandReference(II, OperandName, Op);
1169 if (II->DefRec.is<const CodeGenInstruction*>())
1170 II->BuildInstructionResultOperands();
1172 II->BuildAliasResultOperands();
1175 // Reorder classes so that classes preceed super classes.
1176 std::sort(Classes.begin(), Classes.end(), less_ptr<ClassInfo>());
1179 /// BuildInstructionOperandReference - The specified operand is a reference to a
1180 /// named operand such as $src. Resolve the Class and OperandInfo pointers.
1181 void AsmMatcherInfo::
1182 BuildInstructionOperandReference(MatchableInfo *II,
1183 StringRef OperandName,
1184 unsigned AsmOpIdx) {
1185 const CodeGenInstruction &CGI = *II->DefRec.get<const CodeGenInstruction*>();
1186 const CGIOperandList &Operands = CGI.Operands;
1187 MatchableInfo::AsmOperand *Op = &II->AsmOperands[AsmOpIdx];
1189 // Map this token to an operand.
1191 if (!Operands.hasOperandNamed(OperandName, Idx))
1192 throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" +
1193 OperandName.str() + "'");
1195 // If the instruction operand has multiple suboperands, but the parser
1196 // match class for the asm operand is still the default "ImmAsmOperand",
1197 // then handle each suboperand separately.
1198 if (Op->SubOpIdx == -1 && Operands[Idx].MINumOperands > 1) {
1199 Record *Rec = Operands[Idx].Rec;
1200 assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
1201 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1202 if (MatchClass && MatchClass->getValueAsString("Name") == "Imm") {
1203 // Insert remaining suboperands after AsmOpIdx in II->AsmOperands.
1204 StringRef Token = Op->Token; // save this in case Op gets moved
1205 for (unsigned SI = 1, SE = Operands[Idx].MINumOperands; SI != SE; ++SI) {
1206 MatchableInfo::AsmOperand NewAsmOp(Token);
1207 NewAsmOp.SubOpIdx = SI;
1208 II->AsmOperands.insert(II->AsmOperands.begin()+AsmOpIdx+SI, NewAsmOp);
1210 // Replace Op with first suboperand.
1211 Op = &II->AsmOperands[AsmOpIdx]; // update the pointer in case it moved
1216 // Set up the operand class.
1217 Op->Class = getOperandClass(Operands[Idx], Op->SubOpIdx);
1219 // If the named operand is tied, canonicalize it to the untied operand.
1220 // For example, something like:
1221 // (outs GPR:$dst), (ins GPR:$src)
1222 // with an asmstring of
1224 // we want to canonicalize to:
1226 // so that we know how to provide the $dst operand when filling in the result.
1227 int OITied = Operands[Idx].getTiedRegister();
1229 // The tied operand index is an MIOperand index, find the operand that
1231 std::pair<unsigned, unsigned> Idx = Operands.getSubOperandNumber(OITied);
1232 OperandName = Operands[Idx.first].Name;
1233 Op->SubOpIdx = Idx.second;
1236 Op->SrcOpName = OperandName;
1239 /// BuildAliasOperandReference - When parsing an operand reference out of the
1240 /// matching string (e.g. "movsx $src, $dst"), determine what the class of the
1241 /// operand reference is by looking it up in the result pattern definition.
1242 void AsmMatcherInfo::BuildAliasOperandReference(MatchableInfo *II,
1243 StringRef OperandName,
1244 MatchableInfo::AsmOperand &Op) {
1245 const CodeGenInstAlias &CGA = *II->DefRec.get<const CodeGenInstAlias*>();
1247 // Set up the operand class.
1248 for (unsigned i = 0, e = CGA.ResultOperands.size(); i != e; ++i)
1249 if (CGA.ResultOperands[i].isRecord() &&
1250 CGA.ResultOperands[i].getName() == OperandName) {
1251 // It's safe to go with the first one we find, because CodeGenInstAlias
1252 // validates that all operands with the same name have the same record.
1253 unsigned ResultIdx = CGA.ResultInstOperandIndex[i].first;
1254 Op.SubOpIdx = CGA.ResultInstOperandIndex[i].second;
1255 Op.Class = getOperandClass(CGA.ResultInst->Operands[ResultIdx],
1257 Op.SrcOpName = OperandName;
1261 throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" +
1262 OperandName.str() + "'");
1265 void MatchableInfo::BuildInstructionResultOperands() {
1266 const CodeGenInstruction *ResultInst = getResultInst();
1268 // Loop over all operands of the result instruction, determining how to
1270 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1271 const CGIOperandList::OperandInfo &OpInfo = ResultInst->Operands[i];
1273 // If this is a tied operand, just copy from the previously handled operand.
1274 int TiedOp = OpInfo.getTiedRegister();
1276 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1280 // Find out what operand from the asmparser this MCInst operand comes from.
1281 int SrcOperand = FindAsmOperandNamed(OpInfo.Name);
1282 if (OpInfo.Name.empty() || SrcOperand == -1)
1283 throw TGError(TheDef->getLoc(), "Instruction '" +
1284 TheDef->getName() + "' has operand '" + OpInfo.Name +
1285 "' that doesn't appear in asm string!");
1287 // Check if the one AsmOperand populates the entire operand.
1288 unsigned NumOperands = OpInfo.MINumOperands;
1289 if (AsmOperands[SrcOperand].SubOpIdx == -1) {
1290 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, NumOperands));
1294 // Add a separate ResOperand for each suboperand.
1295 for (unsigned AI = 0; AI < NumOperands; ++AI) {
1296 assert(AsmOperands[SrcOperand+AI].SubOpIdx == (int)AI &&
1297 AsmOperands[SrcOperand+AI].SrcOpName == OpInfo.Name &&
1298 "unexpected AsmOperands for suboperands");
1299 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand + AI, 1));
1304 void MatchableInfo::BuildAliasResultOperands() {
1305 const CodeGenInstAlias &CGA = *DefRec.get<const CodeGenInstAlias*>();
1306 const CodeGenInstruction *ResultInst = getResultInst();
1308 // Loop over all operands of the result instruction, determining how to
1310 unsigned AliasOpNo = 0;
1311 unsigned LastOpNo = CGA.ResultInstOperandIndex.size();
1312 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1313 const CGIOperandList::OperandInfo *OpInfo = &ResultInst->Operands[i];
1315 // If this is a tied operand, just copy from the previously handled operand.
1316 int TiedOp = OpInfo->getTiedRegister();
1318 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1322 // Handle all the suboperands for this operand.
1323 const std::string &OpName = OpInfo->Name;
1324 for ( ; AliasOpNo < LastOpNo &&
1325 CGA.ResultInstOperandIndex[AliasOpNo].first == i; ++AliasOpNo) {
1326 int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second;
1328 // Find out what operand from the asmparser that this MCInst operand
1330 switch (CGA.ResultOperands[AliasOpNo].Kind) {
1331 default: assert(0 && "unexpected InstAlias operand kind");
1332 case CodeGenInstAlias::ResultOperand::K_Record: {
1333 StringRef Name = CGA.ResultOperands[AliasOpNo].getName();
1334 int SrcOperand = FindAsmOperand(Name, SubIdx);
1335 if (SrcOperand == -1)
1336 throw TGError(TheDef->getLoc(), "Instruction '" +
1337 TheDef->getName() + "' has operand '" + OpName +
1338 "' that doesn't appear in asm string!");
1339 unsigned NumOperands = (SubIdx == -1 ? OpInfo->MINumOperands : 1);
1340 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand,
1344 case CodeGenInstAlias::ResultOperand::K_Imm: {
1345 int64_t ImmVal = CGA.ResultOperands[AliasOpNo].getImm();
1346 ResOperands.push_back(ResOperand::getImmOp(ImmVal));
1349 case CodeGenInstAlias::ResultOperand::K_Reg: {
1350 Record *Reg = CGA.ResultOperands[AliasOpNo].getRegister();
1351 ResOperands.push_back(ResOperand::getRegOp(Reg));
1359 static void EmitConvertToMCInst(CodeGenTarget &Target,
1360 std::vector<MatchableInfo*> &Infos,
1362 // Write the convert function to a separate stream, so we can drop it after
1364 std::string ConvertFnBody;
1365 raw_string_ostream CvtOS(ConvertFnBody);
1367 // Function we have already generated.
1368 std::set<std::string> GeneratedFns;
1370 // Start the unified conversion function.
1371 CvtOS << "static void ConvertToMCInst(ConversionKind Kind, MCInst &Inst, "
1372 << "unsigned Opcode,\n"
1373 << " const SmallVectorImpl<MCParsedAsmOperand*"
1374 << "> &Operands) {\n";
1375 CvtOS << " Inst.setOpcode(Opcode);\n";
1376 CvtOS << " switch (Kind) {\n";
1377 CvtOS << " default:\n";
1379 // Start the enum, which we will generate inline.
1381 OS << "// Unified function for converting operands to MCInst instances.\n\n";
1382 OS << "enum ConversionKind {\n";
1384 // TargetOperandClass - This is the target's operand class, like X86Operand.
1385 std::string TargetOperandClass = Target.getName() + "Operand";
1387 for (std::vector<MatchableInfo*>::const_iterator it = Infos.begin(),
1388 ie = Infos.end(); it != ie; ++it) {
1389 MatchableInfo &II = **it;
1391 // Build the conversion function signature.
1392 std::string Signature = "Convert";
1393 std::string CaseBody;
1394 raw_string_ostream CaseOS(CaseBody);
1396 // Compute the convert enum and the case body.
1397 for (unsigned i = 0, e = II.ResOperands.size(); i != e; ++i) {
1398 const MatchableInfo::ResOperand &OpInfo = II.ResOperands[i];
1400 // Generate code to populate each result operand.
1401 switch (OpInfo.Kind) {
1402 case MatchableInfo::ResOperand::RenderAsmOperand: {
1403 // This comes from something we parsed.
1404 MatchableInfo::AsmOperand &Op = II.AsmOperands[OpInfo.AsmOperandNum];
1406 // Registers are always converted the same, don't duplicate the
1407 // conversion function based on them.
1409 if (Op.Class->isRegisterClass())
1412 Signature += Op.Class->ClassName;
1413 Signature += utostr(OpInfo.MINumOperands);
1414 Signature += "_" + itostr(OpInfo.AsmOperandNum);
1416 CaseOS << " ((" << TargetOperandClass << "*)Operands["
1417 << (OpInfo.AsmOperandNum+1) << "])->" << Op.Class->RenderMethod
1418 << "(Inst, " << OpInfo.MINumOperands << ");\n";
1422 case MatchableInfo::ResOperand::TiedOperand: {
1423 // If this operand is tied to a previous one, just copy the MCInst
1424 // operand from the earlier one.We can only tie single MCOperand values.
1425 //assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand");
1426 unsigned TiedOp = OpInfo.TiedOperandNum;
1427 assert(i > TiedOp && "Tied operand preceeds its target!");
1428 CaseOS << " Inst.addOperand(Inst.getOperand(" << TiedOp << "));\n";
1429 Signature += "__Tie" + utostr(TiedOp);
1432 case MatchableInfo::ResOperand::ImmOperand: {
1433 int64_t Val = OpInfo.ImmVal;
1434 CaseOS << " Inst.addOperand(MCOperand::CreateImm(" << Val << "));\n";
1435 Signature += "__imm" + itostr(Val);
1438 case MatchableInfo::ResOperand::RegOperand: {
1439 if (OpInfo.Register == 0) {
1440 CaseOS << " Inst.addOperand(MCOperand::CreateReg(0));\n";
1441 Signature += "__reg0";
1443 std::string N = getQualifiedName(OpInfo.Register);
1444 CaseOS << " Inst.addOperand(MCOperand::CreateReg(" << N << "));\n";
1445 Signature += "__reg" + OpInfo.Register->getName();
1451 II.ConversionFnKind = Signature;
1453 // Check if we have already generated this signature.
1454 if (!GeneratedFns.insert(Signature).second)
1457 // If not, emit it now. Add to the enum list.
1458 OS << " " << Signature << ",\n";
1460 CvtOS << " case " << Signature << ":\n";
1461 CvtOS << CaseOS.str();
1462 CvtOS << " return;\n";
1465 // Finish the convert function.
1470 // Finish the enum, and drop the convert function after it.
1472 OS << " NumConversionVariants\n";
1478 /// EmitMatchClassEnumeration - Emit the enumeration for match class kinds.
1479 static void EmitMatchClassEnumeration(CodeGenTarget &Target,
1480 std::vector<ClassInfo*> &Infos,
1482 OS << "namespace {\n\n";
1484 OS << "/// MatchClassKind - The kinds of classes which participate in\n"
1485 << "/// instruction matching.\n";
1486 OS << "enum MatchClassKind {\n";
1487 OS << " InvalidMatchClass = 0,\n";
1488 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1489 ie = Infos.end(); it != ie; ++it) {
1490 ClassInfo &CI = **it;
1491 OS << " " << CI.Name << ", // ";
1492 if (CI.Kind == ClassInfo::Token) {
1493 OS << "'" << CI.ValueName << "'\n";
1494 } else if (CI.isRegisterClass()) {
1495 if (!CI.ValueName.empty())
1496 OS << "register class '" << CI.ValueName << "'\n";
1498 OS << "derived register class\n";
1500 OS << "user defined class '" << CI.ValueName << "'\n";
1503 OS << " NumMatchClassKinds\n";
1509 /// EmitClassifyOperand - Emit the function to classify an operand.
1510 static void EmitClassifyOperand(AsmMatcherInfo &Info,
1512 OS << "static MatchClassKind ClassifyOperand(MCParsedAsmOperand *GOp) {\n"
1513 << " " << Info.Target.getName() << "Operand &Operand = *("
1514 << Info.Target.getName() << "Operand*)GOp;\n";
1517 OS << " if (Operand.isToken())\n";
1518 OS << " return MatchTokenString(Operand.getToken());\n\n";
1520 // Classify registers.
1522 // FIXME: Don't hardcode isReg, getReg.
1523 OS << " if (Operand.isReg()) {\n";
1524 OS << " switch (Operand.getReg()) {\n";
1525 OS << " default: return InvalidMatchClass;\n";
1526 for (std::map<Record*, ClassInfo*>::iterator
1527 it = Info.RegisterClasses.begin(), ie = Info.RegisterClasses.end();
1529 OS << " case " << Info.Target.getName() << "::"
1530 << it->first->getName() << ": return " << it->second->Name << ";\n";
1534 // Classify user defined operands. To do so, we need to perform a topological
1535 // sort of the superclass relationship graph so that we always match the
1536 // narrowest type first.
1538 // Collect the incoming edge counts for each class.
1539 std::map<ClassInfo*, unsigned> IncomingEdges;
1540 for (std::vector<ClassInfo*>::iterator it = Info.Classes.begin(),
1541 ie = Info.Classes.end(); it != ie; ++it) {
1542 ClassInfo &CI = **it;
1544 if (!CI.isUserClass())
1547 for (std::vector<ClassInfo*>::iterator SI = CI.SuperClasses.begin(),
1548 SE = CI.SuperClasses.end(); SI != SE; ++SI)
1549 ++IncomingEdges[*SI];
1552 // Initialize a worklist of classes with no incoming edges.
1553 std::vector<ClassInfo*> LeafClasses;
1554 for (std::vector<ClassInfo*>::iterator it = Info.Classes.begin(),
1555 ie = Info.Classes.end(); it != ie; ++it) {
1556 if (!IncomingEdges[*it])
1557 LeafClasses.push_back(*it);
1560 // Iteratively pop the list, process that class, and update the incoming
1561 // edge counts for its super classes. When a superclass reaches zero
1562 // incoming edges, push it onto the worklist for processing.
1563 while (!LeafClasses.empty()) {
1564 ClassInfo &CI = *LeafClasses.back();
1565 LeafClasses.pop_back();
1567 if (!CI.isUserClass())
1570 OS << " // '" << CI.ClassName << "' class";
1571 if (!CI.SuperClasses.empty()) {
1572 OS << ", subclass of ";
1573 for (unsigned i = 0, e = CI.SuperClasses.size(); i != e; ++i) {
1575 OS << "'" << CI.SuperClasses[i]->ClassName << "'";
1576 assert(CI < *CI.SuperClasses[i] && "Invalid class relation!");
1578 --IncomingEdges[CI.SuperClasses[i]];
1579 if (!IncomingEdges[CI.SuperClasses[i]])
1580 LeafClasses.push_back(CI.SuperClasses[i]);
1585 OS << " if (Operand." << CI.PredicateMethod << "()) {\n";
1587 // Validate subclass relationships.
1588 if (!CI.SuperClasses.empty()) {
1589 for (unsigned i = 0, e = CI.SuperClasses.size(); i != e; ++i)
1590 OS << " assert(Operand." << CI.SuperClasses[i]->PredicateMethod
1591 << "() && \"Invalid class relationship!\");\n";
1594 OS << " return " << CI.Name << ";\n";
1598 OS << " return InvalidMatchClass;\n";
1602 /// EmitIsSubclass - Emit the subclass predicate function.
1603 static void EmitIsSubclass(CodeGenTarget &Target,
1604 std::vector<ClassInfo*> &Infos,
1606 OS << "/// IsSubclass - Compute whether \\arg A is a subclass of \\arg B.\n";
1607 OS << "static bool IsSubclass(MatchClassKind A, MatchClassKind B) {\n";
1608 OS << " if (A == B)\n";
1609 OS << " return true;\n\n";
1611 OS << " switch (A) {\n";
1612 OS << " default:\n";
1613 OS << " return false;\n";
1614 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1615 ie = Infos.end(); it != ie; ++it) {
1616 ClassInfo &A = **it;
1618 if (A.Kind != ClassInfo::Token) {
1619 std::vector<StringRef> SuperClasses;
1620 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1621 ie = Infos.end(); it != ie; ++it) {
1622 ClassInfo &B = **it;
1624 if (&A != &B && A.isSubsetOf(B))
1625 SuperClasses.push_back(B.Name);
1628 if (SuperClasses.empty())
1631 OS << "\n case " << A.Name << ":\n";
1633 if (SuperClasses.size() == 1) {
1634 OS << " return B == " << SuperClasses.back() << ";\n";
1638 OS << " switch (B) {\n";
1639 OS << " default: return false;\n";
1640 for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i)
1641 OS << " case " << SuperClasses[i] << ": return true;\n";
1649 /// EmitMatchTokenString - Emit the function to match a token string to the
1650 /// appropriate match class value.
1651 static void EmitMatchTokenString(CodeGenTarget &Target,
1652 std::vector<ClassInfo*> &Infos,
1654 // Construct the match list.
1655 std::vector<StringMatcher::StringPair> Matches;
1656 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1657 ie = Infos.end(); it != ie; ++it) {
1658 ClassInfo &CI = **it;
1660 if (CI.Kind == ClassInfo::Token)
1661 Matches.push_back(StringMatcher::StringPair(CI.ValueName,
1662 "return " + CI.Name + ";"));
1665 OS << "static MatchClassKind MatchTokenString(StringRef Name) {\n";
1667 StringMatcher("Name", Matches, OS).Emit();
1669 OS << " return InvalidMatchClass;\n";
1673 /// EmitMatchRegisterName - Emit the function to match a string to the target
1674 /// specific register enum.
1675 static void EmitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
1677 // Construct the match list.
1678 std::vector<StringMatcher::StringPair> Matches;
1679 for (unsigned i = 0, e = Target.getRegisters().size(); i != e; ++i) {
1680 const CodeGenRegister &Reg = Target.getRegisters()[i];
1681 if (Reg.TheDef->getValueAsString("AsmName").empty())
1684 Matches.push_back(StringMatcher::StringPair(
1685 Reg.TheDef->getValueAsString("AsmName"),
1686 "return " + utostr(i + 1) + ";"));
1689 OS << "static unsigned MatchRegisterName(StringRef Name) {\n";
1691 StringMatcher("Name", Matches, OS).Emit();
1693 OS << " return 0;\n";
1697 /// EmitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag
1699 static void EmitSubtargetFeatureFlagEnumeration(AsmMatcherInfo &Info,
1701 OS << "// Flags for subtarget features that participate in "
1702 << "instruction matching.\n";
1703 OS << "enum SubtargetFeatureFlag {\n";
1704 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
1705 it = Info.SubtargetFeatures.begin(),
1706 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
1707 SubtargetFeatureInfo &SFI = *it->second;
1708 OS << " " << SFI.getEnumName() << " = (1 << " << SFI.Index << "),\n";
1710 OS << " Feature_None = 0\n";
1714 /// EmitComputeAvailableFeatures - Emit the function to compute the list of
1715 /// available features given a subtarget.
1716 static void EmitComputeAvailableFeatures(AsmMatcherInfo &Info,
1718 std::string ClassName =
1719 Info.AsmParser->getValueAsString("AsmParserClassName");
1721 OS << "unsigned " << Info.Target.getName() << ClassName << "::\n"
1722 << "ComputeAvailableFeatures(const " << Info.Target.getName()
1723 << "Subtarget *Subtarget) const {\n";
1724 OS << " unsigned Features = 0;\n";
1725 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
1726 it = Info.SubtargetFeatures.begin(),
1727 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
1728 SubtargetFeatureInfo &SFI = *it->second;
1729 OS << " if (" << SFI.TheDef->getValueAsString("CondString")
1731 OS << " Features |= " << SFI.getEnumName() << ";\n";
1733 OS << " return Features;\n";
1737 static std::string GetAliasRequiredFeatures(Record *R,
1738 const AsmMatcherInfo &Info) {
1739 std::vector<Record*> ReqFeatures = R->getValueAsListOfDefs("Predicates");
1741 unsigned NumFeatures = 0;
1742 for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) {
1743 SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]);
1746 throw TGError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() +
1747 "' is not marked as an AssemblerPredicate!");
1752 Result += F->getEnumName();
1756 if (NumFeatures > 1)
1757 Result = '(' + Result + ')';
1761 /// EmitMnemonicAliases - If the target has any MnemonicAlias<> definitions,
1762 /// emit a function for them and return true, otherwise return false.
1763 static bool EmitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info) {
1764 // Ignore aliases when match-prefix is set.
1765 if (!MatchPrefix.empty())
1768 std::vector<Record*> Aliases =
1769 Info.getRecords().getAllDerivedDefinitions("MnemonicAlias");
1770 if (Aliases.empty()) return false;
1772 OS << "static void ApplyMnemonicAliases(StringRef &Mnemonic, "
1773 "unsigned Features) {\n";
1775 // Keep track of all the aliases from a mnemonic. Use an std::map so that the
1776 // iteration order of the map is stable.
1777 std::map<std::string, std::vector<Record*> > AliasesFromMnemonic;
1779 for (unsigned i = 0, e = Aliases.size(); i != e; ++i) {
1780 Record *R = Aliases[i];
1781 AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R);
1784 // Process each alias a "from" mnemonic at a time, building the code executed
1785 // by the string remapper.
1786 std::vector<StringMatcher::StringPair> Cases;
1787 for (std::map<std::string, std::vector<Record*> >::iterator
1788 I = AliasesFromMnemonic.begin(), E = AliasesFromMnemonic.end();
1790 const std::vector<Record*> &ToVec = I->second;
1792 // Loop through each alias and emit code that handles each case. If there
1793 // are two instructions without predicates, emit an error. If there is one,
1795 std::string MatchCode;
1796 int AliasWithNoPredicate = -1;
1798 for (unsigned i = 0, e = ToVec.size(); i != e; ++i) {
1799 Record *R = ToVec[i];
1800 std::string FeatureMask = GetAliasRequiredFeatures(R, Info);
1802 // If this unconditionally matches, remember it for later and diagnose
1804 if (FeatureMask.empty()) {
1805 if (AliasWithNoPredicate != -1) {
1806 // We can't have two aliases from the same mnemonic with no predicate.
1807 PrintError(ToVec[AliasWithNoPredicate]->getLoc(),
1808 "two MnemonicAliases with the same 'from' mnemonic!");
1809 throw TGError(R->getLoc(), "this is the other MnemonicAlias.");
1812 AliasWithNoPredicate = i;
1816 if (!MatchCode.empty())
1817 MatchCode += "else ";
1818 MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n";
1819 MatchCode += " Mnemonic = \"" +R->getValueAsString("ToMnemonic")+"\";\n";
1822 if (AliasWithNoPredicate != -1) {
1823 Record *R = ToVec[AliasWithNoPredicate];
1824 if (!MatchCode.empty())
1825 MatchCode += "else\n ";
1826 MatchCode += "Mnemonic = \"" + R->getValueAsString("ToMnemonic")+"\";\n";
1829 MatchCode += "return;";
1831 Cases.push_back(std::make_pair(I->first, MatchCode));
1834 StringMatcher("Mnemonic", Cases, OS).Emit();
1840 void AsmMatcherEmitter::run(raw_ostream &OS) {
1841 CodeGenTarget Target(Records);
1842 Record *AsmParser = Target.getAsmParser();
1843 std::string ClassName = AsmParser->getValueAsString("AsmParserClassName");
1845 // Compute the information on the instructions to match.
1846 AsmMatcherInfo Info(AsmParser, Target, Records);
1849 // Sort the instruction table using the partial order on classes. We use
1850 // stable_sort to ensure that ambiguous instructions are still
1851 // deterministically ordered.
1852 std::stable_sort(Info.Matchables.begin(), Info.Matchables.end(),
1853 less_ptr<MatchableInfo>());
1855 DEBUG_WITH_TYPE("instruction_info", {
1856 for (std::vector<MatchableInfo*>::iterator
1857 it = Info.Matchables.begin(), ie = Info.Matchables.end();
1862 // Check for ambiguous matchables.
1863 DEBUG_WITH_TYPE("ambiguous_instrs", {
1864 unsigned NumAmbiguous = 0;
1865 for (unsigned i = 0, e = Info.Matchables.size(); i != e; ++i) {
1866 for (unsigned j = i + 1; j != e; ++j) {
1867 MatchableInfo &A = *Info.Matchables[i];
1868 MatchableInfo &B = *Info.Matchables[j];
1870 if (A.CouldMatchAmbiguouslyWith(B)) {
1871 errs() << "warning: ambiguous matchables:\n";
1873 errs() << "\nis incomparable with:\n";
1881 errs() << "warning: " << NumAmbiguous
1882 << " ambiguous matchables!\n";
1885 // Write the output.
1887 EmitSourceFileHeader("Assembly Matcher Source Fragment", OS);
1889 // Information for the class declaration.
1890 OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
1891 OS << "#undef GET_ASSEMBLER_HEADER\n";
1892 OS << " // This should be included into the middle of the declaration of \n";
1893 OS << " // your subclasses implementation of TargetAsmParser.\n";
1894 OS << " unsigned ComputeAvailableFeatures(const " <<
1895 Target.getName() << "Subtarget *Subtarget) const;\n";
1896 OS << " enum MatchResultTy {\n";
1897 OS << " Match_Success, Match_MnemonicFail, Match_InvalidOperand,\n";
1898 OS << " Match_MissingFeature\n";
1900 OS << " bool MnemonicIsValid(StringRef Mnemonic);\n";
1901 OS << " MatchResultTy MatchInstructionImpl(\n";
1902 OS << " const SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n";
1903 OS << " MCInst &Inst, unsigned &ErrorInfo);\n\n";
1904 OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n";
1906 OS << "\n#ifdef GET_REGISTER_MATCHER\n";
1907 OS << "#undef GET_REGISTER_MATCHER\n\n";
1909 // Emit the subtarget feature enumeration.
1910 EmitSubtargetFeatureFlagEnumeration(Info, OS);
1912 // Emit the function to match a register name to number.
1913 EmitMatchRegisterName(Target, AsmParser, OS);
1915 OS << "#endif // GET_REGISTER_MATCHER\n\n";
1918 OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
1919 OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
1921 // Generate the function that remaps for mnemonic aliases.
1922 bool HasMnemonicAliases = EmitMnemonicAliases(OS, Info);
1924 // Generate the unified function to convert operands into an MCInst.
1925 EmitConvertToMCInst(Target, Info.Matchables, OS);
1927 // Emit the enumeration for classes which participate in matching.
1928 EmitMatchClassEnumeration(Target, Info.Classes, OS);
1930 // Emit the routine to match token strings to their match class.
1931 EmitMatchTokenString(Target, Info.Classes, OS);
1933 // Emit the routine to classify an operand.
1934 EmitClassifyOperand(Info, OS);
1936 // Emit the subclass predicate routine.
1937 EmitIsSubclass(Target, Info.Classes, OS);
1939 // Emit the available features compute function.
1940 EmitComputeAvailableFeatures(Info, OS);
1943 size_t MaxNumOperands = 0;
1944 for (std::vector<MatchableInfo*>::const_iterator it =
1945 Info.Matchables.begin(), ie = Info.Matchables.end();
1947 MaxNumOperands = std::max(MaxNumOperands, (*it)->AsmOperands.size());
1949 // Emit the static match table; unused classes get initalized to 0 which is
1950 // guaranteed to be InvalidMatchClass.
1952 // FIXME: We can reduce the size of this table very easily. First, we change
1953 // it so that store the kinds in separate bit-fields for each index, which
1954 // only needs to be the max width used for classes at that index (we also need
1955 // to reject based on this during classification). If we then make sure to
1956 // order the match kinds appropriately (putting mnemonics last), then we
1957 // should only end up using a few bits for each class, especially the ones
1958 // following the mnemonic.
1959 OS << "namespace {\n";
1960 OS << " struct MatchEntry {\n";
1961 OS << " unsigned Opcode;\n";
1962 OS << " const char *Mnemonic;\n";
1963 OS << " ConversionKind ConvertFn;\n";
1964 OS << " MatchClassKind Classes[" << MaxNumOperands << "];\n";
1965 OS << " unsigned RequiredFeatures;\n";
1968 OS << "// Predicate for searching for an opcode.\n";
1969 OS << " struct LessOpcode {\n";
1970 OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n";
1971 OS << " return StringRef(LHS.Mnemonic) < RHS;\n";
1973 OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n";
1974 OS << " return LHS < StringRef(RHS.Mnemonic);\n";
1976 OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n";
1977 OS << " return StringRef(LHS.Mnemonic) < StringRef(RHS.Mnemonic);\n";
1981 OS << "} // end anonymous namespace.\n\n";
1983 OS << "static const MatchEntry MatchTable["
1984 << Info.Matchables.size() << "] = {\n";
1986 for (std::vector<MatchableInfo*>::const_iterator it =
1987 Info.Matchables.begin(), ie = Info.Matchables.end();
1989 MatchableInfo &II = **it;
1992 OS << " { " << Target.getName() << "::"
1993 << II.getResultInst()->TheDef->getName() << ", \"" << II.Mnemonic << "\""
1994 << ", " << II.ConversionFnKind << ", { ";
1995 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) {
1996 MatchableInfo::AsmOperand &Op = II.AsmOperands[i];
1999 OS << Op.Class->Name;
2003 // Write the required features mask.
2004 if (!II.RequiredFeatures.empty()) {
2005 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
2007 OS << II.RequiredFeatures[i]->getEnumName();
2017 // A method to determine if a mnemonic is in the list.
2018 OS << "bool " << Target.getName() << ClassName << "::\n"
2019 << "MnemonicIsValid(StringRef Mnemonic) {\n";
2020 OS << " // Search the table.\n";
2021 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
2022 OS << " std::equal_range(MatchTable, MatchTable+"
2023 << Info.Matchables.size() << ", Mnemonic, LessOpcode());\n";
2024 OS << " return MnemonicRange.first != MnemonicRange.second;\n";
2027 // Finally, build the match function.
2028 OS << Target.getName() << ClassName << "::MatchResultTy "
2029 << Target.getName() << ClassName << "::\n"
2030 << "MatchInstructionImpl(const SmallVectorImpl<MCParsedAsmOperand*>"
2032 OS << " MCInst &Inst, unsigned &ErrorInfo) {\n";
2034 // Emit code to get the available features.
2035 OS << " // Get the current feature set.\n";
2036 OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n";
2038 OS << " // Get the instruction mnemonic, which is the first token.\n";
2039 OS << " StringRef Mnemonic = ((" << Target.getName()
2040 << "Operand*)Operands[0])->getToken();\n\n";
2042 if (HasMnemonicAliases) {
2043 OS << " // Process all MnemonicAliases to remap the mnemonic.\n";
2044 OS << " ApplyMnemonicAliases(Mnemonic, AvailableFeatures);\n\n";
2047 // Emit code to compute the class list for this operand vector.
2048 OS << " // Eliminate obvious mismatches.\n";
2049 OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n";
2050 OS << " ErrorInfo = " << (MaxNumOperands+1) << ";\n";
2051 OS << " return Match_InvalidOperand;\n";
2054 OS << " // Compute the class list for this operand vector.\n";
2055 OS << " MatchClassKind Classes[" << MaxNumOperands << "];\n";
2056 OS << " for (unsigned i = 1, e = Operands.size(); i != e; ++i) {\n";
2057 OS << " Classes[i-1] = ClassifyOperand(Operands[i]);\n\n";
2059 OS << " // Check for invalid operands before matching.\n";
2060 OS << " if (Classes[i-1] == InvalidMatchClass) {\n";
2061 OS << " ErrorInfo = i;\n";
2062 OS << " return Match_InvalidOperand;\n";
2066 OS << " // Mark unused classes.\n";
2067 OS << " for (unsigned i = Operands.size()-1, e = " << MaxNumOperands << "; "
2068 << "i != e; ++i)\n";
2069 OS << " Classes[i] = InvalidMatchClass;\n\n";
2071 OS << " // Some state to try to produce better error messages.\n";
2072 OS << " bool HadMatchOtherThanFeatures = false;\n\n";
2073 OS << " // Set ErrorInfo to the operand that mismatches if it is \n";
2074 OS << " // wrong for all instances of the instruction.\n";
2075 OS << " ErrorInfo = ~0U;\n";
2077 // Emit code to search the table.
2078 OS << " // Search the table.\n";
2079 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
2080 OS << " std::equal_range(MatchTable, MatchTable+"
2081 << Info.Matchables.size() << ", Mnemonic, LessOpcode());\n\n";
2083 OS << " // Return a more specific error code if no mnemonics match.\n";
2084 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2085 OS << " return Match_MnemonicFail;\n\n";
2087 OS << " for (const MatchEntry *it = MnemonicRange.first, "
2088 << "*ie = MnemonicRange.second;\n";
2089 OS << " it != ie; ++it) {\n";
2091 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2092 OS << " assert(Mnemonic == it->Mnemonic);\n";
2094 // Emit check that the subclasses match.
2095 OS << " bool OperandsValid = true;\n";
2096 OS << " for (unsigned i = 0; i != " << MaxNumOperands << "; ++i) {\n";
2097 OS << " if (IsSubclass(Classes[i], it->Classes[i]))\n";
2098 OS << " continue;\n";
2099 OS << " // If this operand is broken for all of the instances of this\n";
2100 OS << " // mnemonic, keep track of it so we can report loc info.\n";
2101 OS << " if (it == MnemonicRange.first || ErrorInfo <= i+1)\n";
2102 OS << " ErrorInfo = i+1;\n";
2103 OS << " // Otherwise, just reject this instance of the mnemonic.\n";
2104 OS << " OperandsValid = false;\n";
2108 OS << " if (!OperandsValid) continue;\n";
2110 // Emit check that the required features are available.
2111 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2112 << "!= it->RequiredFeatures) {\n";
2113 OS << " HadMatchOtherThanFeatures = true;\n";
2114 OS << " continue;\n";
2118 OS << " ConvertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n";
2120 // Call the post-processing function, if used.
2121 std::string InsnCleanupFn =
2122 AsmParser->getValueAsString("AsmParserInstCleanup");
2123 if (!InsnCleanupFn.empty())
2124 OS << " " << InsnCleanupFn << "(Inst);\n";
2126 OS << " return Match_Success;\n";
2129 OS << " // Okay, we had no match. Try to return a useful error code.\n";
2130 OS << " if (HadMatchOtherThanFeatures) return Match_MissingFeature;\n";
2131 OS << " return Match_InvalidOperand;\n";
2134 OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";