1 //===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits a target specifier matcher for converting parsed
11 // assembly operands in the MCInst structures. It also emits a matcher for
12 // custom operand parsing.
14 // Converting assembly operands into MCInst structures
15 // ---------------------------------------------------
17 // The input to the target specific matcher is a list of literal tokens and
18 // operands. The target specific parser should generally eliminate any syntax
19 // which is not relevant for matching; for example, comma tokens should have
20 // already been consumed and eliminated by the parser. Most instructions will
21 // end up with a single literal token (the instruction name) and some number of
24 // Some example inputs, for X86:
25 // 'addl' (immediate ...) (register ...)
26 // 'add' (immediate ...) (memory ...)
29 // The assembly matcher is responsible for converting this input into a precise
30 // machine instruction (i.e., an instruction with a well defined encoding). This
31 // mapping has several properties which complicate matching:
33 // - It may be ambiguous; many architectures can legally encode particular
34 // variants of an instruction in different ways (for example, using a smaller
35 // encoding for small immediates). Such ambiguities should never be
36 // arbitrarily resolved by the assembler, the assembler is always responsible
37 // for choosing the "best" available instruction.
39 // - It may depend on the subtarget or the assembler context. Instructions
40 // which are invalid for the current mode, but otherwise unambiguous (e.g.,
41 // an SSE instruction in a file being assembled for i486) should be accepted
42 // and rejected by the assembler front end. However, if the proper encoding
43 // for an instruction is dependent on the assembler context then the matcher
44 // is responsible for selecting the correct machine instruction for the
47 // The core matching algorithm attempts to exploit the regularity in most
48 // instruction sets to quickly determine the set of possibly matching
49 // instructions, and the simplify the generated code. Additionally, this helps
50 // to ensure that the ambiguities are intentionally resolved by the user.
52 // The matching is divided into two distinct phases:
54 // 1. Classification: Each operand is mapped to the unique set which (a)
55 // contains it, and (b) is the largest such subset for which a single
56 // instruction could match all members.
58 // For register classes, we can generate these subgroups automatically. For
59 // arbitrary operands, we expect the user to define the classes and their
60 // relations to one another (for example, 8-bit signed immediates as a
61 // subset of 32-bit immediates).
63 // By partitioning the operands in this way, we guarantee that for any
64 // tuple of classes, any single instruction must match either all or none
65 // of the sets of operands which could classify to that tuple.
67 // In addition, the subset relation amongst classes induces a partial order
68 // on such tuples, which we use to resolve ambiguities.
70 // 2. The input can now be treated as a tuple of classes (static tokens are
71 // simple singleton sets). Each such tuple should generally map to a single
72 // instruction (we currently ignore cases where this isn't true, whee!!!),
73 // which we can emit a simple matcher for.
75 // Custom Operand Parsing
76 // ----------------------
78 // Some targets need a custom way to parse operands, some specific instructions
79 // can contain arguments that can represent processor flags and other kinds of
80 // identifiers that need to be mapped to specific valeus in the final encoded
81 // instructions. The target specific custom operand parsing works in the
84 // 1. A operand match table is built, each entry contains a mnemonic, an
85 // operand class, a mask for all operand positions for that same
86 // class/mnemonic and target features to be checked while trying to match.
88 // 2. The operand matcher will try every possible entry with the same
89 // mnemonic and will check if the target feature for this mnemonic also
90 // matches. After that, if the operand to be matched has its index
91 // present in the mask, a successful match occurs. Otherwise, fallback
92 // to the regular operand parsing.
94 // 3. For a match success, each operand class that has a 'ParserMethod'
95 // becomes part of a switch from where the custom method is called.
97 //===----------------------------------------------------------------------===//
99 #include "CodeGenTarget.h"
100 #include "StringToOffsetTable.h"
101 #include "llvm/ADT/OwningPtr.h"
102 #include "llvm/ADT/PointerUnion.h"
103 #include "llvm/ADT/SmallPtrSet.h"
104 #include "llvm/ADT/SmallVector.h"
105 #include "llvm/ADT/STLExtras.h"
106 #include "llvm/ADT/StringExtras.h"
107 #include "llvm/Support/CommandLine.h"
108 #include "llvm/Support/Debug.h"
109 #include "llvm/Support/ErrorHandling.h"
110 #include "llvm/TableGen/Error.h"
111 #include "llvm/TableGen/Record.h"
112 #include "llvm/TableGen/StringMatcher.h"
113 #include "llvm/TableGen/TableGenBackend.h"
117 using namespace llvm;
119 static cl::opt<std::string>
120 MatchPrefix("match-prefix", cl::init(""),
121 cl::desc("Only match instructions with the given prefix"));
124 class AsmMatcherInfo;
125 struct SubtargetFeatureInfo;
127 class AsmMatcherEmitter {
128 RecordKeeper &Records;
130 AsmMatcherEmitter(RecordKeeper &R) : Records(R) {}
132 void run(raw_ostream &o);
135 /// ClassInfo - Helper class for storing the information about a particular
136 /// class of operands which can be matched.
139 /// Invalid kind, for use as a sentinel value.
142 /// The class for a particular token.
145 /// The (first) register class, subsequent register classes are
146 /// RegisterClass0+1, and so on.
149 /// The (first) user defined class, subsequent user defined classes are
150 /// UserClass0+1, and so on.
154 /// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
155 /// N) for the Nth user defined class.
158 /// SuperClasses - The super classes of this class. Note that for simplicities
159 /// sake user operands only record their immediate super class, while register
160 /// operands include all superclasses.
161 std::vector<ClassInfo*> SuperClasses;
163 /// Name - The full class name, suitable for use in an enum.
166 /// ClassName - The unadorned generic name for this class (e.g., Token).
167 std::string ClassName;
169 /// ValueName - The name of the value this class represents; for a token this
170 /// is the literal token string, for an operand it is the TableGen class (or
171 /// empty if this is a derived class).
172 std::string ValueName;
174 /// PredicateMethod - The name of the operand method to test whether the
175 /// operand matches this class; this is not valid for Token or register kinds.
176 std::string PredicateMethod;
178 /// RenderMethod - The name of the operand method to add this operand to an
179 /// MCInst; this is not valid for Token or register kinds.
180 std::string RenderMethod;
182 /// ParserMethod - The name of the operand method to do a target specific
183 /// parsing on the operand.
184 std::string ParserMethod;
186 /// For register classes, the records for all the registers in this class.
187 std::set<Record*> Registers;
189 /// For custom match classes, he diagnostic kind for when the predicate fails.
190 std::string DiagnosticType;
192 /// isRegisterClass() - Check if this is a register class.
193 bool isRegisterClass() const {
194 return Kind >= RegisterClass0 && Kind < UserClass0;
197 /// isUserClass() - Check if this is a user defined class.
198 bool isUserClass() const {
199 return Kind >= UserClass0;
202 /// isRelatedTo - Check whether this class is "related" to \arg RHS. Classes
203 /// are related if they are in the same class hierarchy.
204 bool isRelatedTo(const ClassInfo &RHS) const {
205 // Tokens are only related to tokens.
206 if (Kind == Token || RHS.Kind == Token)
207 return Kind == Token && RHS.Kind == Token;
209 // Registers classes are only related to registers classes, and only if
210 // their intersection is non-empty.
211 if (isRegisterClass() || RHS.isRegisterClass()) {
212 if (!isRegisterClass() || !RHS.isRegisterClass())
215 std::set<Record*> Tmp;
216 std::insert_iterator< std::set<Record*> > II(Tmp, Tmp.begin());
217 std::set_intersection(Registers.begin(), Registers.end(),
218 RHS.Registers.begin(), RHS.Registers.end(),
224 // Otherwise we have two users operands; they are related if they are in the
225 // same class hierarchy.
227 // FIXME: This is an oversimplification, they should only be related if they
228 // intersect, however we don't have that information.
229 assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");
230 const ClassInfo *Root = this;
231 while (!Root->SuperClasses.empty())
232 Root = Root->SuperClasses.front();
234 const ClassInfo *RHSRoot = &RHS;
235 while (!RHSRoot->SuperClasses.empty())
236 RHSRoot = RHSRoot->SuperClasses.front();
238 return Root == RHSRoot;
241 /// isSubsetOf - Test whether this class is a subset of \arg RHS;
242 bool isSubsetOf(const ClassInfo &RHS) const {
243 // This is a subset of RHS if it is the same class...
247 // ... or if any of its super classes are a subset of RHS.
248 for (std::vector<ClassInfo*>::const_iterator it = SuperClasses.begin(),
249 ie = SuperClasses.end(); it != ie; ++it)
250 if ((*it)->isSubsetOf(RHS))
256 /// operator< - Compare two classes.
257 bool operator<(const ClassInfo &RHS) const {
261 // Unrelated classes can be ordered by kind.
262 if (!isRelatedTo(RHS))
263 return Kind < RHS.Kind;
267 llvm_unreachable("Invalid kind!");
270 // This class precedes the RHS if it is a proper subset of the RHS.
273 if (RHS.isSubsetOf(*this))
276 // Otherwise, order by name to ensure we have a total ordering.
277 return ValueName < RHS.ValueName;
282 /// MatchableInfo - Helper class for storing the necessary information for an
283 /// instruction or alias which is capable of being matched.
284 struct MatchableInfo {
286 /// Token - This is the token that the operand came from.
289 /// The unique class instance this operand should match.
292 /// The operand name this is, if anything.
295 /// The suboperand index within SrcOpName, or -1 for the entire operand.
298 /// Register record if this token is singleton register.
299 Record *SingletonReg;
301 explicit AsmOperand(StringRef T) : Token(T), Class(0), SubOpIdx(-1),
305 /// ResOperand - This represents a single operand in the result instruction
306 /// generated by the match. In cases (like addressing modes) where a single
307 /// assembler operand expands to multiple MCOperands, this represents the
308 /// single assembler operand, not the MCOperand.
311 /// RenderAsmOperand - This represents an operand result that is
312 /// generated by calling the render method on the assembly operand. The
313 /// corresponding AsmOperand is specified by AsmOperandNum.
316 /// TiedOperand - This represents a result operand that is a duplicate of
317 /// a previous result operand.
320 /// ImmOperand - This represents an immediate value that is dumped into
324 /// RegOperand - This represents a fixed register that is dumped in.
329 /// This is the operand # in the AsmOperands list that this should be
331 unsigned AsmOperandNum;
333 /// TiedOperandNum - This is the (earlier) result operand that should be
335 unsigned TiedOperandNum;
337 /// ImmVal - This is the immediate value added to the instruction.
340 /// Register - This is the register record.
344 /// MINumOperands - The number of MCInst operands populated by this
346 unsigned MINumOperands;
348 static ResOperand getRenderedOp(unsigned AsmOpNum, unsigned NumOperands) {
350 X.Kind = RenderAsmOperand;
351 X.AsmOperandNum = AsmOpNum;
352 X.MINumOperands = NumOperands;
356 static ResOperand getTiedOp(unsigned TiedOperandNum) {
358 X.Kind = TiedOperand;
359 X.TiedOperandNum = TiedOperandNum;
364 static ResOperand getImmOp(int64_t Val) {
372 static ResOperand getRegOp(Record *Reg) {
381 /// AsmVariantID - Target's assembly syntax variant no.
384 /// TheDef - This is the definition of the instruction or InstAlias that this
385 /// matchable came from.
386 Record *const TheDef;
388 /// DefRec - This is the definition that it came from.
389 PointerUnion<const CodeGenInstruction*, const CodeGenInstAlias*> DefRec;
391 const CodeGenInstruction *getResultInst() const {
392 if (DefRec.is<const CodeGenInstruction*>())
393 return DefRec.get<const CodeGenInstruction*>();
394 return DefRec.get<const CodeGenInstAlias*>()->ResultInst;
397 /// ResOperands - This is the operand list that should be built for the result
399 SmallVector<ResOperand, 8> ResOperands;
401 /// AsmString - The assembly string for this instruction (with variants
402 /// removed), e.g. "movsx $src, $dst".
403 std::string AsmString;
405 /// Mnemonic - This is the first token of the matched instruction, its
409 /// AsmOperands - The textual operands that this instruction matches,
410 /// annotated with a class and where in the OperandList they were defined.
411 /// This directly corresponds to the tokenized AsmString after the mnemonic is
413 SmallVector<AsmOperand, 8> AsmOperands;
415 /// Predicates - The required subtarget features to match this instruction.
416 SmallVector<SubtargetFeatureInfo*, 4> RequiredFeatures;
418 /// ConversionFnKind - The enum value which is passed to the generated
419 /// ConvertToMCInst to convert parsed operands into an MCInst for this
421 std::string ConversionFnKind;
423 MatchableInfo(const CodeGenInstruction &CGI)
424 : AsmVariantID(0), TheDef(CGI.TheDef), DefRec(&CGI),
425 AsmString(CGI.AsmString) {
428 MatchableInfo(const CodeGenInstAlias *Alias)
429 : AsmVariantID(0), TheDef(Alias->TheDef), DefRec(Alias),
430 AsmString(Alias->AsmString) {
433 // Two-operand aliases clone from the main matchable, but mark the second
434 // operand as a tied operand of the first for purposes of the assembler.
435 void formTwoOperandAlias(StringRef Constraint);
437 void initialize(const AsmMatcherInfo &Info,
438 SmallPtrSet<Record*, 16> &SingletonRegisters,
439 int AsmVariantNo, std::string &RegisterPrefix);
441 /// validate - Return true if this matchable is a valid thing to match against
442 /// and perform a bunch of validity checking.
443 bool validate(StringRef CommentDelimiter, bool Hack) const;
445 /// extractSingletonRegisterForAsmOperand - Extract singleton register,
446 /// if present, from specified token.
448 extractSingletonRegisterForAsmOperand(unsigned i, const AsmMatcherInfo &Info,
449 std::string &RegisterPrefix);
451 /// findAsmOperand - Find the AsmOperand with the specified name and
452 /// suboperand index.
453 int findAsmOperand(StringRef N, int SubOpIdx) const {
454 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
455 if (N == AsmOperands[i].SrcOpName &&
456 SubOpIdx == AsmOperands[i].SubOpIdx)
461 /// findAsmOperandNamed - Find the first AsmOperand with the specified name.
462 /// This does not check the suboperand index.
463 int findAsmOperandNamed(StringRef N) const {
464 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
465 if (N == AsmOperands[i].SrcOpName)
470 void buildInstructionResultOperands();
471 void buildAliasResultOperands();
473 /// operator< - Compare two matchables.
474 bool operator<(const MatchableInfo &RHS) const {
475 // The primary comparator is the instruction mnemonic.
476 if (Mnemonic != RHS.Mnemonic)
477 return Mnemonic < RHS.Mnemonic;
479 if (AsmOperands.size() != RHS.AsmOperands.size())
480 return AsmOperands.size() < RHS.AsmOperands.size();
482 // Compare lexicographically by operand. The matcher validates that other
483 // orderings wouldn't be ambiguous using \see couldMatchAmbiguouslyWith().
484 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
485 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
487 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
491 // Give matches that require more features higher precedence. This is useful
492 // because we cannot define AssemblerPredicates with the negation of
493 // processor features. For example, ARM v6 "nop" may be either a HINT or
494 // MOV. With v6, we want to match HINT. The assembler has no way to
495 // predicate MOV under "NoV6", but HINT will always match first because it
496 // requires V6 while MOV does not.
497 if (RequiredFeatures.size() != RHS.RequiredFeatures.size())
498 return RequiredFeatures.size() > RHS.RequiredFeatures.size();
503 /// couldMatchAmbiguouslyWith - Check whether this matchable could
504 /// ambiguously match the same set of operands as \arg RHS (without being a
505 /// strictly superior match).
506 bool couldMatchAmbiguouslyWith(const MatchableInfo &RHS) {
507 // The primary comparator is the instruction mnemonic.
508 if (Mnemonic != RHS.Mnemonic)
511 // The number of operands is unambiguous.
512 if (AsmOperands.size() != RHS.AsmOperands.size())
515 // Otherwise, make sure the ordering of the two instructions is unambiguous
516 // by checking that either (a) a token or operand kind discriminates them,
517 // or (b) the ordering among equivalent kinds is consistent.
519 // Tokens and operand kinds are unambiguous (assuming a correct target
521 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
522 if (AsmOperands[i].Class->Kind != RHS.AsmOperands[i].Class->Kind ||
523 AsmOperands[i].Class->Kind == ClassInfo::Token)
524 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class ||
525 *RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
528 // Otherwise, this operand could commute if all operands are equivalent, or
529 // there is a pair of operands that compare less than and a pair that
530 // compare greater than.
531 bool HasLT = false, HasGT = false;
532 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
533 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
535 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
539 return !(HasLT ^ HasGT);
545 void tokenizeAsmString(const AsmMatcherInfo &Info);
548 /// SubtargetFeatureInfo - Helper class for storing information on a subtarget
549 /// feature which participates in instruction matching.
550 struct SubtargetFeatureInfo {
551 /// \brief The predicate record for this feature.
554 /// \brief An unique index assigned to represent this feature.
557 SubtargetFeatureInfo(Record *D, unsigned Idx) : TheDef(D), Index(Idx) {}
559 /// \brief The name of the enumerated constant identifying this feature.
560 std::string getEnumName() const {
561 return "Feature_" + TheDef->getName();
565 struct OperandMatchEntry {
566 unsigned OperandMask;
570 static OperandMatchEntry create(MatchableInfo* mi, ClassInfo *ci,
573 X.OperandMask = opMask;
581 class AsmMatcherInfo {
584 RecordKeeper &Records;
586 /// The tablegen AsmParser record.
589 /// Target - The target information.
590 CodeGenTarget &Target;
592 /// The classes which are needed for matching.
593 std::vector<ClassInfo*> Classes;
595 /// The information on the matchables to match.
596 std::vector<MatchableInfo*> Matchables;
598 /// Info for custom matching operands by user defined methods.
599 std::vector<OperandMatchEntry> OperandMatchInfo;
601 /// Map of Register records to their class information.
602 std::map<Record*, ClassInfo*> RegisterClasses;
604 /// Map of Predicate records to their subtarget information.
605 std::map<Record*, SubtargetFeatureInfo*> SubtargetFeatures;
607 /// Map of AsmOperandClass records to their class information.
608 std::map<Record*, ClassInfo*> AsmOperandClasses;
611 /// Map of token to class information which has already been constructed.
612 std::map<std::string, ClassInfo*> TokenClasses;
614 /// Map of RegisterClass records to their class information.
615 std::map<Record*, ClassInfo*> RegisterClassClasses;
618 /// getTokenClass - Lookup or create the class for the given token.
619 ClassInfo *getTokenClass(StringRef Token);
621 /// getOperandClass - Lookup or create the class for the given operand.
622 ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI,
624 ClassInfo *getOperandClass(Record *Rec, int SubOpIdx);
626 /// buildRegisterClasses - Build the ClassInfo* instances for register
628 void buildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters);
630 /// buildOperandClasses - Build the ClassInfo* instances for user defined
632 void buildOperandClasses();
634 void buildInstructionOperandReference(MatchableInfo *II, StringRef OpName,
636 void buildAliasOperandReference(MatchableInfo *II, StringRef OpName,
637 MatchableInfo::AsmOperand &Op);
640 AsmMatcherInfo(Record *AsmParser,
641 CodeGenTarget &Target,
642 RecordKeeper &Records);
644 /// buildInfo - Construct the various tables used during matching.
647 /// buildOperandMatchInfo - Build the necessary information to handle user
648 /// defined operand parsing methods.
649 void buildOperandMatchInfo();
651 /// getSubtargetFeature - Lookup or create the subtarget feature info for the
653 SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const {
654 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
655 std::map<Record*, SubtargetFeatureInfo*>::const_iterator I =
656 SubtargetFeatures.find(Def);
657 return I == SubtargetFeatures.end() ? 0 : I->second;
660 RecordKeeper &getRecords() const {
665 } // End anonymous namespace
667 void MatchableInfo::dump() {
668 errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n";
670 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
671 AsmOperand &Op = AsmOperands[i];
672 errs() << " op[" << i << "] = " << Op.Class->ClassName << " - ";
673 errs() << '\"' << Op.Token << "\"\n";
677 static std::pair<StringRef, StringRef>
678 parseTwoOperandConstraint(StringRef S, ArrayRef<SMLoc> Loc) {
679 // Split via the '='.
680 std::pair<StringRef, StringRef> Ops = S.split('=');
681 if (Ops.second == "")
682 throw TGError(Loc, "missing '=' in two-operand alias constraint");
683 // Trim whitespace and the leading '$' on the operand names.
684 size_t start = Ops.first.find_first_of('$');
685 if (start == std::string::npos)
686 throw TGError(Loc, "expected '$' prefix on asm operand name");
687 Ops.first = Ops.first.slice(start + 1, std::string::npos);
688 size_t end = Ops.first.find_last_of(" \t");
689 Ops.first = Ops.first.slice(0, end);
690 // Now the second operand.
691 start = Ops.second.find_first_of('$');
692 if (start == std::string::npos)
693 throw TGError(Loc, "expected '$' prefix on asm operand name");
694 Ops.second = Ops.second.slice(start + 1, std::string::npos);
695 end = Ops.second.find_last_of(" \t");
696 Ops.first = Ops.first.slice(0, end);
700 void MatchableInfo::formTwoOperandAlias(StringRef Constraint) {
701 // Figure out which operands are aliased and mark them as tied.
702 std::pair<StringRef, StringRef> Ops =
703 parseTwoOperandConstraint(Constraint, TheDef->getLoc());
705 // Find the AsmOperands that refer to the operands we're aliasing.
706 int SrcAsmOperand = findAsmOperandNamed(Ops.first);
707 int DstAsmOperand = findAsmOperandNamed(Ops.second);
708 if (SrcAsmOperand == -1)
709 throw TGError(TheDef->getLoc(),
710 "unknown source two-operand alias operand '" +
711 Ops.first.str() + "'.");
712 if (DstAsmOperand == -1)
713 throw TGError(TheDef->getLoc(),
714 "unknown destination two-operand alias operand '" +
715 Ops.second.str() + "'.");
717 // Find the ResOperand that refers to the operand we're aliasing away
718 // and update it to refer to the combined operand instead.
719 for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) {
720 ResOperand &Op = ResOperands[i];
721 if (Op.Kind == ResOperand::RenderAsmOperand &&
722 Op.AsmOperandNum == (unsigned)SrcAsmOperand) {
723 Op.AsmOperandNum = DstAsmOperand;
727 // Remove the AsmOperand for the alias operand.
728 AsmOperands.erase(AsmOperands.begin() + SrcAsmOperand);
729 // Adjust the ResOperand references to any AsmOperands that followed
730 // the one we just deleted.
731 for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) {
732 ResOperand &Op = ResOperands[i];
735 // Nothing to do for operands that don't reference AsmOperands.
737 case ResOperand::RenderAsmOperand:
738 if (Op.AsmOperandNum > (unsigned)SrcAsmOperand)
741 case ResOperand::TiedOperand:
742 if (Op.TiedOperandNum > (unsigned)SrcAsmOperand)
749 void MatchableInfo::initialize(const AsmMatcherInfo &Info,
750 SmallPtrSet<Record*, 16> &SingletonRegisters,
751 int AsmVariantNo, std::string &RegisterPrefix) {
752 AsmVariantID = AsmVariantNo;
754 CodeGenInstruction::FlattenAsmStringVariants(AsmString, AsmVariantNo);
756 tokenizeAsmString(Info);
758 // Compute the require features.
759 std::vector<Record*> Predicates =TheDef->getValueAsListOfDefs("Predicates");
760 for (unsigned i = 0, e = Predicates.size(); i != e; ++i)
761 if (SubtargetFeatureInfo *Feature =
762 Info.getSubtargetFeature(Predicates[i]))
763 RequiredFeatures.push_back(Feature);
765 // Collect singleton registers, if used.
766 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
767 extractSingletonRegisterForAsmOperand(i, Info, RegisterPrefix);
768 if (Record *Reg = AsmOperands[i].SingletonReg)
769 SingletonRegisters.insert(Reg);
773 /// tokenizeAsmString - Tokenize a simplified assembly string.
774 void MatchableInfo::tokenizeAsmString(const AsmMatcherInfo &Info) {
775 StringRef String = AsmString;
778 for (unsigned i = 0, e = String.size(); i != e; ++i) {
788 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
791 if (!isspace(String[i]) && String[i] != ',')
792 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
798 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
802 assert(i != String.size() && "Invalid quoted character");
803 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
809 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
813 // If this isn't "${", treat like a normal token.
814 if (i + 1 == String.size() || String[i + 1] != '{') {
819 StringRef::iterator End = std::find(String.begin() + i, String.end(),'}');
820 assert(End != String.end() && "Missing brace in operand reference!");
821 size_t EndPos = End - String.begin();
822 AsmOperands.push_back(AsmOperand(String.slice(i, EndPos+1)));
830 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
839 if (InTok && Prev != String.size())
840 AsmOperands.push_back(AsmOperand(String.substr(Prev)));
842 // The first token of the instruction is the mnemonic, which must be a
843 // simple string, not a $foo variable or a singleton register.
844 if (AsmOperands.empty())
845 throw TGError(TheDef->getLoc(),
846 "Instruction '" + TheDef->getName() + "' has no tokens");
847 Mnemonic = AsmOperands[0].Token;
848 if (Mnemonic.empty())
849 throw TGError(TheDef->getLoc(),
850 "Missing instruction mnemonic");
851 // FIXME : Check and raise an error if it is a register.
852 if (Mnemonic[0] == '$')
853 throw TGError(TheDef->getLoc(),
854 "Invalid instruction mnemonic '" + Mnemonic.str() + "'!");
856 // Remove the first operand, it is tracked in the mnemonic field.
857 AsmOperands.erase(AsmOperands.begin());
860 bool MatchableInfo::validate(StringRef CommentDelimiter, bool Hack) const {
861 // Reject matchables with no .s string.
862 if (AsmString.empty())
863 throw TGError(TheDef->getLoc(), "instruction with empty asm string");
865 // Reject any matchables with a newline in them, they should be marked
866 // isCodeGenOnly if they are pseudo instructions.
867 if (AsmString.find('\n') != std::string::npos)
868 throw TGError(TheDef->getLoc(),
869 "multiline instruction is not valid for the asmparser, "
870 "mark it isCodeGenOnly");
872 // Remove comments from the asm string. We know that the asmstring only
874 if (!CommentDelimiter.empty() &&
875 StringRef(AsmString).find(CommentDelimiter) != StringRef::npos)
876 throw TGError(TheDef->getLoc(),
877 "asmstring for instruction has comment character in it, "
878 "mark it isCodeGenOnly");
880 // Reject matchables with operand modifiers, these aren't something we can
881 // handle, the target should be refactored to use operands instead of
884 // Also, check for instructions which reference the operand multiple times;
885 // this implies a constraint we would not honor.
886 std::set<std::string> OperandNames;
887 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
888 StringRef Tok = AsmOperands[i].Token;
889 if (Tok[0] == '$' && Tok.find(':') != StringRef::npos)
890 throw TGError(TheDef->getLoc(),
891 "matchable with operand modifier '" + Tok.str() +
892 "' not supported by asm matcher. Mark isCodeGenOnly!");
894 // Verify that any operand is only mentioned once.
895 // We reject aliases and ignore instructions for now.
896 if (Tok[0] == '$' && !OperandNames.insert(Tok).second) {
898 throw TGError(TheDef->getLoc(),
899 "ERROR: matchable with tied operand '" + Tok.str() +
900 "' can never be matched!");
901 // FIXME: Should reject these. The ARM backend hits this with $lane in a
902 // bunch of instructions. It is unclear what the right answer is.
904 errs() << "warning: '" << TheDef->getName() << "': "
905 << "ignoring instruction with tied operand '"
906 << Tok.str() << "'\n";
915 /// extractSingletonRegisterForAsmOperand - Extract singleton register,
916 /// if present, from specified token.
918 extractSingletonRegisterForAsmOperand(unsigned OperandNo,
919 const AsmMatcherInfo &Info,
920 std::string &RegisterPrefix) {
921 StringRef Tok = AsmOperands[OperandNo].Token;
922 if (RegisterPrefix.empty()) {
923 std::string LoweredTok = Tok.lower();
924 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(LoweredTok))
925 AsmOperands[OperandNo].SingletonReg = Reg->TheDef;
929 if (!Tok.startswith(RegisterPrefix))
932 StringRef RegName = Tok.substr(RegisterPrefix.size());
933 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName))
934 AsmOperands[OperandNo].SingletonReg = Reg->TheDef;
936 // If there is no register prefix (i.e. "%" in "%eax"), then this may
937 // be some random non-register token, just ignore it.
941 static std::string getEnumNameForToken(StringRef Str) {
944 for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) {
946 case '*': Res += "_STAR_"; break;
947 case '%': Res += "_PCT_"; break;
948 case ':': Res += "_COLON_"; break;
949 case '!': Res += "_EXCLAIM_"; break;
950 case '.': Res += "_DOT_"; break;
955 Res += "_" + utostr((unsigned) *it) + "_";
962 ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) {
963 ClassInfo *&Entry = TokenClasses[Token];
966 Entry = new ClassInfo();
967 Entry->Kind = ClassInfo::Token;
968 Entry->ClassName = "Token";
969 Entry->Name = "MCK_" + getEnumNameForToken(Token);
970 Entry->ValueName = Token;
971 Entry->PredicateMethod = "<invalid>";
972 Entry->RenderMethod = "<invalid>";
973 Entry->ParserMethod = "";
974 Entry->DiagnosticType = "";
975 Classes.push_back(Entry);
982 AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI,
984 Record *Rec = OI.Rec;
986 Rec = dynamic_cast<DefInit*>(OI.MIOperandInfo->getArg(SubOpIdx))->getDef();
987 return getOperandClass(Rec, SubOpIdx);
991 AsmMatcherInfo::getOperandClass(Record *Rec, int SubOpIdx) {
992 if (Rec->isSubClassOf("RegisterOperand")) {
993 // RegisterOperand may have an associated ParserMatchClass. If it does,
994 // use it, else just fall back to the underlying register class.
995 const RecordVal *R = Rec->getValue("ParserMatchClass");
996 if (R == 0 || R->getValue() == 0)
997 throw "Record `" + Rec->getName() +
998 "' does not have a ParserMatchClass!\n";
1000 if (DefInit *DI= dynamic_cast<DefInit*>(R->getValue())) {
1001 Record *MatchClass = DI->getDef();
1002 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1006 // No custom match class. Just use the register class.
1007 Record *ClassRec = Rec->getValueAsDef("RegClass");
1009 throw TGError(Rec->getLoc(), "RegisterOperand `" + Rec->getName() +
1010 "' has no associated register class!\n");
1011 if (ClassInfo *CI = RegisterClassClasses[ClassRec])
1013 throw TGError(Rec->getLoc(), "register class has no class info!");
1017 if (Rec->isSubClassOf("RegisterClass")) {
1018 if (ClassInfo *CI = RegisterClassClasses[Rec])
1020 throw TGError(Rec->getLoc(), "register class has no class info!");
1023 assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
1024 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1025 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1028 throw TGError(Rec->getLoc(), "operand has no match class!");
1031 void AsmMatcherInfo::
1032 buildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters) {
1033 const std::vector<CodeGenRegister*> &Registers =
1034 Target.getRegBank().getRegisters();
1035 ArrayRef<CodeGenRegisterClass*> RegClassList =
1036 Target.getRegBank().getRegClasses();
1038 // The register sets used for matching.
1039 std::set< std::set<Record*> > RegisterSets;
1041 // Gather the defined sets.
1042 for (ArrayRef<CodeGenRegisterClass*>::const_iterator it =
1043 RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it)
1044 RegisterSets.insert(std::set<Record*>(
1045 (*it)->getOrder().begin(), (*it)->getOrder().end()));
1047 // Add any required singleton sets.
1048 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
1049 ie = SingletonRegisters.end(); it != ie; ++it) {
1051 RegisterSets.insert(std::set<Record*>(&Rec, &Rec + 1));
1054 // Introduce derived sets where necessary (when a register does not determine
1055 // a unique register set class), and build the mapping of registers to the set
1056 // they should classify to.
1057 std::map<Record*, std::set<Record*> > RegisterMap;
1058 for (std::vector<CodeGenRegister*>::const_iterator it = Registers.begin(),
1059 ie = Registers.end(); it != ie; ++it) {
1060 const CodeGenRegister &CGR = **it;
1061 // Compute the intersection of all sets containing this register.
1062 std::set<Record*> ContainingSet;
1064 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
1065 ie = RegisterSets.end(); it != ie; ++it) {
1066 if (!it->count(CGR.TheDef))
1069 if (ContainingSet.empty()) {
1070 ContainingSet = *it;
1074 std::set<Record*> Tmp;
1075 std::swap(Tmp, ContainingSet);
1076 std::insert_iterator< std::set<Record*> > II(ContainingSet,
1077 ContainingSet.begin());
1078 std::set_intersection(Tmp.begin(), Tmp.end(), it->begin(), it->end(), II);
1081 if (!ContainingSet.empty()) {
1082 RegisterSets.insert(ContainingSet);
1083 RegisterMap.insert(std::make_pair(CGR.TheDef, ContainingSet));
1087 // Construct the register classes.
1088 std::map<std::set<Record*>, ClassInfo*> RegisterSetClasses;
1090 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
1091 ie = RegisterSets.end(); it != ie; ++it, ++Index) {
1092 ClassInfo *CI = new ClassInfo();
1093 CI->Kind = ClassInfo::RegisterClass0 + Index;
1094 CI->ClassName = "Reg" + utostr(Index);
1095 CI->Name = "MCK_Reg" + utostr(Index);
1097 CI->PredicateMethod = ""; // unused
1098 CI->RenderMethod = "addRegOperands";
1099 CI->Registers = *it;
1100 // FIXME: diagnostic type.
1101 CI->DiagnosticType = "";
1102 Classes.push_back(CI);
1103 RegisterSetClasses.insert(std::make_pair(*it, CI));
1106 // Find the superclasses; we could compute only the subgroup lattice edges,
1107 // but there isn't really a point.
1108 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
1109 ie = RegisterSets.end(); it != ie; ++it) {
1110 ClassInfo *CI = RegisterSetClasses[*it];
1111 for (std::set< std::set<Record*> >::iterator it2 = RegisterSets.begin(),
1112 ie2 = RegisterSets.end(); it2 != ie2; ++it2)
1114 std::includes(it2->begin(), it2->end(), it->begin(), it->end()))
1115 CI->SuperClasses.push_back(RegisterSetClasses[*it2]);
1118 // Name the register classes which correspond to a user defined RegisterClass.
1119 for (ArrayRef<CodeGenRegisterClass*>::const_iterator
1120 it = RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it) {
1121 const CodeGenRegisterClass &RC = **it;
1122 // Def will be NULL for non-user defined register classes.
1123 Record *Def = RC.getDef();
1126 ClassInfo *CI = RegisterSetClasses[std::set<Record*>(RC.getOrder().begin(),
1127 RC.getOrder().end())];
1128 if (CI->ValueName.empty()) {
1129 CI->ClassName = RC.getName();
1130 CI->Name = "MCK_" + RC.getName();
1131 CI->ValueName = RC.getName();
1133 CI->ValueName = CI->ValueName + "," + RC.getName();
1135 RegisterClassClasses.insert(std::make_pair(Def, CI));
1138 // Populate the map for individual registers.
1139 for (std::map<Record*, std::set<Record*> >::iterator it = RegisterMap.begin(),
1140 ie = RegisterMap.end(); it != ie; ++it)
1141 RegisterClasses[it->first] = RegisterSetClasses[it->second];
1143 // Name the register classes which correspond to singleton registers.
1144 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
1145 ie = SingletonRegisters.end(); it != ie; ++it) {
1147 ClassInfo *CI = RegisterClasses[Rec];
1148 assert(CI && "Missing singleton register class info!");
1150 if (CI->ValueName.empty()) {
1151 CI->ClassName = Rec->getName();
1152 CI->Name = "MCK_" + Rec->getName();
1153 CI->ValueName = Rec->getName();
1155 CI->ValueName = CI->ValueName + "," + Rec->getName();
1159 void AsmMatcherInfo::buildOperandClasses() {
1160 std::vector<Record*> AsmOperands =
1161 Records.getAllDerivedDefinitions("AsmOperandClass");
1163 // Pre-populate AsmOperandClasses map.
1164 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
1165 ie = AsmOperands.end(); it != ie; ++it)
1166 AsmOperandClasses[*it] = new ClassInfo();
1169 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
1170 ie = AsmOperands.end(); it != ie; ++it, ++Index) {
1171 ClassInfo *CI = AsmOperandClasses[*it];
1172 CI->Kind = ClassInfo::UserClass0 + Index;
1174 ListInit *Supers = (*it)->getValueAsListInit("SuperClasses");
1175 for (unsigned i = 0, e = Supers->getSize(); i != e; ++i) {
1176 DefInit *DI = dynamic_cast<DefInit*>(Supers->getElement(i));
1178 PrintError((*it)->getLoc(), "Invalid super class reference!");
1182 ClassInfo *SC = AsmOperandClasses[DI->getDef()];
1184 PrintError((*it)->getLoc(), "Invalid super class reference!");
1186 CI->SuperClasses.push_back(SC);
1188 CI->ClassName = (*it)->getValueAsString("Name");
1189 CI->Name = "MCK_" + CI->ClassName;
1190 CI->ValueName = (*it)->getName();
1192 // Get or construct the predicate method name.
1193 Init *PMName = (*it)->getValueInit("PredicateMethod");
1194 if (StringInit *SI = dynamic_cast<StringInit*>(PMName)) {
1195 CI->PredicateMethod = SI->getValue();
1197 assert(dynamic_cast<UnsetInit*>(PMName) &&
1198 "Unexpected PredicateMethod field!");
1199 CI->PredicateMethod = "is" + CI->ClassName;
1202 // Get or construct the render method name.
1203 Init *RMName = (*it)->getValueInit("RenderMethod");
1204 if (StringInit *SI = dynamic_cast<StringInit*>(RMName)) {
1205 CI->RenderMethod = SI->getValue();
1207 assert(dynamic_cast<UnsetInit*>(RMName) &&
1208 "Unexpected RenderMethod field!");
1209 CI->RenderMethod = "add" + CI->ClassName + "Operands";
1212 // Get the parse method name or leave it as empty.
1213 Init *PRMName = (*it)->getValueInit("ParserMethod");
1214 if (StringInit *SI = dynamic_cast<StringInit*>(PRMName))
1215 CI->ParserMethod = SI->getValue();
1217 // Get the diagnostic type or leave it as empty.
1218 // Get the parse method name or leave it as empty.
1219 Init *DiagnosticType = (*it)->getValueInit("DiagnosticType");
1220 if (StringInit *SI = dynamic_cast<StringInit*>(DiagnosticType))
1221 CI->DiagnosticType = SI->getValue();
1223 AsmOperandClasses[*it] = CI;
1224 Classes.push_back(CI);
1228 AsmMatcherInfo::AsmMatcherInfo(Record *asmParser,
1229 CodeGenTarget &target,
1230 RecordKeeper &records)
1231 : Records(records), AsmParser(asmParser), Target(target) {
1234 /// buildOperandMatchInfo - Build the necessary information to handle user
1235 /// defined operand parsing methods.
1236 void AsmMatcherInfo::buildOperandMatchInfo() {
1238 /// Map containing a mask with all operands indices that can be found for
1239 /// that class inside a instruction.
1240 std::map<ClassInfo*, unsigned> OpClassMask;
1242 for (std::vector<MatchableInfo*>::const_iterator it =
1243 Matchables.begin(), ie = Matchables.end();
1245 MatchableInfo &II = **it;
1246 OpClassMask.clear();
1248 // Keep track of all operands of this instructions which belong to the
1250 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) {
1251 MatchableInfo::AsmOperand &Op = II.AsmOperands[i];
1252 if (Op.Class->ParserMethod.empty())
1254 unsigned &OperandMask = OpClassMask[Op.Class];
1255 OperandMask |= (1 << i);
1258 // Generate operand match info for each mnemonic/operand class pair.
1259 for (std::map<ClassInfo*, unsigned>::iterator iit = OpClassMask.begin(),
1260 iie = OpClassMask.end(); iit != iie; ++iit) {
1261 unsigned OpMask = iit->second;
1262 ClassInfo *CI = iit->first;
1263 OperandMatchInfo.push_back(OperandMatchEntry::create(&II, CI, OpMask));
1268 void AsmMatcherInfo::buildInfo() {
1269 // Build information about all of the AssemblerPredicates.
1270 std::vector<Record*> AllPredicates =
1271 Records.getAllDerivedDefinitions("Predicate");
1272 for (unsigned i = 0, e = AllPredicates.size(); i != e; ++i) {
1273 Record *Pred = AllPredicates[i];
1274 // Ignore predicates that are not intended for the assembler.
1275 if (!Pred->getValueAsBit("AssemblerMatcherPredicate"))
1278 if (Pred->getName().empty())
1279 throw TGError(Pred->getLoc(), "Predicate has no name!");
1281 unsigned FeatureNo = SubtargetFeatures.size();
1282 SubtargetFeatures[Pred] = new SubtargetFeatureInfo(Pred, FeatureNo);
1283 assert(FeatureNo < 32 && "Too many subtarget features!");
1286 // Parse the instructions; we need to do this first so that we can gather the
1287 // singleton register classes.
1288 SmallPtrSet<Record*, 16> SingletonRegisters;
1289 unsigned VariantCount = Target.getAsmParserVariantCount();
1290 for (unsigned VC = 0; VC != VariantCount; ++VC) {
1291 Record *AsmVariant = Target.getAsmParserVariant(VC);
1292 std::string CommentDelimiter =
1293 AsmVariant->getValueAsString("CommentDelimiter");
1294 std::string RegisterPrefix = AsmVariant->getValueAsString("RegisterPrefix");
1295 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
1297 for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
1298 E = Target.inst_end(); I != E; ++I) {
1299 const CodeGenInstruction &CGI = **I;
1301 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1302 // filter the set of instructions we consider.
1303 if (!StringRef(CGI.TheDef->getName()).startswith(MatchPrefix))
1306 // Ignore "codegen only" instructions.
1307 if (CGI.TheDef->getValueAsBit("isCodeGenOnly"))
1310 // Validate the operand list to ensure we can handle this instruction.
1311 for (unsigned i = 0, e = CGI.Operands.size(); i != e; ++i) {
1312 const CGIOperandList::OperandInfo &OI = CGI.Operands[i];
1314 // Validate tied operands.
1315 if (OI.getTiedRegister() != -1) {
1316 // If we have a tied operand that consists of multiple MCOperands,
1317 // reject it. We reject aliases and ignore instructions for now.
1318 if (OI.MINumOperands != 1) {
1319 // FIXME: Should reject these. The ARM backend hits this with $lane
1320 // in a bunch of instructions. The right answer is unclear.
1322 errs() << "warning: '" << CGI.TheDef->getName() << "': "
1323 << "ignoring instruction with multi-operand tied operand '"
1324 << OI.Name << "'\n";
1331 OwningPtr<MatchableInfo> II(new MatchableInfo(CGI));
1333 II->initialize(*this, SingletonRegisters, AsmVariantNo, RegisterPrefix);
1335 // Ignore instructions which shouldn't be matched and diagnose invalid
1336 // instruction definitions with an error.
1337 if (!II->validate(CommentDelimiter, true))
1340 // Ignore "Int_*" and "*_Int" instructions, which are internal aliases.
1342 // FIXME: This is a total hack.
1343 if (StringRef(II->TheDef->getName()).startswith("Int_") ||
1344 StringRef(II->TheDef->getName()).endswith("_Int"))
1347 Matchables.push_back(II.take());
1350 // Parse all of the InstAlias definitions and stick them in the list of
1352 std::vector<Record*> AllInstAliases =
1353 Records.getAllDerivedDefinitions("InstAlias");
1354 for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) {
1355 CodeGenInstAlias *Alias = new CodeGenInstAlias(AllInstAliases[i], Target);
1357 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1358 // filter the set of instruction aliases we consider, based on the target
1360 if (!StringRef(Alias->ResultInst->TheDef->getName())
1361 .startswith( MatchPrefix))
1364 OwningPtr<MatchableInfo> II(new MatchableInfo(Alias));
1366 II->initialize(*this, SingletonRegisters, AsmVariantNo, RegisterPrefix);
1368 // Validate the alias definitions.
1369 II->validate(CommentDelimiter, false);
1371 Matchables.push_back(II.take());
1375 // Build info for the register classes.
1376 buildRegisterClasses(SingletonRegisters);
1378 // Build info for the user defined assembly operand classes.
1379 buildOperandClasses();
1381 // Build the information about matchables, now that we have fully formed
1383 std::vector<MatchableInfo*> NewMatchables;
1384 for (std::vector<MatchableInfo*>::iterator it = Matchables.begin(),
1385 ie = Matchables.end(); it != ie; ++it) {
1386 MatchableInfo *II = *it;
1388 // Parse the tokens after the mnemonic.
1389 // Note: buildInstructionOperandReference may insert new AsmOperands, so
1390 // don't precompute the loop bound.
1391 for (unsigned i = 0; i != II->AsmOperands.size(); ++i) {
1392 MatchableInfo::AsmOperand &Op = II->AsmOperands[i];
1393 StringRef Token = Op.Token;
1395 // Check for singleton registers.
1396 if (Record *RegRecord = II->AsmOperands[i].SingletonReg) {
1397 Op.Class = RegisterClasses[RegRecord];
1398 assert(Op.Class && Op.Class->Registers.size() == 1 &&
1399 "Unexpected class for singleton register");
1403 // Check for simple tokens.
1404 if (Token[0] != '$') {
1405 Op.Class = getTokenClass(Token);
1409 if (Token.size() > 1 && isdigit(Token[1])) {
1410 Op.Class = getTokenClass(Token);
1414 // Otherwise this is an operand reference.
1415 StringRef OperandName;
1416 if (Token[1] == '{')
1417 OperandName = Token.substr(2, Token.size() - 3);
1419 OperandName = Token.substr(1);
1421 if (II->DefRec.is<const CodeGenInstruction*>())
1422 buildInstructionOperandReference(II, OperandName, i);
1424 buildAliasOperandReference(II, OperandName, Op);
1427 if (II->DefRec.is<const CodeGenInstruction*>()) {
1428 II->buildInstructionResultOperands();
1429 // If the instruction has a two-operand alias, build up the
1430 // matchable here. We'll add them in bulk at the end to avoid
1431 // confusing this loop.
1432 std::string Constraint =
1433 II->TheDef->getValueAsString("TwoOperandAliasConstraint");
1434 if (Constraint != "") {
1435 // Start by making a copy of the original matchable.
1436 OwningPtr<MatchableInfo> AliasII(new MatchableInfo(*II));
1438 // Adjust it to be a two-operand alias.
1439 AliasII->formTwoOperandAlias(Constraint);
1441 // Add the alias to the matchables list.
1442 NewMatchables.push_back(AliasII.take());
1445 II->buildAliasResultOperands();
1447 if (!NewMatchables.empty())
1448 Matchables.insert(Matchables.end(), NewMatchables.begin(),
1449 NewMatchables.end());
1451 // Process token alias definitions and set up the associated superclass
1453 std::vector<Record*> AllTokenAliases =
1454 Records.getAllDerivedDefinitions("TokenAlias");
1455 for (unsigned i = 0, e = AllTokenAliases.size(); i != e; ++i) {
1456 Record *Rec = AllTokenAliases[i];
1457 ClassInfo *FromClass = getTokenClass(Rec->getValueAsString("FromToken"));
1458 ClassInfo *ToClass = getTokenClass(Rec->getValueAsString("ToToken"));
1459 if (FromClass == ToClass)
1460 throw TGError(Rec->getLoc(),
1461 "error: Destination value identical to source value.");
1462 FromClass->SuperClasses.push_back(ToClass);
1465 // Reorder classes so that classes precede super classes.
1466 std::sort(Classes.begin(), Classes.end(), less_ptr<ClassInfo>());
1469 /// buildInstructionOperandReference - The specified operand is a reference to a
1470 /// named operand such as $src. Resolve the Class and OperandInfo pointers.
1471 void AsmMatcherInfo::
1472 buildInstructionOperandReference(MatchableInfo *II,
1473 StringRef OperandName,
1474 unsigned AsmOpIdx) {
1475 const CodeGenInstruction &CGI = *II->DefRec.get<const CodeGenInstruction*>();
1476 const CGIOperandList &Operands = CGI.Operands;
1477 MatchableInfo::AsmOperand *Op = &II->AsmOperands[AsmOpIdx];
1479 // Map this token to an operand.
1481 if (!Operands.hasOperandNamed(OperandName, Idx))
1482 throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" +
1483 OperandName.str() + "'");
1485 // If the instruction operand has multiple suboperands, but the parser
1486 // match class for the asm operand is still the default "ImmAsmOperand",
1487 // then handle each suboperand separately.
1488 if (Op->SubOpIdx == -1 && Operands[Idx].MINumOperands > 1) {
1489 Record *Rec = Operands[Idx].Rec;
1490 assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
1491 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1492 if (MatchClass && MatchClass->getValueAsString("Name") == "Imm") {
1493 // Insert remaining suboperands after AsmOpIdx in II->AsmOperands.
1494 StringRef Token = Op->Token; // save this in case Op gets moved
1495 for (unsigned SI = 1, SE = Operands[Idx].MINumOperands; SI != SE; ++SI) {
1496 MatchableInfo::AsmOperand NewAsmOp(Token);
1497 NewAsmOp.SubOpIdx = SI;
1498 II->AsmOperands.insert(II->AsmOperands.begin()+AsmOpIdx+SI, NewAsmOp);
1500 // Replace Op with first suboperand.
1501 Op = &II->AsmOperands[AsmOpIdx]; // update the pointer in case it moved
1506 // Set up the operand class.
1507 Op->Class = getOperandClass(Operands[Idx], Op->SubOpIdx);
1509 // If the named operand is tied, canonicalize it to the untied operand.
1510 // For example, something like:
1511 // (outs GPR:$dst), (ins GPR:$src)
1512 // with an asmstring of
1514 // we want to canonicalize to:
1516 // so that we know how to provide the $dst operand when filling in the result.
1517 int OITied = Operands[Idx].getTiedRegister();
1519 // The tied operand index is an MIOperand index, find the operand that
1521 std::pair<unsigned, unsigned> Idx = Operands.getSubOperandNumber(OITied);
1522 OperandName = Operands[Idx.first].Name;
1523 Op->SubOpIdx = Idx.second;
1526 Op->SrcOpName = OperandName;
1529 /// buildAliasOperandReference - When parsing an operand reference out of the
1530 /// matching string (e.g. "movsx $src, $dst"), determine what the class of the
1531 /// operand reference is by looking it up in the result pattern definition.
1532 void AsmMatcherInfo::buildAliasOperandReference(MatchableInfo *II,
1533 StringRef OperandName,
1534 MatchableInfo::AsmOperand &Op) {
1535 const CodeGenInstAlias &CGA = *II->DefRec.get<const CodeGenInstAlias*>();
1537 // Set up the operand class.
1538 for (unsigned i = 0, e = CGA.ResultOperands.size(); i != e; ++i)
1539 if (CGA.ResultOperands[i].isRecord() &&
1540 CGA.ResultOperands[i].getName() == OperandName) {
1541 // It's safe to go with the first one we find, because CodeGenInstAlias
1542 // validates that all operands with the same name have the same record.
1543 Op.SubOpIdx = CGA.ResultInstOperandIndex[i].second;
1544 // Use the match class from the Alias definition, not the
1545 // destination instruction, as we may have an immediate that's
1546 // being munged by the match class.
1547 Op.Class = getOperandClass(CGA.ResultOperands[i].getRecord(),
1549 Op.SrcOpName = OperandName;
1553 throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" +
1554 OperandName.str() + "'");
1557 void MatchableInfo::buildInstructionResultOperands() {
1558 const CodeGenInstruction *ResultInst = getResultInst();
1560 // Loop over all operands of the result instruction, determining how to
1562 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1563 const CGIOperandList::OperandInfo &OpInfo = ResultInst->Operands[i];
1565 // If this is a tied operand, just copy from the previously handled operand.
1566 int TiedOp = OpInfo.getTiedRegister();
1568 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1572 // Find out what operand from the asmparser this MCInst operand comes from.
1573 int SrcOperand = findAsmOperandNamed(OpInfo.Name);
1574 if (OpInfo.Name.empty() || SrcOperand == -1)
1575 throw TGError(TheDef->getLoc(), "Instruction '" +
1576 TheDef->getName() + "' has operand '" + OpInfo.Name +
1577 "' that doesn't appear in asm string!");
1579 // Check if the one AsmOperand populates the entire operand.
1580 unsigned NumOperands = OpInfo.MINumOperands;
1581 if (AsmOperands[SrcOperand].SubOpIdx == -1) {
1582 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, NumOperands));
1586 // Add a separate ResOperand for each suboperand.
1587 for (unsigned AI = 0; AI < NumOperands; ++AI) {
1588 assert(AsmOperands[SrcOperand+AI].SubOpIdx == (int)AI &&
1589 AsmOperands[SrcOperand+AI].SrcOpName == OpInfo.Name &&
1590 "unexpected AsmOperands for suboperands");
1591 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand + AI, 1));
1596 void MatchableInfo::buildAliasResultOperands() {
1597 const CodeGenInstAlias &CGA = *DefRec.get<const CodeGenInstAlias*>();
1598 const CodeGenInstruction *ResultInst = getResultInst();
1600 // Loop over all operands of the result instruction, determining how to
1602 unsigned AliasOpNo = 0;
1603 unsigned LastOpNo = CGA.ResultInstOperandIndex.size();
1604 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1605 const CGIOperandList::OperandInfo *OpInfo = &ResultInst->Operands[i];
1607 // If this is a tied operand, just copy from the previously handled operand.
1608 int TiedOp = OpInfo->getTiedRegister();
1610 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1614 // Handle all the suboperands for this operand.
1615 const std::string &OpName = OpInfo->Name;
1616 for ( ; AliasOpNo < LastOpNo &&
1617 CGA.ResultInstOperandIndex[AliasOpNo].first == i; ++AliasOpNo) {
1618 int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second;
1620 // Find out what operand from the asmparser that this MCInst operand
1622 switch (CGA.ResultOperands[AliasOpNo].Kind) {
1623 case CodeGenInstAlias::ResultOperand::K_Record: {
1624 StringRef Name = CGA.ResultOperands[AliasOpNo].getName();
1625 int SrcOperand = findAsmOperand(Name, SubIdx);
1626 if (SrcOperand == -1)
1627 throw TGError(TheDef->getLoc(), "Instruction '" +
1628 TheDef->getName() + "' has operand '" + OpName +
1629 "' that doesn't appear in asm string!");
1630 unsigned NumOperands = (SubIdx == -1 ? OpInfo->MINumOperands : 1);
1631 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand,
1635 case CodeGenInstAlias::ResultOperand::K_Imm: {
1636 int64_t ImmVal = CGA.ResultOperands[AliasOpNo].getImm();
1637 ResOperands.push_back(ResOperand::getImmOp(ImmVal));
1640 case CodeGenInstAlias::ResultOperand::K_Reg: {
1641 Record *Reg = CGA.ResultOperands[AliasOpNo].getRegister();
1642 ResOperands.push_back(ResOperand::getRegOp(Reg));
1650 static unsigned getConverterOperandID(const std::string &Name,
1651 SetVector<std::string> &Table,
1653 IsNew = Table.insert(Name);
1655 unsigned ID = IsNew ? Table.size() - 1 :
1656 std::find(Table.begin(), Table.end(), Name) - Table.begin();
1658 assert(ID < Table.size());
1664 static void emitConvertToMCInst(CodeGenTarget &Target, StringRef ClassName,
1665 std::vector<MatchableInfo*> &Infos,
1667 SetVector<std::string> OperandConversionKinds;
1668 SetVector<std::string> InstructionConversionKinds;
1669 std::vector<std::vector<uint8_t> > ConversionTable;
1670 size_t MaxRowLength = 2; // minimum is custom converter plus terminator.
1672 // TargetOperandClass - This is the target's operand class, like X86Operand.
1673 std::string TargetOperandClass = Target.getName() + "Operand";
1675 // Write the convert function to a separate stream, so we can drop it after
1676 // the enum. We'll build up the conversion handlers for the individual
1677 // operand types opportunistically as we encounter them.
1678 std::string ConvertFnBody;
1679 raw_string_ostream CvtOS(ConvertFnBody);
1680 // Start the unified conversion function.
1681 CvtOS << "bool " << Target.getName() << ClassName << "::\n"
1682 << "ConvertToMCInst(unsigned Kind, MCInst &Inst, "
1683 << "unsigned Opcode,\n"
1684 << " const SmallVectorImpl<MCParsedAsmOperand*"
1685 << "> &Operands) {\n"
1686 << " if (Kind >= CVT_NUM_SIGNATURES) return false;\n"
1687 << " uint8_t *Converter = ConversionTable[Kind];\n"
1688 << " Inst.setOpcode(Opcode);\n"
1689 << " for (uint8_t *p = Converter; *p; p+= 2) {\n"
1690 << " switch (*p) {\n"
1691 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
1692 << " case CVT_Reg:\n"
1693 << " static_cast<" << TargetOperandClass
1694 << "*>(Operands[*(p + 1)])->addRegOperands(Inst, 1);\n"
1696 << " case CVT_Tied:\n"
1697 << " Inst.addOperand(Inst.getOperand(*(p + 1)));\n"
1700 std::string OperandFnBody;
1701 raw_string_ostream OpOS(OperandFnBody);
1702 // Start the operand number lookup function.
1703 OpOS << "bool " << Target.getName() << ClassName << "::\n"
1704 << "GetMCInstOperandNum(unsigned Kind, MCInst &Inst,\n"
1705 << " const SmallVectorImpl<MCParsedAsmOperand*> &Operands,"
1706 << "\n unsigned OperandNum, unsigned &MCOperandNum) {\n"
1707 << " if (Kind >= CVT_NUM_SIGNATURES) return false;\n"
1708 << " MCOperandNum = 0;\n"
1709 << " uint8_t *Converter = ConversionTable[Kind];\n"
1710 << " for (uint8_t *p = Converter; *p; p+= 2) {\n"
1711 << " if (*(p + 1) > OperandNum) continue;\n"
1712 << " switch (*p) {\n"
1713 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
1714 << " case CVT_Reg:\n"
1715 << " ++MCOperandNum;\n"
1717 << " case CVT_Tied:\n"
1718 << " //Inst.getOperand(*(p + 1)));\n"
1721 // Pre-populate the operand conversion kinds with the standard always
1722 // available entries.
1723 OperandConversionKinds.insert("CVT_Done");
1724 OperandConversionKinds.insert("CVT_Reg");
1725 OperandConversionKinds.insert("CVT_Tied");
1726 enum { CVT_Done, CVT_Reg, CVT_Tied };
1728 for (std::vector<MatchableInfo*>::const_iterator it = Infos.begin(),
1729 ie = Infos.end(); it != ie; ++it) {
1730 MatchableInfo &II = **it;
1732 // Check if we have a custom match function.
1733 std::string AsmMatchConverter =
1734 II.getResultInst()->TheDef->getValueAsString("AsmMatchConverter");
1735 if (!AsmMatchConverter.empty()) {
1736 std::string Signature = "ConvertCustom_" + AsmMatchConverter;
1737 II.ConversionFnKind = Signature;
1739 // Check if we have already generated this signature.
1740 if (!InstructionConversionKinds.insert(Signature))
1743 // Remember this converter for the kind enum.
1744 unsigned KindID = OperandConversionKinds.size();
1745 OperandConversionKinds.insert("CVT_" + AsmMatchConverter);
1747 // Add the converter row for this instruction.
1748 ConversionTable.push_back(std::vector<uint8_t>());
1749 ConversionTable.back().push_back(KindID);
1750 ConversionTable.back().push_back(CVT_Done);
1752 // Add the handler to the conversion driver function.
1753 CvtOS << " case CVT_" << AsmMatchConverter << ":\n"
1754 << " return " << AsmMatchConverter
1755 << "(Inst, Opcode, Operands);\n";
1757 // FIXME: Handle the operand number lookup for custom match functions.
1761 // Build the conversion function signature.
1762 std::string Signature = "Convert";
1764 std::vector<uint8_t> ConversionRow;
1766 // Compute the convert enum and the case body.
1767 MaxRowLength = std::max(MaxRowLength, II.ResOperands.size()*2 + 1 );
1769 for (unsigned i = 0, e = II.ResOperands.size(); i != e; ++i) {
1770 const MatchableInfo::ResOperand &OpInfo = II.ResOperands[i];
1772 // Generate code to populate each result operand.
1773 switch (OpInfo.Kind) {
1774 case MatchableInfo::ResOperand::RenderAsmOperand: {
1775 // This comes from something we parsed.
1776 MatchableInfo::AsmOperand &Op = II.AsmOperands[OpInfo.AsmOperandNum];
1778 // Registers are always converted the same, don't duplicate the
1779 // conversion function based on them.
1782 Class = Op.Class->isRegisterClass() ? "Reg" : Op.Class->ClassName;
1784 Signature += utostr(OpInfo.MINumOperands);
1785 Signature += "_" + itostr(OpInfo.AsmOperandNum);
1787 // Add the conversion kind, if necessary, and get the associated ID
1788 // the index of its entry in the vector).
1789 std::string Name = "CVT_" + (Op.Class->isRegisterClass() ? "Reg" :
1790 Op.Class->RenderMethod);
1792 bool IsNewConverter = false;
1793 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1796 // Add the operand entry to the instruction kind conversion row.
1797 ConversionRow.push_back(ID);
1798 ConversionRow.push_back(OpInfo.AsmOperandNum + 1);
1800 if (!IsNewConverter)
1803 // This is a new operand kind. Add a handler for it to the
1804 // converter driver.
1805 CvtOS << " case " << Name << ":\n"
1806 << " static_cast<" << TargetOperandClass
1807 << "*>(Operands[*(p + 1)])->"
1808 << Op.Class->RenderMethod << "(Inst, " << OpInfo.MINumOperands
1812 // Add a handler for the operand number lookup.
1813 OpOS << " case " << Name << ":\n"
1814 << " MCOperandNum += " << OpInfo.MINumOperands << ";\n"
1818 case MatchableInfo::ResOperand::TiedOperand: {
1819 // If this operand is tied to a previous one, just copy the MCInst
1820 // operand from the earlier one.We can only tie single MCOperand values.
1821 //assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand");
1822 unsigned TiedOp = OpInfo.TiedOperandNum;
1823 assert(i > TiedOp && "Tied operand precedes its target!");
1824 Signature += "__Tie" + utostr(TiedOp);
1825 ConversionRow.push_back(CVT_Tied);
1826 ConversionRow.push_back(TiedOp);
1827 // FIXME: Handle the operand number lookup for tied operands.
1830 case MatchableInfo::ResOperand::ImmOperand: {
1831 int64_t Val = OpInfo.ImmVal;
1832 std::string Ty = "imm_" + itostr(Val);
1833 Signature += "__" + Ty;
1835 std::string Name = "CVT_" + Ty;
1836 bool IsNewConverter = false;
1837 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1839 // Add the operand entry to the instruction kind conversion row.
1840 ConversionRow.push_back(ID);
1841 ConversionRow.push_back(0);
1843 if (!IsNewConverter)
1846 CvtOS << " case " << Name << ":\n"
1847 << " Inst.addOperand(MCOperand::CreateImm(" << Val << "));\n"
1850 OpOS << " case " << Name << ":\n"
1851 << " ++MCOperandNum;\n"
1855 case MatchableInfo::ResOperand::RegOperand: {
1856 std::string Reg, Name;
1857 if (OpInfo.Register == 0) {
1861 Reg = getQualifiedName(OpInfo.Register);
1862 Name = "reg" + OpInfo.Register->getName();
1864 Signature += "__" + Name;
1865 Name = "CVT_" + Name;
1866 bool IsNewConverter = false;
1867 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1869 // Add the operand entry to the instruction kind conversion row.
1870 ConversionRow.push_back(ID);
1871 ConversionRow.push_back(0);
1873 if (!IsNewConverter)
1875 CvtOS << " case " << Name << ":\n"
1876 << " Inst.addOperand(MCOperand::CreateReg(" << Reg << "));\n"
1879 OpOS << " case " << Name << ":\n"
1880 << " ++MCOperandNum;\n"
1886 // If there were no operands, add to the signature to that effect
1887 if (Signature == "Convert")
1888 Signature += "_NoOperands";
1890 II.ConversionFnKind = Signature;
1892 // Save the signature. If we already have it, don't add a new row
1894 if (!InstructionConversionKinds.insert(Signature))
1897 // Add the row to the table.
1898 ConversionTable.push_back(ConversionRow);
1901 // Finish up the converter driver function.
1902 CvtOS << " }\n }\n return true;\n}\n\n";
1904 // Finish up the operand number lookup function.
1905 OpOS << " }\n }\n return true;\n}\n\n";
1907 OS << "namespace {\n";
1909 // Output the operand conversion kind enum.
1910 OS << "enum OperatorConversionKind {\n";
1911 for (unsigned i = 0, e = OperandConversionKinds.size(); i != e; ++i)
1912 OS << " " << OperandConversionKinds[i] << ",\n";
1913 OS << " CVT_NUM_CONVERTERS\n";
1916 // Output the instruction conversion kind enum.
1917 OS << "enum InstructionConversionKind {\n";
1918 for (SetVector<std::string>::const_iterator
1919 i = InstructionConversionKinds.begin(),
1920 e = InstructionConversionKinds.end(); i != e; ++i)
1921 OS << " " << *i << ",\n";
1922 OS << " CVT_NUM_SIGNATURES\n";
1926 OS << "} // end anonymous namespace\n\n";
1928 // Output the conversion table.
1929 OS << "static uint8_t ConversionTable[CVT_NUM_SIGNATURES]["
1930 << MaxRowLength << "] = {\n";
1932 for (unsigned Row = 0, ERow = ConversionTable.size(); Row != ERow; ++Row) {
1933 assert(ConversionTable[Row].size() % 2 == 0 && "bad conversion row!");
1934 OS << " // " << InstructionConversionKinds[Row] << "\n";
1936 for (unsigned i = 0, e = ConversionTable[Row].size(); i != e; i += 2)
1937 OS << OperandConversionKinds[ConversionTable[Row][i]] << ", "
1938 << (unsigned)(ConversionTable[Row][i + 1]) << ", ";
1939 OS << "CVT_Done },\n";
1944 // Spit out the conversion driver function.
1947 // Spit out the operand number lookup function.
1951 /// emitMatchClassEnumeration - Emit the enumeration for match class kinds.
1952 static void emitMatchClassEnumeration(CodeGenTarget &Target,
1953 std::vector<ClassInfo*> &Infos,
1955 OS << "namespace {\n\n";
1957 OS << "/// MatchClassKind - The kinds of classes which participate in\n"
1958 << "/// instruction matching.\n";
1959 OS << "enum MatchClassKind {\n";
1960 OS << " InvalidMatchClass = 0,\n";
1961 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1962 ie = Infos.end(); it != ie; ++it) {
1963 ClassInfo &CI = **it;
1964 OS << " " << CI.Name << ", // ";
1965 if (CI.Kind == ClassInfo::Token) {
1966 OS << "'" << CI.ValueName << "'\n";
1967 } else if (CI.isRegisterClass()) {
1968 if (!CI.ValueName.empty())
1969 OS << "register class '" << CI.ValueName << "'\n";
1971 OS << "derived register class\n";
1973 OS << "user defined class '" << CI.ValueName << "'\n";
1976 OS << " NumMatchClassKinds\n";
1982 /// emitValidateOperandClass - Emit the function to validate an operand class.
1983 static void emitValidateOperandClass(AsmMatcherInfo &Info,
1985 OS << "static unsigned validateOperandClass(MCParsedAsmOperand *GOp, "
1986 << "MatchClassKind Kind) {\n";
1987 OS << " " << Info.Target.getName() << "Operand &Operand = *("
1988 << Info.Target.getName() << "Operand*)GOp;\n";
1990 // The InvalidMatchClass is not to match any operand.
1991 OS << " if (Kind == InvalidMatchClass)\n";
1992 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n\n";
1994 // Check for Token operands first.
1995 // FIXME: Use a more specific diagnostic type.
1996 OS << " if (Operand.isToken())\n";
1997 OS << " return isSubclass(matchTokenString(Operand.getToken()), Kind) ?\n"
1998 << " MCTargetAsmParser::Match_Success :\n"
1999 << " MCTargetAsmParser::Match_InvalidOperand;\n\n";
2001 // Check the user classes. We don't care what order since we're only
2002 // actually matching against one of them.
2003 for (std::vector<ClassInfo*>::iterator it = Info.Classes.begin(),
2004 ie = Info.Classes.end(); it != ie; ++it) {
2005 ClassInfo &CI = **it;
2007 if (!CI.isUserClass())
2010 OS << " // '" << CI.ClassName << "' class\n";
2011 OS << " if (Kind == " << CI.Name << ") {\n";
2012 OS << " if (Operand." << CI.PredicateMethod << "())\n";
2013 OS << " return MCTargetAsmParser::Match_Success;\n";
2014 if (!CI.DiagnosticType.empty())
2015 OS << " return " << Info.Target.getName() << "AsmParser::Match_"
2016 << CI.DiagnosticType << ";\n";
2020 // Check for register operands, including sub-classes.
2021 OS << " if (Operand.isReg()) {\n";
2022 OS << " MatchClassKind OpKind;\n";
2023 OS << " switch (Operand.getReg()) {\n";
2024 OS << " default: OpKind = InvalidMatchClass; break;\n";
2025 for (std::map<Record*, ClassInfo*>::iterator
2026 it = Info.RegisterClasses.begin(), ie = Info.RegisterClasses.end();
2028 OS << " case " << Info.Target.getName() << "::"
2029 << it->first->getName() << ": OpKind = " << it->second->Name
2032 OS << " return isSubclass(OpKind, Kind) ? "
2033 << "MCTargetAsmParser::Match_Success :\n "
2034 << " MCTargetAsmParser::Match_InvalidOperand;\n }\n\n";
2036 // Generic fallthrough match failure case for operands that don't have
2037 // specialized diagnostic types.
2038 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n";
2042 /// emitIsSubclass - Emit the subclass predicate function.
2043 static void emitIsSubclass(CodeGenTarget &Target,
2044 std::vector<ClassInfo*> &Infos,
2046 OS << "/// isSubclass - Compute whether \\arg A is a subclass of \\arg B.\n";
2047 OS << "static bool isSubclass(MatchClassKind A, MatchClassKind B) {\n";
2048 OS << " if (A == B)\n";
2049 OS << " return true;\n\n";
2051 OS << " switch (A) {\n";
2052 OS << " default:\n";
2053 OS << " return false;\n";
2054 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
2055 ie = Infos.end(); it != ie; ++it) {
2056 ClassInfo &A = **it;
2058 std::vector<StringRef> SuperClasses;
2059 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
2060 ie = Infos.end(); it != ie; ++it) {
2061 ClassInfo &B = **it;
2063 if (&A != &B && A.isSubsetOf(B))
2064 SuperClasses.push_back(B.Name);
2067 if (SuperClasses.empty())
2070 OS << "\n case " << A.Name << ":\n";
2072 if (SuperClasses.size() == 1) {
2073 OS << " return B == " << SuperClasses.back() << ";\n";
2077 OS << " switch (B) {\n";
2078 OS << " default: return false;\n";
2079 for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i)
2080 OS << " case " << SuperClasses[i] << ": return true;\n";
2087 /// emitMatchTokenString - Emit the function to match a token string to the
2088 /// appropriate match class value.
2089 static void emitMatchTokenString(CodeGenTarget &Target,
2090 std::vector<ClassInfo*> &Infos,
2092 // Construct the match list.
2093 std::vector<StringMatcher::StringPair> Matches;
2094 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
2095 ie = Infos.end(); it != ie; ++it) {
2096 ClassInfo &CI = **it;
2098 if (CI.Kind == ClassInfo::Token)
2099 Matches.push_back(StringMatcher::StringPair(CI.ValueName,
2100 "return " + CI.Name + ";"));
2103 OS << "static MatchClassKind matchTokenString(StringRef Name) {\n";
2105 StringMatcher("Name", Matches, OS).Emit();
2107 OS << " return InvalidMatchClass;\n";
2111 /// emitMatchRegisterName - Emit the function to match a string to the target
2112 /// specific register enum.
2113 static void emitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
2115 // Construct the match list.
2116 std::vector<StringMatcher::StringPair> Matches;
2117 const std::vector<CodeGenRegister*> &Regs =
2118 Target.getRegBank().getRegisters();
2119 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
2120 const CodeGenRegister *Reg = Regs[i];
2121 if (Reg->TheDef->getValueAsString("AsmName").empty())
2124 Matches.push_back(StringMatcher::StringPair(
2125 Reg->TheDef->getValueAsString("AsmName"),
2126 "return " + utostr(Reg->EnumValue) + ";"));
2129 OS << "static unsigned MatchRegisterName(StringRef Name) {\n";
2131 StringMatcher("Name", Matches, OS).Emit();
2133 OS << " return 0;\n";
2137 /// emitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag
2139 static void emitSubtargetFeatureFlagEnumeration(AsmMatcherInfo &Info,
2141 OS << "// Flags for subtarget features that participate in "
2142 << "instruction matching.\n";
2143 OS << "enum SubtargetFeatureFlag {\n";
2144 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
2145 it = Info.SubtargetFeatures.begin(),
2146 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
2147 SubtargetFeatureInfo &SFI = *it->second;
2148 OS << " " << SFI.getEnumName() << " = (1 << " << SFI.Index << "),\n";
2150 OS << " Feature_None = 0\n";
2154 /// emitOperandDiagnosticTypes - Emit the operand matching diagnostic types.
2155 static void emitOperandDiagnosticTypes(AsmMatcherInfo &Info, raw_ostream &OS) {
2156 // Get the set of diagnostic types from all of the operand classes.
2157 std::set<StringRef> Types;
2158 for (std::map<Record*, ClassInfo*>::const_iterator
2159 I = Info.AsmOperandClasses.begin(),
2160 E = Info.AsmOperandClasses.end(); I != E; ++I) {
2161 if (!I->second->DiagnosticType.empty())
2162 Types.insert(I->second->DiagnosticType);
2165 if (Types.empty()) return;
2167 // Now emit the enum entries.
2168 for (std::set<StringRef>::const_iterator I = Types.begin(), E = Types.end();
2170 OS << " Match_" << *I << ",\n";
2171 OS << " END_OPERAND_DIAGNOSTIC_TYPES\n";
2174 /// emitGetSubtargetFeatureName - Emit the helper function to get the
2175 /// user-level name for a subtarget feature.
2176 static void emitGetSubtargetFeatureName(AsmMatcherInfo &Info, raw_ostream &OS) {
2177 OS << "// User-level names for subtarget features that participate in\n"
2178 << "// instruction matching.\n"
2179 << "static const char *getSubtargetFeatureName(unsigned Val) {\n"
2180 << " switch(Val) {\n";
2181 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
2182 it = Info.SubtargetFeatures.begin(),
2183 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
2184 SubtargetFeatureInfo &SFI = *it->second;
2185 // FIXME: Totally just a placeholder name to get the algorithm working.
2186 OS << " case " << SFI.getEnumName() << ": return \""
2187 << SFI.TheDef->getValueAsString("PredicateName") << "\";\n";
2189 OS << " default: return \"(unknown)\";\n";
2193 /// emitComputeAvailableFeatures - Emit the function to compute the list of
2194 /// available features given a subtarget.
2195 static void emitComputeAvailableFeatures(AsmMatcherInfo &Info,
2197 std::string ClassName =
2198 Info.AsmParser->getValueAsString("AsmParserClassName");
2200 OS << "unsigned " << Info.Target.getName() << ClassName << "::\n"
2201 << "ComputeAvailableFeatures(uint64_t FB) const {\n";
2202 OS << " unsigned Features = 0;\n";
2203 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
2204 it = Info.SubtargetFeatures.begin(),
2205 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
2206 SubtargetFeatureInfo &SFI = *it->second;
2209 std::string CondStorage =
2210 SFI.TheDef->getValueAsString("AssemblerCondString");
2211 StringRef Conds = CondStorage;
2212 std::pair<StringRef,StringRef> Comma = Conds.split(',');
2219 StringRef Cond = Comma.first;
2220 if (Cond[0] == '!') {
2222 Cond = Cond.substr(1);
2225 OS << "((FB & " << Info.Target.getName() << "::" << Cond << ")";
2232 if (Comma.second.empty())
2236 Comma = Comma.second.split(',');
2240 OS << " Features |= " << SFI.getEnumName() << ";\n";
2242 OS << " return Features;\n";
2246 static std::string GetAliasRequiredFeatures(Record *R,
2247 const AsmMatcherInfo &Info) {
2248 std::vector<Record*> ReqFeatures = R->getValueAsListOfDefs("Predicates");
2250 unsigned NumFeatures = 0;
2251 for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) {
2252 SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]);
2255 throw TGError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() +
2256 "' is not marked as an AssemblerPredicate!");
2261 Result += F->getEnumName();
2265 if (NumFeatures > 1)
2266 Result = '(' + Result + ')';
2270 /// emitMnemonicAliases - If the target has any MnemonicAlias<> definitions,
2271 /// emit a function for them and return true, otherwise return false.
2272 static bool emitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info) {
2273 // Ignore aliases when match-prefix is set.
2274 if (!MatchPrefix.empty())
2277 std::vector<Record*> Aliases =
2278 Info.getRecords().getAllDerivedDefinitions("MnemonicAlias");
2279 if (Aliases.empty()) return false;
2281 OS << "static void applyMnemonicAliases(StringRef &Mnemonic, "
2282 "unsigned Features) {\n";
2284 // Keep track of all the aliases from a mnemonic. Use an std::map so that the
2285 // iteration order of the map is stable.
2286 std::map<std::string, std::vector<Record*> > AliasesFromMnemonic;
2288 for (unsigned i = 0, e = Aliases.size(); i != e; ++i) {
2289 Record *R = Aliases[i];
2290 AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R);
2293 // Process each alias a "from" mnemonic at a time, building the code executed
2294 // by the string remapper.
2295 std::vector<StringMatcher::StringPair> Cases;
2296 for (std::map<std::string, std::vector<Record*> >::iterator
2297 I = AliasesFromMnemonic.begin(), E = AliasesFromMnemonic.end();
2299 const std::vector<Record*> &ToVec = I->second;
2301 // Loop through each alias and emit code that handles each case. If there
2302 // are two instructions without predicates, emit an error. If there is one,
2304 std::string MatchCode;
2305 int AliasWithNoPredicate = -1;
2307 for (unsigned i = 0, e = ToVec.size(); i != e; ++i) {
2308 Record *R = ToVec[i];
2309 std::string FeatureMask = GetAliasRequiredFeatures(R, Info);
2311 // If this unconditionally matches, remember it for later and diagnose
2313 if (FeatureMask.empty()) {
2314 if (AliasWithNoPredicate != -1) {
2315 // We can't have two aliases from the same mnemonic with no predicate.
2316 PrintError(ToVec[AliasWithNoPredicate]->getLoc(),
2317 "two MnemonicAliases with the same 'from' mnemonic!");
2318 throw TGError(R->getLoc(), "this is the other MnemonicAlias.");
2321 AliasWithNoPredicate = i;
2324 if (R->getValueAsString("ToMnemonic") == I->first)
2325 throw TGError(R->getLoc(), "MnemonicAlias to the same string");
2327 if (!MatchCode.empty())
2328 MatchCode += "else ";
2329 MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n";
2330 MatchCode += " Mnemonic = \"" +R->getValueAsString("ToMnemonic")+"\";\n";
2333 if (AliasWithNoPredicate != -1) {
2334 Record *R = ToVec[AliasWithNoPredicate];
2335 if (!MatchCode.empty())
2336 MatchCode += "else\n ";
2337 MatchCode += "Mnemonic = \"" + R->getValueAsString("ToMnemonic")+"\";\n";
2340 MatchCode += "return;";
2342 Cases.push_back(std::make_pair(I->first, MatchCode));
2345 StringMatcher("Mnemonic", Cases, OS).Emit();
2351 static const char *getMinimalTypeForRange(uint64_t Range) {
2352 assert(Range < 0xFFFFFFFFULL && "Enum too large");
2360 static void emitCustomOperandParsing(raw_ostream &OS, CodeGenTarget &Target,
2361 const AsmMatcherInfo &Info, StringRef ClassName) {
2362 // Emit the static custom operand parsing table;
2363 OS << "namespace {\n";
2364 OS << " struct OperandMatchEntry {\n";
2365 OS << " static const char *const MnemonicTable;\n";
2366 OS << " uint32_t OperandMask;\n";
2367 OS << " uint32_t Mnemonic;\n";
2368 OS << " " << getMinimalTypeForRange(1ULL << Info.SubtargetFeatures.size())
2369 << " RequiredFeatures;\n";
2370 OS << " " << getMinimalTypeForRange(Info.Classes.size())
2372 OS << " StringRef getMnemonic() const {\n";
2373 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2374 OS << " MnemonicTable[Mnemonic]);\n";
2378 OS << " // Predicate for searching for an opcode.\n";
2379 OS << " struct LessOpcodeOperand {\n";
2380 OS << " bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {\n";
2381 OS << " return LHS.getMnemonic() < RHS;\n";
2383 OS << " bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {\n";
2384 OS << " return LHS < RHS.getMnemonic();\n";
2386 OS << " bool operator()(const OperandMatchEntry &LHS,";
2387 OS << " const OperandMatchEntry &RHS) {\n";
2388 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2392 OS << "} // end anonymous namespace.\n\n";
2394 StringToOffsetTable StringTable;
2396 OS << "static const OperandMatchEntry OperandMatchTable["
2397 << Info.OperandMatchInfo.size() << "] = {\n";
2399 OS << " /* Operand List Mask, Mnemonic, Operand Class, Features */\n";
2400 for (std::vector<OperandMatchEntry>::const_iterator it =
2401 Info.OperandMatchInfo.begin(), ie = Info.OperandMatchInfo.end();
2403 const OperandMatchEntry &OMI = *it;
2404 const MatchableInfo &II = *OMI.MI;
2406 OS << " { " << OMI.OperandMask;
2409 bool printComma = false;
2410 for (int i = 0, e = 31; i !=e; ++i)
2411 if (OMI.OperandMask & (1 << i)) {
2419 // Store a pascal-style length byte in the mnemonic.
2420 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2421 OS << ", " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2422 << " /* " << II.Mnemonic << " */, ";
2424 // Write the required features mask.
2425 if (!II.RequiredFeatures.empty()) {
2426 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
2428 OS << II.RequiredFeatures[i]->getEnumName();
2433 OS << ", " << OMI.CI->Name;
2439 OS << "const char *const OperandMatchEntry::MnemonicTable =\n";
2440 StringTable.EmitString(OS);
2443 // Emit the operand class switch to call the correct custom parser for
2444 // the found operand class.
2445 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
2446 << Target.getName() << ClassName << "::\n"
2447 << "tryCustomParseOperand(SmallVectorImpl<MCParsedAsmOperand*>"
2448 << " &Operands,\n unsigned MCK) {\n\n"
2449 << " switch(MCK) {\n";
2451 for (std::vector<ClassInfo*>::const_iterator it = Info.Classes.begin(),
2452 ie = Info.Classes.end(); it != ie; ++it) {
2453 ClassInfo *CI = *it;
2454 if (CI->ParserMethod.empty())
2456 OS << " case " << CI->Name << ":\n"
2457 << " return " << CI->ParserMethod << "(Operands);\n";
2460 OS << " default:\n";
2461 OS << " return MatchOperand_NoMatch;\n";
2463 OS << " return MatchOperand_NoMatch;\n";
2466 // Emit the static custom operand parser. This code is very similar with
2467 // the other matcher. Also use MatchResultTy here just in case we go for
2468 // a better error handling.
2469 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
2470 << Target.getName() << ClassName << "::\n"
2471 << "MatchOperandParserImpl(SmallVectorImpl<MCParsedAsmOperand*>"
2472 << " &Operands,\n StringRef Mnemonic) {\n";
2474 // Emit code to get the available features.
2475 OS << " // Get the current feature set.\n";
2476 OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n";
2478 OS << " // Get the next operand index.\n";
2479 OS << " unsigned NextOpNum = Operands.size()-1;\n";
2481 // Emit code to search the table.
2482 OS << " // Search the table.\n";
2483 OS << " std::pair<const OperandMatchEntry*, const OperandMatchEntry*>";
2484 OS << " MnemonicRange =\n";
2485 OS << " std::equal_range(OperandMatchTable, OperandMatchTable+"
2486 << Info.OperandMatchInfo.size() << ", Mnemonic,\n"
2487 << " LessOpcodeOperand());\n\n";
2489 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2490 OS << " return MatchOperand_NoMatch;\n\n";
2492 OS << " for (const OperandMatchEntry *it = MnemonicRange.first,\n"
2493 << " *ie = MnemonicRange.second; it != ie; ++it) {\n";
2495 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2496 OS << " assert(Mnemonic == it->getMnemonic());\n\n";
2498 // Emit check that the required features are available.
2499 OS << " // check if the available features match\n";
2500 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2501 << "!= it->RequiredFeatures) {\n";
2502 OS << " continue;\n";
2505 // Emit check to ensure the operand number matches.
2506 OS << " // check if the operand in question has a custom parser.\n";
2507 OS << " if (!(it->OperandMask & (1 << NextOpNum)))\n";
2508 OS << " continue;\n\n";
2510 // Emit call to the custom parser method
2511 OS << " // call custom parse method to handle the operand\n";
2512 OS << " OperandMatchResultTy Result = ";
2513 OS << "tryCustomParseOperand(Operands, it->Class);\n";
2514 OS << " if (Result != MatchOperand_NoMatch)\n";
2515 OS << " return Result;\n";
2518 OS << " // Okay, we had no match.\n";
2519 OS << " return MatchOperand_NoMatch;\n";
2523 void AsmMatcherEmitter::run(raw_ostream &OS) {
2524 CodeGenTarget Target(Records);
2525 Record *AsmParser = Target.getAsmParser();
2526 std::string ClassName = AsmParser->getValueAsString("AsmParserClassName");
2528 // Compute the information on the instructions to match.
2529 AsmMatcherInfo Info(AsmParser, Target, Records);
2532 // Sort the instruction table using the partial order on classes. We use
2533 // stable_sort to ensure that ambiguous instructions are still
2534 // deterministically ordered.
2535 std::stable_sort(Info.Matchables.begin(), Info.Matchables.end(),
2536 less_ptr<MatchableInfo>());
2538 DEBUG_WITH_TYPE("instruction_info", {
2539 for (std::vector<MatchableInfo*>::iterator
2540 it = Info.Matchables.begin(), ie = Info.Matchables.end();
2545 // Check for ambiguous matchables.
2546 DEBUG_WITH_TYPE("ambiguous_instrs", {
2547 unsigned NumAmbiguous = 0;
2548 for (unsigned i = 0, e = Info.Matchables.size(); i != e; ++i) {
2549 for (unsigned j = i + 1; j != e; ++j) {
2550 MatchableInfo &A = *Info.Matchables[i];
2551 MatchableInfo &B = *Info.Matchables[j];
2553 if (A.couldMatchAmbiguouslyWith(B)) {
2554 errs() << "warning: ambiguous matchables:\n";
2556 errs() << "\nis incomparable with:\n";
2564 errs() << "warning: " << NumAmbiguous
2565 << " ambiguous matchables!\n";
2568 // Compute the information on the custom operand parsing.
2569 Info.buildOperandMatchInfo();
2571 // Write the output.
2573 // Information for the class declaration.
2574 OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
2575 OS << "#undef GET_ASSEMBLER_HEADER\n";
2576 OS << " // This should be included into the middle of the declaration of\n";
2577 OS << " // your subclasses implementation of MCTargetAsmParser.\n";
2578 OS << " unsigned ComputeAvailableFeatures(uint64_t FeatureBits) const;\n";
2579 OS << " bool ConvertToMCInst(unsigned Kind, MCInst &Inst, "
2580 << "unsigned Opcode,\n"
2581 << " const SmallVectorImpl<MCParsedAsmOperand*> "
2583 OS << " bool GetMCInstOperandNum(unsigned Kind, MCInst &Inst,\n"
2584 << " const SmallVectorImpl<MCParsedAsmOperand*> "
2585 << "&Operands,\n unsigned OperandNum, unsigned "
2586 << "&MCOperandNum);\n";
2587 OS << " bool MnemonicIsValid(StringRef Mnemonic);\n";
2588 OS << " unsigned MatchInstructionImpl(\n";
2589 OS << " const SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n";
2590 OS << " MCInst &Inst, unsigned &ErrorInfo, unsigned VariantID = 0);\n";
2592 if (Info.OperandMatchInfo.size()) {
2593 OS << "\n enum OperandMatchResultTy {\n";
2594 OS << " MatchOperand_Success, // operand matched successfully\n";
2595 OS << " MatchOperand_NoMatch, // operand did not match\n";
2596 OS << " MatchOperand_ParseFail // operand matched but had errors\n";
2598 OS << " OperandMatchResultTy MatchOperandParserImpl(\n";
2599 OS << " SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n";
2600 OS << " StringRef Mnemonic);\n";
2602 OS << " OperandMatchResultTy tryCustomParseOperand(\n";
2603 OS << " SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n";
2604 OS << " unsigned MCK);\n\n";
2607 OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n";
2609 // Emit the operand match diagnostic enum names.
2610 OS << "\n#ifdef GET_OPERAND_DIAGNOSTIC_TYPES\n";
2611 OS << "#undef GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
2612 emitOperandDiagnosticTypes(Info, OS);
2613 OS << "#endif // GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
2616 OS << "\n#ifdef GET_REGISTER_MATCHER\n";
2617 OS << "#undef GET_REGISTER_MATCHER\n\n";
2619 // Emit the subtarget feature enumeration.
2620 emitSubtargetFeatureFlagEnumeration(Info, OS);
2622 // Emit the function to match a register name to number.
2623 // This should be omitted for Mips target
2624 if (AsmParser->getValueAsBit("ShouldEmitMatchRegisterName"))
2625 emitMatchRegisterName(Target, AsmParser, OS);
2627 OS << "#endif // GET_REGISTER_MATCHER\n\n";
2629 OS << "\n#ifdef GET_SUBTARGET_FEATURE_NAME\n";
2630 OS << "#undef GET_SUBTARGET_FEATURE_NAME\n\n";
2632 // Generate the helper function to get the names for subtarget features.
2633 emitGetSubtargetFeatureName(Info, OS);
2635 OS << "#endif // GET_SUBTARGET_FEATURE_NAME\n\n";
2637 OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
2638 OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
2640 // Generate the function that remaps for mnemonic aliases.
2641 bool HasMnemonicAliases = emitMnemonicAliases(OS, Info);
2643 // Generate the unified function to convert operands into an MCInst.
2644 emitConvertToMCInst(Target, ClassName, Info.Matchables, OS);
2646 // Emit the enumeration for classes which participate in matching.
2647 emitMatchClassEnumeration(Target, Info.Classes, OS);
2649 // Emit the routine to match token strings to their match class.
2650 emitMatchTokenString(Target, Info.Classes, OS);
2652 // Emit the subclass predicate routine.
2653 emitIsSubclass(Target, Info.Classes, OS);
2655 // Emit the routine to validate an operand against a match class.
2656 emitValidateOperandClass(Info, OS);
2658 // Emit the available features compute function.
2659 emitComputeAvailableFeatures(Info, OS);
2662 size_t MaxNumOperands = 0;
2663 for (std::vector<MatchableInfo*>::const_iterator it =
2664 Info.Matchables.begin(), ie = Info.Matchables.end();
2666 MaxNumOperands = std::max(MaxNumOperands, (*it)->AsmOperands.size());
2668 // Emit the static match table; unused classes get initalized to 0 which is
2669 // guaranteed to be InvalidMatchClass.
2671 // FIXME: We can reduce the size of this table very easily. First, we change
2672 // it so that store the kinds in separate bit-fields for each index, which
2673 // only needs to be the max width used for classes at that index (we also need
2674 // to reject based on this during classification). If we then make sure to
2675 // order the match kinds appropriately (putting mnemonics last), then we
2676 // should only end up using a few bits for each class, especially the ones
2677 // following the mnemonic.
2678 OS << "namespace {\n";
2679 OS << " struct MatchEntry {\n";
2680 OS << " static const char *const MnemonicTable;\n";
2681 OS << " uint32_t Mnemonic;\n";
2682 OS << " uint16_t Opcode;\n";
2683 OS << " " << getMinimalTypeForRange(Info.Matchables.size())
2685 OS << " " << getMinimalTypeForRange(1ULL << Info.SubtargetFeatures.size())
2686 << " RequiredFeatures;\n";
2687 OS << " " << getMinimalTypeForRange(Info.Classes.size())
2688 << " Classes[" << MaxNumOperands << "];\n";
2689 OS << " uint8_t AsmVariantID;\n\n";
2690 OS << " StringRef getMnemonic() const {\n";
2691 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2692 OS << " MnemonicTable[Mnemonic]);\n";
2696 OS << " // Predicate for searching for an opcode.\n";
2697 OS << " struct LessOpcode {\n";
2698 OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n";
2699 OS << " return LHS.getMnemonic() < RHS;\n";
2701 OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n";
2702 OS << " return LHS < RHS.getMnemonic();\n";
2704 OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n";
2705 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2709 OS << "} // end anonymous namespace.\n\n";
2711 StringToOffsetTable StringTable;
2713 OS << "static const MatchEntry MatchTable["
2714 << Info.Matchables.size() << "] = {\n";
2716 for (std::vector<MatchableInfo*>::const_iterator it =
2717 Info.Matchables.begin(), ie = Info.Matchables.end();
2719 MatchableInfo &II = **it;
2721 // Store a pascal-style length byte in the mnemonic.
2722 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2723 OS << " { " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2724 << " /* " << II.Mnemonic << " */, "
2725 << Target.getName() << "::"
2726 << II.getResultInst()->TheDef->getName() << ", "
2727 << II.ConversionFnKind << ", ";
2729 // Write the required features mask.
2730 if (!II.RequiredFeatures.empty()) {
2731 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
2733 OS << II.RequiredFeatures[i]->getEnumName();
2739 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) {
2740 MatchableInfo::AsmOperand &Op = II.AsmOperands[i];
2743 OS << Op.Class->Name;
2745 OS << " }, " << II.AsmVariantID;
2751 OS << "const char *const MatchEntry::MnemonicTable =\n";
2752 StringTable.EmitString(OS);
2755 // A method to determine if a mnemonic is in the list.
2756 OS << "bool " << Target.getName() << ClassName << "::\n"
2757 << "MnemonicIsValid(StringRef Mnemonic) {\n";
2758 OS << " // Search the table.\n";
2759 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
2760 OS << " std::equal_range(MatchTable, MatchTable+"
2761 << Info.Matchables.size() << ", Mnemonic, LessOpcode());\n";
2762 OS << " return MnemonicRange.first != MnemonicRange.second;\n";
2765 // Finally, build the match function.
2767 << Target.getName() << ClassName << "::\n"
2768 << "MatchInstructionImpl(const SmallVectorImpl<MCParsedAsmOperand*>"
2770 OS << " MCInst &Inst, unsigned &ErrorInfo, ";
2771 OS << "unsigned VariantID) {\n";
2773 OS << " // Eliminate obvious mismatches.\n";
2774 OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n";
2775 OS << " ErrorInfo = " << (MaxNumOperands+1) << ";\n";
2776 OS << " return Match_InvalidOperand;\n";
2779 // Emit code to get the available features.
2780 OS << " // Get the current feature set.\n";
2781 OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n";
2783 OS << " // Get the instruction mnemonic, which is the first token.\n";
2784 OS << " StringRef Mnemonic = ((" << Target.getName()
2785 << "Operand*)Operands[0])->getToken();\n\n";
2787 if (HasMnemonicAliases) {
2788 OS << " // Process all MnemonicAliases to remap the mnemonic.\n";
2789 OS << " // FIXME : Add an entry in AsmParserVariant to check this.\n";
2790 OS << " if (!VariantID)\n";
2791 OS << " applyMnemonicAliases(Mnemonic, AvailableFeatures);\n\n";
2794 // Emit code to compute the class list for this operand vector.
2795 OS << " // Some state to try to produce better error messages.\n";
2796 OS << " bool HadMatchOtherThanFeatures = false;\n";
2797 OS << " bool HadMatchOtherThanPredicate = false;\n";
2798 OS << " unsigned RetCode = Match_InvalidOperand;\n";
2799 OS << " unsigned MissingFeatures = ~0U;\n";
2800 OS << " // Set ErrorInfo to the operand that mismatches if it is\n";
2801 OS << " // wrong for all instances of the instruction.\n";
2802 OS << " ErrorInfo = ~0U;\n";
2804 // Emit code to search the table.
2805 OS << " // Search the table.\n";
2806 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
2807 OS << " std::equal_range(MatchTable, MatchTable+"
2808 << Info.Matchables.size() << ", Mnemonic, LessOpcode());\n\n";
2810 OS << " // Return a more specific error code if no mnemonics match.\n";
2811 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2812 OS << " return Match_MnemonicFail;\n\n";
2814 OS << " for (const MatchEntry *it = MnemonicRange.first, "
2815 << "*ie = MnemonicRange.second;\n";
2816 OS << " it != ie; ++it) {\n";
2818 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2819 OS << " assert(Mnemonic == it->getMnemonic());\n";
2821 // Emit check that the subclasses match.
2822 OS << " if (VariantID != it->AsmVariantID) continue;\n";
2823 OS << " bool OperandsValid = true;\n";
2824 OS << " for (unsigned i = 0; i != " << MaxNumOperands << "; ++i) {\n";
2825 OS << " if (i + 1 >= Operands.size()) {\n";
2826 OS << " OperandsValid = (it->Classes[i] == " <<"InvalidMatchClass);\n";
2827 OS << " if (!OperandsValid) ErrorInfo = i + 1;\n";
2830 OS << " unsigned Diag = validateOperandClass(Operands[i+1],\n";
2832 OS << "(MatchClassKind)it->Classes[i]);\n";
2833 OS << " if (Diag == Match_Success)\n";
2834 OS << " continue;\n";
2835 OS << " // If this operand is broken for all of the instances of this\n";
2836 OS << " // mnemonic, keep track of it so we can report loc info.\n";
2837 OS << " // If we already had a match that only failed due to a\n";
2838 OS << " // target predicate, that diagnostic is preferred.\n";
2839 OS << " if (!HadMatchOtherThanPredicate &&\n";
2840 OS << " (it == MnemonicRange.first || ErrorInfo <= i+1)) {\n";
2841 OS << " ErrorInfo = i+1;\n";
2842 OS << " // InvalidOperand is the default. Prefer specificity.\n";
2843 OS << " if (Diag != Match_InvalidOperand)\n";
2844 OS << " RetCode = Diag;\n";
2846 OS << " // Otherwise, just reject this instance of the mnemonic.\n";
2847 OS << " OperandsValid = false;\n";
2851 OS << " if (!OperandsValid) continue;\n";
2853 // Emit check that the required features are available.
2854 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2855 << "!= it->RequiredFeatures) {\n";
2856 OS << " HadMatchOtherThanFeatures = true;\n";
2857 OS << " unsigned NewMissingFeatures = it->RequiredFeatures & "
2858 "~AvailableFeatures;\n";
2859 OS << " if (CountPopulation_32(NewMissingFeatures) <=\n"
2860 " CountPopulation_32(MissingFeatures))\n";
2861 OS << " MissingFeatures = NewMissingFeatures;\n";
2862 OS << " continue;\n";
2865 OS << " // We have selected a definite instruction, convert the parsed\n"
2866 << " // operands into the appropriate MCInst.\n";
2867 OS << " if (!ConvertToMCInst(it->ConvertFn, Inst,\n"
2868 << " it->Opcode, Operands))\n";
2869 OS << " return Match_ConversionFail;\n";
2872 // Verify the instruction with the target-specific match predicate function.
2873 OS << " // We have a potential match. Check the target predicate to\n"
2874 << " // handle any context sensitive constraints.\n"
2875 << " unsigned MatchResult;\n"
2876 << " if ((MatchResult = checkTargetMatchPredicate(Inst)) !="
2877 << " Match_Success) {\n"
2878 << " Inst.clear();\n"
2879 << " RetCode = MatchResult;\n"
2880 << " HadMatchOtherThanPredicate = true;\n"
2884 // Call the post-processing function, if used.
2885 std::string InsnCleanupFn =
2886 AsmParser->getValueAsString("AsmParserInstCleanup");
2887 if (!InsnCleanupFn.empty())
2888 OS << " " << InsnCleanupFn << "(Inst);\n";
2890 OS << " return Match_Success;\n";
2893 OS << " // Okay, we had no match. Try to return a useful error code.\n";
2894 OS << " if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)\n";
2895 OS << " return RetCode;\n\n";
2896 OS << " // Missing feature matches return which features were missing\n";
2897 OS << " ErrorInfo = MissingFeatures;\n";
2898 OS << " return Match_MissingFeature;\n";
2901 if (Info.OperandMatchInfo.size())
2902 emitCustomOperandParsing(OS, Target, Info, ClassName);
2904 OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";
2909 void EmitAsmMatcher(RecordKeeper &RK, raw_ostream &OS) {
2910 emitSourceFileHeader("Assembly Matcher Source Fragment", OS);
2911 AsmMatcherEmitter(RK).run(OS);
2914 } // End llvm namespace