1 //===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits a target specifier matcher for converting parsed
11 // assembly operands in the MCInst structures. It also emits a matcher for
12 // custom operand parsing.
14 // Converting assembly operands into MCInst structures
15 // ---------------------------------------------------
17 // The input to the target specific matcher is a list of literal tokens and
18 // operands. The target specific parser should generally eliminate any syntax
19 // which is not relevant for matching; for example, comma tokens should have
20 // already been consumed and eliminated by the parser. Most instructions will
21 // end up with a single literal token (the instruction name) and some number of
24 // Some example inputs, for X86:
25 // 'addl' (immediate ...) (register ...)
26 // 'add' (immediate ...) (memory ...)
29 // The assembly matcher is responsible for converting this input into a precise
30 // machine instruction (i.e., an instruction with a well defined encoding). This
31 // mapping has several properties which complicate matching:
33 // - It may be ambiguous; many architectures can legally encode particular
34 // variants of an instruction in different ways (for example, using a smaller
35 // encoding for small immediates). Such ambiguities should never be
36 // arbitrarily resolved by the assembler, the assembler is always responsible
37 // for choosing the "best" available instruction.
39 // - It may depend on the subtarget or the assembler context. Instructions
40 // which are invalid for the current mode, but otherwise unambiguous (e.g.,
41 // an SSE instruction in a file being assembled for i486) should be accepted
42 // and rejected by the assembler front end. However, if the proper encoding
43 // for an instruction is dependent on the assembler context then the matcher
44 // is responsible for selecting the correct machine instruction for the
47 // The core matching algorithm attempts to exploit the regularity in most
48 // instruction sets to quickly determine the set of possibly matching
49 // instructions, and the simplify the generated code. Additionally, this helps
50 // to ensure that the ambiguities are intentionally resolved by the user.
52 // The matching is divided into two distinct phases:
54 // 1. Classification: Each operand is mapped to the unique set which (a)
55 // contains it, and (b) is the largest such subset for which a single
56 // instruction could match all members.
58 // For register classes, we can generate these subgroups automatically. For
59 // arbitrary operands, we expect the user to define the classes and their
60 // relations to one another (for example, 8-bit signed immediates as a
61 // subset of 32-bit immediates).
63 // By partitioning the operands in this way, we guarantee that for any
64 // tuple of classes, any single instruction must match either all or none
65 // of the sets of operands which could classify to that tuple.
67 // In addition, the subset relation amongst classes induces a partial order
68 // on such tuples, which we use to resolve ambiguities.
70 // 2. The input can now be treated as a tuple of classes (static tokens are
71 // simple singleton sets). Each such tuple should generally map to a single
72 // instruction (we currently ignore cases where this isn't true, whee!!!),
73 // which we can emit a simple matcher for.
75 // Custom Operand Parsing
76 // ----------------------
78 // Some targets need a custom way to parse operands, some specific instructions
79 // can contain arguments that can represent processor flags and other kinds of
80 // identifiers that need to be mapped to specific values in the final encoded
81 // instructions. The target specific custom operand parsing works in the
84 // 1. A operand match table is built, each entry contains a mnemonic, an
85 // operand class, a mask for all operand positions for that same
86 // class/mnemonic and target features to be checked while trying to match.
88 // 2. The operand matcher will try every possible entry with the same
89 // mnemonic and will check if the target feature for this mnemonic also
90 // matches. After that, if the operand to be matched has its index
91 // present in the mask, a successful match occurs. Otherwise, fallback
92 // to the regular operand parsing.
94 // 3. For a match success, each operand class that has a 'ParserMethod'
95 // becomes part of a switch from where the custom method is called.
97 //===----------------------------------------------------------------------===//
99 #include "CodeGenTarget.h"
100 #include "StringToOffsetTable.h"
101 #include "llvm/ADT/OwningPtr.h"
102 #include "llvm/ADT/PointerUnion.h"
103 #include "llvm/ADT/SmallPtrSet.h"
104 #include "llvm/ADT/SmallVector.h"
105 #include "llvm/ADT/STLExtras.h"
106 #include "llvm/ADT/StringExtras.h"
107 #include "llvm/Support/CommandLine.h"
108 #include "llvm/Support/Debug.h"
109 #include "llvm/Support/ErrorHandling.h"
110 #include "llvm/TableGen/Error.h"
111 #include "llvm/TableGen/Record.h"
112 #include "llvm/TableGen/StringMatcher.h"
113 #include "llvm/TableGen/TableGenBackend.h"
117 using namespace llvm;
119 static cl::opt<std::string>
120 MatchPrefix("match-prefix", cl::init(""),
121 cl::desc("Only match instructions with the given prefix"));
124 class AsmMatcherInfo;
125 struct SubtargetFeatureInfo;
127 class AsmMatcherEmitter {
128 RecordKeeper &Records;
130 AsmMatcherEmitter(RecordKeeper &R) : Records(R) {}
132 void run(raw_ostream &o);
135 /// ClassInfo - Helper class for storing the information about a particular
136 /// class of operands which can be matched.
139 /// Invalid kind, for use as a sentinel value.
142 /// The class for a particular token.
145 /// The (first) register class, subsequent register classes are
146 /// RegisterClass0+1, and so on.
149 /// The (first) user defined class, subsequent user defined classes are
150 /// UserClass0+1, and so on.
154 /// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
155 /// N) for the Nth user defined class.
158 /// SuperClasses - The super classes of this class. Note that for simplicities
159 /// sake user operands only record their immediate super class, while register
160 /// operands include all superclasses.
161 std::vector<ClassInfo*> SuperClasses;
163 /// Name - The full class name, suitable for use in an enum.
166 /// ClassName - The unadorned generic name for this class (e.g., Token).
167 std::string ClassName;
169 /// ValueName - The name of the value this class represents; for a token this
170 /// is the literal token string, for an operand it is the TableGen class (or
171 /// empty if this is a derived class).
172 std::string ValueName;
174 /// PredicateMethod - The name of the operand method to test whether the
175 /// operand matches this class; this is not valid for Token or register kinds.
176 std::string PredicateMethod;
178 /// RenderMethod - The name of the operand method to add this operand to an
179 /// MCInst; this is not valid for Token or register kinds.
180 std::string RenderMethod;
182 /// ParserMethod - The name of the operand method to do a target specific
183 /// parsing on the operand.
184 std::string ParserMethod;
186 /// For register classes, the records for all the registers in this class.
187 std::set<Record*> Registers;
189 /// For custom match classes, he diagnostic kind for when the predicate fails.
190 std::string DiagnosticType;
192 /// isRegisterClass() - Check if this is a register class.
193 bool isRegisterClass() const {
194 return Kind >= RegisterClass0 && Kind < UserClass0;
197 /// isUserClass() - Check if this is a user defined class.
198 bool isUserClass() const {
199 return Kind >= UserClass0;
202 /// isRelatedTo - Check whether this class is "related" to \p RHS. Classes
203 /// are related if they are in the same class hierarchy.
204 bool isRelatedTo(const ClassInfo &RHS) const {
205 // Tokens are only related to tokens.
206 if (Kind == Token || RHS.Kind == Token)
207 return Kind == Token && RHS.Kind == Token;
209 // Registers classes are only related to registers classes, and only if
210 // their intersection is non-empty.
211 if (isRegisterClass() || RHS.isRegisterClass()) {
212 if (!isRegisterClass() || !RHS.isRegisterClass())
215 std::set<Record*> Tmp;
216 std::insert_iterator< std::set<Record*> > II(Tmp, Tmp.begin());
217 std::set_intersection(Registers.begin(), Registers.end(),
218 RHS.Registers.begin(), RHS.Registers.end(),
224 // Otherwise we have two users operands; they are related if they are in the
225 // same class hierarchy.
227 // FIXME: This is an oversimplification, they should only be related if they
228 // intersect, however we don't have that information.
229 assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");
230 const ClassInfo *Root = this;
231 while (!Root->SuperClasses.empty())
232 Root = Root->SuperClasses.front();
234 const ClassInfo *RHSRoot = &RHS;
235 while (!RHSRoot->SuperClasses.empty())
236 RHSRoot = RHSRoot->SuperClasses.front();
238 return Root == RHSRoot;
241 /// isSubsetOf - Test whether this class is a subset of \p RHS.
242 bool isSubsetOf(const ClassInfo &RHS) const {
243 // This is a subset of RHS if it is the same class...
247 // ... or if any of its super classes are a subset of RHS.
248 for (std::vector<ClassInfo*>::const_iterator it = SuperClasses.begin(),
249 ie = SuperClasses.end(); it != ie; ++it)
250 if ((*it)->isSubsetOf(RHS))
256 /// operator< - Compare two classes.
257 bool operator<(const ClassInfo &RHS) const {
261 // Unrelated classes can be ordered by kind.
262 if (!isRelatedTo(RHS))
263 return Kind < RHS.Kind;
267 llvm_unreachable("Invalid kind!");
270 // This class precedes the RHS if it is a proper subset of the RHS.
273 if (RHS.isSubsetOf(*this))
276 // Otherwise, order by name to ensure we have a total ordering.
277 return ValueName < RHS.ValueName;
282 /// MatchableInfo - Helper class for storing the necessary information for an
283 /// instruction or alias which is capable of being matched.
284 struct MatchableInfo {
286 /// Token - This is the token that the operand came from.
289 /// The unique class instance this operand should match.
292 /// The operand name this is, if anything.
295 /// The suboperand index within SrcOpName, or -1 for the entire operand.
298 /// Register record if this token is singleton register.
299 Record *SingletonReg;
301 explicit AsmOperand(StringRef T) : Token(T), Class(0), SubOpIdx(-1),
305 /// ResOperand - This represents a single operand in the result instruction
306 /// generated by the match. In cases (like addressing modes) where a single
307 /// assembler operand expands to multiple MCOperands, this represents the
308 /// single assembler operand, not the MCOperand.
311 /// RenderAsmOperand - This represents an operand result that is
312 /// generated by calling the render method on the assembly operand. The
313 /// corresponding AsmOperand is specified by AsmOperandNum.
316 /// TiedOperand - This represents a result operand that is a duplicate of
317 /// a previous result operand.
320 /// ImmOperand - This represents an immediate value that is dumped into
324 /// RegOperand - This represents a fixed register that is dumped in.
329 /// This is the operand # in the AsmOperands list that this should be
331 unsigned AsmOperandNum;
333 /// TiedOperandNum - This is the (earlier) result operand that should be
335 unsigned TiedOperandNum;
337 /// ImmVal - This is the immediate value added to the instruction.
340 /// Register - This is the register record.
344 /// MINumOperands - The number of MCInst operands populated by this
346 unsigned MINumOperands;
348 static ResOperand getRenderedOp(unsigned AsmOpNum, unsigned NumOperands) {
350 X.Kind = RenderAsmOperand;
351 X.AsmOperandNum = AsmOpNum;
352 X.MINumOperands = NumOperands;
356 static ResOperand getTiedOp(unsigned TiedOperandNum) {
358 X.Kind = TiedOperand;
359 X.TiedOperandNum = TiedOperandNum;
364 static ResOperand getImmOp(int64_t Val) {
372 static ResOperand getRegOp(Record *Reg) {
381 /// AsmVariantID - Target's assembly syntax variant no.
384 /// TheDef - This is the definition of the instruction or InstAlias that this
385 /// matchable came from.
386 Record *const TheDef;
388 /// DefRec - This is the definition that it came from.
389 PointerUnion<const CodeGenInstruction*, const CodeGenInstAlias*> DefRec;
391 const CodeGenInstruction *getResultInst() const {
392 if (DefRec.is<const CodeGenInstruction*>())
393 return DefRec.get<const CodeGenInstruction*>();
394 return DefRec.get<const CodeGenInstAlias*>()->ResultInst;
397 /// ResOperands - This is the operand list that should be built for the result
399 SmallVector<ResOperand, 8> ResOperands;
401 /// AsmString - The assembly string for this instruction (with variants
402 /// removed), e.g. "movsx $src, $dst".
403 std::string AsmString;
405 /// Mnemonic - This is the first token of the matched instruction, its
409 /// AsmOperands - The textual operands that this instruction matches,
410 /// annotated with a class and where in the OperandList they were defined.
411 /// This directly corresponds to the tokenized AsmString after the mnemonic is
413 SmallVector<AsmOperand, 8> AsmOperands;
415 /// Predicates - The required subtarget features to match this instruction.
416 SmallVector<SubtargetFeatureInfo*, 4> RequiredFeatures;
418 /// ConversionFnKind - The enum value which is passed to the generated
419 /// convertToMCInst to convert parsed operands into an MCInst for this
421 std::string ConversionFnKind;
423 MatchableInfo(const CodeGenInstruction &CGI)
424 : AsmVariantID(0), TheDef(CGI.TheDef), DefRec(&CGI),
425 AsmString(CGI.AsmString) {
428 MatchableInfo(const CodeGenInstAlias *Alias)
429 : AsmVariantID(0), TheDef(Alias->TheDef), DefRec(Alias),
430 AsmString(Alias->AsmString) {
433 // Two-operand aliases clone from the main matchable, but mark the second
434 // operand as a tied operand of the first for purposes of the assembler.
435 void formTwoOperandAlias(StringRef Constraint);
437 void initialize(const AsmMatcherInfo &Info,
438 SmallPtrSet<Record*, 16> &SingletonRegisters,
439 int AsmVariantNo, std::string &RegisterPrefix);
441 /// validate - Return true if this matchable is a valid thing to match against
442 /// and perform a bunch of validity checking.
443 bool validate(StringRef CommentDelimiter, bool Hack) const;
445 /// extractSingletonRegisterForAsmOperand - Extract singleton register,
446 /// if present, from specified token.
448 extractSingletonRegisterForAsmOperand(unsigned i, const AsmMatcherInfo &Info,
449 std::string &RegisterPrefix);
451 /// findAsmOperand - Find the AsmOperand with the specified name and
452 /// suboperand index.
453 int findAsmOperand(StringRef N, int SubOpIdx) const {
454 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
455 if (N == AsmOperands[i].SrcOpName &&
456 SubOpIdx == AsmOperands[i].SubOpIdx)
461 /// findAsmOperandNamed - Find the first AsmOperand with the specified name.
462 /// This does not check the suboperand index.
463 int findAsmOperandNamed(StringRef N) const {
464 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
465 if (N == AsmOperands[i].SrcOpName)
470 void buildInstructionResultOperands();
471 void buildAliasResultOperands();
473 /// operator< - Compare two matchables.
474 bool operator<(const MatchableInfo &RHS) const {
475 // The primary comparator is the instruction mnemonic.
476 if (Mnemonic != RHS.Mnemonic)
477 return Mnemonic < RHS.Mnemonic;
479 if (AsmOperands.size() != RHS.AsmOperands.size())
480 return AsmOperands.size() < RHS.AsmOperands.size();
482 // Compare lexicographically by operand. The matcher validates that other
483 // orderings wouldn't be ambiguous using \see couldMatchAmbiguouslyWith().
484 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
485 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
487 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
491 // Give matches that require more features higher precedence. This is useful
492 // because we cannot define AssemblerPredicates with the negation of
493 // processor features. For example, ARM v6 "nop" may be either a HINT or
494 // MOV. With v6, we want to match HINT. The assembler has no way to
495 // predicate MOV under "NoV6", but HINT will always match first because it
496 // requires V6 while MOV does not.
497 if (RequiredFeatures.size() != RHS.RequiredFeatures.size())
498 return RequiredFeatures.size() > RHS.RequiredFeatures.size();
503 /// couldMatchAmbiguouslyWith - Check whether this matchable could
504 /// ambiguously match the same set of operands as \p RHS (without being a
505 /// strictly superior match).
506 bool couldMatchAmbiguouslyWith(const MatchableInfo &RHS) {
507 // The primary comparator is the instruction mnemonic.
508 if (Mnemonic != RHS.Mnemonic)
511 // The number of operands is unambiguous.
512 if (AsmOperands.size() != RHS.AsmOperands.size())
515 // Otherwise, make sure the ordering of the two instructions is unambiguous
516 // by checking that either (a) a token or operand kind discriminates them,
517 // or (b) the ordering among equivalent kinds is consistent.
519 // Tokens and operand kinds are unambiguous (assuming a correct target
521 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
522 if (AsmOperands[i].Class->Kind != RHS.AsmOperands[i].Class->Kind ||
523 AsmOperands[i].Class->Kind == ClassInfo::Token)
524 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class ||
525 *RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
528 // Otherwise, this operand could commute if all operands are equivalent, or
529 // there is a pair of operands that compare less than and a pair that
530 // compare greater than.
531 bool HasLT = false, HasGT = false;
532 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
533 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
535 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
539 return !(HasLT ^ HasGT);
545 void tokenizeAsmString(const AsmMatcherInfo &Info);
548 /// SubtargetFeatureInfo - Helper class for storing information on a subtarget
549 /// feature which participates in instruction matching.
550 struct SubtargetFeatureInfo {
551 /// \brief The predicate record for this feature.
554 /// \brief An unique index assigned to represent this feature.
557 SubtargetFeatureInfo(Record *D, unsigned Idx) : TheDef(D), Index(Idx) {}
559 /// \brief The name of the enumerated constant identifying this feature.
560 std::string getEnumName() const {
561 return "Feature_" + TheDef->getName();
565 struct OperandMatchEntry {
566 unsigned OperandMask;
570 static OperandMatchEntry create(MatchableInfo* mi, ClassInfo *ci,
573 X.OperandMask = opMask;
581 class AsmMatcherInfo {
584 RecordKeeper &Records;
586 /// The tablegen AsmParser record.
589 /// Target - The target information.
590 CodeGenTarget &Target;
592 /// The classes which are needed for matching.
593 std::vector<ClassInfo*> Classes;
595 /// The information on the matchables to match.
596 std::vector<MatchableInfo*> Matchables;
598 /// Info for custom matching operands by user defined methods.
599 std::vector<OperandMatchEntry> OperandMatchInfo;
601 /// Map of Register records to their class information.
602 typedef std::map<Record*, ClassInfo*, LessRecordByID> RegisterClassesTy;
603 RegisterClassesTy RegisterClasses;
605 /// Map of Predicate records to their subtarget information.
606 std::map<Record*, SubtargetFeatureInfo*> SubtargetFeatures;
608 /// Map of AsmOperandClass records to their class information.
609 std::map<Record*, ClassInfo*> AsmOperandClasses;
612 /// Map of token to class information which has already been constructed.
613 std::map<std::string, ClassInfo*> TokenClasses;
615 /// Map of RegisterClass records to their class information.
616 std::map<Record*, ClassInfo*> RegisterClassClasses;
619 /// getTokenClass - Lookup or create the class for the given token.
620 ClassInfo *getTokenClass(StringRef Token);
622 /// getOperandClass - Lookup or create the class for the given operand.
623 ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI,
625 ClassInfo *getOperandClass(Record *Rec, int SubOpIdx);
627 /// buildRegisterClasses - Build the ClassInfo* instances for register
629 void buildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters);
631 /// buildOperandClasses - Build the ClassInfo* instances for user defined
633 void buildOperandClasses();
635 void buildInstructionOperandReference(MatchableInfo *II, StringRef OpName,
637 void buildAliasOperandReference(MatchableInfo *II, StringRef OpName,
638 MatchableInfo::AsmOperand &Op);
641 AsmMatcherInfo(Record *AsmParser,
642 CodeGenTarget &Target,
643 RecordKeeper &Records);
645 /// buildInfo - Construct the various tables used during matching.
648 /// buildOperandMatchInfo - Build the necessary information to handle user
649 /// defined operand parsing methods.
650 void buildOperandMatchInfo();
652 /// getSubtargetFeature - Lookup or create the subtarget feature info for the
654 SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const {
655 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
656 std::map<Record*, SubtargetFeatureInfo*>::const_iterator I =
657 SubtargetFeatures.find(Def);
658 return I == SubtargetFeatures.end() ? 0 : I->second;
661 RecordKeeper &getRecords() const {
666 } // End anonymous namespace
668 void MatchableInfo::dump() {
669 errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n";
671 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
672 AsmOperand &Op = AsmOperands[i];
673 errs() << " op[" << i << "] = " << Op.Class->ClassName << " - ";
674 errs() << '\"' << Op.Token << "\"\n";
678 static std::pair<StringRef, StringRef>
679 parseTwoOperandConstraint(StringRef S, ArrayRef<SMLoc> Loc) {
680 // Split via the '='.
681 std::pair<StringRef, StringRef> Ops = S.split('=');
682 if (Ops.second == "")
683 throw TGError(Loc, "missing '=' in two-operand alias constraint");
684 // Trim whitespace and the leading '$' on the operand names.
685 size_t start = Ops.first.find_first_of('$');
686 if (start == std::string::npos)
687 throw TGError(Loc, "expected '$' prefix on asm operand name");
688 Ops.first = Ops.first.slice(start + 1, std::string::npos);
689 size_t end = Ops.first.find_last_of(" \t");
690 Ops.first = Ops.first.slice(0, end);
691 // Now the second operand.
692 start = Ops.second.find_first_of('$');
693 if (start == std::string::npos)
694 throw TGError(Loc, "expected '$' prefix on asm operand name");
695 Ops.second = Ops.second.slice(start + 1, std::string::npos);
696 end = Ops.second.find_last_of(" \t");
697 Ops.first = Ops.first.slice(0, end);
701 void MatchableInfo::formTwoOperandAlias(StringRef Constraint) {
702 // Figure out which operands are aliased and mark them as tied.
703 std::pair<StringRef, StringRef> Ops =
704 parseTwoOperandConstraint(Constraint, TheDef->getLoc());
706 // Find the AsmOperands that refer to the operands we're aliasing.
707 int SrcAsmOperand = findAsmOperandNamed(Ops.first);
708 int DstAsmOperand = findAsmOperandNamed(Ops.second);
709 if (SrcAsmOperand == -1)
710 throw TGError(TheDef->getLoc(),
711 "unknown source two-operand alias operand '" +
712 Ops.first.str() + "'.");
713 if (DstAsmOperand == -1)
714 throw TGError(TheDef->getLoc(),
715 "unknown destination two-operand alias operand '" +
716 Ops.second.str() + "'.");
718 // Find the ResOperand that refers to the operand we're aliasing away
719 // and update it to refer to the combined operand instead.
720 for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) {
721 ResOperand &Op = ResOperands[i];
722 if (Op.Kind == ResOperand::RenderAsmOperand &&
723 Op.AsmOperandNum == (unsigned)SrcAsmOperand) {
724 Op.AsmOperandNum = DstAsmOperand;
728 // Remove the AsmOperand for the alias operand.
729 AsmOperands.erase(AsmOperands.begin() + SrcAsmOperand);
730 // Adjust the ResOperand references to any AsmOperands that followed
731 // the one we just deleted.
732 for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) {
733 ResOperand &Op = ResOperands[i];
736 // Nothing to do for operands that don't reference AsmOperands.
738 case ResOperand::RenderAsmOperand:
739 if (Op.AsmOperandNum > (unsigned)SrcAsmOperand)
742 case ResOperand::TiedOperand:
743 if (Op.TiedOperandNum > (unsigned)SrcAsmOperand)
750 void MatchableInfo::initialize(const AsmMatcherInfo &Info,
751 SmallPtrSet<Record*, 16> &SingletonRegisters,
752 int AsmVariantNo, std::string &RegisterPrefix) {
753 AsmVariantID = AsmVariantNo;
755 CodeGenInstruction::FlattenAsmStringVariants(AsmString, AsmVariantNo);
757 tokenizeAsmString(Info);
759 // Compute the require features.
760 std::vector<Record*> Predicates =TheDef->getValueAsListOfDefs("Predicates");
761 for (unsigned i = 0, e = Predicates.size(); i != e; ++i)
762 if (SubtargetFeatureInfo *Feature =
763 Info.getSubtargetFeature(Predicates[i]))
764 RequiredFeatures.push_back(Feature);
766 // Collect singleton registers, if used.
767 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
768 extractSingletonRegisterForAsmOperand(i, Info, RegisterPrefix);
769 if (Record *Reg = AsmOperands[i].SingletonReg)
770 SingletonRegisters.insert(Reg);
774 /// tokenizeAsmString - Tokenize a simplified assembly string.
775 void MatchableInfo::tokenizeAsmString(const AsmMatcherInfo &Info) {
776 StringRef String = AsmString;
779 for (unsigned i = 0, e = String.size(); i != e; ++i) {
789 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
792 if (!isspace(String[i]) && String[i] != ',')
793 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
799 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
803 assert(i != String.size() && "Invalid quoted character");
804 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
810 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
814 // If this isn't "${", treat like a normal token.
815 if (i + 1 == String.size() || String[i + 1] != '{') {
820 StringRef::iterator End = std::find(String.begin() + i, String.end(),'}');
821 assert(End != String.end() && "Missing brace in operand reference!");
822 size_t EndPos = End - String.begin();
823 AsmOperands.push_back(AsmOperand(String.slice(i, EndPos+1)));
831 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
840 if (InTok && Prev != String.size())
841 AsmOperands.push_back(AsmOperand(String.substr(Prev)));
843 // The first token of the instruction is the mnemonic, which must be a
844 // simple string, not a $foo variable or a singleton register.
845 if (AsmOperands.empty())
846 throw TGError(TheDef->getLoc(),
847 "Instruction '" + TheDef->getName() + "' has no tokens");
848 Mnemonic = AsmOperands[0].Token;
849 if (Mnemonic.empty())
850 throw TGError(TheDef->getLoc(),
851 "Missing instruction mnemonic");
852 // FIXME : Check and raise an error if it is a register.
853 if (Mnemonic[0] == '$')
854 throw TGError(TheDef->getLoc(),
855 "Invalid instruction mnemonic '" + Mnemonic.str() + "'!");
857 // Remove the first operand, it is tracked in the mnemonic field.
858 AsmOperands.erase(AsmOperands.begin());
861 bool MatchableInfo::validate(StringRef CommentDelimiter, bool Hack) const {
862 // Reject matchables with no .s string.
863 if (AsmString.empty())
864 throw TGError(TheDef->getLoc(), "instruction with empty asm string");
866 // Reject any matchables with a newline in them, they should be marked
867 // isCodeGenOnly if they are pseudo instructions.
868 if (AsmString.find('\n') != std::string::npos)
869 throw TGError(TheDef->getLoc(),
870 "multiline instruction is not valid for the asmparser, "
871 "mark it isCodeGenOnly");
873 // Remove comments from the asm string. We know that the asmstring only
875 if (!CommentDelimiter.empty() &&
876 StringRef(AsmString).find(CommentDelimiter) != StringRef::npos)
877 throw TGError(TheDef->getLoc(),
878 "asmstring for instruction has comment character in it, "
879 "mark it isCodeGenOnly");
881 // Reject matchables with operand modifiers, these aren't something we can
882 // handle, the target should be refactored to use operands instead of
885 // Also, check for instructions which reference the operand multiple times;
886 // this implies a constraint we would not honor.
887 std::set<std::string> OperandNames;
888 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
889 StringRef Tok = AsmOperands[i].Token;
890 if (Tok[0] == '$' && Tok.find(':') != StringRef::npos)
891 throw TGError(TheDef->getLoc(),
892 "matchable with operand modifier '" + Tok.str() +
893 "' not supported by asm matcher. Mark isCodeGenOnly!");
895 // Verify that any operand is only mentioned once.
896 // We reject aliases and ignore instructions for now.
897 if (Tok[0] == '$' && !OperandNames.insert(Tok).second) {
899 throw TGError(TheDef->getLoc(),
900 "ERROR: matchable with tied operand '" + Tok.str() +
901 "' can never be matched!");
902 // FIXME: Should reject these. The ARM backend hits this with $lane in a
903 // bunch of instructions. It is unclear what the right answer is.
905 errs() << "warning: '" << TheDef->getName() << "': "
906 << "ignoring instruction with tied operand '"
907 << Tok.str() << "'\n";
916 /// extractSingletonRegisterForAsmOperand - Extract singleton register,
917 /// if present, from specified token.
919 extractSingletonRegisterForAsmOperand(unsigned OperandNo,
920 const AsmMatcherInfo &Info,
921 std::string &RegisterPrefix) {
922 StringRef Tok = AsmOperands[OperandNo].Token;
923 if (RegisterPrefix.empty()) {
924 std::string LoweredTok = Tok.lower();
925 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(LoweredTok))
926 AsmOperands[OperandNo].SingletonReg = Reg->TheDef;
930 if (!Tok.startswith(RegisterPrefix))
933 StringRef RegName = Tok.substr(RegisterPrefix.size());
934 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName))
935 AsmOperands[OperandNo].SingletonReg = Reg->TheDef;
937 // If there is no register prefix (i.e. "%" in "%eax"), then this may
938 // be some random non-register token, just ignore it.
942 static std::string getEnumNameForToken(StringRef Str) {
945 for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) {
947 case '*': Res += "_STAR_"; break;
948 case '%': Res += "_PCT_"; break;
949 case ':': Res += "_COLON_"; break;
950 case '!': Res += "_EXCLAIM_"; break;
951 case '.': Res += "_DOT_"; break;
956 Res += "_" + utostr((unsigned) *it) + "_";
963 ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) {
964 ClassInfo *&Entry = TokenClasses[Token];
967 Entry = new ClassInfo();
968 Entry->Kind = ClassInfo::Token;
969 Entry->ClassName = "Token";
970 Entry->Name = "MCK_" + getEnumNameForToken(Token);
971 Entry->ValueName = Token;
972 Entry->PredicateMethod = "<invalid>";
973 Entry->RenderMethod = "<invalid>";
974 Entry->ParserMethod = "";
975 Entry->DiagnosticType = "";
976 Classes.push_back(Entry);
983 AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI,
985 Record *Rec = OI.Rec;
987 Rec = dynamic_cast<DefInit*>(OI.MIOperandInfo->getArg(SubOpIdx))->getDef();
988 return getOperandClass(Rec, SubOpIdx);
992 AsmMatcherInfo::getOperandClass(Record *Rec, int SubOpIdx) {
993 if (Rec->isSubClassOf("RegisterOperand")) {
994 // RegisterOperand may have an associated ParserMatchClass. If it does,
995 // use it, else just fall back to the underlying register class.
996 const RecordVal *R = Rec->getValue("ParserMatchClass");
997 if (R == 0 || R->getValue() == 0)
998 throw "Record `" + Rec->getName() +
999 "' does not have a ParserMatchClass!\n";
1001 if (DefInit *DI= dynamic_cast<DefInit*>(R->getValue())) {
1002 Record *MatchClass = DI->getDef();
1003 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1007 // No custom match class. Just use the register class.
1008 Record *ClassRec = Rec->getValueAsDef("RegClass");
1010 throw TGError(Rec->getLoc(), "RegisterOperand `" + Rec->getName() +
1011 "' has no associated register class!\n");
1012 if (ClassInfo *CI = RegisterClassClasses[ClassRec])
1014 throw TGError(Rec->getLoc(), "register class has no class info!");
1018 if (Rec->isSubClassOf("RegisterClass")) {
1019 if (ClassInfo *CI = RegisterClassClasses[Rec])
1021 throw TGError(Rec->getLoc(), "register class has no class info!");
1024 if (!Rec->isSubClassOf("Operand"))
1025 throw TGError(Rec->getLoc(), "Operand `" + Rec->getName() +
1026 "' does not derive from class Operand!\n");
1027 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1028 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1031 throw TGError(Rec->getLoc(), "operand has no match class!");
1034 void AsmMatcherInfo::
1035 buildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters) {
1036 const std::vector<CodeGenRegister*> &Registers =
1037 Target.getRegBank().getRegisters();
1038 ArrayRef<CodeGenRegisterClass*> RegClassList =
1039 Target.getRegBank().getRegClasses();
1041 // The register sets used for matching.
1042 std::set< std::set<Record*> > RegisterSets;
1044 // Gather the defined sets.
1045 for (ArrayRef<CodeGenRegisterClass*>::const_iterator it =
1046 RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it)
1047 RegisterSets.insert(std::set<Record*>(
1048 (*it)->getOrder().begin(), (*it)->getOrder().end()));
1050 // Add any required singleton sets.
1051 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
1052 ie = SingletonRegisters.end(); it != ie; ++it) {
1054 RegisterSets.insert(std::set<Record*>(&Rec, &Rec + 1));
1057 // Introduce derived sets where necessary (when a register does not determine
1058 // a unique register set class), and build the mapping of registers to the set
1059 // they should classify to.
1060 std::map<Record*, std::set<Record*> > RegisterMap;
1061 for (std::vector<CodeGenRegister*>::const_iterator it = Registers.begin(),
1062 ie = Registers.end(); it != ie; ++it) {
1063 const CodeGenRegister &CGR = **it;
1064 // Compute the intersection of all sets containing this register.
1065 std::set<Record*> ContainingSet;
1067 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
1068 ie = RegisterSets.end(); it != ie; ++it) {
1069 if (!it->count(CGR.TheDef))
1072 if (ContainingSet.empty()) {
1073 ContainingSet = *it;
1077 std::set<Record*> Tmp;
1078 std::swap(Tmp, ContainingSet);
1079 std::insert_iterator< std::set<Record*> > II(ContainingSet,
1080 ContainingSet.begin());
1081 std::set_intersection(Tmp.begin(), Tmp.end(), it->begin(), it->end(), II);
1084 if (!ContainingSet.empty()) {
1085 RegisterSets.insert(ContainingSet);
1086 RegisterMap.insert(std::make_pair(CGR.TheDef, ContainingSet));
1090 // Construct the register classes.
1091 std::map<std::set<Record*>, ClassInfo*> RegisterSetClasses;
1093 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
1094 ie = RegisterSets.end(); it != ie; ++it, ++Index) {
1095 ClassInfo *CI = new ClassInfo();
1096 CI->Kind = ClassInfo::RegisterClass0 + Index;
1097 CI->ClassName = "Reg" + utostr(Index);
1098 CI->Name = "MCK_Reg" + utostr(Index);
1100 CI->PredicateMethod = ""; // unused
1101 CI->RenderMethod = "addRegOperands";
1102 CI->Registers = *it;
1103 // FIXME: diagnostic type.
1104 CI->DiagnosticType = "";
1105 Classes.push_back(CI);
1106 RegisterSetClasses.insert(std::make_pair(*it, CI));
1109 // Find the superclasses; we could compute only the subgroup lattice edges,
1110 // but there isn't really a point.
1111 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
1112 ie = RegisterSets.end(); it != ie; ++it) {
1113 ClassInfo *CI = RegisterSetClasses[*it];
1114 for (std::set< std::set<Record*> >::iterator it2 = RegisterSets.begin(),
1115 ie2 = RegisterSets.end(); it2 != ie2; ++it2)
1117 std::includes(it2->begin(), it2->end(), it->begin(), it->end()))
1118 CI->SuperClasses.push_back(RegisterSetClasses[*it2]);
1121 // Name the register classes which correspond to a user defined RegisterClass.
1122 for (ArrayRef<CodeGenRegisterClass*>::const_iterator
1123 it = RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it) {
1124 const CodeGenRegisterClass &RC = **it;
1125 // Def will be NULL for non-user defined register classes.
1126 Record *Def = RC.getDef();
1129 ClassInfo *CI = RegisterSetClasses[std::set<Record*>(RC.getOrder().begin(),
1130 RC.getOrder().end())];
1131 if (CI->ValueName.empty()) {
1132 CI->ClassName = RC.getName();
1133 CI->Name = "MCK_" + RC.getName();
1134 CI->ValueName = RC.getName();
1136 CI->ValueName = CI->ValueName + "," + RC.getName();
1138 RegisterClassClasses.insert(std::make_pair(Def, CI));
1141 // Populate the map for individual registers.
1142 for (std::map<Record*, std::set<Record*> >::iterator it = RegisterMap.begin(),
1143 ie = RegisterMap.end(); it != ie; ++it)
1144 RegisterClasses[it->first] = RegisterSetClasses[it->second];
1146 // Name the register classes which correspond to singleton registers.
1147 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
1148 ie = SingletonRegisters.end(); it != ie; ++it) {
1150 ClassInfo *CI = RegisterClasses[Rec];
1151 assert(CI && "Missing singleton register class info!");
1153 if (CI->ValueName.empty()) {
1154 CI->ClassName = Rec->getName();
1155 CI->Name = "MCK_" + Rec->getName();
1156 CI->ValueName = Rec->getName();
1158 CI->ValueName = CI->ValueName + "," + Rec->getName();
1162 void AsmMatcherInfo::buildOperandClasses() {
1163 std::vector<Record*> AsmOperands =
1164 Records.getAllDerivedDefinitions("AsmOperandClass");
1166 // Pre-populate AsmOperandClasses map.
1167 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
1168 ie = AsmOperands.end(); it != ie; ++it)
1169 AsmOperandClasses[*it] = new ClassInfo();
1172 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
1173 ie = AsmOperands.end(); it != ie; ++it, ++Index) {
1174 ClassInfo *CI = AsmOperandClasses[*it];
1175 CI->Kind = ClassInfo::UserClass0 + Index;
1177 ListInit *Supers = (*it)->getValueAsListInit("SuperClasses");
1178 for (unsigned i = 0, e = Supers->getSize(); i != e; ++i) {
1179 DefInit *DI = dynamic_cast<DefInit*>(Supers->getElement(i));
1181 PrintError((*it)->getLoc(), "Invalid super class reference!");
1185 ClassInfo *SC = AsmOperandClasses[DI->getDef()];
1187 PrintError((*it)->getLoc(), "Invalid super class reference!");
1189 CI->SuperClasses.push_back(SC);
1191 CI->ClassName = (*it)->getValueAsString("Name");
1192 CI->Name = "MCK_" + CI->ClassName;
1193 CI->ValueName = (*it)->getName();
1195 // Get or construct the predicate method name.
1196 Init *PMName = (*it)->getValueInit("PredicateMethod");
1197 if (StringInit *SI = dynamic_cast<StringInit*>(PMName)) {
1198 CI->PredicateMethod = SI->getValue();
1200 assert(dynamic_cast<UnsetInit*>(PMName) &&
1201 "Unexpected PredicateMethod field!");
1202 CI->PredicateMethod = "is" + CI->ClassName;
1205 // Get or construct the render method name.
1206 Init *RMName = (*it)->getValueInit("RenderMethod");
1207 if (StringInit *SI = dynamic_cast<StringInit*>(RMName)) {
1208 CI->RenderMethod = SI->getValue();
1210 assert(dynamic_cast<UnsetInit*>(RMName) &&
1211 "Unexpected RenderMethod field!");
1212 CI->RenderMethod = "add" + CI->ClassName + "Operands";
1215 // Get the parse method name or leave it as empty.
1216 Init *PRMName = (*it)->getValueInit("ParserMethod");
1217 if (StringInit *SI = dynamic_cast<StringInit*>(PRMName))
1218 CI->ParserMethod = SI->getValue();
1220 // Get the diagnostic type or leave it as empty.
1221 // Get the parse method name or leave it as empty.
1222 Init *DiagnosticType = (*it)->getValueInit("DiagnosticType");
1223 if (StringInit *SI = dynamic_cast<StringInit*>(DiagnosticType))
1224 CI->DiagnosticType = SI->getValue();
1226 AsmOperandClasses[*it] = CI;
1227 Classes.push_back(CI);
1231 AsmMatcherInfo::AsmMatcherInfo(Record *asmParser,
1232 CodeGenTarget &target,
1233 RecordKeeper &records)
1234 : Records(records), AsmParser(asmParser), Target(target) {
1237 /// buildOperandMatchInfo - Build the necessary information to handle user
1238 /// defined operand parsing methods.
1239 void AsmMatcherInfo::buildOperandMatchInfo() {
1241 /// Map containing a mask with all operands indices that can be found for
1242 /// that class inside a instruction.
1243 std::map<ClassInfo*, unsigned> OpClassMask;
1245 for (std::vector<MatchableInfo*>::const_iterator it =
1246 Matchables.begin(), ie = Matchables.end();
1248 MatchableInfo &II = **it;
1249 OpClassMask.clear();
1251 // Keep track of all operands of this instructions which belong to the
1253 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) {
1254 MatchableInfo::AsmOperand &Op = II.AsmOperands[i];
1255 if (Op.Class->ParserMethod.empty())
1257 unsigned &OperandMask = OpClassMask[Op.Class];
1258 OperandMask |= (1 << i);
1261 // Generate operand match info for each mnemonic/operand class pair.
1262 for (std::map<ClassInfo*, unsigned>::iterator iit = OpClassMask.begin(),
1263 iie = OpClassMask.end(); iit != iie; ++iit) {
1264 unsigned OpMask = iit->second;
1265 ClassInfo *CI = iit->first;
1266 OperandMatchInfo.push_back(OperandMatchEntry::create(&II, CI, OpMask));
1271 void AsmMatcherInfo::buildInfo() {
1272 // Build information about all of the AssemblerPredicates.
1273 std::vector<Record*> AllPredicates =
1274 Records.getAllDerivedDefinitions("Predicate");
1275 for (unsigned i = 0, e = AllPredicates.size(); i != e; ++i) {
1276 Record *Pred = AllPredicates[i];
1277 // Ignore predicates that are not intended for the assembler.
1278 if (!Pred->getValueAsBit("AssemblerMatcherPredicate"))
1281 if (Pred->getName().empty())
1282 throw TGError(Pred->getLoc(), "Predicate has no name!");
1284 unsigned FeatureNo = SubtargetFeatures.size();
1285 SubtargetFeatures[Pred] = new SubtargetFeatureInfo(Pred, FeatureNo);
1286 assert(FeatureNo < 32 && "Too many subtarget features!");
1289 // Parse the instructions; we need to do this first so that we can gather the
1290 // singleton register classes.
1291 SmallPtrSet<Record*, 16> SingletonRegisters;
1292 unsigned VariantCount = Target.getAsmParserVariantCount();
1293 for (unsigned VC = 0; VC != VariantCount; ++VC) {
1294 Record *AsmVariant = Target.getAsmParserVariant(VC);
1295 std::string CommentDelimiter =
1296 AsmVariant->getValueAsString("CommentDelimiter");
1297 std::string RegisterPrefix = AsmVariant->getValueAsString("RegisterPrefix");
1298 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
1300 for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
1301 E = Target.inst_end(); I != E; ++I) {
1302 const CodeGenInstruction &CGI = **I;
1304 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1305 // filter the set of instructions we consider.
1306 if (!StringRef(CGI.TheDef->getName()).startswith(MatchPrefix))
1309 // Ignore "codegen only" instructions.
1310 if (CGI.TheDef->getValueAsBit("isCodeGenOnly"))
1313 // Validate the operand list to ensure we can handle this instruction.
1314 for (unsigned i = 0, e = CGI.Operands.size(); i != e; ++i) {
1315 const CGIOperandList::OperandInfo &OI = CGI.Operands[i];
1317 // Validate tied operands.
1318 if (OI.getTiedRegister() != -1) {
1319 // If we have a tied operand that consists of multiple MCOperands,
1320 // reject it. We reject aliases and ignore instructions for now.
1321 if (OI.MINumOperands != 1) {
1322 // FIXME: Should reject these. The ARM backend hits this with $lane
1323 // in a bunch of instructions. The right answer is unclear.
1325 errs() << "warning: '" << CGI.TheDef->getName() << "': "
1326 << "ignoring instruction with multi-operand tied operand '"
1327 << OI.Name << "'\n";
1334 OwningPtr<MatchableInfo> II(new MatchableInfo(CGI));
1336 II->initialize(*this, SingletonRegisters, AsmVariantNo, RegisterPrefix);
1338 // Ignore instructions which shouldn't be matched and diagnose invalid
1339 // instruction definitions with an error.
1340 if (!II->validate(CommentDelimiter, true))
1343 // Ignore "Int_*" and "*_Int" instructions, which are internal aliases.
1345 // FIXME: This is a total hack.
1346 if (StringRef(II->TheDef->getName()).startswith("Int_") ||
1347 StringRef(II->TheDef->getName()).endswith("_Int"))
1350 Matchables.push_back(II.take());
1353 // Parse all of the InstAlias definitions and stick them in the list of
1355 std::vector<Record*> AllInstAliases =
1356 Records.getAllDerivedDefinitions("InstAlias");
1357 for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) {
1358 CodeGenInstAlias *Alias = new CodeGenInstAlias(AllInstAliases[i], Target);
1360 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1361 // filter the set of instruction aliases we consider, based on the target
1363 if (!StringRef(Alias->ResultInst->TheDef->getName())
1364 .startswith( MatchPrefix))
1367 OwningPtr<MatchableInfo> II(new MatchableInfo(Alias));
1369 II->initialize(*this, SingletonRegisters, AsmVariantNo, RegisterPrefix);
1371 // Validate the alias definitions.
1372 II->validate(CommentDelimiter, false);
1374 Matchables.push_back(II.take());
1378 // Build info for the register classes.
1379 buildRegisterClasses(SingletonRegisters);
1381 // Build info for the user defined assembly operand classes.
1382 buildOperandClasses();
1384 // Build the information about matchables, now that we have fully formed
1386 std::vector<MatchableInfo*> NewMatchables;
1387 for (std::vector<MatchableInfo*>::iterator it = Matchables.begin(),
1388 ie = Matchables.end(); it != ie; ++it) {
1389 MatchableInfo *II = *it;
1391 // Parse the tokens after the mnemonic.
1392 // Note: buildInstructionOperandReference may insert new AsmOperands, so
1393 // don't precompute the loop bound.
1394 for (unsigned i = 0; i != II->AsmOperands.size(); ++i) {
1395 MatchableInfo::AsmOperand &Op = II->AsmOperands[i];
1396 StringRef Token = Op.Token;
1398 // Check for singleton registers.
1399 if (Record *RegRecord = II->AsmOperands[i].SingletonReg) {
1400 Op.Class = RegisterClasses[RegRecord];
1401 assert(Op.Class && Op.Class->Registers.size() == 1 &&
1402 "Unexpected class for singleton register");
1406 // Check for simple tokens.
1407 if (Token[0] != '$') {
1408 Op.Class = getTokenClass(Token);
1412 if (Token.size() > 1 && isdigit(Token[1])) {
1413 Op.Class = getTokenClass(Token);
1417 // Otherwise this is an operand reference.
1418 StringRef OperandName;
1419 if (Token[1] == '{')
1420 OperandName = Token.substr(2, Token.size() - 3);
1422 OperandName = Token.substr(1);
1424 if (II->DefRec.is<const CodeGenInstruction*>())
1425 buildInstructionOperandReference(II, OperandName, i);
1427 buildAliasOperandReference(II, OperandName, Op);
1430 if (II->DefRec.is<const CodeGenInstruction*>()) {
1431 II->buildInstructionResultOperands();
1432 // If the instruction has a two-operand alias, build up the
1433 // matchable here. We'll add them in bulk at the end to avoid
1434 // confusing this loop.
1435 std::string Constraint =
1436 II->TheDef->getValueAsString("TwoOperandAliasConstraint");
1437 if (Constraint != "") {
1438 // Start by making a copy of the original matchable.
1439 OwningPtr<MatchableInfo> AliasII(new MatchableInfo(*II));
1441 // Adjust it to be a two-operand alias.
1442 AliasII->formTwoOperandAlias(Constraint);
1444 // Add the alias to the matchables list.
1445 NewMatchables.push_back(AliasII.take());
1448 II->buildAliasResultOperands();
1450 if (!NewMatchables.empty())
1451 Matchables.insert(Matchables.end(), NewMatchables.begin(),
1452 NewMatchables.end());
1454 // Process token alias definitions and set up the associated superclass
1456 std::vector<Record*> AllTokenAliases =
1457 Records.getAllDerivedDefinitions("TokenAlias");
1458 for (unsigned i = 0, e = AllTokenAliases.size(); i != e; ++i) {
1459 Record *Rec = AllTokenAliases[i];
1460 ClassInfo *FromClass = getTokenClass(Rec->getValueAsString("FromToken"));
1461 ClassInfo *ToClass = getTokenClass(Rec->getValueAsString("ToToken"));
1462 if (FromClass == ToClass)
1463 throw TGError(Rec->getLoc(),
1464 "error: Destination value identical to source value.");
1465 FromClass->SuperClasses.push_back(ToClass);
1468 // Reorder classes so that classes precede super classes.
1469 std::sort(Classes.begin(), Classes.end(), less_ptr<ClassInfo>());
1472 /// buildInstructionOperandReference - The specified operand is a reference to a
1473 /// named operand such as $src. Resolve the Class and OperandInfo pointers.
1474 void AsmMatcherInfo::
1475 buildInstructionOperandReference(MatchableInfo *II,
1476 StringRef OperandName,
1477 unsigned AsmOpIdx) {
1478 const CodeGenInstruction &CGI = *II->DefRec.get<const CodeGenInstruction*>();
1479 const CGIOperandList &Operands = CGI.Operands;
1480 MatchableInfo::AsmOperand *Op = &II->AsmOperands[AsmOpIdx];
1482 // Map this token to an operand.
1484 if (!Operands.hasOperandNamed(OperandName, Idx))
1485 throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" +
1486 OperandName.str() + "'");
1488 // If the instruction operand has multiple suboperands, but the parser
1489 // match class for the asm operand is still the default "ImmAsmOperand",
1490 // then handle each suboperand separately.
1491 if (Op->SubOpIdx == -1 && Operands[Idx].MINumOperands > 1) {
1492 Record *Rec = Operands[Idx].Rec;
1493 assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
1494 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1495 if (MatchClass && MatchClass->getValueAsString("Name") == "Imm") {
1496 // Insert remaining suboperands after AsmOpIdx in II->AsmOperands.
1497 StringRef Token = Op->Token; // save this in case Op gets moved
1498 for (unsigned SI = 1, SE = Operands[Idx].MINumOperands; SI != SE; ++SI) {
1499 MatchableInfo::AsmOperand NewAsmOp(Token);
1500 NewAsmOp.SubOpIdx = SI;
1501 II->AsmOperands.insert(II->AsmOperands.begin()+AsmOpIdx+SI, NewAsmOp);
1503 // Replace Op with first suboperand.
1504 Op = &II->AsmOperands[AsmOpIdx]; // update the pointer in case it moved
1509 // Set up the operand class.
1510 Op->Class = getOperandClass(Operands[Idx], Op->SubOpIdx);
1512 // If the named operand is tied, canonicalize it to the untied operand.
1513 // For example, something like:
1514 // (outs GPR:$dst), (ins GPR:$src)
1515 // with an asmstring of
1517 // we want to canonicalize to:
1519 // so that we know how to provide the $dst operand when filling in the result.
1520 int OITied = Operands[Idx].getTiedRegister();
1522 // The tied operand index is an MIOperand index, find the operand that
1524 std::pair<unsigned, unsigned> Idx = Operands.getSubOperandNumber(OITied);
1525 OperandName = Operands[Idx.first].Name;
1526 Op->SubOpIdx = Idx.second;
1529 Op->SrcOpName = OperandName;
1532 /// buildAliasOperandReference - When parsing an operand reference out of the
1533 /// matching string (e.g. "movsx $src, $dst"), determine what the class of the
1534 /// operand reference is by looking it up in the result pattern definition.
1535 void AsmMatcherInfo::buildAliasOperandReference(MatchableInfo *II,
1536 StringRef OperandName,
1537 MatchableInfo::AsmOperand &Op) {
1538 const CodeGenInstAlias &CGA = *II->DefRec.get<const CodeGenInstAlias*>();
1540 // Set up the operand class.
1541 for (unsigned i = 0, e = CGA.ResultOperands.size(); i != e; ++i)
1542 if (CGA.ResultOperands[i].isRecord() &&
1543 CGA.ResultOperands[i].getName() == OperandName) {
1544 // It's safe to go with the first one we find, because CodeGenInstAlias
1545 // validates that all operands with the same name have the same record.
1546 Op.SubOpIdx = CGA.ResultInstOperandIndex[i].second;
1547 // Use the match class from the Alias definition, not the
1548 // destination instruction, as we may have an immediate that's
1549 // being munged by the match class.
1550 Op.Class = getOperandClass(CGA.ResultOperands[i].getRecord(),
1552 Op.SrcOpName = OperandName;
1556 throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" +
1557 OperandName.str() + "'");
1560 void MatchableInfo::buildInstructionResultOperands() {
1561 const CodeGenInstruction *ResultInst = getResultInst();
1563 // Loop over all operands of the result instruction, determining how to
1565 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1566 const CGIOperandList::OperandInfo &OpInfo = ResultInst->Operands[i];
1568 // If this is a tied operand, just copy from the previously handled operand.
1569 int TiedOp = OpInfo.getTiedRegister();
1571 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1575 // Find out what operand from the asmparser this MCInst operand comes from.
1576 int SrcOperand = findAsmOperandNamed(OpInfo.Name);
1577 if (OpInfo.Name.empty() || SrcOperand == -1)
1578 throw TGError(TheDef->getLoc(), "Instruction '" +
1579 TheDef->getName() + "' has operand '" + OpInfo.Name +
1580 "' that doesn't appear in asm string!");
1582 // Check if the one AsmOperand populates the entire operand.
1583 unsigned NumOperands = OpInfo.MINumOperands;
1584 if (AsmOperands[SrcOperand].SubOpIdx == -1) {
1585 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, NumOperands));
1589 // Add a separate ResOperand for each suboperand.
1590 for (unsigned AI = 0; AI < NumOperands; ++AI) {
1591 assert(AsmOperands[SrcOperand+AI].SubOpIdx == (int)AI &&
1592 AsmOperands[SrcOperand+AI].SrcOpName == OpInfo.Name &&
1593 "unexpected AsmOperands for suboperands");
1594 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand + AI, 1));
1599 void MatchableInfo::buildAliasResultOperands() {
1600 const CodeGenInstAlias &CGA = *DefRec.get<const CodeGenInstAlias*>();
1601 const CodeGenInstruction *ResultInst = getResultInst();
1603 // Loop over all operands of the result instruction, determining how to
1605 unsigned AliasOpNo = 0;
1606 unsigned LastOpNo = CGA.ResultInstOperandIndex.size();
1607 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1608 const CGIOperandList::OperandInfo *OpInfo = &ResultInst->Operands[i];
1610 // If this is a tied operand, just copy from the previously handled operand.
1611 int TiedOp = OpInfo->getTiedRegister();
1613 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1617 // Handle all the suboperands for this operand.
1618 const std::string &OpName = OpInfo->Name;
1619 for ( ; AliasOpNo < LastOpNo &&
1620 CGA.ResultInstOperandIndex[AliasOpNo].first == i; ++AliasOpNo) {
1621 int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second;
1623 // Find out what operand from the asmparser that this MCInst operand
1625 switch (CGA.ResultOperands[AliasOpNo].Kind) {
1626 case CodeGenInstAlias::ResultOperand::K_Record: {
1627 StringRef Name = CGA.ResultOperands[AliasOpNo].getName();
1628 int SrcOperand = findAsmOperand(Name, SubIdx);
1629 if (SrcOperand == -1)
1630 throw TGError(TheDef->getLoc(), "Instruction '" +
1631 TheDef->getName() + "' has operand '" + OpName +
1632 "' that doesn't appear in asm string!");
1633 unsigned NumOperands = (SubIdx == -1 ? OpInfo->MINumOperands : 1);
1634 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand,
1638 case CodeGenInstAlias::ResultOperand::K_Imm: {
1639 int64_t ImmVal = CGA.ResultOperands[AliasOpNo].getImm();
1640 ResOperands.push_back(ResOperand::getImmOp(ImmVal));
1643 case CodeGenInstAlias::ResultOperand::K_Reg: {
1644 Record *Reg = CGA.ResultOperands[AliasOpNo].getRegister();
1645 ResOperands.push_back(ResOperand::getRegOp(Reg));
1653 static unsigned getConverterOperandID(const std::string &Name,
1654 SetVector<std::string> &Table,
1656 IsNew = Table.insert(Name);
1658 unsigned ID = IsNew ? Table.size() - 1 :
1659 std::find(Table.begin(), Table.end(), Name) - Table.begin();
1661 assert(ID < Table.size());
1667 static void emitConvertToMCInst(CodeGenTarget &Target, StringRef ClassName,
1668 std::vector<MatchableInfo*> &Infos,
1670 SetVector<std::string> OperandConversionKinds;
1671 SetVector<std::string> InstructionConversionKinds;
1672 std::vector<std::vector<uint8_t> > ConversionTable;
1673 size_t MaxRowLength = 2; // minimum is custom converter plus terminator.
1675 // TargetOperandClass - This is the target's operand class, like X86Operand.
1676 std::string TargetOperandClass = Target.getName() + "Operand";
1678 // Write the convert function to a separate stream, so we can drop it after
1679 // the enum. We'll build up the conversion handlers for the individual
1680 // operand types opportunistically as we encounter them.
1681 std::string ConvertFnBody;
1682 raw_string_ostream CvtOS(ConvertFnBody);
1683 // Start the unified conversion function.
1684 CvtOS << "void " << Target.getName() << ClassName << "::\n"
1685 << "convertToMCInst(unsigned Kind, MCInst &Inst, "
1686 << "unsigned Opcode,\n"
1687 << " const SmallVectorImpl<MCParsedAsmOperand*"
1688 << "> &Operands) {\n"
1689 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
1690 << " const uint8_t *Converter = ConversionTable[Kind];\n"
1691 << " Inst.setOpcode(Opcode);\n"
1692 << " for (const uint8_t *p = Converter; *p; p+= 2) {\n"
1693 << " switch (*p) {\n"
1694 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
1695 << " case CVT_Reg:\n"
1696 << " static_cast<" << TargetOperandClass
1697 << "*>(Operands[*(p + 1)])->addRegOperands(Inst, 1);\n"
1699 << " case CVT_Tied:\n"
1700 << " Inst.addOperand(Inst.getOperand(*(p + 1)));\n"
1703 std::string OperandFnBody;
1704 raw_string_ostream OpOS(OperandFnBody);
1705 // Start the operand number lookup function.
1706 OpOS << "unsigned " << Target.getName() << ClassName << "::\n"
1707 << "getMCInstOperandNumImpl(unsigned Kind, MCInst &Inst,\n"
1708 << " const SmallVectorImpl<MCParsedAsmOperand*> "
1709 << "&Operands,\n unsigned OperandNum, unsigned "
1710 << "&NumMCOperands) {\n"
1711 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
1712 << " NumMCOperands = 0;\n"
1713 << " unsigned MCOperandNum = 0;\n"
1714 << " const uint8_t *Converter = ConversionTable[Kind];\n"
1715 << " for (const uint8_t *p = Converter; *p; p+= 2) {\n"
1716 << " if (*(p + 1) > OperandNum) continue;\n"
1717 << " switch (*p) {\n"
1718 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
1719 << " case CVT_Reg:\n"
1720 << " if (*(p + 1) == OperandNum) {\n"
1721 << " NumMCOperands = 1;\n"
1724 << " ++MCOperandNum;\n"
1726 << " case CVT_Tied:\n"
1727 << " // FIXME: Tied operand calculation not supported.\n"
1728 << " assert (0 && \"getMCInstOperandNumImpl() doesn't support tied operands, yet!\");\n"
1731 // Pre-populate the operand conversion kinds with the standard always
1732 // available entries.
1733 OperandConversionKinds.insert("CVT_Done");
1734 OperandConversionKinds.insert("CVT_Reg");
1735 OperandConversionKinds.insert("CVT_Tied");
1736 enum { CVT_Done, CVT_Reg, CVT_Tied };
1738 for (std::vector<MatchableInfo*>::const_iterator it = Infos.begin(),
1739 ie = Infos.end(); it != ie; ++it) {
1740 MatchableInfo &II = **it;
1742 // Check if we have a custom match function.
1743 std::string AsmMatchConverter =
1744 II.getResultInst()->TheDef->getValueAsString("AsmMatchConverter");
1745 if (!AsmMatchConverter.empty()) {
1746 std::string Signature = "ConvertCustom_" + AsmMatchConverter;
1747 II.ConversionFnKind = Signature;
1749 // Check if we have already generated this signature.
1750 if (!InstructionConversionKinds.insert(Signature))
1753 // Remember this converter for the kind enum.
1754 unsigned KindID = OperandConversionKinds.size();
1755 OperandConversionKinds.insert("CVT_" + AsmMatchConverter);
1757 // Add the converter row for this instruction.
1758 ConversionTable.push_back(std::vector<uint8_t>());
1759 ConversionTable.back().push_back(KindID);
1760 ConversionTable.back().push_back(CVT_Done);
1762 // Add the handler to the conversion driver function.
1763 CvtOS << " case CVT_" << AsmMatchConverter << ":\n"
1764 << " " << AsmMatchConverter << "(Inst, Operands);\n"
1767 // FIXME: Handle the operand number lookup for custom match functions.
1771 // Build the conversion function signature.
1772 std::string Signature = "Convert";
1774 std::vector<uint8_t> ConversionRow;
1776 // Compute the convert enum and the case body.
1777 MaxRowLength = std::max(MaxRowLength, II.ResOperands.size()*2 + 1 );
1779 for (unsigned i = 0, e = II.ResOperands.size(); i != e; ++i) {
1780 const MatchableInfo::ResOperand &OpInfo = II.ResOperands[i];
1782 // Generate code to populate each result operand.
1783 switch (OpInfo.Kind) {
1784 case MatchableInfo::ResOperand::RenderAsmOperand: {
1785 // This comes from something we parsed.
1786 MatchableInfo::AsmOperand &Op = II.AsmOperands[OpInfo.AsmOperandNum];
1788 // Registers are always converted the same, don't duplicate the
1789 // conversion function based on them.
1792 Class = Op.Class->isRegisterClass() ? "Reg" : Op.Class->ClassName;
1794 Signature += utostr(OpInfo.MINumOperands);
1795 Signature += "_" + itostr(OpInfo.AsmOperandNum);
1797 // Add the conversion kind, if necessary, and get the associated ID
1798 // the index of its entry in the vector).
1799 std::string Name = "CVT_" + (Op.Class->isRegisterClass() ? "Reg" :
1800 Op.Class->RenderMethod);
1802 bool IsNewConverter = false;
1803 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1806 // Add the operand entry to the instruction kind conversion row.
1807 ConversionRow.push_back(ID);
1808 ConversionRow.push_back(OpInfo.AsmOperandNum + 1);
1810 if (!IsNewConverter)
1813 // This is a new operand kind. Add a handler for it to the
1814 // converter driver.
1815 CvtOS << " case " << Name << ":\n"
1816 << " static_cast<" << TargetOperandClass
1817 << "*>(Operands[*(p + 1)])->"
1818 << Op.Class->RenderMethod << "(Inst, " << OpInfo.MINumOperands
1822 // Add a handler for the operand number lookup.
1823 OpOS << " case " << Name << ":\n"
1824 << " if (*(p + 1) == OperandNum) {\n"
1825 << " NumMCOperands = " << OpInfo.MINumOperands << ";\n"
1828 << " MCOperandNum += " << OpInfo.MINumOperands << ";\n"
1832 case MatchableInfo::ResOperand::TiedOperand: {
1833 // If this operand is tied to a previous one, just copy the MCInst
1834 // operand from the earlier one.We can only tie single MCOperand values.
1835 //assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand");
1836 unsigned TiedOp = OpInfo.TiedOperandNum;
1837 assert(i > TiedOp && "Tied operand precedes its target!");
1838 Signature += "__Tie" + utostr(TiedOp);
1839 ConversionRow.push_back(CVT_Tied);
1840 ConversionRow.push_back(TiedOp);
1841 // FIXME: Handle the operand number lookup for tied operands.
1844 case MatchableInfo::ResOperand::ImmOperand: {
1845 int64_t Val = OpInfo.ImmVal;
1846 std::string Ty = "imm_" + itostr(Val);
1847 Signature += "__" + Ty;
1849 std::string Name = "CVT_" + Ty;
1850 bool IsNewConverter = false;
1851 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1853 // Add the operand entry to the instruction kind conversion row.
1854 ConversionRow.push_back(ID);
1855 ConversionRow.push_back(0);
1857 if (!IsNewConverter)
1860 CvtOS << " case " << Name << ":\n"
1861 << " Inst.addOperand(MCOperand::CreateImm(" << Val << "));\n"
1864 OpOS << " case " << Name << ":\n"
1865 << " if (*(p + 1) == OperandNum) {\n"
1866 << " NumMCOperands = 1;\n"
1869 << " ++MCOperandNum;\n"
1873 case MatchableInfo::ResOperand::RegOperand: {
1874 std::string Reg, Name;
1875 if (OpInfo.Register == 0) {
1879 Reg = getQualifiedName(OpInfo.Register);
1880 Name = "reg" + OpInfo.Register->getName();
1882 Signature += "__" + Name;
1883 Name = "CVT_" + Name;
1884 bool IsNewConverter = false;
1885 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1887 // Add the operand entry to the instruction kind conversion row.
1888 ConversionRow.push_back(ID);
1889 ConversionRow.push_back(0);
1891 if (!IsNewConverter)
1893 CvtOS << " case " << Name << ":\n"
1894 << " Inst.addOperand(MCOperand::CreateReg(" << Reg << "));\n"
1897 OpOS << " case " << Name << ":\n"
1898 << " if (*(p + 1) == OperandNum) {\n"
1899 << " NumMCOperands = 1;\n"
1902 << " ++MCOperandNum;\n"
1908 // If there were no operands, add to the signature to that effect
1909 if (Signature == "Convert")
1910 Signature += "_NoOperands";
1912 II.ConversionFnKind = Signature;
1914 // Save the signature. If we already have it, don't add a new row
1916 if (!InstructionConversionKinds.insert(Signature))
1919 // Add the row to the table.
1920 ConversionTable.push_back(ConversionRow);
1923 // Finish up the converter driver function.
1924 CvtOS << " }\n }\n}\n\n";
1926 // Finish up the operand number lookup function.
1927 OpOS << " }\n }\n return MCOperandNum;\n}\n\n";
1929 OS << "namespace {\n";
1931 // Output the operand conversion kind enum.
1932 OS << "enum OperatorConversionKind {\n";
1933 for (unsigned i = 0, e = OperandConversionKinds.size(); i != e; ++i)
1934 OS << " " << OperandConversionKinds[i] << ",\n";
1935 OS << " CVT_NUM_CONVERTERS\n";
1938 // Output the instruction conversion kind enum.
1939 OS << "enum InstructionConversionKind {\n";
1940 for (SetVector<std::string>::const_iterator
1941 i = InstructionConversionKinds.begin(),
1942 e = InstructionConversionKinds.end(); i != e; ++i)
1943 OS << " " << *i << ",\n";
1944 OS << " CVT_NUM_SIGNATURES\n";
1948 OS << "} // end anonymous namespace\n\n";
1950 // Output the conversion table.
1951 OS << "static const uint8_t ConversionTable[CVT_NUM_SIGNATURES]["
1952 << MaxRowLength << "] = {\n";
1954 for (unsigned Row = 0, ERow = ConversionTable.size(); Row != ERow; ++Row) {
1955 assert(ConversionTable[Row].size() % 2 == 0 && "bad conversion row!");
1956 OS << " // " << InstructionConversionKinds[Row] << "\n";
1958 for (unsigned i = 0, e = ConversionTable[Row].size(); i != e; i += 2)
1959 OS << OperandConversionKinds[ConversionTable[Row][i]] << ", "
1960 << (unsigned)(ConversionTable[Row][i + 1]) << ", ";
1961 OS << "CVT_Done },\n";
1966 // Spit out the conversion driver function.
1969 // Spit out the operand number lookup function.
1973 /// emitMatchClassEnumeration - Emit the enumeration for match class kinds.
1974 static void emitMatchClassEnumeration(CodeGenTarget &Target,
1975 std::vector<ClassInfo*> &Infos,
1977 OS << "namespace {\n\n";
1979 OS << "/// MatchClassKind - The kinds of classes which participate in\n"
1980 << "/// instruction matching.\n";
1981 OS << "enum MatchClassKind {\n";
1982 OS << " InvalidMatchClass = 0,\n";
1983 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1984 ie = Infos.end(); it != ie; ++it) {
1985 ClassInfo &CI = **it;
1986 OS << " " << CI.Name << ", // ";
1987 if (CI.Kind == ClassInfo::Token) {
1988 OS << "'" << CI.ValueName << "'\n";
1989 } else if (CI.isRegisterClass()) {
1990 if (!CI.ValueName.empty())
1991 OS << "register class '" << CI.ValueName << "'\n";
1993 OS << "derived register class\n";
1995 OS << "user defined class '" << CI.ValueName << "'\n";
1998 OS << " NumMatchClassKinds\n";
2004 /// emitValidateOperandClass - Emit the function to validate an operand class.
2005 static void emitValidateOperandClass(AsmMatcherInfo &Info,
2007 OS << "static unsigned validateOperandClass(MCParsedAsmOperand *GOp, "
2008 << "MatchClassKind Kind) {\n";
2009 OS << " " << Info.Target.getName() << "Operand &Operand = *("
2010 << Info.Target.getName() << "Operand*)GOp;\n";
2012 // The InvalidMatchClass is not to match any operand.
2013 OS << " if (Kind == InvalidMatchClass)\n";
2014 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n\n";
2016 // Check for Token operands first.
2017 // FIXME: Use a more specific diagnostic type.
2018 OS << " if (Operand.isToken())\n";
2019 OS << " return isSubclass(matchTokenString(Operand.getToken()), Kind) ?\n"
2020 << " MCTargetAsmParser::Match_Success :\n"
2021 << " MCTargetAsmParser::Match_InvalidOperand;\n\n";
2023 // Check the user classes. We don't care what order since we're only
2024 // actually matching against one of them.
2025 for (std::vector<ClassInfo*>::iterator it = Info.Classes.begin(),
2026 ie = Info.Classes.end(); it != ie; ++it) {
2027 ClassInfo &CI = **it;
2029 if (!CI.isUserClass())
2032 OS << " // '" << CI.ClassName << "' class\n";
2033 OS << " if (Kind == " << CI.Name << ") {\n";
2034 OS << " if (Operand." << CI.PredicateMethod << "())\n";
2035 OS << " return MCTargetAsmParser::Match_Success;\n";
2036 if (!CI.DiagnosticType.empty())
2037 OS << " return " << Info.Target.getName() << "AsmParser::Match_"
2038 << CI.DiagnosticType << ";\n";
2042 // Check for register operands, including sub-classes.
2043 OS << " if (Operand.isReg()) {\n";
2044 OS << " MatchClassKind OpKind;\n";
2045 OS << " switch (Operand.getReg()) {\n";
2046 OS << " default: OpKind = InvalidMatchClass; break;\n";
2047 for (AsmMatcherInfo::RegisterClassesTy::iterator
2048 it = Info.RegisterClasses.begin(), ie = Info.RegisterClasses.end();
2050 OS << " case " << Info.Target.getName() << "::"
2051 << it->first->getName() << ": OpKind = " << it->second->Name
2054 OS << " return isSubclass(OpKind, Kind) ? "
2055 << "MCTargetAsmParser::Match_Success :\n "
2056 << " MCTargetAsmParser::Match_InvalidOperand;\n }\n\n";
2058 // Generic fallthrough match failure case for operands that don't have
2059 // specialized diagnostic types.
2060 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n";
2064 /// emitIsSubclass - Emit the subclass predicate function.
2065 static void emitIsSubclass(CodeGenTarget &Target,
2066 std::vector<ClassInfo*> &Infos,
2068 OS << "/// isSubclass - Compute whether \\p A is a subclass of \\p B.\n";
2069 OS << "static bool isSubclass(MatchClassKind A, MatchClassKind B) {\n";
2070 OS << " if (A == B)\n";
2071 OS << " return true;\n\n";
2073 OS << " switch (A) {\n";
2074 OS << " default:\n";
2075 OS << " return false;\n";
2076 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
2077 ie = Infos.end(); it != ie; ++it) {
2078 ClassInfo &A = **it;
2080 std::vector<StringRef> SuperClasses;
2081 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
2082 ie = Infos.end(); it != ie; ++it) {
2083 ClassInfo &B = **it;
2085 if (&A != &B && A.isSubsetOf(B))
2086 SuperClasses.push_back(B.Name);
2089 if (SuperClasses.empty())
2092 OS << "\n case " << A.Name << ":\n";
2094 if (SuperClasses.size() == 1) {
2095 OS << " return B == " << SuperClasses.back() << ";\n";
2099 OS << " switch (B) {\n";
2100 OS << " default: return false;\n";
2101 for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i)
2102 OS << " case " << SuperClasses[i] << ": return true;\n";
2109 /// emitMatchTokenString - Emit the function to match a token string to the
2110 /// appropriate match class value.
2111 static void emitMatchTokenString(CodeGenTarget &Target,
2112 std::vector<ClassInfo*> &Infos,
2114 // Construct the match list.
2115 std::vector<StringMatcher::StringPair> Matches;
2116 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
2117 ie = Infos.end(); it != ie; ++it) {
2118 ClassInfo &CI = **it;
2120 if (CI.Kind == ClassInfo::Token)
2121 Matches.push_back(StringMatcher::StringPair(CI.ValueName,
2122 "return " + CI.Name + ";"));
2125 OS << "static MatchClassKind matchTokenString(StringRef Name) {\n";
2127 StringMatcher("Name", Matches, OS).Emit();
2129 OS << " return InvalidMatchClass;\n";
2133 /// emitMatchRegisterName - Emit the function to match a string to the target
2134 /// specific register enum.
2135 static void emitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
2137 // Construct the match list.
2138 std::vector<StringMatcher::StringPair> Matches;
2139 const std::vector<CodeGenRegister*> &Regs =
2140 Target.getRegBank().getRegisters();
2141 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
2142 const CodeGenRegister *Reg = Regs[i];
2143 if (Reg->TheDef->getValueAsString("AsmName").empty())
2146 Matches.push_back(StringMatcher::StringPair(
2147 Reg->TheDef->getValueAsString("AsmName"),
2148 "return " + utostr(Reg->EnumValue) + ";"));
2151 OS << "static unsigned MatchRegisterName(StringRef Name) {\n";
2153 StringMatcher("Name", Matches, OS).Emit();
2155 OS << " return 0;\n";
2159 /// emitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag
2161 static void emitSubtargetFeatureFlagEnumeration(AsmMatcherInfo &Info,
2163 OS << "// Flags for subtarget features that participate in "
2164 << "instruction matching.\n";
2165 OS << "enum SubtargetFeatureFlag {\n";
2166 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
2167 it = Info.SubtargetFeatures.begin(),
2168 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
2169 SubtargetFeatureInfo &SFI = *it->second;
2170 OS << " " << SFI.getEnumName() << " = (1 << " << SFI.Index << "),\n";
2172 OS << " Feature_None = 0\n";
2176 /// emitOperandDiagnosticTypes - Emit the operand matching diagnostic types.
2177 static void emitOperandDiagnosticTypes(AsmMatcherInfo &Info, raw_ostream &OS) {
2178 // Get the set of diagnostic types from all of the operand classes.
2179 std::set<StringRef> Types;
2180 for (std::map<Record*, ClassInfo*>::const_iterator
2181 I = Info.AsmOperandClasses.begin(),
2182 E = Info.AsmOperandClasses.end(); I != E; ++I) {
2183 if (!I->second->DiagnosticType.empty())
2184 Types.insert(I->second->DiagnosticType);
2187 if (Types.empty()) return;
2189 // Now emit the enum entries.
2190 for (std::set<StringRef>::const_iterator I = Types.begin(), E = Types.end();
2192 OS << " Match_" << *I << ",\n";
2193 OS << " END_OPERAND_DIAGNOSTIC_TYPES\n";
2196 /// emitGetSubtargetFeatureName - Emit the helper function to get the
2197 /// user-level name for a subtarget feature.
2198 static void emitGetSubtargetFeatureName(AsmMatcherInfo &Info, raw_ostream &OS) {
2199 OS << "// User-level names for subtarget features that participate in\n"
2200 << "// instruction matching.\n"
2201 << "static const char *getSubtargetFeatureName(unsigned Val) {\n"
2202 << " switch(Val) {\n";
2203 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
2204 it = Info.SubtargetFeatures.begin(),
2205 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
2206 SubtargetFeatureInfo &SFI = *it->second;
2207 // FIXME: Totally just a placeholder name to get the algorithm working.
2208 OS << " case " << SFI.getEnumName() << ": return \""
2209 << SFI.TheDef->getValueAsString("PredicateName") << "\";\n";
2211 OS << " default: return \"(unknown)\";\n";
2215 /// emitComputeAvailableFeatures - Emit the function to compute the list of
2216 /// available features given a subtarget.
2217 static void emitComputeAvailableFeatures(AsmMatcherInfo &Info,
2219 std::string ClassName =
2220 Info.AsmParser->getValueAsString("AsmParserClassName");
2222 OS << "unsigned " << Info.Target.getName() << ClassName << "::\n"
2223 << "ComputeAvailableFeatures(uint64_t FB) const {\n";
2224 OS << " unsigned Features = 0;\n";
2225 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
2226 it = Info.SubtargetFeatures.begin(),
2227 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
2228 SubtargetFeatureInfo &SFI = *it->second;
2231 std::string CondStorage =
2232 SFI.TheDef->getValueAsString("AssemblerCondString");
2233 StringRef Conds = CondStorage;
2234 std::pair<StringRef,StringRef> Comma = Conds.split(',');
2241 StringRef Cond = Comma.first;
2242 if (Cond[0] == '!') {
2244 Cond = Cond.substr(1);
2247 OS << "((FB & " << Info.Target.getName() << "::" << Cond << ")";
2254 if (Comma.second.empty())
2258 Comma = Comma.second.split(',');
2262 OS << " Features |= " << SFI.getEnumName() << ";\n";
2264 OS << " return Features;\n";
2268 static std::string GetAliasRequiredFeatures(Record *R,
2269 const AsmMatcherInfo &Info) {
2270 std::vector<Record*> ReqFeatures = R->getValueAsListOfDefs("Predicates");
2272 unsigned NumFeatures = 0;
2273 for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) {
2274 SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]);
2277 throw TGError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() +
2278 "' is not marked as an AssemblerPredicate!");
2283 Result += F->getEnumName();
2287 if (NumFeatures > 1)
2288 Result = '(' + Result + ')';
2292 /// emitMnemonicAliases - If the target has any MnemonicAlias<> definitions,
2293 /// emit a function for them and return true, otherwise return false.
2294 static bool emitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info) {
2295 // Ignore aliases when match-prefix is set.
2296 if (!MatchPrefix.empty())
2299 std::vector<Record*> Aliases =
2300 Info.getRecords().getAllDerivedDefinitions("MnemonicAlias");
2301 if (Aliases.empty()) return false;
2303 OS << "static void applyMnemonicAliases(StringRef &Mnemonic, "
2304 "unsigned Features) {\n";
2306 // Keep track of all the aliases from a mnemonic. Use an std::map so that the
2307 // iteration order of the map is stable.
2308 std::map<std::string, std::vector<Record*> > AliasesFromMnemonic;
2310 for (unsigned i = 0, e = Aliases.size(); i != e; ++i) {
2311 Record *R = Aliases[i];
2312 AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R);
2315 // Process each alias a "from" mnemonic at a time, building the code executed
2316 // by the string remapper.
2317 std::vector<StringMatcher::StringPair> Cases;
2318 for (std::map<std::string, std::vector<Record*> >::iterator
2319 I = AliasesFromMnemonic.begin(), E = AliasesFromMnemonic.end();
2321 const std::vector<Record*> &ToVec = I->second;
2323 // Loop through each alias and emit code that handles each case. If there
2324 // are two instructions without predicates, emit an error. If there is one,
2326 std::string MatchCode;
2327 int AliasWithNoPredicate = -1;
2329 for (unsigned i = 0, e = ToVec.size(); i != e; ++i) {
2330 Record *R = ToVec[i];
2331 std::string FeatureMask = GetAliasRequiredFeatures(R, Info);
2333 // If this unconditionally matches, remember it for later and diagnose
2335 if (FeatureMask.empty()) {
2336 if (AliasWithNoPredicate != -1) {
2337 // We can't have two aliases from the same mnemonic with no predicate.
2338 PrintError(ToVec[AliasWithNoPredicate]->getLoc(),
2339 "two MnemonicAliases with the same 'from' mnemonic!");
2340 throw TGError(R->getLoc(), "this is the other MnemonicAlias.");
2343 AliasWithNoPredicate = i;
2346 if (R->getValueAsString("ToMnemonic") == I->first)
2347 throw TGError(R->getLoc(), "MnemonicAlias to the same string");
2349 if (!MatchCode.empty())
2350 MatchCode += "else ";
2351 MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n";
2352 MatchCode += " Mnemonic = \"" +R->getValueAsString("ToMnemonic")+"\";\n";
2355 if (AliasWithNoPredicate != -1) {
2356 Record *R = ToVec[AliasWithNoPredicate];
2357 if (!MatchCode.empty())
2358 MatchCode += "else\n ";
2359 MatchCode += "Mnemonic = \"" + R->getValueAsString("ToMnemonic")+"\";\n";
2362 MatchCode += "return;";
2364 Cases.push_back(std::make_pair(I->first, MatchCode));
2367 StringMatcher("Mnemonic", Cases, OS).Emit();
2373 static const char *getMinimalTypeForRange(uint64_t Range) {
2374 assert(Range < 0xFFFFFFFFULL && "Enum too large");
2382 static void emitCustomOperandParsing(raw_ostream &OS, CodeGenTarget &Target,
2383 const AsmMatcherInfo &Info, StringRef ClassName,
2384 StringToOffsetTable &StringTable,
2385 unsigned MaxMnemonicIndex) {
2386 unsigned MaxMask = 0;
2387 for (std::vector<OperandMatchEntry>::const_iterator it =
2388 Info.OperandMatchInfo.begin(), ie = Info.OperandMatchInfo.end();
2390 MaxMask |= it->OperandMask;
2393 // Emit the static custom operand parsing table;
2394 OS << "namespace {\n";
2395 OS << " struct OperandMatchEntry {\n";
2396 OS << " " << getMinimalTypeForRange(1ULL << Info.SubtargetFeatures.size())
2397 << " RequiredFeatures;\n";
2398 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex)
2400 OS << " " << getMinimalTypeForRange(Info.Classes.size())
2402 OS << " " << getMinimalTypeForRange(MaxMask)
2403 << " OperandMask;\n\n";
2404 OS << " StringRef getMnemonic() const {\n";
2405 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2406 OS << " MnemonicTable[Mnemonic]);\n";
2410 OS << " // Predicate for searching for an opcode.\n";
2411 OS << " struct LessOpcodeOperand {\n";
2412 OS << " bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {\n";
2413 OS << " return LHS.getMnemonic() < RHS;\n";
2415 OS << " bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {\n";
2416 OS << " return LHS < RHS.getMnemonic();\n";
2418 OS << " bool operator()(const OperandMatchEntry &LHS,";
2419 OS << " const OperandMatchEntry &RHS) {\n";
2420 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2424 OS << "} // end anonymous namespace.\n\n";
2426 OS << "static const OperandMatchEntry OperandMatchTable["
2427 << Info.OperandMatchInfo.size() << "] = {\n";
2429 OS << " /* Operand List Mask, Mnemonic, Operand Class, Features */\n";
2430 for (std::vector<OperandMatchEntry>::const_iterator it =
2431 Info.OperandMatchInfo.begin(), ie = Info.OperandMatchInfo.end();
2433 const OperandMatchEntry &OMI = *it;
2434 const MatchableInfo &II = *OMI.MI;
2438 // Write the required features mask.
2439 if (!II.RequiredFeatures.empty()) {
2440 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
2442 OS << II.RequiredFeatures[i]->getEnumName();
2447 // Store a pascal-style length byte in the mnemonic.
2448 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2449 OS << ", " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2450 << " /* " << II.Mnemonic << " */, ";
2454 OS << ", " << OMI.OperandMask;
2456 bool printComma = false;
2457 for (int i = 0, e = 31; i !=e; ++i)
2458 if (OMI.OperandMask & (1 << i)) {
2470 // Emit the operand class switch to call the correct custom parser for
2471 // the found operand class.
2472 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
2473 << Target.getName() << ClassName << "::\n"
2474 << "tryCustomParseOperand(SmallVectorImpl<MCParsedAsmOperand*>"
2475 << " &Operands,\n unsigned MCK) {\n\n"
2476 << " switch(MCK) {\n";
2478 for (std::vector<ClassInfo*>::const_iterator it = Info.Classes.begin(),
2479 ie = Info.Classes.end(); it != ie; ++it) {
2480 ClassInfo *CI = *it;
2481 if (CI->ParserMethod.empty())
2483 OS << " case " << CI->Name << ":\n"
2484 << " return " << CI->ParserMethod << "(Operands);\n";
2487 OS << " default:\n";
2488 OS << " return MatchOperand_NoMatch;\n";
2490 OS << " return MatchOperand_NoMatch;\n";
2493 // Emit the static custom operand parser. This code is very similar with
2494 // the other matcher. Also use MatchResultTy here just in case we go for
2495 // a better error handling.
2496 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
2497 << Target.getName() << ClassName << "::\n"
2498 << "MatchOperandParserImpl(SmallVectorImpl<MCParsedAsmOperand*>"
2499 << " &Operands,\n StringRef Mnemonic) {\n";
2501 // Emit code to get the available features.
2502 OS << " // Get the current feature set.\n";
2503 OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n";
2505 OS << " // Get the next operand index.\n";
2506 OS << " unsigned NextOpNum = Operands.size()-1;\n";
2508 // Emit code to search the table.
2509 OS << " // Search the table.\n";
2510 OS << " std::pair<const OperandMatchEntry*, const OperandMatchEntry*>";
2511 OS << " MnemonicRange =\n";
2512 OS << " std::equal_range(OperandMatchTable, OperandMatchTable+"
2513 << Info.OperandMatchInfo.size() << ", Mnemonic,\n"
2514 << " LessOpcodeOperand());\n\n";
2516 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2517 OS << " return MatchOperand_NoMatch;\n\n";
2519 OS << " for (const OperandMatchEntry *it = MnemonicRange.first,\n"
2520 << " *ie = MnemonicRange.second; it != ie; ++it) {\n";
2522 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2523 OS << " assert(Mnemonic == it->getMnemonic());\n\n";
2525 // Emit check that the required features are available.
2526 OS << " // check if the available features match\n";
2527 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2528 << "!= it->RequiredFeatures) {\n";
2529 OS << " continue;\n";
2532 // Emit check to ensure the operand number matches.
2533 OS << " // check if the operand in question has a custom parser.\n";
2534 OS << " if (!(it->OperandMask & (1 << NextOpNum)))\n";
2535 OS << " continue;\n\n";
2537 // Emit call to the custom parser method
2538 OS << " // call custom parse method to handle the operand\n";
2539 OS << " OperandMatchResultTy Result = ";
2540 OS << "tryCustomParseOperand(Operands, it->Class);\n";
2541 OS << " if (Result != MatchOperand_NoMatch)\n";
2542 OS << " return Result;\n";
2545 OS << " // Okay, we had no match.\n";
2546 OS << " return MatchOperand_NoMatch;\n";
2550 void AsmMatcherEmitter::run(raw_ostream &OS) {
2551 CodeGenTarget Target(Records);
2552 Record *AsmParser = Target.getAsmParser();
2553 std::string ClassName = AsmParser->getValueAsString("AsmParserClassName");
2555 // Compute the information on the instructions to match.
2556 AsmMatcherInfo Info(AsmParser, Target, Records);
2559 // Sort the instruction table using the partial order on classes. We use
2560 // stable_sort to ensure that ambiguous instructions are still
2561 // deterministically ordered.
2562 std::stable_sort(Info.Matchables.begin(), Info.Matchables.end(),
2563 less_ptr<MatchableInfo>());
2565 DEBUG_WITH_TYPE("instruction_info", {
2566 for (std::vector<MatchableInfo*>::iterator
2567 it = Info.Matchables.begin(), ie = Info.Matchables.end();
2572 // Check for ambiguous matchables.
2573 DEBUG_WITH_TYPE("ambiguous_instrs", {
2574 unsigned NumAmbiguous = 0;
2575 for (unsigned i = 0, e = Info.Matchables.size(); i != e; ++i) {
2576 for (unsigned j = i + 1; j != e; ++j) {
2577 MatchableInfo &A = *Info.Matchables[i];
2578 MatchableInfo &B = *Info.Matchables[j];
2580 if (A.couldMatchAmbiguouslyWith(B)) {
2581 errs() << "warning: ambiguous matchables:\n";
2583 errs() << "\nis incomparable with:\n";
2591 errs() << "warning: " << NumAmbiguous
2592 << " ambiguous matchables!\n";
2595 // Compute the information on the custom operand parsing.
2596 Info.buildOperandMatchInfo();
2598 // Write the output.
2600 // Information for the class declaration.
2601 OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
2602 OS << "#undef GET_ASSEMBLER_HEADER\n";
2603 OS << " // This should be included into the middle of the declaration of\n";
2604 OS << " // your subclasses implementation of MCTargetAsmParser.\n";
2605 OS << " unsigned ComputeAvailableFeatures(uint64_t FeatureBits) const;\n";
2606 OS << " void convertToMCInst(unsigned Kind, MCInst &Inst, "
2607 << "unsigned Opcode,\n"
2608 << " const SmallVectorImpl<MCParsedAsmOperand*> "
2610 OS << " unsigned getMCInstOperandNumImpl(unsigned Kind, MCInst &Inst,\n "
2612 << "SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n "
2613 << " unsigned OperandNum, unsigned &NumMCOperands);\n";
2614 OS << " bool MnemonicIsValid(StringRef Mnemonic);\n";
2615 OS << " unsigned MatchInstructionImpl(\n"
2616 << " const SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n"
2617 << " unsigned &Kind, MCInst &Inst, "
2618 << "unsigned &ErrorInfo,\n unsigned VariantID = 0);\n";
2620 if (Info.OperandMatchInfo.size()) {
2621 OS << "\n enum OperandMatchResultTy {\n";
2622 OS << " MatchOperand_Success, // operand matched successfully\n";
2623 OS << " MatchOperand_NoMatch, // operand did not match\n";
2624 OS << " MatchOperand_ParseFail // operand matched but had errors\n";
2626 OS << " OperandMatchResultTy MatchOperandParserImpl(\n";
2627 OS << " SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n";
2628 OS << " StringRef Mnemonic);\n";
2630 OS << " OperandMatchResultTy tryCustomParseOperand(\n";
2631 OS << " SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n";
2632 OS << " unsigned MCK);\n\n";
2635 OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n";
2637 // Emit the operand match diagnostic enum names.
2638 OS << "\n#ifdef GET_OPERAND_DIAGNOSTIC_TYPES\n";
2639 OS << "#undef GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
2640 emitOperandDiagnosticTypes(Info, OS);
2641 OS << "#endif // GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
2644 OS << "\n#ifdef GET_REGISTER_MATCHER\n";
2645 OS << "#undef GET_REGISTER_MATCHER\n\n";
2647 // Emit the subtarget feature enumeration.
2648 emitSubtargetFeatureFlagEnumeration(Info, OS);
2650 // Emit the function to match a register name to number.
2651 // This should be omitted for Mips target
2652 if (AsmParser->getValueAsBit("ShouldEmitMatchRegisterName"))
2653 emitMatchRegisterName(Target, AsmParser, OS);
2655 OS << "#endif // GET_REGISTER_MATCHER\n\n";
2657 OS << "\n#ifdef GET_SUBTARGET_FEATURE_NAME\n";
2658 OS << "#undef GET_SUBTARGET_FEATURE_NAME\n\n";
2660 // Generate the helper function to get the names for subtarget features.
2661 emitGetSubtargetFeatureName(Info, OS);
2663 OS << "#endif // GET_SUBTARGET_FEATURE_NAME\n\n";
2665 OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
2666 OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
2668 // Generate the function that remaps for mnemonic aliases.
2669 bool HasMnemonicAliases = emitMnemonicAliases(OS, Info);
2671 // Generate the unified function to convert operands into an MCInst.
2672 emitConvertToMCInst(Target, ClassName, Info.Matchables, OS);
2674 // Emit the enumeration for classes which participate in matching.
2675 emitMatchClassEnumeration(Target, Info.Classes, OS);
2677 // Emit the routine to match token strings to their match class.
2678 emitMatchTokenString(Target, Info.Classes, OS);
2680 // Emit the subclass predicate routine.
2681 emitIsSubclass(Target, Info.Classes, OS);
2683 // Emit the routine to validate an operand against a match class.
2684 emitValidateOperandClass(Info, OS);
2686 // Emit the available features compute function.
2687 emitComputeAvailableFeatures(Info, OS);
2690 StringToOffsetTable StringTable;
2692 size_t MaxNumOperands = 0;
2693 unsigned MaxMnemonicIndex = 0;
2694 for (std::vector<MatchableInfo*>::const_iterator it =
2695 Info.Matchables.begin(), ie = Info.Matchables.end();
2697 MatchableInfo &II = **it;
2698 MaxNumOperands = std::max(MaxNumOperands, II.AsmOperands.size());
2700 // Store a pascal-style length byte in the mnemonic.
2701 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2702 MaxMnemonicIndex = std::max(MaxMnemonicIndex,
2703 StringTable.GetOrAddStringOffset(LenMnemonic, false));
2706 OS << "static const char *const MnemonicTable =\n";
2707 StringTable.EmitString(OS);
2710 // Emit the static match table; unused classes get initalized to 0 which is
2711 // guaranteed to be InvalidMatchClass.
2713 // FIXME: We can reduce the size of this table very easily. First, we change
2714 // it so that store the kinds in separate bit-fields for each index, which
2715 // only needs to be the max width used for classes at that index (we also need
2716 // to reject based on this during classification). If we then make sure to
2717 // order the match kinds appropriately (putting mnemonics last), then we
2718 // should only end up using a few bits for each class, especially the ones
2719 // following the mnemonic.
2720 OS << "namespace {\n";
2721 OS << " struct MatchEntry {\n";
2722 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex)
2724 OS << " uint16_t Opcode;\n";
2725 OS << " " << getMinimalTypeForRange(Info.Matchables.size())
2727 OS << " " << getMinimalTypeForRange(1ULL << Info.SubtargetFeatures.size())
2728 << " RequiredFeatures;\n";
2729 OS << " " << getMinimalTypeForRange(Info.Classes.size())
2730 << " Classes[" << MaxNumOperands << "];\n";
2731 OS << " uint8_t AsmVariantID;\n\n";
2732 OS << " StringRef getMnemonic() const {\n";
2733 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2734 OS << " MnemonicTable[Mnemonic]);\n";
2738 OS << " // Predicate for searching for an opcode.\n";
2739 OS << " struct LessOpcode {\n";
2740 OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n";
2741 OS << " return LHS.getMnemonic() < RHS;\n";
2743 OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n";
2744 OS << " return LHS < RHS.getMnemonic();\n";
2746 OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n";
2747 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2751 OS << "} // end anonymous namespace.\n\n";
2753 OS << "static const MatchEntry MatchTable["
2754 << Info.Matchables.size() << "] = {\n";
2756 for (std::vector<MatchableInfo*>::const_iterator it =
2757 Info.Matchables.begin(), ie = Info.Matchables.end();
2759 MatchableInfo &II = **it;
2761 // Store a pascal-style length byte in the mnemonic.
2762 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2763 OS << " { " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2764 << " /* " << II.Mnemonic << " */, "
2765 << Target.getName() << "::"
2766 << II.getResultInst()->TheDef->getName() << ", "
2767 << II.ConversionFnKind << ", ";
2769 // Write the required features mask.
2770 if (!II.RequiredFeatures.empty()) {
2771 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
2773 OS << II.RequiredFeatures[i]->getEnumName();
2779 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) {
2780 MatchableInfo::AsmOperand &Op = II.AsmOperands[i];
2783 OS << Op.Class->Name;
2785 OS << " }, " << II.AsmVariantID;
2791 // A method to determine if a mnemonic is in the list.
2792 OS << "bool " << Target.getName() << ClassName << "::\n"
2793 << "MnemonicIsValid(StringRef Mnemonic) {\n";
2794 OS << " // Search the table.\n";
2795 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
2796 OS << " std::equal_range(MatchTable, MatchTable+"
2797 << Info.Matchables.size() << ", Mnemonic, LessOpcode());\n";
2798 OS << " return MnemonicRange.first != MnemonicRange.second;\n";
2801 // Finally, build the match function.
2803 << Target.getName() << ClassName << "::\n"
2804 << "MatchInstructionImpl(const SmallVectorImpl<MCParsedAsmOperand*>"
2806 OS << " unsigned &Kind, MCInst &Inst, unsigned ";
2807 OS << "&ErrorInfo,\n unsigned VariantID) {\n";
2809 OS << " // Eliminate obvious mismatches.\n";
2810 OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n";
2811 OS << " ErrorInfo = " << (MaxNumOperands+1) << ";\n";
2812 OS << " return Match_InvalidOperand;\n";
2815 // Emit code to get the available features.
2816 OS << " // Get the current feature set.\n";
2817 OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n";
2819 OS << " // Get the instruction mnemonic, which is the first token.\n";
2820 OS << " StringRef Mnemonic = ((" << Target.getName()
2821 << "Operand*)Operands[0])->getToken();\n\n";
2823 if (HasMnemonicAliases) {
2824 OS << " // Process all MnemonicAliases to remap the mnemonic.\n";
2825 OS << " // FIXME : Add an entry in AsmParserVariant to check this.\n";
2826 OS << " if (!VariantID)\n";
2827 OS << " applyMnemonicAliases(Mnemonic, AvailableFeatures);\n\n";
2830 // Emit code to compute the class list for this operand vector.
2831 OS << " // Some state to try to produce better error messages.\n";
2832 OS << " bool HadMatchOtherThanFeatures = false;\n";
2833 OS << " bool HadMatchOtherThanPredicate = false;\n";
2834 OS << " unsigned RetCode = Match_InvalidOperand;\n";
2835 OS << " unsigned MissingFeatures = ~0U;\n";
2836 OS << " // Set ErrorInfo to the operand that mismatches if it is\n";
2837 OS << " // wrong for all instances of the instruction.\n";
2838 OS << " ErrorInfo = ~0U;\n";
2840 // Emit code to search the table.
2841 OS << " // Search the table.\n";
2842 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
2843 OS << " std::equal_range(MatchTable, MatchTable+"
2844 << Info.Matchables.size() << ", Mnemonic, LessOpcode());\n\n";
2846 OS << " // Return a more specific error code if no mnemonics match.\n";
2847 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2848 OS << " return Match_MnemonicFail;\n\n";
2850 OS << " for (const MatchEntry *it = MnemonicRange.first, "
2851 << "*ie = MnemonicRange.second;\n";
2852 OS << " it != ie; ++it) {\n";
2854 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2855 OS << " assert(Mnemonic == it->getMnemonic());\n";
2857 // Emit check that the subclasses match.
2858 OS << " if (VariantID != it->AsmVariantID) continue;\n";
2859 OS << " bool OperandsValid = true;\n";
2860 OS << " for (unsigned i = 0; i != " << MaxNumOperands << "; ++i) {\n";
2861 OS << " if (i + 1 >= Operands.size()) {\n";
2862 OS << " OperandsValid = (it->Classes[i] == " <<"InvalidMatchClass);\n";
2863 OS << " if (!OperandsValid) ErrorInfo = i + 1;\n";
2866 OS << " unsigned Diag = validateOperandClass(Operands[i+1],\n";
2868 OS << "(MatchClassKind)it->Classes[i]);\n";
2869 OS << " if (Diag == Match_Success)\n";
2870 OS << " continue;\n";
2871 OS << " // If this operand is broken for all of the instances of this\n";
2872 OS << " // mnemonic, keep track of it so we can report loc info.\n";
2873 OS << " // If we already had a match that only failed due to a\n";
2874 OS << " // target predicate, that diagnostic is preferred.\n";
2875 OS << " if (!HadMatchOtherThanPredicate &&\n";
2876 OS << " (it == MnemonicRange.first || ErrorInfo <= i+1)) {\n";
2877 OS << " ErrorInfo = i+1;\n";
2878 OS << " // InvalidOperand is the default. Prefer specificity.\n";
2879 OS << " if (Diag != Match_InvalidOperand)\n";
2880 OS << " RetCode = Diag;\n";
2882 OS << " // Otherwise, just reject this instance of the mnemonic.\n";
2883 OS << " OperandsValid = false;\n";
2887 OS << " if (!OperandsValid) continue;\n";
2889 // Emit check that the required features are available.
2890 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2891 << "!= it->RequiredFeatures) {\n";
2892 OS << " HadMatchOtherThanFeatures = true;\n";
2893 OS << " unsigned NewMissingFeatures = it->RequiredFeatures & "
2894 "~AvailableFeatures;\n";
2895 OS << " if (CountPopulation_32(NewMissingFeatures) <=\n"
2896 " CountPopulation_32(MissingFeatures))\n";
2897 OS << " MissingFeatures = NewMissingFeatures;\n";
2898 OS << " continue;\n";
2901 OS << " // We have selected a definite instruction, convert the parsed\n"
2902 << " // operands into the appropriate MCInst.\n";
2903 OS << " convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n";
2906 // Verify the instruction with the target-specific match predicate function.
2907 OS << " // We have a potential match. Check the target predicate to\n"
2908 << " // handle any context sensitive constraints.\n"
2909 << " unsigned MatchResult;\n"
2910 << " if ((MatchResult = checkTargetMatchPredicate(Inst)) !="
2911 << " Match_Success) {\n"
2912 << " Inst.clear();\n"
2913 << " RetCode = MatchResult;\n"
2914 << " HadMatchOtherThanPredicate = true;\n"
2918 // Call the post-processing function, if used.
2919 std::string InsnCleanupFn =
2920 AsmParser->getValueAsString("AsmParserInstCleanup");
2921 if (!InsnCleanupFn.empty())
2922 OS << " " << InsnCleanupFn << "(Inst);\n";
2924 OS << " Kind = it->ConvertFn;\n";
2925 OS << " return Match_Success;\n";
2928 OS << " // Okay, we had no match. Try to return a useful error code.\n";
2929 OS << " if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)\n";
2930 OS << " return RetCode;\n\n";
2931 OS << " // Missing feature matches return which features were missing\n";
2932 OS << " ErrorInfo = MissingFeatures;\n";
2933 OS << " return Match_MissingFeature;\n";
2936 if (Info.OperandMatchInfo.size())
2937 emitCustomOperandParsing(OS, Target, Info, ClassName, StringTable,
2940 OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";
2945 void EmitAsmMatcher(RecordKeeper &RK, raw_ostream &OS) {
2946 emitSourceFileHeader("Assembly Matcher Source Fragment", OS);
2947 AsmMatcherEmitter(RK).run(OS);
2950 } // End llvm namespace