1 //===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits a target specifier matcher for converting parsed
11 // assembly operands in the MCInst structures. It also emits a matcher for
12 // custom operand parsing.
14 // Converting assembly operands into MCInst structures
15 // ---------------------------------------------------
17 // The input to the target specific matcher is a list of literal tokens and
18 // operands. The target specific parser should generally eliminate any syntax
19 // which is not relevant for matching; for example, comma tokens should have
20 // already been consumed and eliminated by the parser. Most instructions will
21 // end up with a single literal token (the instruction name) and some number of
24 // Some example inputs, for X86:
25 // 'addl' (immediate ...) (register ...)
26 // 'add' (immediate ...) (memory ...)
29 // The assembly matcher is responsible for converting this input into a precise
30 // machine instruction (i.e., an instruction with a well defined encoding). This
31 // mapping has several properties which complicate matching:
33 // - It may be ambiguous; many architectures can legally encode particular
34 // variants of an instruction in different ways (for example, using a smaller
35 // encoding for small immediates). Such ambiguities should never be
36 // arbitrarily resolved by the assembler, the assembler is always responsible
37 // for choosing the "best" available instruction.
39 // - It may depend on the subtarget or the assembler context. Instructions
40 // which are invalid for the current mode, but otherwise unambiguous (e.g.,
41 // an SSE instruction in a file being assembled for i486) should be accepted
42 // and rejected by the assembler front end. However, if the proper encoding
43 // for an instruction is dependent on the assembler context then the matcher
44 // is responsible for selecting the correct machine instruction for the
47 // The core matching algorithm attempts to exploit the regularity in most
48 // instruction sets to quickly determine the set of possibly matching
49 // instructions, and the simplify the generated code. Additionally, this helps
50 // to ensure that the ambiguities are intentionally resolved by the user.
52 // The matching is divided into two distinct phases:
54 // 1. Classification: Each operand is mapped to the unique set which (a)
55 // contains it, and (b) is the largest such subset for which a single
56 // instruction could match all members.
58 // For register classes, we can generate these subgroups automatically. For
59 // arbitrary operands, we expect the user to define the classes and their
60 // relations to one another (for example, 8-bit signed immediates as a
61 // subset of 32-bit immediates).
63 // By partitioning the operands in this way, we guarantee that for any
64 // tuple of classes, any single instruction must match either all or none
65 // of the sets of operands which could classify to that tuple.
67 // In addition, the subset relation amongst classes induces a partial order
68 // on such tuples, which we use to resolve ambiguities.
70 // 2. The input can now be treated as a tuple of classes (static tokens are
71 // simple singleton sets). Each such tuple should generally map to a single
72 // instruction (we currently ignore cases where this isn't true, whee!!!),
73 // which we can emit a simple matcher for.
75 // Custom Operand Parsing
76 // ----------------------
78 // Some targets need a custom way to parse operands, some specific instructions
79 // can contain arguments that can represent processor flags and other kinds of
80 // identifiers that need to be mapped to specific valeus in the final encoded
81 // instructions. The target specific custom operand parsing works in the
84 // 1. A operand match table is built, each entry contains a mnemonic, an
85 // operand class, a mask for all operand positions for that same
86 // class/mnemonic and target features to be checked while trying to match.
88 // 2. The operand matcher will try every possible entry with the same
89 // mnemonic and will check if the target feature for this mnemonic also
90 // matches. After that, if the operand to be matched has its index
91 // present in the mask, a successful match occurs. Otherwise, fallback
92 // to the regular operand parsing.
94 // 3. For a match success, each operand class that has a 'ParserMethod'
95 // becomes part of a switch from where the custom method is called.
97 //===----------------------------------------------------------------------===//
99 #include "CodeGenTarget.h"
100 #include "StringToOffsetTable.h"
101 #include "llvm/ADT/OwningPtr.h"
102 #include "llvm/ADT/PointerUnion.h"
103 #include "llvm/ADT/SmallPtrSet.h"
104 #include "llvm/ADT/SmallVector.h"
105 #include "llvm/ADT/STLExtras.h"
106 #include "llvm/ADT/StringExtras.h"
107 #include "llvm/Support/CommandLine.h"
108 #include "llvm/Support/Debug.h"
109 #include "llvm/Support/ErrorHandling.h"
110 #include "llvm/TableGen/Error.h"
111 #include "llvm/TableGen/Record.h"
112 #include "llvm/TableGen/StringMatcher.h"
113 #include "llvm/TableGen/TableGenBackend.h"
117 using namespace llvm;
119 static cl::opt<std::string>
120 MatchPrefix("match-prefix", cl::init(""),
121 cl::desc("Only match instructions with the given prefix"));
124 class AsmMatcherInfo;
125 struct SubtargetFeatureInfo;
127 class AsmMatcherEmitter {
128 RecordKeeper &Records;
130 AsmMatcherEmitter(RecordKeeper &R) : Records(R) {}
132 void run(raw_ostream &o);
135 /// ClassInfo - Helper class for storing the information about a particular
136 /// class of operands which can be matched.
139 /// Invalid kind, for use as a sentinel value.
142 /// The class for a particular token.
145 /// The (first) register class, subsequent register classes are
146 /// RegisterClass0+1, and so on.
149 /// The (first) user defined class, subsequent user defined classes are
150 /// UserClass0+1, and so on.
154 /// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
155 /// N) for the Nth user defined class.
158 /// SuperClasses - The super classes of this class. Note that for simplicities
159 /// sake user operands only record their immediate super class, while register
160 /// operands include all superclasses.
161 std::vector<ClassInfo*> SuperClasses;
163 /// Name - The full class name, suitable for use in an enum.
166 /// ClassName - The unadorned generic name for this class (e.g., Token).
167 std::string ClassName;
169 /// ValueName - The name of the value this class represents; for a token this
170 /// is the literal token string, for an operand it is the TableGen class (or
171 /// empty if this is a derived class).
172 std::string ValueName;
174 /// PredicateMethod - The name of the operand method to test whether the
175 /// operand matches this class; this is not valid for Token or register kinds.
176 std::string PredicateMethod;
178 /// RenderMethod - The name of the operand method to add this operand to an
179 /// MCInst; this is not valid for Token or register kinds.
180 std::string RenderMethod;
182 /// ParserMethod - The name of the operand method to do a target specific
183 /// parsing on the operand.
184 std::string ParserMethod;
186 /// For register classes, the records for all the registers in this class.
187 std::set<Record*> Registers;
189 /// For custom match classes, he diagnostic kind for when the predicate fails.
190 std::string DiagnosticType;
192 /// isRegisterClass() - Check if this is a register class.
193 bool isRegisterClass() const {
194 return Kind >= RegisterClass0 && Kind < UserClass0;
197 /// isUserClass() - Check if this is a user defined class.
198 bool isUserClass() const {
199 return Kind >= UserClass0;
202 /// isRelatedTo - Check whether this class is "related" to \p RHS. Classes
203 /// are related if they are in the same class hierarchy.
204 bool isRelatedTo(const ClassInfo &RHS) const {
205 // Tokens are only related to tokens.
206 if (Kind == Token || RHS.Kind == Token)
207 return Kind == Token && RHS.Kind == Token;
209 // Registers classes are only related to registers classes, and only if
210 // their intersection is non-empty.
211 if (isRegisterClass() || RHS.isRegisterClass()) {
212 if (!isRegisterClass() || !RHS.isRegisterClass())
215 std::set<Record*> Tmp;
216 std::insert_iterator< std::set<Record*> > II(Tmp, Tmp.begin());
217 std::set_intersection(Registers.begin(), Registers.end(),
218 RHS.Registers.begin(), RHS.Registers.end(),
224 // Otherwise we have two users operands; they are related if they are in the
225 // same class hierarchy.
227 // FIXME: This is an oversimplification, they should only be related if they
228 // intersect, however we don't have that information.
229 assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");
230 const ClassInfo *Root = this;
231 while (!Root->SuperClasses.empty())
232 Root = Root->SuperClasses.front();
234 const ClassInfo *RHSRoot = &RHS;
235 while (!RHSRoot->SuperClasses.empty())
236 RHSRoot = RHSRoot->SuperClasses.front();
238 return Root == RHSRoot;
241 /// isSubsetOf - Test whether this class is a subset of \p RHS.
242 bool isSubsetOf(const ClassInfo &RHS) const {
243 // This is a subset of RHS if it is the same class...
247 // ... or if any of its super classes are a subset of RHS.
248 for (std::vector<ClassInfo*>::const_iterator it = SuperClasses.begin(),
249 ie = SuperClasses.end(); it != ie; ++it)
250 if ((*it)->isSubsetOf(RHS))
256 /// operator< - Compare two classes.
257 bool operator<(const ClassInfo &RHS) const {
261 // Unrelated classes can be ordered by kind.
262 if (!isRelatedTo(RHS))
263 return Kind < RHS.Kind;
267 llvm_unreachable("Invalid kind!");
270 // This class precedes the RHS if it is a proper subset of the RHS.
273 if (RHS.isSubsetOf(*this))
276 // Otherwise, order by name to ensure we have a total ordering.
277 return ValueName < RHS.ValueName;
282 /// MatchableInfo - Helper class for storing the necessary information for an
283 /// instruction or alias which is capable of being matched.
284 struct MatchableInfo {
286 /// Token - This is the token that the operand came from.
289 /// The unique class instance this operand should match.
292 /// The operand name this is, if anything.
295 /// The suboperand index within SrcOpName, or -1 for the entire operand.
298 /// Register record if this token is singleton register.
299 Record *SingletonReg;
301 explicit AsmOperand(StringRef T) : Token(T), Class(0), SubOpIdx(-1),
305 /// ResOperand - This represents a single operand in the result instruction
306 /// generated by the match. In cases (like addressing modes) where a single
307 /// assembler operand expands to multiple MCOperands, this represents the
308 /// single assembler operand, not the MCOperand.
311 /// RenderAsmOperand - This represents an operand result that is
312 /// generated by calling the render method on the assembly operand. The
313 /// corresponding AsmOperand is specified by AsmOperandNum.
316 /// TiedOperand - This represents a result operand that is a duplicate of
317 /// a previous result operand.
320 /// ImmOperand - This represents an immediate value that is dumped into
324 /// RegOperand - This represents a fixed register that is dumped in.
329 /// This is the operand # in the AsmOperands list that this should be
331 unsigned AsmOperandNum;
333 /// TiedOperandNum - This is the (earlier) result operand that should be
335 unsigned TiedOperandNum;
337 /// ImmVal - This is the immediate value added to the instruction.
340 /// Register - This is the register record.
344 /// MINumOperands - The number of MCInst operands populated by this
346 unsigned MINumOperands;
348 static ResOperand getRenderedOp(unsigned AsmOpNum, unsigned NumOperands) {
350 X.Kind = RenderAsmOperand;
351 X.AsmOperandNum = AsmOpNum;
352 X.MINumOperands = NumOperands;
356 static ResOperand getTiedOp(unsigned TiedOperandNum) {
358 X.Kind = TiedOperand;
359 X.TiedOperandNum = TiedOperandNum;
364 static ResOperand getImmOp(int64_t Val) {
372 static ResOperand getRegOp(Record *Reg) {
381 /// AsmVariantID - Target's assembly syntax variant no.
384 /// TheDef - This is the definition of the instruction or InstAlias that this
385 /// matchable came from.
386 Record *const TheDef;
388 /// DefRec - This is the definition that it came from.
389 PointerUnion<const CodeGenInstruction*, const CodeGenInstAlias*> DefRec;
391 const CodeGenInstruction *getResultInst() const {
392 if (DefRec.is<const CodeGenInstruction*>())
393 return DefRec.get<const CodeGenInstruction*>();
394 return DefRec.get<const CodeGenInstAlias*>()->ResultInst;
397 /// ResOperands - This is the operand list that should be built for the result
399 SmallVector<ResOperand, 8> ResOperands;
401 /// AsmString - The assembly string for this instruction (with variants
402 /// removed), e.g. "movsx $src, $dst".
403 std::string AsmString;
405 /// Mnemonic - This is the first token of the matched instruction, its
409 /// AsmOperands - The textual operands that this instruction matches,
410 /// annotated with a class and where in the OperandList they were defined.
411 /// This directly corresponds to the tokenized AsmString after the mnemonic is
413 SmallVector<AsmOperand, 8> AsmOperands;
415 /// Predicates - The required subtarget features to match this instruction.
416 SmallVector<SubtargetFeatureInfo*, 4> RequiredFeatures;
418 /// ConversionFnKind - The enum value which is passed to the generated
419 /// convertToMCInst to convert parsed operands into an MCInst for this
421 std::string ConversionFnKind;
423 MatchableInfo(const CodeGenInstruction &CGI)
424 : AsmVariantID(0), TheDef(CGI.TheDef), DefRec(&CGI),
425 AsmString(CGI.AsmString) {
428 MatchableInfo(const CodeGenInstAlias *Alias)
429 : AsmVariantID(0), TheDef(Alias->TheDef), DefRec(Alias),
430 AsmString(Alias->AsmString) {
433 // Two-operand aliases clone from the main matchable, but mark the second
434 // operand as a tied operand of the first for purposes of the assembler.
435 void formTwoOperandAlias(StringRef Constraint);
437 void initialize(const AsmMatcherInfo &Info,
438 SmallPtrSet<Record*, 16> &SingletonRegisters,
439 int AsmVariantNo, std::string &RegisterPrefix);
441 /// validate - Return true if this matchable is a valid thing to match against
442 /// and perform a bunch of validity checking.
443 bool validate(StringRef CommentDelimiter, bool Hack) const;
445 /// extractSingletonRegisterForAsmOperand - Extract singleton register,
446 /// if present, from specified token.
448 extractSingletonRegisterForAsmOperand(unsigned i, const AsmMatcherInfo &Info,
449 std::string &RegisterPrefix);
451 /// findAsmOperand - Find the AsmOperand with the specified name and
452 /// suboperand index.
453 int findAsmOperand(StringRef N, int SubOpIdx) const {
454 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
455 if (N == AsmOperands[i].SrcOpName &&
456 SubOpIdx == AsmOperands[i].SubOpIdx)
461 /// findAsmOperandNamed - Find the first AsmOperand with the specified name.
462 /// This does not check the suboperand index.
463 int findAsmOperandNamed(StringRef N) const {
464 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
465 if (N == AsmOperands[i].SrcOpName)
470 void buildInstructionResultOperands();
471 void buildAliasResultOperands();
473 /// operator< - Compare two matchables.
474 bool operator<(const MatchableInfo &RHS) const {
475 // The primary comparator is the instruction mnemonic.
476 if (Mnemonic != RHS.Mnemonic)
477 return Mnemonic < RHS.Mnemonic;
479 if (AsmOperands.size() != RHS.AsmOperands.size())
480 return AsmOperands.size() < RHS.AsmOperands.size();
482 // Compare lexicographically by operand. The matcher validates that other
483 // orderings wouldn't be ambiguous using \see couldMatchAmbiguouslyWith().
484 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
485 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
487 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
491 // Give matches that require more features higher precedence. This is useful
492 // because we cannot define AssemblerPredicates with the negation of
493 // processor features. For example, ARM v6 "nop" may be either a HINT or
494 // MOV. With v6, we want to match HINT. The assembler has no way to
495 // predicate MOV under "NoV6", but HINT will always match first because it
496 // requires V6 while MOV does not.
497 if (RequiredFeatures.size() != RHS.RequiredFeatures.size())
498 return RequiredFeatures.size() > RHS.RequiredFeatures.size();
503 /// couldMatchAmbiguouslyWith - Check whether this matchable could
504 /// ambiguously match the same set of operands as \p RHS (without being a
505 /// strictly superior match).
506 bool couldMatchAmbiguouslyWith(const MatchableInfo &RHS) {
507 // The primary comparator is the instruction mnemonic.
508 if (Mnemonic != RHS.Mnemonic)
511 // The number of operands is unambiguous.
512 if (AsmOperands.size() != RHS.AsmOperands.size())
515 // Otherwise, make sure the ordering of the two instructions is unambiguous
516 // by checking that either (a) a token or operand kind discriminates them,
517 // or (b) the ordering among equivalent kinds is consistent.
519 // Tokens and operand kinds are unambiguous (assuming a correct target
521 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
522 if (AsmOperands[i].Class->Kind != RHS.AsmOperands[i].Class->Kind ||
523 AsmOperands[i].Class->Kind == ClassInfo::Token)
524 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class ||
525 *RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
528 // Otherwise, this operand could commute if all operands are equivalent, or
529 // there is a pair of operands that compare less than and a pair that
530 // compare greater than.
531 bool HasLT = false, HasGT = false;
532 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
533 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
535 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
539 return !(HasLT ^ HasGT);
545 void tokenizeAsmString(const AsmMatcherInfo &Info);
548 /// SubtargetFeatureInfo - Helper class for storing information on a subtarget
549 /// feature which participates in instruction matching.
550 struct SubtargetFeatureInfo {
551 /// \brief The predicate record for this feature.
554 /// \brief An unique index assigned to represent this feature.
557 SubtargetFeatureInfo(Record *D, unsigned Idx) : TheDef(D), Index(Idx) {}
559 /// \brief The name of the enumerated constant identifying this feature.
560 std::string getEnumName() const {
561 return "Feature_" + TheDef->getName();
565 struct OperandMatchEntry {
566 unsigned OperandMask;
570 static OperandMatchEntry create(MatchableInfo* mi, ClassInfo *ci,
573 X.OperandMask = opMask;
581 class AsmMatcherInfo {
584 RecordKeeper &Records;
586 /// The tablegen AsmParser record.
589 /// Target - The target information.
590 CodeGenTarget &Target;
592 /// The classes which are needed for matching.
593 std::vector<ClassInfo*> Classes;
595 /// The information on the matchables to match.
596 std::vector<MatchableInfo*> Matchables;
598 /// Info for custom matching operands by user defined methods.
599 std::vector<OperandMatchEntry> OperandMatchInfo;
601 /// Map of Register records to their class information.
602 std::map<Record*, ClassInfo*> RegisterClasses;
604 /// Map of Predicate records to their subtarget information.
605 std::map<Record*, SubtargetFeatureInfo*> SubtargetFeatures;
607 /// Map of AsmOperandClass records to their class information.
608 std::map<Record*, ClassInfo*> AsmOperandClasses;
611 /// Map of token to class information which has already been constructed.
612 std::map<std::string, ClassInfo*> TokenClasses;
614 /// Map of RegisterClass records to their class information.
615 std::map<Record*, ClassInfo*> RegisterClassClasses;
618 /// getTokenClass - Lookup or create the class for the given token.
619 ClassInfo *getTokenClass(StringRef Token);
621 /// getOperandClass - Lookup or create the class for the given operand.
622 ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI,
624 ClassInfo *getOperandClass(Record *Rec, int SubOpIdx);
626 /// buildRegisterClasses - Build the ClassInfo* instances for register
628 void buildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters);
630 /// buildOperandClasses - Build the ClassInfo* instances for user defined
632 void buildOperandClasses();
634 void buildInstructionOperandReference(MatchableInfo *II, StringRef OpName,
636 void buildAliasOperandReference(MatchableInfo *II, StringRef OpName,
637 MatchableInfo::AsmOperand &Op);
640 AsmMatcherInfo(Record *AsmParser,
641 CodeGenTarget &Target,
642 RecordKeeper &Records);
644 /// buildInfo - Construct the various tables used during matching.
647 /// buildOperandMatchInfo - Build the necessary information to handle user
648 /// defined operand parsing methods.
649 void buildOperandMatchInfo();
651 /// getSubtargetFeature - Lookup or create the subtarget feature info for the
653 SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const {
654 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
655 std::map<Record*, SubtargetFeatureInfo*>::const_iterator I =
656 SubtargetFeatures.find(Def);
657 return I == SubtargetFeatures.end() ? 0 : I->second;
660 RecordKeeper &getRecords() const {
665 } // End anonymous namespace
667 void MatchableInfo::dump() {
668 errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n";
670 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
671 AsmOperand &Op = AsmOperands[i];
672 errs() << " op[" << i << "] = " << Op.Class->ClassName << " - ";
673 errs() << '\"' << Op.Token << "\"\n";
677 static std::pair<StringRef, StringRef>
678 parseTwoOperandConstraint(StringRef S, ArrayRef<SMLoc> Loc) {
679 // Split via the '='.
680 std::pair<StringRef, StringRef> Ops = S.split('=');
681 if (Ops.second == "")
682 throw TGError(Loc, "missing '=' in two-operand alias constraint");
683 // Trim whitespace and the leading '$' on the operand names.
684 size_t start = Ops.first.find_first_of('$');
685 if (start == std::string::npos)
686 throw TGError(Loc, "expected '$' prefix on asm operand name");
687 Ops.first = Ops.first.slice(start + 1, std::string::npos);
688 size_t end = Ops.first.find_last_of(" \t");
689 Ops.first = Ops.first.slice(0, end);
690 // Now the second operand.
691 start = Ops.second.find_first_of('$');
692 if (start == std::string::npos)
693 throw TGError(Loc, "expected '$' prefix on asm operand name");
694 Ops.second = Ops.second.slice(start + 1, std::string::npos);
695 end = Ops.second.find_last_of(" \t");
696 Ops.first = Ops.first.slice(0, end);
700 void MatchableInfo::formTwoOperandAlias(StringRef Constraint) {
701 // Figure out which operands are aliased and mark them as tied.
702 std::pair<StringRef, StringRef> Ops =
703 parseTwoOperandConstraint(Constraint, TheDef->getLoc());
705 // Find the AsmOperands that refer to the operands we're aliasing.
706 int SrcAsmOperand = findAsmOperandNamed(Ops.first);
707 int DstAsmOperand = findAsmOperandNamed(Ops.second);
708 if (SrcAsmOperand == -1)
709 throw TGError(TheDef->getLoc(),
710 "unknown source two-operand alias operand '" +
711 Ops.first.str() + "'.");
712 if (DstAsmOperand == -1)
713 throw TGError(TheDef->getLoc(),
714 "unknown destination two-operand alias operand '" +
715 Ops.second.str() + "'.");
717 // Find the ResOperand that refers to the operand we're aliasing away
718 // and update it to refer to the combined operand instead.
719 for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) {
720 ResOperand &Op = ResOperands[i];
721 if (Op.Kind == ResOperand::RenderAsmOperand &&
722 Op.AsmOperandNum == (unsigned)SrcAsmOperand) {
723 Op.AsmOperandNum = DstAsmOperand;
727 // Remove the AsmOperand for the alias operand.
728 AsmOperands.erase(AsmOperands.begin() + SrcAsmOperand);
729 // Adjust the ResOperand references to any AsmOperands that followed
730 // the one we just deleted.
731 for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) {
732 ResOperand &Op = ResOperands[i];
735 // Nothing to do for operands that don't reference AsmOperands.
737 case ResOperand::RenderAsmOperand:
738 if (Op.AsmOperandNum > (unsigned)SrcAsmOperand)
741 case ResOperand::TiedOperand:
742 if (Op.TiedOperandNum > (unsigned)SrcAsmOperand)
749 void MatchableInfo::initialize(const AsmMatcherInfo &Info,
750 SmallPtrSet<Record*, 16> &SingletonRegisters,
751 int AsmVariantNo, std::string &RegisterPrefix) {
752 AsmVariantID = AsmVariantNo;
754 CodeGenInstruction::FlattenAsmStringVariants(AsmString, AsmVariantNo);
756 tokenizeAsmString(Info);
758 // Compute the require features.
759 std::vector<Record*> Predicates =TheDef->getValueAsListOfDefs("Predicates");
760 for (unsigned i = 0, e = Predicates.size(); i != e; ++i)
761 if (SubtargetFeatureInfo *Feature =
762 Info.getSubtargetFeature(Predicates[i]))
763 RequiredFeatures.push_back(Feature);
765 // Collect singleton registers, if used.
766 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
767 extractSingletonRegisterForAsmOperand(i, Info, RegisterPrefix);
768 if (Record *Reg = AsmOperands[i].SingletonReg)
769 SingletonRegisters.insert(Reg);
773 /// tokenizeAsmString - Tokenize a simplified assembly string.
774 void MatchableInfo::tokenizeAsmString(const AsmMatcherInfo &Info) {
775 StringRef String = AsmString;
778 for (unsigned i = 0, e = String.size(); i != e; ++i) {
788 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
791 if (!isspace(String[i]) && String[i] != ',')
792 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
798 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
802 assert(i != String.size() && "Invalid quoted character");
803 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
809 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
813 // If this isn't "${", treat like a normal token.
814 if (i + 1 == String.size() || String[i + 1] != '{') {
819 StringRef::iterator End = std::find(String.begin() + i, String.end(),'}');
820 assert(End != String.end() && "Missing brace in operand reference!");
821 size_t EndPos = End - String.begin();
822 AsmOperands.push_back(AsmOperand(String.slice(i, EndPos+1)));
830 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
839 if (InTok && Prev != String.size())
840 AsmOperands.push_back(AsmOperand(String.substr(Prev)));
842 // The first token of the instruction is the mnemonic, which must be a
843 // simple string, not a $foo variable or a singleton register.
844 if (AsmOperands.empty())
845 throw TGError(TheDef->getLoc(),
846 "Instruction '" + TheDef->getName() + "' has no tokens");
847 Mnemonic = AsmOperands[0].Token;
848 if (Mnemonic.empty())
849 throw TGError(TheDef->getLoc(),
850 "Missing instruction mnemonic");
851 // FIXME : Check and raise an error if it is a register.
852 if (Mnemonic[0] == '$')
853 throw TGError(TheDef->getLoc(),
854 "Invalid instruction mnemonic '" + Mnemonic.str() + "'!");
856 // Remove the first operand, it is tracked in the mnemonic field.
857 AsmOperands.erase(AsmOperands.begin());
860 bool MatchableInfo::validate(StringRef CommentDelimiter, bool Hack) const {
861 // Reject matchables with no .s string.
862 if (AsmString.empty())
863 throw TGError(TheDef->getLoc(), "instruction with empty asm string");
865 // Reject any matchables with a newline in them, they should be marked
866 // isCodeGenOnly if they are pseudo instructions.
867 if (AsmString.find('\n') != std::string::npos)
868 throw TGError(TheDef->getLoc(),
869 "multiline instruction is not valid for the asmparser, "
870 "mark it isCodeGenOnly");
872 // Remove comments from the asm string. We know that the asmstring only
874 if (!CommentDelimiter.empty() &&
875 StringRef(AsmString).find(CommentDelimiter) != StringRef::npos)
876 throw TGError(TheDef->getLoc(),
877 "asmstring for instruction has comment character in it, "
878 "mark it isCodeGenOnly");
880 // Reject matchables with operand modifiers, these aren't something we can
881 // handle, the target should be refactored to use operands instead of
884 // Also, check for instructions which reference the operand multiple times;
885 // this implies a constraint we would not honor.
886 std::set<std::string> OperandNames;
887 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
888 StringRef Tok = AsmOperands[i].Token;
889 if (Tok[0] == '$' && Tok.find(':') != StringRef::npos)
890 throw TGError(TheDef->getLoc(),
891 "matchable with operand modifier '" + Tok.str() +
892 "' not supported by asm matcher. Mark isCodeGenOnly!");
894 // Verify that any operand is only mentioned once.
895 // We reject aliases and ignore instructions for now.
896 if (Tok[0] == '$' && !OperandNames.insert(Tok).second) {
898 throw TGError(TheDef->getLoc(),
899 "ERROR: matchable with tied operand '" + Tok.str() +
900 "' can never be matched!");
901 // FIXME: Should reject these. The ARM backend hits this with $lane in a
902 // bunch of instructions. It is unclear what the right answer is.
904 errs() << "warning: '" << TheDef->getName() << "': "
905 << "ignoring instruction with tied operand '"
906 << Tok.str() << "'\n";
915 /// extractSingletonRegisterForAsmOperand - Extract singleton register,
916 /// if present, from specified token.
918 extractSingletonRegisterForAsmOperand(unsigned OperandNo,
919 const AsmMatcherInfo &Info,
920 std::string &RegisterPrefix) {
921 StringRef Tok = AsmOperands[OperandNo].Token;
922 if (RegisterPrefix.empty()) {
923 std::string LoweredTok = Tok.lower();
924 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(LoweredTok))
925 AsmOperands[OperandNo].SingletonReg = Reg->TheDef;
929 if (!Tok.startswith(RegisterPrefix))
932 StringRef RegName = Tok.substr(RegisterPrefix.size());
933 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName))
934 AsmOperands[OperandNo].SingletonReg = Reg->TheDef;
936 // If there is no register prefix (i.e. "%" in "%eax"), then this may
937 // be some random non-register token, just ignore it.
941 static std::string getEnumNameForToken(StringRef Str) {
944 for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) {
946 case '*': Res += "_STAR_"; break;
947 case '%': Res += "_PCT_"; break;
948 case ':': Res += "_COLON_"; break;
949 case '!': Res += "_EXCLAIM_"; break;
950 case '.': Res += "_DOT_"; break;
955 Res += "_" + utostr((unsigned) *it) + "_";
962 ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) {
963 ClassInfo *&Entry = TokenClasses[Token];
966 Entry = new ClassInfo();
967 Entry->Kind = ClassInfo::Token;
968 Entry->ClassName = "Token";
969 Entry->Name = "MCK_" + getEnumNameForToken(Token);
970 Entry->ValueName = Token;
971 Entry->PredicateMethod = "<invalid>";
972 Entry->RenderMethod = "<invalid>";
973 Entry->ParserMethod = "";
974 Entry->DiagnosticType = "";
975 Classes.push_back(Entry);
982 AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI,
984 Record *Rec = OI.Rec;
986 Rec = dynamic_cast<DefInit*>(OI.MIOperandInfo->getArg(SubOpIdx))->getDef();
987 return getOperandClass(Rec, SubOpIdx);
991 AsmMatcherInfo::getOperandClass(Record *Rec, int SubOpIdx) {
992 if (Rec->isSubClassOf("RegisterOperand")) {
993 // RegisterOperand may have an associated ParserMatchClass. If it does,
994 // use it, else just fall back to the underlying register class.
995 const RecordVal *R = Rec->getValue("ParserMatchClass");
996 if (R == 0 || R->getValue() == 0)
997 throw "Record `" + Rec->getName() +
998 "' does not have a ParserMatchClass!\n";
1000 if (DefInit *DI= dynamic_cast<DefInit*>(R->getValue())) {
1001 Record *MatchClass = DI->getDef();
1002 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1006 // No custom match class. Just use the register class.
1007 Record *ClassRec = Rec->getValueAsDef("RegClass");
1009 throw TGError(Rec->getLoc(), "RegisterOperand `" + Rec->getName() +
1010 "' has no associated register class!\n");
1011 if (ClassInfo *CI = RegisterClassClasses[ClassRec])
1013 throw TGError(Rec->getLoc(), "register class has no class info!");
1017 if (Rec->isSubClassOf("RegisterClass")) {
1018 if (ClassInfo *CI = RegisterClassClasses[Rec])
1020 throw TGError(Rec->getLoc(), "register class has no class info!");
1023 if (!Rec->isSubClassOf("Operand"))
1024 throw TGError(Rec->getLoc(), "Operand `" + Rec->getName() +
1025 "' does not derive from class Operand!\n");
1026 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1027 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1030 throw TGError(Rec->getLoc(), "operand has no match class!");
1033 void AsmMatcherInfo::
1034 buildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters) {
1035 const std::vector<CodeGenRegister*> &Registers =
1036 Target.getRegBank().getRegisters();
1037 ArrayRef<CodeGenRegisterClass*> RegClassList =
1038 Target.getRegBank().getRegClasses();
1040 // The register sets used for matching.
1041 std::set< std::set<Record*> > RegisterSets;
1043 // Gather the defined sets.
1044 for (ArrayRef<CodeGenRegisterClass*>::const_iterator it =
1045 RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it)
1046 RegisterSets.insert(std::set<Record*>(
1047 (*it)->getOrder().begin(), (*it)->getOrder().end()));
1049 // Add any required singleton sets.
1050 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
1051 ie = SingletonRegisters.end(); it != ie; ++it) {
1053 RegisterSets.insert(std::set<Record*>(&Rec, &Rec + 1));
1056 // Introduce derived sets where necessary (when a register does not determine
1057 // a unique register set class), and build the mapping of registers to the set
1058 // they should classify to.
1059 std::map<Record*, std::set<Record*> > RegisterMap;
1060 for (std::vector<CodeGenRegister*>::const_iterator it = Registers.begin(),
1061 ie = Registers.end(); it != ie; ++it) {
1062 const CodeGenRegister &CGR = **it;
1063 // Compute the intersection of all sets containing this register.
1064 std::set<Record*> ContainingSet;
1066 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
1067 ie = RegisterSets.end(); it != ie; ++it) {
1068 if (!it->count(CGR.TheDef))
1071 if (ContainingSet.empty()) {
1072 ContainingSet = *it;
1076 std::set<Record*> Tmp;
1077 std::swap(Tmp, ContainingSet);
1078 std::insert_iterator< std::set<Record*> > II(ContainingSet,
1079 ContainingSet.begin());
1080 std::set_intersection(Tmp.begin(), Tmp.end(), it->begin(), it->end(), II);
1083 if (!ContainingSet.empty()) {
1084 RegisterSets.insert(ContainingSet);
1085 RegisterMap.insert(std::make_pair(CGR.TheDef, ContainingSet));
1089 // Construct the register classes.
1090 std::map<std::set<Record*>, ClassInfo*> RegisterSetClasses;
1092 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
1093 ie = RegisterSets.end(); it != ie; ++it, ++Index) {
1094 ClassInfo *CI = new ClassInfo();
1095 CI->Kind = ClassInfo::RegisterClass0 + Index;
1096 CI->ClassName = "Reg" + utostr(Index);
1097 CI->Name = "MCK_Reg" + utostr(Index);
1099 CI->PredicateMethod = ""; // unused
1100 CI->RenderMethod = "addRegOperands";
1101 CI->Registers = *it;
1102 // FIXME: diagnostic type.
1103 CI->DiagnosticType = "";
1104 Classes.push_back(CI);
1105 RegisterSetClasses.insert(std::make_pair(*it, CI));
1108 // Find the superclasses; we could compute only the subgroup lattice edges,
1109 // but there isn't really a point.
1110 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
1111 ie = RegisterSets.end(); it != ie; ++it) {
1112 ClassInfo *CI = RegisterSetClasses[*it];
1113 for (std::set< std::set<Record*> >::iterator it2 = RegisterSets.begin(),
1114 ie2 = RegisterSets.end(); it2 != ie2; ++it2)
1116 std::includes(it2->begin(), it2->end(), it->begin(), it->end()))
1117 CI->SuperClasses.push_back(RegisterSetClasses[*it2]);
1120 // Name the register classes which correspond to a user defined RegisterClass.
1121 for (ArrayRef<CodeGenRegisterClass*>::const_iterator
1122 it = RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it) {
1123 const CodeGenRegisterClass &RC = **it;
1124 // Def will be NULL for non-user defined register classes.
1125 Record *Def = RC.getDef();
1128 ClassInfo *CI = RegisterSetClasses[std::set<Record*>(RC.getOrder().begin(),
1129 RC.getOrder().end())];
1130 if (CI->ValueName.empty()) {
1131 CI->ClassName = RC.getName();
1132 CI->Name = "MCK_" + RC.getName();
1133 CI->ValueName = RC.getName();
1135 CI->ValueName = CI->ValueName + "," + RC.getName();
1137 RegisterClassClasses.insert(std::make_pair(Def, CI));
1140 // Populate the map for individual registers.
1141 for (std::map<Record*, std::set<Record*> >::iterator it = RegisterMap.begin(),
1142 ie = RegisterMap.end(); it != ie; ++it)
1143 RegisterClasses[it->first] = RegisterSetClasses[it->second];
1145 // Name the register classes which correspond to singleton registers.
1146 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
1147 ie = SingletonRegisters.end(); it != ie; ++it) {
1149 ClassInfo *CI = RegisterClasses[Rec];
1150 assert(CI && "Missing singleton register class info!");
1152 if (CI->ValueName.empty()) {
1153 CI->ClassName = Rec->getName();
1154 CI->Name = "MCK_" + Rec->getName();
1155 CI->ValueName = Rec->getName();
1157 CI->ValueName = CI->ValueName + "," + Rec->getName();
1161 void AsmMatcherInfo::buildOperandClasses() {
1162 std::vector<Record*> AsmOperands =
1163 Records.getAllDerivedDefinitions("AsmOperandClass");
1165 // Pre-populate AsmOperandClasses map.
1166 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
1167 ie = AsmOperands.end(); it != ie; ++it)
1168 AsmOperandClasses[*it] = new ClassInfo();
1171 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
1172 ie = AsmOperands.end(); it != ie; ++it, ++Index) {
1173 ClassInfo *CI = AsmOperandClasses[*it];
1174 CI->Kind = ClassInfo::UserClass0 + Index;
1176 ListInit *Supers = (*it)->getValueAsListInit("SuperClasses");
1177 for (unsigned i = 0, e = Supers->getSize(); i != e; ++i) {
1178 DefInit *DI = dynamic_cast<DefInit*>(Supers->getElement(i));
1180 PrintError((*it)->getLoc(), "Invalid super class reference!");
1184 ClassInfo *SC = AsmOperandClasses[DI->getDef()];
1186 PrintError((*it)->getLoc(), "Invalid super class reference!");
1188 CI->SuperClasses.push_back(SC);
1190 CI->ClassName = (*it)->getValueAsString("Name");
1191 CI->Name = "MCK_" + CI->ClassName;
1192 CI->ValueName = (*it)->getName();
1194 // Get or construct the predicate method name.
1195 Init *PMName = (*it)->getValueInit("PredicateMethod");
1196 if (StringInit *SI = dynamic_cast<StringInit*>(PMName)) {
1197 CI->PredicateMethod = SI->getValue();
1199 assert(dynamic_cast<UnsetInit*>(PMName) &&
1200 "Unexpected PredicateMethod field!");
1201 CI->PredicateMethod = "is" + CI->ClassName;
1204 // Get or construct the render method name.
1205 Init *RMName = (*it)->getValueInit("RenderMethod");
1206 if (StringInit *SI = dynamic_cast<StringInit*>(RMName)) {
1207 CI->RenderMethod = SI->getValue();
1209 assert(dynamic_cast<UnsetInit*>(RMName) &&
1210 "Unexpected RenderMethod field!");
1211 CI->RenderMethod = "add" + CI->ClassName + "Operands";
1214 // Get the parse method name or leave it as empty.
1215 Init *PRMName = (*it)->getValueInit("ParserMethod");
1216 if (StringInit *SI = dynamic_cast<StringInit*>(PRMName))
1217 CI->ParserMethod = SI->getValue();
1219 // Get the diagnostic type or leave it as empty.
1220 // Get the parse method name or leave it as empty.
1221 Init *DiagnosticType = (*it)->getValueInit("DiagnosticType");
1222 if (StringInit *SI = dynamic_cast<StringInit*>(DiagnosticType))
1223 CI->DiagnosticType = SI->getValue();
1225 AsmOperandClasses[*it] = CI;
1226 Classes.push_back(CI);
1230 AsmMatcherInfo::AsmMatcherInfo(Record *asmParser,
1231 CodeGenTarget &target,
1232 RecordKeeper &records)
1233 : Records(records), AsmParser(asmParser), Target(target) {
1236 /// buildOperandMatchInfo - Build the necessary information to handle user
1237 /// defined operand parsing methods.
1238 void AsmMatcherInfo::buildOperandMatchInfo() {
1240 /// Map containing a mask with all operands indices that can be found for
1241 /// that class inside a instruction.
1242 std::map<ClassInfo*, unsigned> OpClassMask;
1244 for (std::vector<MatchableInfo*>::const_iterator it =
1245 Matchables.begin(), ie = Matchables.end();
1247 MatchableInfo &II = **it;
1248 OpClassMask.clear();
1250 // Keep track of all operands of this instructions which belong to the
1252 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) {
1253 MatchableInfo::AsmOperand &Op = II.AsmOperands[i];
1254 if (Op.Class->ParserMethod.empty())
1256 unsigned &OperandMask = OpClassMask[Op.Class];
1257 OperandMask |= (1 << i);
1260 // Generate operand match info for each mnemonic/operand class pair.
1261 for (std::map<ClassInfo*, unsigned>::iterator iit = OpClassMask.begin(),
1262 iie = OpClassMask.end(); iit != iie; ++iit) {
1263 unsigned OpMask = iit->second;
1264 ClassInfo *CI = iit->first;
1265 OperandMatchInfo.push_back(OperandMatchEntry::create(&II, CI, OpMask));
1270 void AsmMatcherInfo::buildInfo() {
1271 // Build information about all of the AssemblerPredicates.
1272 std::vector<Record*> AllPredicates =
1273 Records.getAllDerivedDefinitions("Predicate");
1274 for (unsigned i = 0, e = AllPredicates.size(); i != e; ++i) {
1275 Record *Pred = AllPredicates[i];
1276 // Ignore predicates that are not intended for the assembler.
1277 if (!Pred->getValueAsBit("AssemblerMatcherPredicate"))
1280 if (Pred->getName().empty())
1281 throw TGError(Pred->getLoc(), "Predicate has no name!");
1283 unsigned FeatureNo = SubtargetFeatures.size();
1284 SubtargetFeatures[Pred] = new SubtargetFeatureInfo(Pred, FeatureNo);
1285 assert(FeatureNo < 32 && "Too many subtarget features!");
1288 // Parse the instructions; we need to do this first so that we can gather the
1289 // singleton register classes.
1290 SmallPtrSet<Record*, 16> SingletonRegisters;
1291 unsigned VariantCount = Target.getAsmParserVariantCount();
1292 for (unsigned VC = 0; VC != VariantCount; ++VC) {
1293 Record *AsmVariant = Target.getAsmParserVariant(VC);
1294 std::string CommentDelimiter =
1295 AsmVariant->getValueAsString("CommentDelimiter");
1296 std::string RegisterPrefix = AsmVariant->getValueAsString("RegisterPrefix");
1297 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
1299 for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
1300 E = Target.inst_end(); I != E; ++I) {
1301 const CodeGenInstruction &CGI = **I;
1303 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1304 // filter the set of instructions we consider.
1305 if (!StringRef(CGI.TheDef->getName()).startswith(MatchPrefix))
1308 // Ignore "codegen only" instructions.
1309 if (CGI.TheDef->getValueAsBit("isCodeGenOnly"))
1312 // Validate the operand list to ensure we can handle this instruction.
1313 for (unsigned i = 0, e = CGI.Operands.size(); i != e; ++i) {
1314 const CGIOperandList::OperandInfo &OI = CGI.Operands[i];
1316 // Validate tied operands.
1317 if (OI.getTiedRegister() != -1) {
1318 // If we have a tied operand that consists of multiple MCOperands,
1319 // reject it. We reject aliases and ignore instructions for now.
1320 if (OI.MINumOperands != 1) {
1321 // FIXME: Should reject these. The ARM backend hits this with $lane
1322 // in a bunch of instructions. The right answer is unclear.
1324 errs() << "warning: '" << CGI.TheDef->getName() << "': "
1325 << "ignoring instruction with multi-operand tied operand '"
1326 << OI.Name << "'\n";
1333 OwningPtr<MatchableInfo> II(new MatchableInfo(CGI));
1335 II->initialize(*this, SingletonRegisters, AsmVariantNo, RegisterPrefix);
1337 // Ignore instructions which shouldn't be matched and diagnose invalid
1338 // instruction definitions with an error.
1339 if (!II->validate(CommentDelimiter, true))
1342 // Ignore "Int_*" and "*_Int" instructions, which are internal aliases.
1344 // FIXME: This is a total hack.
1345 if (StringRef(II->TheDef->getName()).startswith("Int_") ||
1346 StringRef(II->TheDef->getName()).endswith("_Int"))
1349 Matchables.push_back(II.take());
1352 // Parse all of the InstAlias definitions and stick them in the list of
1354 std::vector<Record*> AllInstAliases =
1355 Records.getAllDerivedDefinitions("InstAlias");
1356 for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) {
1357 CodeGenInstAlias *Alias = new CodeGenInstAlias(AllInstAliases[i], Target);
1359 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1360 // filter the set of instruction aliases we consider, based on the target
1362 if (!StringRef(Alias->ResultInst->TheDef->getName())
1363 .startswith( MatchPrefix))
1366 OwningPtr<MatchableInfo> II(new MatchableInfo(Alias));
1368 II->initialize(*this, SingletonRegisters, AsmVariantNo, RegisterPrefix);
1370 // Validate the alias definitions.
1371 II->validate(CommentDelimiter, false);
1373 Matchables.push_back(II.take());
1377 // Build info for the register classes.
1378 buildRegisterClasses(SingletonRegisters);
1380 // Build info for the user defined assembly operand classes.
1381 buildOperandClasses();
1383 // Build the information about matchables, now that we have fully formed
1385 std::vector<MatchableInfo*> NewMatchables;
1386 for (std::vector<MatchableInfo*>::iterator it = Matchables.begin(),
1387 ie = Matchables.end(); it != ie; ++it) {
1388 MatchableInfo *II = *it;
1390 // Parse the tokens after the mnemonic.
1391 // Note: buildInstructionOperandReference may insert new AsmOperands, so
1392 // don't precompute the loop bound.
1393 for (unsigned i = 0; i != II->AsmOperands.size(); ++i) {
1394 MatchableInfo::AsmOperand &Op = II->AsmOperands[i];
1395 StringRef Token = Op.Token;
1397 // Check for singleton registers.
1398 if (Record *RegRecord = II->AsmOperands[i].SingletonReg) {
1399 Op.Class = RegisterClasses[RegRecord];
1400 assert(Op.Class && Op.Class->Registers.size() == 1 &&
1401 "Unexpected class for singleton register");
1405 // Check for simple tokens.
1406 if (Token[0] != '$') {
1407 Op.Class = getTokenClass(Token);
1411 if (Token.size() > 1 && isdigit(Token[1])) {
1412 Op.Class = getTokenClass(Token);
1416 // Otherwise this is an operand reference.
1417 StringRef OperandName;
1418 if (Token[1] == '{')
1419 OperandName = Token.substr(2, Token.size() - 3);
1421 OperandName = Token.substr(1);
1423 if (II->DefRec.is<const CodeGenInstruction*>())
1424 buildInstructionOperandReference(II, OperandName, i);
1426 buildAliasOperandReference(II, OperandName, Op);
1429 if (II->DefRec.is<const CodeGenInstruction*>()) {
1430 II->buildInstructionResultOperands();
1431 // If the instruction has a two-operand alias, build up the
1432 // matchable here. We'll add them in bulk at the end to avoid
1433 // confusing this loop.
1434 std::string Constraint =
1435 II->TheDef->getValueAsString("TwoOperandAliasConstraint");
1436 if (Constraint != "") {
1437 // Start by making a copy of the original matchable.
1438 OwningPtr<MatchableInfo> AliasII(new MatchableInfo(*II));
1440 // Adjust it to be a two-operand alias.
1441 AliasII->formTwoOperandAlias(Constraint);
1443 // Add the alias to the matchables list.
1444 NewMatchables.push_back(AliasII.take());
1447 II->buildAliasResultOperands();
1449 if (!NewMatchables.empty())
1450 Matchables.insert(Matchables.end(), NewMatchables.begin(),
1451 NewMatchables.end());
1453 // Process token alias definitions and set up the associated superclass
1455 std::vector<Record*> AllTokenAliases =
1456 Records.getAllDerivedDefinitions("TokenAlias");
1457 for (unsigned i = 0, e = AllTokenAliases.size(); i != e; ++i) {
1458 Record *Rec = AllTokenAliases[i];
1459 ClassInfo *FromClass = getTokenClass(Rec->getValueAsString("FromToken"));
1460 ClassInfo *ToClass = getTokenClass(Rec->getValueAsString("ToToken"));
1461 if (FromClass == ToClass)
1462 throw TGError(Rec->getLoc(),
1463 "error: Destination value identical to source value.");
1464 FromClass->SuperClasses.push_back(ToClass);
1467 // Reorder classes so that classes precede super classes.
1468 std::sort(Classes.begin(), Classes.end(), less_ptr<ClassInfo>());
1471 /// buildInstructionOperandReference - The specified operand is a reference to a
1472 /// named operand such as $src. Resolve the Class and OperandInfo pointers.
1473 void AsmMatcherInfo::
1474 buildInstructionOperandReference(MatchableInfo *II,
1475 StringRef OperandName,
1476 unsigned AsmOpIdx) {
1477 const CodeGenInstruction &CGI = *II->DefRec.get<const CodeGenInstruction*>();
1478 const CGIOperandList &Operands = CGI.Operands;
1479 MatchableInfo::AsmOperand *Op = &II->AsmOperands[AsmOpIdx];
1481 // Map this token to an operand.
1483 if (!Operands.hasOperandNamed(OperandName, Idx))
1484 throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" +
1485 OperandName.str() + "'");
1487 // If the instruction operand has multiple suboperands, but the parser
1488 // match class for the asm operand is still the default "ImmAsmOperand",
1489 // then handle each suboperand separately.
1490 if (Op->SubOpIdx == -1 && Operands[Idx].MINumOperands > 1) {
1491 Record *Rec = Operands[Idx].Rec;
1492 assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
1493 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1494 if (MatchClass && MatchClass->getValueAsString("Name") == "Imm") {
1495 // Insert remaining suboperands after AsmOpIdx in II->AsmOperands.
1496 StringRef Token = Op->Token; // save this in case Op gets moved
1497 for (unsigned SI = 1, SE = Operands[Idx].MINumOperands; SI != SE; ++SI) {
1498 MatchableInfo::AsmOperand NewAsmOp(Token);
1499 NewAsmOp.SubOpIdx = SI;
1500 II->AsmOperands.insert(II->AsmOperands.begin()+AsmOpIdx+SI, NewAsmOp);
1502 // Replace Op with first suboperand.
1503 Op = &II->AsmOperands[AsmOpIdx]; // update the pointer in case it moved
1508 // Set up the operand class.
1509 Op->Class = getOperandClass(Operands[Idx], Op->SubOpIdx);
1511 // If the named operand is tied, canonicalize it to the untied operand.
1512 // For example, something like:
1513 // (outs GPR:$dst), (ins GPR:$src)
1514 // with an asmstring of
1516 // we want to canonicalize to:
1518 // so that we know how to provide the $dst operand when filling in the result.
1519 int OITied = Operands[Idx].getTiedRegister();
1521 // The tied operand index is an MIOperand index, find the operand that
1523 std::pair<unsigned, unsigned> Idx = Operands.getSubOperandNumber(OITied);
1524 OperandName = Operands[Idx.first].Name;
1525 Op->SubOpIdx = Idx.second;
1528 Op->SrcOpName = OperandName;
1531 /// buildAliasOperandReference - When parsing an operand reference out of the
1532 /// matching string (e.g. "movsx $src, $dst"), determine what the class of the
1533 /// operand reference is by looking it up in the result pattern definition.
1534 void AsmMatcherInfo::buildAliasOperandReference(MatchableInfo *II,
1535 StringRef OperandName,
1536 MatchableInfo::AsmOperand &Op) {
1537 const CodeGenInstAlias &CGA = *II->DefRec.get<const CodeGenInstAlias*>();
1539 // Set up the operand class.
1540 for (unsigned i = 0, e = CGA.ResultOperands.size(); i != e; ++i)
1541 if (CGA.ResultOperands[i].isRecord() &&
1542 CGA.ResultOperands[i].getName() == OperandName) {
1543 // It's safe to go with the first one we find, because CodeGenInstAlias
1544 // validates that all operands with the same name have the same record.
1545 Op.SubOpIdx = CGA.ResultInstOperandIndex[i].second;
1546 // Use the match class from the Alias definition, not the
1547 // destination instruction, as we may have an immediate that's
1548 // being munged by the match class.
1549 Op.Class = getOperandClass(CGA.ResultOperands[i].getRecord(),
1551 Op.SrcOpName = OperandName;
1555 throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" +
1556 OperandName.str() + "'");
1559 void MatchableInfo::buildInstructionResultOperands() {
1560 const CodeGenInstruction *ResultInst = getResultInst();
1562 // Loop over all operands of the result instruction, determining how to
1564 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1565 const CGIOperandList::OperandInfo &OpInfo = ResultInst->Operands[i];
1567 // If this is a tied operand, just copy from the previously handled operand.
1568 int TiedOp = OpInfo.getTiedRegister();
1570 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1574 // Find out what operand from the asmparser this MCInst operand comes from.
1575 int SrcOperand = findAsmOperandNamed(OpInfo.Name);
1576 if (OpInfo.Name.empty() || SrcOperand == -1)
1577 throw TGError(TheDef->getLoc(), "Instruction '" +
1578 TheDef->getName() + "' has operand '" + OpInfo.Name +
1579 "' that doesn't appear in asm string!");
1581 // Check if the one AsmOperand populates the entire operand.
1582 unsigned NumOperands = OpInfo.MINumOperands;
1583 if (AsmOperands[SrcOperand].SubOpIdx == -1) {
1584 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, NumOperands));
1588 // Add a separate ResOperand for each suboperand.
1589 for (unsigned AI = 0; AI < NumOperands; ++AI) {
1590 assert(AsmOperands[SrcOperand+AI].SubOpIdx == (int)AI &&
1591 AsmOperands[SrcOperand+AI].SrcOpName == OpInfo.Name &&
1592 "unexpected AsmOperands for suboperands");
1593 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand + AI, 1));
1598 void MatchableInfo::buildAliasResultOperands() {
1599 const CodeGenInstAlias &CGA = *DefRec.get<const CodeGenInstAlias*>();
1600 const CodeGenInstruction *ResultInst = getResultInst();
1602 // Loop over all operands of the result instruction, determining how to
1604 unsigned AliasOpNo = 0;
1605 unsigned LastOpNo = CGA.ResultInstOperandIndex.size();
1606 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1607 const CGIOperandList::OperandInfo *OpInfo = &ResultInst->Operands[i];
1609 // If this is a tied operand, just copy from the previously handled operand.
1610 int TiedOp = OpInfo->getTiedRegister();
1612 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1616 // Handle all the suboperands for this operand.
1617 const std::string &OpName = OpInfo->Name;
1618 for ( ; AliasOpNo < LastOpNo &&
1619 CGA.ResultInstOperandIndex[AliasOpNo].first == i; ++AliasOpNo) {
1620 int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second;
1622 // Find out what operand from the asmparser that this MCInst operand
1624 switch (CGA.ResultOperands[AliasOpNo].Kind) {
1625 case CodeGenInstAlias::ResultOperand::K_Record: {
1626 StringRef Name = CGA.ResultOperands[AliasOpNo].getName();
1627 int SrcOperand = findAsmOperand(Name, SubIdx);
1628 if (SrcOperand == -1)
1629 throw TGError(TheDef->getLoc(), "Instruction '" +
1630 TheDef->getName() + "' has operand '" + OpName +
1631 "' that doesn't appear in asm string!");
1632 unsigned NumOperands = (SubIdx == -1 ? OpInfo->MINumOperands : 1);
1633 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand,
1637 case CodeGenInstAlias::ResultOperand::K_Imm: {
1638 int64_t ImmVal = CGA.ResultOperands[AliasOpNo].getImm();
1639 ResOperands.push_back(ResOperand::getImmOp(ImmVal));
1642 case CodeGenInstAlias::ResultOperand::K_Reg: {
1643 Record *Reg = CGA.ResultOperands[AliasOpNo].getRegister();
1644 ResOperands.push_back(ResOperand::getRegOp(Reg));
1652 static unsigned getConverterOperandID(const std::string &Name,
1653 SetVector<std::string> &Table,
1655 IsNew = Table.insert(Name);
1657 unsigned ID = IsNew ? Table.size() - 1 :
1658 std::find(Table.begin(), Table.end(), Name) - Table.begin();
1660 assert(ID < Table.size());
1666 static void emitConvertToMCInst(CodeGenTarget &Target, StringRef ClassName,
1667 std::vector<MatchableInfo*> &Infos,
1669 SetVector<std::string> OperandConversionKinds;
1670 SetVector<std::string> InstructionConversionKinds;
1671 std::vector<std::vector<uint8_t> > ConversionTable;
1672 size_t MaxRowLength = 2; // minimum is custom converter plus terminator.
1674 // TargetOperandClass - This is the target's operand class, like X86Operand.
1675 std::string TargetOperandClass = Target.getName() + "Operand";
1677 // Write the convert function to a separate stream, so we can drop it after
1678 // the enum. We'll build up the conversion handlers for the individual
1679 // operand types opportunistically as we encounter them.
1680 std::string ConvertFnBody;
1681 raw_string_ostream CvtOS(ConvertFnBody);
1682 // Start the unified conversion function.
1683 CvtOS << "void " << Target.getName() << ClassName << "::\n"
1684 << "convertToMCInst(unsigned Kind, MCInst &Inst, "
1685 << "unsigned Opcode,\n"
1686 << " const SmallVectorImpl<MCParsedAsmOperand*"
1687 << "> &Operands) {\n"
1688 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
1689 << " uint8_t *Converter = ConversionTable[Kind];\n"
1690 << " Inst.setOpcode(Opcode);\n"
1691 << " for (uint8_t *p = Converter; *p; p+= 2) {\n"
1692 << " switch (*p) {\n"
1693 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
1694 << " case CVT_Reg:\n"
1695 << " static_cast<" << TargetOperandClass
1696 << "*>(Operands[*(p + 1)])->addRegOperands(Inst, 1);\n"
1698 << " case CVT_Tied:\n"
1699 << " Inst.addOperand(Inst.getOperand(*(p + 1)));\n"
1702 std::string OperandFnBody;
1703 raw_string_ostream OpOS(OperandFnBody);
1704 // Start the operand number lookup function.
1705 OpOS << "unsigned " << Target.getName() << ClassName << "::\n"
1706 << "getMCInstOperandNumImpl(unsigned Kind, MCInst &Inst,\n"
1707 << " const SmallVectorImpl<MCParsedAsmOperand*> "
1708 << "&Operands,\n unsigned OperandNum, unsigned "
1709 << "&NumMCOperands) {\n"
1710 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
1711 << " NumMCOperands = 0;\n"
1712 << " unsigned MCOperandNum = 0;\n"
1713 << " uint8_t *Converter = ConversionTable[Kind];\n"
1714 << " for (uint8_t *p = Converter; *p; p+= 2) {\n"
1715 << " if (*(p + 1) > OperandNum) continue;\n"
1716 << " switch (*p) {\n"
1717 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
1718 << " case CVT_Reg:\n"
1719 << " if (*(p + 1) == OperandNum) {\n"
1720 << " NumMCOperands = 1;\n"
1723 << " ++MCOperandNum;\n"
1725 << " case CVT_Tied:\n"
1726 << " // FIXME: Tied operand calculation not supported.\n"
1727 << " assert (0 && \"getMCInstOperandNumImpl() doesn't support tied operands, yet!\");\n"
1730 // Pre-populate the operand conversion kinds with the standard always
1731 // available entries.
1732 OperandConversionKinds.insert("CVT_Done");
1733 OperandConversionKinds.insert("CVT_Reg");
1734 OperandConversionKinds.insert("CVT_Tied");
1735 enum { CVT_Done, CVT_Reg, CVT_Tied };
1737 for (std::vector<MatchableInfo*>::const_iterator it = Infos.begin(),
1738 ie = Infos.end(); it != ie; ++it) {
1739 MatchableInfo &II = **it;
1741 // Check if we have a custom match function.
1742 std::string AsmMatchConverter =
1743 II.getResultInst()->TheDef->getValueAsString("AsmMatchConverter");
1744 if (!AsmMatchConverter.empty()) {
1745 std::string Signature = "ConvertCustom_" + AsmMatchConverter;
1746 II.ConversionFnKind = Signature;
1748 // Check if we have already generated this signature.
1749 if (!InstructionConversionKinds.insert(Signature))
1752 // Remember this converter for the kind enum.
1753 unsigned KindID = OperandConversionKinds.size();
1754 OperandConversionKinds.insert("CVT_" + AsmMatchConverter);
1756 // Add the converter row for this instruction.
1757 ConversionTable.push_back(std::vector<uint8_t>());
1758 ConversionTable.back().push_back(KindID);
1759 ConversionTable.back().push_back(CVT_Done);
1761 // Add the handler to the conversion driver function.
1762 CvtOS << " case CVT_" << AsmMatchConverter << ":\n"
1763 << " " << AsmMatchConverter << "(Inst, Operands);\n"
1766 // FIXME: Handle the operand number lookup for custom match functions.
1770 // Build the conversion function signature.
1771 std::string Signature = "Convert";
1773 std::vector<uint8_t> ConversionRow;
1775 // Compute the convert enum and the case body.
1776 MaxRowLength = std::max(MaxRowLength, II.ResOperands.size()*2 + 1 );
1778 for (unsigned i = 0, e = II.ResOperands.size(); i != e; ++i) {
1779 const MatchableInfo::ResOperand &OpInfo = II.ResOperands[i];
1781 // Generate code to populate each result operand.
1782 switch (OpInfo.Kind) {
1783 case MatchableInfo::ResOperand::RenderAsmOperand: {
1784 // This comes from something we parsed.
1785 MatchableInfo::AsmOperand &Op = II.AsmOperands[OpInfo.AsmOperandNum];
1787 // Registers are always converted the same, don't duplicate the
1788 // conversion function based on them.
1791 Class = Op.Class->isRegisterClass() ? "Reg" : Op.Class->ClassName;
1793 Signature += utostr(OpInfo.MINumOperands);
1794 Signature += "_" + itostr(OpInfo.AsmOperandNum);
1796 // Add the conversion kind, if necessary, and get the associated ID
1797 // the index of its entry in the vector).
1798 std::string Name = "CVT_" + (Op.Class->isRegisterClass() ? "Reg" :
1799 Op.Class->RenderMethod);
1801 bool IsNewConverter = false;
1802 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1805 // Add the operand entry to the instruction kind conversion row.
1806 ConversionRow.push_back(ID);
1807 ConversionRow.push_back(OpInfo.AsmOperandNum + 1);
1809 if (!IsNewConverter)
1812 // This is a new operand kind. Add a handler for it to the
1813 // converter driver.
1814 CvtOS << " case " << Name << ":\n"
1815 << " static_cast<" << TargetOperandClass
1816 << "*>(Operands[*(p + 1)])->"
1817 << Op.Class->RenderMethod << "(Inst, " << OpInfo.MINumOperands
1821 // Add a handler for the operand number lookup.
1822 OpOS << " case " << Name << ":\n"
1823 << " if (*(p + 1) == OperandNum) {\n"
1824 << " NumMCOperands = " << OpInfo.MINumOperands << ";\n"
1827 << " MCOperandNum += " << OpInfo.MINumOperands << ";\n"
1831 case MatchableInfo::ResOperand::TiedOperand: {
1832 // If this operand is tied to a previous one, just copy the MCInst
1833 // operand from the earlier one.We can only tie single MCOperand values.
1834 //assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand");
1835 unsigned TiedOp = OpInfo.TiedOperandNum;
1836 assert(i > TiedOp && "Tied operand precedes its target!");
1837 Signature += "__Tie" + utostr(TiedOp);
1838 ConversionRow.push_back(CVT_Tied);
1839 ConversionRow.push_back(TiedOp);
1840 // FIXME: Handle the operand number lookup for tied operands.
1843 case MatchableInfo::ResOperand::ImmOperand: {
1844 int64_t Val = OpInfo.ImmVal;
1845 std::string Ty = "imm_" + itostr(Val);
1846 Signature += "__" + Ty;
1848 std::string Name = "CVT_" + Ty;
1849 bool IsNewConverter = false;
1850 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1852 // Add the operand entry to the instruction kind conversion row.
1853 ConversionRow.push_back(ID);
1854 ConversionRow.push_back(0);
1856 if (!IsNewConverter)
1859 CvtOS << " case " << Name << ":\n"
1860 << " Inst.addOperand(MCOperand::CreateImm(" << Val << "));\n"
1863 OpOS << " case " << Name << ":\n"
1864 << " if (*(p + 1) == OperandNum) {\n"
1865 << " NumMCOperands = 1;\n"
1868 << " ++MCOperandNum;\n"
1872 case MatchableInfo::ResOperand::RegOperand: {
1873 std::string Reg, Name;
1874 if (OpInfo.Register == 0) {
1878 Reg = getQualifiedName(OpInfo.Register);
1879 Name = "reg" + OpInfo.Register->getName();
1881 Signature += "__" + Name;
1882 Name = "CVT_" + Name;
1883 bool IsNewConverter = false;
1884 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1886 // Add the operand entry to the instruction kind conversion row.
1887 ConversionRow.push_back(ID);
1888 ConversionRow.push_back(0);
1890 if (!IsNewConverter)
1892 CvtOS << " case " << Name << ":\n"
1893 << " Inst.addOperand(MCOperand::CreateReg(" << Reg << "));\n"
1896 OpOS << " case " << Name << ":\n"
1897 << " if (*(p + 1) == OperandNum) {\n"
1898 << " NumMCOperands = 1;\n"
1901 << " ++MCOperandNum;\n"
1907 // If there were no operands, add to the signature to that effect
1908 if (Signature == "Convert")
1909 Signature += "_NoOperands";
1911 II.ConversionFnKind = Signature;
1913 // Save the signature. If we already have it, don't add a new row
1915 if (!InstructionConversionKinds.insert(Signature))
1918 // Add the row to the table.
1919 ConversionTable.push_back(ConversionRow);
1922 // Finish up the converter driver function.
1923 CvtOS << " }\n }\n}\n\n";
1925 // Finish up the operand number lookup function.
1926 OpOS << " }\n }\n return MCOperandNum;\n}\n\n";
1928 OS << "namespace {\n";
1930 // Output the operand conversion kind enum.
1931 OS << "enum OperatorConversionKind {\n";
1932 for (unsigned i = 0, e = OperandConversionKinds.size(); i != e; ++i)
1933 OS << " " << OperandConversionKinds[i] << ",\n";
1934 OS << " CVT_NUM_CONVERTERS\n";
1937 // Output the instruction conversion kind enum.
1938 OS << "enum InstructionConversionKind {\n";
1939 for (SetVector<std::string>::const_iterator
1940 i = InstructionConversionKinds.begin(),
1941 e = InstructionConversionKinds.end(); i != e; ++i)
1942 OS << " " << *i << ",\n";
1943 OS << " CVT_NUM_SIGNATURES\n";
1947 OS << "} // end anonymous namespace\n\n";
1949 // Output the conversion table.
1950 OS << "static uint8_t ConversionTable[CVT_NUM_SIGNATURES]["
1951 << MaxRowLength << "] = {\n";
1953 for (unsigned Row = 0, ERow = ConversionTable.size(); Row != ERow; ++Row) {
1954 assert(ConversionTable[Row].size() % 2 == 0 && "bad conversion row!");
1955 OS << " // " << InstructionConversionKinds[Row] << "\n";
1957 for (unsigned i = 0, e = ConversionTable[Row].size(); i != e; i += 2)
1958 OS << OperandConversionKinds[ConversionTable[Row][i]] << ", "
1959 << (unsigned)(ConversionTable[Row][i + 1]) << ", ";
1960 OS << "CVT_Done },\n";
1965 // Spit out the conversion driver function.
1968 // Spit out the operand number lookup function.
1972 /// emitMatchClassEnumeration - Emit the enumeration for match class kinds.
1973 static void emitMatchClassEnumeration(CodeGenTarget &Target,
1974 std::vector<ClassInfo*> &Infos,
1976 OS << "namespace {\n\n";
1978 OS << "/// MatchClassKind - The kinds of classes which participate in\n"
1979 << "/// instruction matching.\n";
1980 OS << "enum MatchClassKind {\n";
1981 OS << " InvalidMatchClass = 0,\n";
1982 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1983 ie = Infos.end(); it != ie; ++it) {
1984 ClassInfo &CI = **it;
1985 OS << " " << CI.Name << ", // ";
1986 if (CI.Kind == ClassInfo::Token) {
1987 OS << "'" << CI.ValueName << "'\n";
1988 } else if (CI.isRegisterClass()) {
1989 if (!CI.ValueName.empty())
1990 OS << "register class '" << CI.ValueName << "'\n";
1992 OS << "derived register class\n";
1994 OS << "user defined class '" << CI.ValueName << "'\n";
1997 OS << " NumMatchClassKinds\n";
2003 /// emitValidateOperandClass - Emit the function to validate an operand class.
2004 static void emitValidateOperandClass(AsmMatcherInfo &Info,
2006 OS << "static unsigned validateOperandClass(MCParsedAsmOperand *GOp, "
2007 << "MatchClassKind Kind) {\n";
2008 OS << " " << Info.Target.getName() << "Operand &Operand = *("
2009 << Info.Target.getName() << "Operand*)GOp;\n";
2011 // The InvalidMatchClass is not to match any operand.
2012 OS << " if (Kind == InvalidMatchClass)\n";
2013 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n\n";
2015 // Check for Token operands first.
2016 // FIXME: Use a more specific diagnostic type.
2017 OS << " if (Operand.isToken())\n";
2018 OS << " return isSubclass(matchTokenString(Operand.getToken()), Kind) ?\n"
2019 << " MCTargetAsmParser::Match_Success :\n"
2020 << " MCTargetAsmParser::Match_InvalidOperand;\n\n";
2022 // Check the user classes. We don't care what order since we're only
2023 // actually matching against one of them.
2024 for (std::vector<ClassInfo*>::iterator it = Info.Classes.begin(),
2025 ie = Info.Classes.end(); it != ie; ++it) {
2026 ClassInfo &CI = **it;
2028 if (!CI.isUserClass())
2031 OS << " // '" << CI.ClassName << "' class\n";
2032 OS << " if (Kind == " << CI.Name << ") {\n";
2033 OS << " if (Operand." << CI.PredicateMethod << "())\n";
2034 OS << " return MCTargetAsmParser::Match_Success;\n";
2035 if (!CI.DiagnosticType.empty())
2036 OS << " return " << Info.Target.getName() << "AsmParser::Match_"
2037 << CI.DiagnosticType << ";\n";
2041 // Check for register operands, including sub-classes.
2042 OS << " if (Operand.isReg()) {\n";
2043 OS << " MatchClassKind OpKind;\n";
2044 OS << " switch (Operand.getReg()) {\n";
2045 OS << " default: OpKind = InvalidMatchClass; break;\n";
2046 for (std::map<Record*, ClassInfo*>::iterator
2047 it = Info.RegisterClasses.begin(), ie = Info.RegisterClasses.end();
2049 OS << " case " << Info.Target.getName() << "::"
2050 << it->first->getName() << ": OpKind = " << it->second->Name
2053 OS << " return isSubclass(OpKind, Kind) ? "
2054 << "MCTargetAsmParser::Match_Success :\n "
2055 << " MCTargetAsmParser::Match_InvalidOperand;\n }\n\n";
2057 // Generic fallthrough match failure case for operands that don't have
2058 // specialized diagnostic types.
2059 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n";
2063 /// emitIsSubclass - Emit the subclass predicate function.
2064 static void emitIsSubclass(CodeGenTarget &Target,
2065 std::vector<ClassInfo*> &Infos,
2067 OS << "/// isSubclass - Compute whether \\p A is a subclass of \\p B.\n";
2068 OS << "static bool isSubclass(MatchClassKind A, MatchClassKind B) {\n";
2069 OS << " if (A == B)\n";
2070 OS << " return true;\n\n";
2072 OS << " switch (A) {\n";
2073 OS << " default:\n";
2074 OS << " return false;\n";
2075 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
2076 ie = Infos.end(); it != ie; ++it) {
2077 ClassInfo &A = **it;
2079 std::vector<StringRef> SuperClasses;
2080 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
2081 ie = Infos.end(); it != ie; ++it) {
2082 ClassInfo &B = **it;
2084 if (&A != &B && A.isSubsetOf(B))
2085 SuperClasses.push_back(B.Name);
2088 if (SuperClasses.empty())
2091 OS << "\n case " << A.Name << ":\n";
2093 if (SuperClasses.size() == 1) {
2094 OS << " return B == " << SuperClasses.back() << ";\n";
2098 OS << " switch (B) {\n";
2099 OS << " default: return false;\n";
2100 for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i)
2101 OS << " case " << SuperClasses[i] << ": return true;\n";
2108 /// emitMatchTokenString - Emit the function to match a token string to the
2109 /// appropriate match class value.
2110 static void emitMatchTokenString(CodeGenTarget &Target,
2111 std::vector<ClassInfo*> &Infos,
2113 // Construct the match list.
2114 std::vector<StringMatcher::StringPair> Matches;
2115 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
2116 ie = Infos.end(); it != ie; ++it) {
2117 ClassInfo &CI = **it;
2119 if (CI.Kind == ClassInfo::Token)
2120 Matches.push_back(StringMatcher::StringPair(CI.ValueName,
2121 "return " + CI.Name + ";"));
2124 OS << "static MatchClassKind matchTokenString(StringRef Name) {\n";
2126 StringMatcher("Name", Matches, OS).Emit();
2128 OS << " return InvalidMatchClass;\n";
2132 /// emitMatchRegisterName - Emit the function to match a string to the target
2133 /// specific register enum.
2134 static void emitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
2136 // Construct the match list.
2137 std::vector<StringMatcher::StringPair> Matches;
2138 const std::vector<CodeGenRegister*> &Regs =
2139 Target.getRegBank().getRegisters();
2140 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
2141 const CodeGenRegister *Reg = Regs[i];
2142 if (Reg->TheDef->getValueAsString("AsmName").empty())
2145 Matches.push_back(StringMatcher::StringPair(
2146 Reg->TheDef->getValueAsString("AsmName"),
2147 "return " + utostr(Reg->EnumValue) + ";"));
2150 OS << "static unsigned MatchRegisterName(StringRef Name) {\n";
2152 StringMatcher("Name", Matches, OS).Emit();
2154 OS << " return 0;\n";
2158 /// emitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag
2160 static void emitSubtargetFeatureFlagEnumeration(AsmMatcherInfo &Info,
2162 OS << "// Flags for subtarget features that participate in "
2163 << "instruction matching.\n";
2164 OS << "enum SubtargetFeatureFlag {\n";
2165 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
2166 it = Info.SubtargetFeatures.begin(),
2167 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
2168 SubtargetFeatureInfo &SFI = *it->second;
2169 OS << " " << SFI.getEnumName() << " = (1 << " << SFI.Index << "),\n";
2171 OS << " Feature_None = 0\n";
2175 /// emitOperandDiagnosticTypes - Emit the operand matching diagnostic types.
2176 static void emitOperandDiagnosticTypes(AsmMatcherInfo &Info, raw_ostream &OS) {
2177 // Get the set of diagnostic types from all of the operand classes.
2178 std::set<StringRef> Types;
2179 for (std::map<Record*, ClassInfo*>::const_iterator
2180 I = Info.AsmOperandClasses.begin(),
2181 E = Info.AsmOperandClasses.end(); I != E; ++I) {
2182 if (!I->second->DiagnosticType.empty())
2183 Types.insert(I->second->DiagnosticType);
2186 if (Types.empty()) return;
2188 // Now emit the enum entries.
2189 for (std::set<StringRef>::const_iterator I = Types.begin(), E = Types.end();
2191 OS << " Match_" << *I << ",\n";
2192 OS << " END_OPERAND_DIAGNOSTIC_TYPES\n";
2195 /// emitGetSubtargetFeatureName - Emit the helper function to get the
2196 /// user-level name for a subtarget feature.
2197 static void emitGetSubtargetFeatureName(AsmMatcherInfo &Info, raw_ostream &OS) {
2198 OS << "// User-level names for subtarget features that participate in\n"
2199 << "// instruction matching.\n"
2200 << "static const char *getSubtargetFeatureName(unsigned Val) {\n"
2201 << " switch(Val) {\n";
2202 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
2203 it = Info.SubtargetFeatures.begin(),
2204 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
2205 SubtargetFeatureInfo &SFI = *it->second;
2206 // FIXME: Totally just a placeholder name to get the algorithm working.
2207 OS << " case " << SFI.getEnumName() << ": return \""
2208 << SFI.TheDef->getValueAsString("PredicateName") << "\";\n";
2210 OS << " default: return \"(unknown)\";\n";
2214 /// emitComputeAvailableFeatures - Emit the function to compute the list of
2215 /// available features given a subtarget.
2216 static void emitComputeAvailableFeatures(AsmMatcherInfo &Info,
2218 std::string ClassName =
2219 Info.AsmParser->getValueAsString("AsmParserClassName");
2221 OS << "unsigned " << Info.Target.getName() << ClassName << "::\n"
2222 << "ComputeAvailableFeatures(uint64_t FB) const {\n";
2223 OS << " unsigned Features = 0;\n";
2224 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
2225 it = Info.SubtargetFeatures.begin(),
2226 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
2227 SubtargetFeatureInfo &SFI = *it->second;
2230 std::string CondStorage =
2231 SFI.TheDef->getValueAsString("AssemblerCondString");
2232 StringRef Conds = CondStorage;
2233 std::pair<StringRef,StringRef> Comma = Conds.split(',');
2240 StringRef Cond = Comma.first;
2241 if (Cond[0] == '!') {
2243 Cond = Cond.substr(1);
2246 OS << "((FB & " << Info.Target.getName() << "::" << Cond << ")";
2253 if (Comma.second.empty())
2257 Comma = Comma.second.split(',');
2261 OS << " Features |= " << SFI.getEnumName() << ";\n";
2263 OS << " return Features;\n";
2267 static std::string GetAliasRequiredFeatures(Record *R,
2268 const AsmMatcherInfo &Info) {
2269 std::vector<Record*> ReqFeatures = R->getValueAsListOfDefs("Predicates");
2271 unsigned NumFeatures = 0;
2272 for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) {
2273 SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]);
2276 throw TGError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() +
2277 "' is not marked as an AssemblerPredicate!");
2282 Result += F->getEnumName();
2286 if (NumFeatures > 1)
2287 Result = '(' + Result + ')';
2291 /// emitMnemonicAliases - If the target has any MnemonicAlias<> definitions,
2292 /// emit a function for them and return true, otherwise return false.
2293 static bool emitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info) {
2294 // Ignore aliases when match-prefix is set.
2295 if (!MatchPrefix.empty())
2298 std::vector<Record*> Aliases =
2299 Info.getRecords().getAllDerivedDefinitions("MnemonicAlias");
2300 if (Aliases.empty()) return false;
2302 OS << "static void applyMnemonicAliases(StringRef &Mnemonic, "
2303 "unsigned Features) {\n";
2305 // Keep track of all the aliases from a mnemonic. Use an std::map so that the
2306 // iteration order of the map is stable.
2307 std::map<std::string, std::vector<Record*> > AliasesFromMnemonic;
2309 for (unsigned i = 0, e = Aliases.size(); i != e; ++i) {
2310 Record *R = Aliases[i];
2311 AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R);
2314 // Process each alias a "from" mnemonic at a time, building the code executed
2315 // by the string remapper.
2316 std::vector<StringMatcher::StringPair> Cases;
2317 for (std::map<std::string, std::vector<Record*> >::iterator
2318 I = AliasesFromMnemonic.begin(), E = AliasesFromMnemonic.end();
2320 const std::vector<Record*> &ToVec = I->second;
2322 // Loop through each alias and emit code that handles each case. If there
2323 // are two instructions without predicates, emit an error. If there is one,
2325 std::string MatchCode;
2326 int AliasWithNoPredicate = -1;
2328 for (unsigned i = 0, e = ToVec.size(); i != e; ++i) {
2329 Record *R = ToVec[i];
2330 std::string FeatureMask = GetAliasRequiredFeatures(R, Info);
2332 // If this unconditionally matches, remember it for later and diagnose
2334 if (FeatureMask.empty()) {
2335 if (AliasWithNoPredicate != -1) {
2336 // We can't have two aliases from the same mnemonic with no predicate.
2337 PrintError(ToVec[AliasWithNoPredicate]->getLoc(),
2338 "two MnemonicAliases with the same 'from' mnemonic!");
2339 throw TGError(R->getLoc(), "this is the other MnemonicAlias.");
2342 AliasWithNoPredicate = i;
2345 if (R->getValueAsString("ToMnemonic") == I->first)
2346 throw TGError(R->getLoc(), "MnemonicAlias to the same string");
2348 if (!MatchCode.empty())
2349 MatchCode += "else ";
2350 MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n";
2351 MatchCode += " Mnemonic = \"" +R->getValueAsString("ToMnemonic")+"\";\n";
2354 if (AliasWithNoPredicate != -1) {
2355 Record *R = ToVec[AliasWithNoPredicate];
2356 if (!MatchCode.empty())
2357 MatchCode += "else\n ";
2358 MatchCode += "Mnemonic = \"" + R->getValueAsString("ToMnemonic")+"\";\n";
2361 MatchCode += "return;";
2363 Cases.push_back(std::make_pair(I->first, MatchCode));
2366 StringMatcher("Mnemonic", Cases, OS).Emit();
2372 static const char *getMinimalTypeForRange(uint64_t Range) {
2373 assert(Range < 0xFFFFFFFFULL && "Enum too large");
2381 static void emitCustomOperandParsing(raw_ostream &OS, CodeGenTarget &Target,
2382 const AsmMatcherInfo &Info, StringRef ClassName) {
2383 // Emit the static custom operand parsing table;
2384 OS << "namespace {\n";
2385 OS << " struct OperandMatchEntry {\n";
2386 OS << " static const char *const MnemonicTable;\n";
2387 OS << " uint32_t OperandMask;\n";
2388 OS << " uint32_t Mnemonic;\n";
2389 OS << " " << getMinimalTypeForRange(1ULL << Info.SubtargetFeatures.size())
2390 << " RequiredFeatures;\n";
2391 OS << " " << getMinimalTypeForRange(Info.Classes.size())
2393 OS << " StringRef getMnemonic() const {\n";
2394 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2395 OS << " MnemonicTable[Mnemonic]);\n";
2399 OS << " // Predicate for searching for an opcode.\n";
2400 OS << " struct LessOpcodeOperand {\n";
2401 OS << " bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {\n";
2402 OS << " return LHS.getMnemonic() < RHS;\n";
2404 OS << " bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {\n";
2405 OS << " return LHS < RHS.getMnemonic();\n";
2407 OS << " bool operator()(const OperandMatchEntry &LHS,";
2408 OS << " const OperandMatchEntry &RHS) {\n";
2409 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2413 OS << "} // end anonymous namespace.\n\n";
2415 StringToOffsetTable StringTable;
2417 OS << "static const OperandMatchEntry OperandMatchTable["
2418 << Info.OperandMatchInfo.size() << "] = {\n";
2420 OS << " /* Operand List Mask, Mnemonic, Operand Class, Features */\n";
2421 for (std::vector<OperandMatchEntry>::const_iterator it =
2422 Info.OperandMatchInfo.begin(), ie = Info.OperandMatchInfo.end();
2424 const OperandMatchEntry &OMI = *it;
2425 const MatchableInfo &II = *OMI.MI;
2427 OS << " { " << OMI.OperandMask;
2430 bool printComma = false;
2431 for (int i = 0, e = 31; i !=e; ++i)
2432 if (OMI.OperandMask & (1 << i)) {
2440 // Store a pascal-style length byte in the mnemonic.
2441 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2442 OS << ", " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2443 << " /* " << II.Mnemonic << " */, ";
2445 // Write the required features mask.
2446 if (!II.RequiredFeatures.empty()) {
2447 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
2449 OS << II.RequiredFeatures[i]->getEnumName();
2454 OS << ", " << OMI.CI->Name;
2460 OS << "const char *const OperandMatchEntry::MnemonicTable =\n";
2461 StringTable.EmitString(OS);
2464 // Emit the operand class switch to call the correct custom parser for
2465 // the found operand class.
2466 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
2467 << Target.getName() << ClassName << "::\n"
2468 << "tryCustomParseOperand(SmallVectorImpl<MCParsedAsmOperand*>"
2469 << " &Operands,\n unsigned MCK) {\n\n"
2470 << " switch(MCK) {\n";
2472 for (std::vector<ClassInfo*>::const_iterator it = Info.Classes.begin(),
2473 ie = Info.Classes.end(); it != ie; ++it) {
2474 ClassInfo *CI = *it;
2475 if (CI->ParserMethod.empty())
2477 OS << " case " << CI->Name << ":\n"
2478 << " return " << CI->ParserMethod << "(Operands);\n";
2481 OS << " default:\n";
2482 OS << " return MatchOperand_NoMatch;\n";
2484 OS << " return MatchOperand_NoMatch;\n";
2487 // Emit the static custom operand parser. This code is very similar with
2488 // the other matcher. Also use MatchResultTy here just in case we go for
2489 // a better error handling.
2490 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
2491 << Target.getName() << ClassName << "::\n"
2492 << "MatchOperandParserImpl(SmallVectorImpl<MCParsedAsmOperand*>"
2493 << " &Operands,\n StringRef Mnemonic) {\n";
2495 // Emit code to get the available features.
2496 OS << " // Get the current feature set.\n";
2497 OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n";
2499 OS << " // Get the next operand index.\n";
2500 OS << " unsigned NextOpNum = Operands.size()-1;\n";
2502 // Emit code to search the table.
2503 OS << " // Search the table.\n";
2504 OS << " std::pair<const OperandMatchEntry*, const OperandMatchEntry*>";
2505 OS << " MnemonicRange =\n";
2506 OS << " std::equal_range(OperandMatchTable, OperandMatchTable+"
2507 << Info.OperandMatchInfo.size() << ", Mnemonic,\n"
2508 << " LessOpcodeOperand());\n\n";
2510 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2511 OS << " return MatchOperand_NoMatch;\n\n";
2513 OS << " for (const OperandMatchEntry *it = MnemonicRange.first,\n"
2514 << " *ie = MnemonicRange.second; it != ie; ++it) {\n";
2516 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2517 OS << " assert(Mnemonic == it->getMnemonic());\n\n";
2519 // Emit check that the required features are available.
2520 OS << " // check if the available features match\n";
2521 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2522 << "!= it->RequiredFeatures) {\n";
2523 OS << " continue;\n";
2526 // Emit check to ensure the operand number matches.
2527 OS << " // check if the operand in question has a custom parser.\n";
2528 OS << " if (!(it->OperandMask & (1 << NextOpNum)))\n";
2529 OS << " continue;\n\n";
2531 // Emit call to the custom parser method
2532 OS << " // call custom parse method to handle the operand\n";
2533 OS << " OperandMatchResultTy Result = ";
2534 OS << "tryCustomParseOperand(Operands, it->Class);\n";
2535 OS << " if (Result != MatchOperand_NoMatch)\n";
2536 OS << " return Result;\n";
2539 OS << " // Okay, we had no match.\n";
2540 OS << " return MatchOperand_NoMatch;\n";
2544 void AsmMatcherEmitter::run(raw_ostream &OS) {
2545 CodeGenTarget Target(Records);
2546 Record *AsmParser = Target.getAsmParser();
2547 std::string ClassName = AsmParser->getValueAsString("AsmParserClassName");
2549 // Compute the information on the instructions to match.
2550 AsmMatcherInfo Info(AsmParser, Target, Records);
2553 // Sort the instruction table using the partial order on classes. We use
2554 // stable_sort to ensure that ambiguous instructions are still
2555 // deterministically ordered.
2556 std::stable_sort(Info.Matchables.begin(), Info.Matchables.end(),
2557 less_ptr<MatchableInfo>());
2559 DEBUG_WITH_TYPE("instruction_info", {
2560 for (std::vector<MatchableInfo*>::iterator
2561 it = Info.Matchables.begin(), ie = Info.Matchables.end();
2566 // Check for ambiguous matchables.
2567 DEBUG_WITH_TYPE("ambiguous_instrs", {
2568 unsigned NumAmbiguous = 0;
2569 for (unsigned i = 0, e = Info.Matchables.size(); i != e; ++i) {
2570 for (unsigned j = i + 1; j != e; ++j) {
2571 MatchableInfo &A = *Info.Matchables[i];
2572 MatchableInfo &B = *Info.Matchables[j];
2574 if (A.couldMatchAmbiguouslyWith(B)) {
2575 errs() << "warning: ambiguous matchables:\n";
2577 errs() << "\nis incomparable with:\n";
2585 errs() << "warning: " << NumAmbiguous
2586 << " ambiguous matchables!\n";
2589 // Compute the information on the custom operand parsing.
2590 Info.buildOperandMatchInfo();
2592 // Write the output.
2594 // Information for the class declaration.
2595 OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
2596 OS << "#undef GET_ASSEMBLER_HEADER\n";
2597 OS << " // This should be included into the middle of the declaration of\n";
2598 OS << " // your subclasses implementation of MCTargetAsmParser.\n";
2599 OS << " unsigned ComputeAvailableFeatures(uint64_t FeatureBits) const;\n";
2600 OS << " void convertToMCInst(unsigned Kind, MCInst &Inst, "
2601 << "unsigned Opcode,\n"
2602 << " const SmallVectorImpl<MCParsedAsmOperand*> "
2604 OS << " unsigned getMCInstOperandNumImpl(unsigned Kind, MCInst &Inst,\n "
2606 << "SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n "
2607 << " unsigned OperandNum, unsigned &NumMCOperands);\n";
2608 OS << " bool MnemonicIsValid(StringRef Mnemonic);\n";
2609 OS << " unsigned MatchInstructionImpl(\n"
2610 << " const SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n"
2611 << " unsigned &Kind, MCInst &Inst, "
2612 << "unsigned &ErrorInfo,\n unsigned VariantID = 0);\n";
2614 if (Info.OperandMatchInfo.size()) {
2615 OS << "\n enum OperandMatchResultTy {\n";
2616 OS << " MatchOperand_Success, // operand matched successfully\n";
2617 OS << " MatchOperand_NoMatch, // operand did not match\n";
2618 OS << " MatchOperand_ParseFail // operand matched but had errors\n";
2620 OS << " OperandMatchResultTy MatchOperandParserImpl(\n";
2621 OS << " SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n";
2622 OS << " StringRef Mnemonic);\n";
2624 OS << " OperandMatchResultTy tryCustomParseOperand(\n";
2625 OS << " SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n";
2626 OS << " unsigned MCK);\n\n";
2629 OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n";
2631 // Emit the operand match diagnostic enum names.
2632 OS << "\n#ifdef GET_OPERAND_DIAGNOSTIC_TYPES\n";
2633 OS << "#undef GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
2634 emitOperandDiagnosticTypes(Info, OS);
2635 OS << "#endif // GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
2638 OS << "\n#ifdef GET_REGISTER_MATCHER\n";
2639 OS << "#undef GET_REGISTER_MATCHER\n\n";
2641 // Emit the subtarget feature enumeration.
2642 emitSubtargetFeatureFlagEnumeration(Info, OS);
2644 // Emit the function to match a register name to number.
2645 // This should be omitted for Mips target
2646 if (AsmParser->getValueAsBit("ShouldEmitMatchRegisterName"))
2647 emitMatchRegisterName(Target, AsmParser, OS);
2649 OS << "#endif // GET_REGISTER_MATCHER\n\n";
2651 OS << "\n#ifdef GET_SUBTARGET_FEATURE_NAME\n";
2652 OS << "#undef GET_SUBTARGET_FEATURE_NAME\n\n";
2654 // Generate the helper function to get the names for subtarget features.
2655 emitGetSubtargetFeatureName(Info, OS);
2657 OS << "#endif // GET_SUBTARGET_FEATURE_NAME\n\n";
2659 OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
2660 OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
2662 // Generate the function that remaps for mnemonic aliases.
2663 bool HasMnemonicAliases = emitMnemonicAliases(OS, Info);
2665 // Generate the unified function to convert operands into an MCInst.
2666 emitConvertToMCInst(Target, ClassName, Info.Matchables, OS);
2668 // Emit the enumeration for classes which participate in matching.
2669 emitMatchClassEnumeration(Target, Info.Classes, OS);
2671 // Emit the routine to match token strings to their match class.
2672 emitMatchTokenString(Target, Info.Classes, OS);
2674 // Emit the subclass predicate routine.
2675 emitIsSubclass(Target, Info.Classes, OS);
2677 // Emit the routine to validate an operand against a match class.
2678 emitValidateOperandClass(Info, OS);
2680 // Emit the available features compute function.
2681 emitComputeAvailableFeatures(Info, OS);
2684 size_t MaxNumOperands = 0;
2685 for (std::vector<MatchableInfo*>::const_iterator it =
2686 Info.Matchables.begin(), ie = Info.Matchables.end();
2688 MaxNumOperands = std::max(MaxNumOperands, (*it)->AsmOperands.size());
2690 // Emit the static match table; unused classes get initalized to 0 which is
2691 // guaranteed to be InvalidMatchClass.
2693 // FIXME: We can reduce the size of this table very easily. First, we change
2694 // it so that store the kinds in separate bit-fields for each index, which
2695 // only needs to be the max width used for classes at that index (we also need
2696 // to reject based on this during classification). If we then make sure to
2697 // order the match kinds appropriately (putting mnemonics last), then we
2698 // should only end up using a few bits for each class, especially the ones
2699 // following the mnemonic.
2700 OS << "namespace {\n";
2701 OS << " struct MatchEntry {\n";
2702 OS << " static const char *const MnemonicTable;\n";
2703 OS << " uint32_t Mnemonic;\n";
2704 OS << " uint16_t Opcode;\n";
2705 OS << " " << getMinimalTypeForRange(Info.Matchables.size())
2707 OS << " " << getMinimalTypeForRange(1ULL << Info.SubtargetFeatures.size())
2708 << " RequiredFeatures;\n";
2709 OS << " " << getMinimalTypeForRange(Info.Classes.size())
2710 << " Classes[" << MaxNumOperands << "];\n";
2711 OS << " uint8_t AsmVariantID;\n\n";
2712 OS << " StringRef getMnemonic() const {\n";
2713 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2714 OS << " MnemonicTable[Mnemonic]);\n";
2718 OS << " // Predicate for searching for an opcode.\n";
2719 OS << " struct LessOpcode {\n";
2720 OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n";
2721 OS << " return LHS.getMnemonic() < RHS;\n";
2723 OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n";
2724 OS << " return LHS < RHS.getMnemonic();\n";
2726 OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n";
2727 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2731 OS << "} // end anonymous namespace.\n\n";
2733 StringToOffsetTable StringTable;
2735 OS << "static const MatchEntry MatchTable["
2736 << Info.Matchables.size() << "] = {\n";
2738 for (std::vector<MatchableInfo*>::const_iterator it =
2739 Info.Matchables.begin(), ie = Info.Matchables.end();
2741 MatchableInfo &II = **it;
2743 // Store a pascal-style length byte in the mnemonic.
2744 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2745 OS << " { " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2746 << " /* " << II.Mnemonic << " */, "
2747 << Target.getName() << "::"
2748 << II.getResultInst()->TheDef->getName() << ", "
2749 << II.ConversionFnKind << ", ";
2751 // Write the required features mask.
2752 if (!II.RequiredFeatures.empty()) {
2753 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
2755 OS << II.RequiredFeatures[i]->getEnumName();
2761 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) {
2762 MatchableInfo::AsmOperand &Op = II.AsmOperands[i];
2765 OS << Op.Class->Name;
2767 OS << " }, " << II.AsmVariantID;
2773 OS << "const char *const MatchEntry::MnemonicTable =\n";
2774 StringTable.EmitString(OS);
2777 // A method to determine if a mnemonic is in the list.
2778 OS << "bool " << Target.getName() << ClassName << "::\n"
2779 << "MnemonicIsValid(StringRef Mnemonic) {\n";
2780 OS << " // Search the table.\n";
2781 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
2782 OS << " std::equal_range(MatchTable, MatchTable+"
2783 << Info.Matchables.size() << ", Mnemonic, LessOpcode());\n";
2784 OS << " return MnemonicRange.first != MnemonicRange.second;\n";
2787 // Finally, build the match function.
2789 << Target.getName() << ClassName << "::\n"
2790 << "MatchInstructionImpl(const SmallVectorImpl<MCParsedAsmOperand*>"
2792 OS << " unsigned &Kind, MCInst &Inst, unsigned ";
2793 OS << "&ErrorInfo,\n unsigned VariantID) {\n";
2795 OS << " // Eliminate obvious mismatches.\n";
2796 OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n";
2797 OS << " ErrorInfo = " << (MaxNumOperands+1) << ";\n";
2798 OS << " return Match_InvalidOperand;\n";
2801 // Emit code to get the available features.
2802 OS << " // Get the current feature set.\n";
2803 OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n";
2805 OS << " // Get the instruction mnemonic, which is the first token.\n";
2806 OS << " StringRef Mnemonic = ((" << Target.getName()
2807 << "Operand*)Operands[0])->getToken();\n\n";
2809 if (HasMnemonicAliases) {
2810 OS << " // Process all MnemonicAliases to remap the mnemonic.\n";
2811 OS << " // FIXME : Add an entry in AsmParserVariant to check this.\n";
2812 OS << " if (!VariantID)\n";
2813 OS << " applyMnemonicAliases(Mnemonic, AvailableFeatures);\n\n";
2816 // Emit code to compute the class list for this operand vector.
2817 OS << " // Some state to try to produce better error messages.\n";
2818 OS << " bool HadMatchOtherThanFeatures = false;\n";
2819 OS << " bool HadMatchOtherThanPredicate = false;\n";
2820 OS << " unsigned RetCode = Match_InvalidOperand;\n";
2821 OS << " unsigned MissingFeatures = ~0U;\n";
2822 OS << " // Set ErrorInfo to the operand that mismatches if it is\n";
2823 OS << " // wrong for all instances of the instruction.\n";
2824 OS << " ErrorInfo = ~0U;\n";
2826 // Emit code to search the table.
2827 OS << " // Search the table.\n";
2828 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
2829 OS << " std::equal_range(MatchTable, MatchTable+"
2830 << Info.Matchables.size() << ", Mnemonic, LessOpcode());\n\n";
2832 OS << " // Return a more specific error code if no mnemonics match.\n";
2833 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2834 OS << " return Match_MnemonicFail;\n\n";
2836 OS << " for (const MatchEntry *it = MnemonicRange.first, "
2837 << "*ie = MnemonicRange.second;\n";
2838 OS << " it != ie; ++it) {\n";
2840 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2841 OS << " assert(Mnemonic == it->getMnemonic());\n";
2843 // Emit check that the subclasses match.
2844 OS << " if (VariantID != it->AsmVariantID) continue;\n";
2845 OS << " bool OperandsValid = true;\n";
2846 OS << " for (unsigned i = 0; i != " << MaxNumOperands << "; ++i) {\n";
2847 OS << " if (i + 1 >= Operands.size()) {\n";
2848 OS << " OperandsValid = (it->Classes[i] == " <<"InvalidMatchClass);\n";
2849 OS << " if (!OperandsValid) ErrorInfo = i + 1;\n";
2852 OS << " unsigned Diag = validateOperandClass(Operands[i+1],\n";
2854 OS << "(MatchClassKind)it->Classes[i]);\n";
2855 OS << " if (Diag == Match_Success)\n";
2856 OS << " continue;\n";
2857 OS << " // If this operand is broken for all of the instances of this\n";
2858 OS << " // mnemonic, keep track of it so we can report loc info.\n";
2859 OS << " // If we already had a match that only failed due to a\n";
2860 OS << " // target predicate, that diagnostic is preferred.\n";
2861 OS << " if (!HadMatchOtherThanPredicate &&\n";
2862 OS << " (it == MnemonicRange.first || ErrorInfo <= i+1)) {\n";
2863 OS << " ErrorInfo = i+1;\n";
2864 OS << " // InvalidOperand is the default. Prefer specificity.\n";
2865 OS << " if (Diag != Match_InvalidOperand)\n";
2866 OS << " RetCode = Diag;\n";
2868 OS << " // Otherwise, just reject this instance of the mnemonic.\n";
2869 OS << " OperandsValid = false;\n";
2873 OS << " if (!OperandsValid) continue;\n";
2875 // Emit check that the required features are available.
2876 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2877 << "!= it->RequiredFeatures) {\n";
2878 OS << " HadMatchOtherThanFeatures = true;\n";
2879 OS << " unsigned NewMissingFeatures = it->RequiredFeatures & "
2880 "~AvailableFeatures;\n";
2881 OS << " if (CountPopulation_32(NewMissingFeatures) <=\n"
2882 " CountPopulation_32(MissingFeatures))\n";
2883 OS << " MissingFeatures = NewMissingFeatures;\n";
2884 OS << " continue;\n";
2887 OS << " // We have selected a definite instruction, convert the parsed\n"
2888 << " // operands into the appropriate MCInst.\n";
2889 OS << " convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n";
2892 // Verify the instruction with the target-specific match predicate function.
2893 OS << " // We have a potential match. Check the target predicate to\n"
2894 << " // handle any context sensitive constraints.\n"
2895 << " unsigned MatchResult;\n"
2896 << " if ((MatchResult = checkTargetMatchPredicate(Inst)) !="
2897 << " Match_Success) {\n"
2898 << " Inst.clear();\n"
2899 << " RetCode = MatchResult;\n"
2900 << " HadMatchOtherThanPredicate = true;\n"
2904 // Call the post-processing function, if used.
2905 std::string InsnCleanupFn =
2906 AsmParser->getValueAsString("AsmParserInstCleanup");
2907 if (!InsnCleanupFn.empty())
2908 OS << " " << InsnCleanupFn << "(Inst);\n";
2910 OS << " Kind = it->ConvertFn;\n";
2911 OS << " return Match_Success;\n";
2914 OS << " // Okay, we had no match. Try to return a useful error code.\n";
2915 OS << " if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)\n";
2916 OS << " return RetCode;\n\n";
2917 OS << " // Missing feature matches return which features were missing\n";
2918 OS << " ErrorInfo = MissingFeatures;\n";
2919 OS << " return Match_MissingFeature;\n";
2922 if (Info.OperandMatchInfo.size())
2923 emitCustomOperandParsing(OS, Target, Info, ClassName);
2925 OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";
2930 void EmitAsmMatcher(RecordKeeper &RK, raw_ostream &OS) {
2931 emitSourceFileHeader("Assembly Matcher Source Fragment", OS);
2932 AsmMatcherEmitter(RK).run(OS);
2935 } // End llvm namespace