1 //===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits a target specifier matcher for converting parsed
11 // assembly operands in the MCInst structures. It also emits a matcher for
12 // custom operand parsing.
14 // Converting assembly operands into MCInst structures
15 // ---------------------------------------------------
17 // The input to the target specific matcher is a list of literal tokens and
18 // operands. The target specific parser should generally eliminate any syntax
19 // which is not relevant for matching; for example, comma tokens should have
20 // already been consumed and eliminated by the parser. Most instructions will
21 // end up with a single literal token (the instruction name) and some number of
24 // Some example inputs, for X86:
25 // 'addl' (immediate ...) (register ...)
26 // 'add' (immediate ...) (memory ...)
29 // The assembly matcher is responsible for converting this input into a precise
30 // machine instruction (i.e., an instruction with a well defined encoding). This
31 // mapping has several properties which complicate matching:
33 // - It may be ambiguous; many architectures can legally encode particular
34 // variants of an instruction in different ways (for example, using a smaller
35 // encoding for small immediates). Such ambiguities should never be
36 // arbitrarily resolved by the assembler, the assembler is always responsible
37 // for choosing the "best" available instruction.
39 // - It may depend on the subtarget or the assembler context. Instructions
40 // which are invalid for the current mode, but otherwise unambiguous (e.g.,
41 // an SSE instruction in a file being assembled for i486) should be accepted
42 // and rejected by the assembler front end. However, if the proper encoding
43 // for an instruction is dependent on the assembler context then the matcher
44 // is responsible for selecting the correct machine instruction for the
47 // The core matching algorithm attempts to exploit the regularity in most
48 // instruction sets to quickly determine the set of possibly matching
49 // instructions, and the simplify the generated code. Additionally, this helps
50 // to ensure that the ambiguities are intentionally resolved by the user.
52 // The matching is divided into two distinct phases:
54 // 1. Classification: Each operand is mapped to the unique set which (a)
55 // contains it, and (b) is the largest such subset for which a single
56 // instruction could match all members.
58 // For register classes, we can generate these subgroups automatically. For
59 // arbitrary operands, we expect the user to define the classes and their
60 // relations to one another (for example, 8-bit signed immediates as a
61 // subset of 32-bit immediates).
63 // By partitioning the operands in this way, we guarantee that for any
64 // tuple of classes, any single instruction must match either all or none
65 // of the sets of operands which could classify to that tuple.
67 // In addition, the subset relation amongst classes induces a partial order
68 // on such tuples, which we use to resolve ambiguities.
70 // 2. The input can now be treated as a tuple of classes (static tokens are
71 // simple singleton sets). Each such tuple should generally map to a single
72 // instruction (we currently ignore cases where this isn't true, whee!!!),
73 // which we can emit a simple matcher for.
75 // Custom Operand Parsing
76 // ----------------------
78 // Some targets need a custom way to parse operands, some specific instructions
79 // can contain arguments that can represent processor flags and other kinds of
80 // identifiers that need to be mapped to specific values in the final encoded
81 // instructions. The target specific custom operand parsing works in the
84 // 1. A operand match table is built, each entry contains a mnemonic, an
85 // operand class, a mask for all operand positions for that same
86 // class/mnemonic and target features to be checked while trying to match.
88 // 2. The operand matcher will try every possible entry with the same
89 // mnemonic and will check if the target feature for this mnemonic also
90 // matches. After that, if the operand to be matched has its index
91 // present in the mask, a successful match occurs. Otherwise, fallback
92 // to the regular operand parsing.
94 // 3. For a match success, each operand class that has a 'ParserMethod'
95 // becomes part of a switch from where the custom method is called.
97 //===----------------------------------------------------------------------===//
99 #include "CodeGenTarget.h"
100 #include "llvm/ADT/OwningPtr.h"
101 #include "llvm/ADT/PointerUnion.h"
102 #include "llvm/ADT/STLExtras.h"
103 #include "llvm/ADT/SmallPtrSet.h"
104 #include "llvm/ADT/SmallVector.h"
105 #include "llvm/ADT/StringExtras.h"
106 #include "llvm/Support/CommandLine.h"
107 #include "llvm/Support/Debug.h"
108 #include "llvm/Support/ErrorHandling.h"
109 #include "llvm/TableGen/Error.h"
110 #include "llvm/TableGen/Record.h"
111 #include "llvm/TableGen/StringMatcher.h"
112 #include "llvm/TableGen/StringToOffsetTable.h"
113 #include "llvm/TableGen/TableGenBackend.h"
119 using namespace llvm;
121 static cl::opt<std::string>
122 MatchPrefix("match-prefix", cl::init(""),
123 cl::desc("Only match instructions with the given prefix"));
126 class AsmMatcherInfo;
127 struct SubtargetFeatureInfo;
129 // Register sets are used as keys in some second-order sets TableGen creates
130 // when generating its data structures. This means that the order of two
131 // RegisterSets can be seen in the outputted AsmMatcher tables occasionally, and
132 // can even affect compiler output (at least seen in diagnostics produced when
133 // all matches fail). So we use a type that sorts them consistently.
134 typedef std::set<Record*, LessRecordByID> RegisterSet;
136 class AsmMatcherEmitter {
137 RecordKeeper &Records;
139 AsmMatcherEmitter(RecordKeeper &R) : Records(R) {}
141 void run(raw_ostream &o);
144 /// ClassInfo - Helper class for storing the information about a particular
145 /// class of operands which can be matched.
148 /// Invalid kind, for use as a sentinel value.
151 /// The class for a particular token.
154 /// The (first) register class, subsequent register classes are
155 /// RegisterClass0+1, and so on.
158 /// The (first) user defined class, subsequent user defined classes are
159 /// UserClass0+1, and so on.
163 /// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
164 /// N) for the Nth user defined class.
167 /// SuperClasses - The super classes of this class. Note that for simplicities
168 /// sake user operands only record their immediate super class, while register
169 /// operands include all superclasses.
170 std::vector<ClassInfo*> SuperClasses;
172 /// Name - The full class name, suitable for use in an enum.
175 /// ClassName - The unadorned generic name for this class (e.g., Token).
176 std::string ClassName;
178 /// ValueName - The name of the value this class represents; for a token this
179 /// is the literal token string, for an operand it is the TableGen class (or
180 /// empty if this is a derived class).
181 std::string ValueName;
183 /// PredicateMethod - The name of the operand method to test whether the
184 /// operand matches this class; this is not valid for Token or register kinds.
185 std::string PredicateMethod;
187 /// RenderMethod - The name of the operand method to add this operand to an
188 /// MCInst; this is not valid for Token or register kinds.
189 std::string RenderMethod;
191 /// ParserMethod - The name of the operand method to do a target specific
192 /// parsing on the operand.
193 std::string ParserMethod;
195 /// For register classes, the records for all the registers in this class.
196 RegisterSet Registers;
198 /// For custom match classes, he diagnostic kind for when the predicate fails.
199 std::string DiagnosticType;
201 /// isRegisterClass() - Check if this is a register class.
202 bool isRegisterClass() const {
203 return Kind >= RegisterClass0 && Kind < UserClass0;
206 /// isUserClass() - Check if this is a user defined class.
207 bool isUserClass() const {
208 return Kind >= UserClass0;
211 /// isRelatedTo - Check whether this class is "related" to \p RHS. Classes
212 /// are related if they are in the same class hierarchy.
213 bool isRelatedTo(const ClassInfo &RHS) const {
214 // Tokens are only related to tokens.
215 if (Kind == Token || RHS.Kind == Token)
216 return Kind == Token && RHS.Kind == Token;
218 // Registers classes are only related to registers classes, and only if
219 // their intersection is non-empty.
220 if (isRegisterClass() || RHS.isRegisterClass()) {
221 if (!isRegisterClass() || !RHS.isRegisterClass())
225 std::insert_iterator<RegisterSet> II(Tmp, Tmp.begin());
226 std::set_intersection(Registers.begin(), Registers.end(),
227 RHS.Registers.begin(), RHS.Registers.end(),
228 II, LessRecordByID());
233 // Otherwise we have two users operands; they are related if they are in the
234 // same class hierarchy.
236 // FIXME: This is an oversimplification, they should only be related if they
237 // intersect, however we don't have that information.
238 assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");
239 const ClassInfo *Root = this;
240 while (!Root->SuperClasses.empty())
241 Root = Root->SuperClasses.front();
243 const ClassInfo *RHSRoot = &RHS;
244 while (!RHSRoot->SuperClasses.empty())
245 RHSRoot = RHSRoot->SuperClasses.front();
247 return Root == RHSRoot;
250 /// isSubsetOf - Test whether this class is a subset of \p RHS.
251 bool isSubsetOf(const ClassInfo &RHS) const {
252 // This is a subset of RHS if it is the same class...
256 // ... or if any of its super classes are a subset of RHS.
257 for (std::vector<ClassInfo*>::const_iterator it = SuperClasses.begin(),
258 ie = SuperClasses.end(); it != ie; ++it)
259 if ((*it)->isSubsetOf(RHS))
265 /// operator< - Compare two classes.
266 bool operator<(const ClassInfo &RHS) const {
270 // Unrelated classes can be ordered by kind.
271 if (!isRelatedTo(RHS))
272 return Kind < RHS.Kind;
276 llvm_unreachable("Invalid kind!");
279 // This class precedes the RHS if it is a proper subset of the RHS.
282 if (RHS.isSubsetOf(*this))
285 // Otherwise, order by name to ensure we have a total ordering.
286 return ValueName < RHS.ValueName;
292 /// Sort ClassInfo pointers independently of pointer value.
293 struct LessClassInfoPtr {
294 bool operator()(const ClassInfo *LHS, const ClassInfo *RHS) const {
300 /// MatchableInfo - Helper class for storing the necessary information for an
301 /// instruction or alias which is capable of being matched.
302 struct MatchableInfo {
304 /// Token - This is the token that the operand came from.
307 /// The unique class instance this operand should match.
310 /// The operand name this is, if anything.
313 /// The suboperand index within SrcOpName, or -1 for the entire operand.
316 /// Register record if this token is singleton register.
317 Record *SingletonReg;
319 explicit AsmOperand(StringRef T) : Token(T), Class(0), SubOpIdx(-1),
323 /// ResOperand - This represents a single operand in the result instruction
324 /// generated by the match. In cases (like addressing modes) where a single
325 /// assembler operand expands to multiple MCOperands, this represents the
326 /// single assembler operand, not the MCOperand.
329 /// RenderAsmOperand - This represents an operand result that is
330 /// generated by calling the render method on the assembly operand. The
331 /// corresponding AsmOperand is specified by AsmOperandNum.
334 /// TiedOperand - This represents a result operand that is a duplicate of
335 /// a previous result operand.
338 /// ImmOperand - This represents an immediate value that is dumped into
342 /// RegOperand - This represents a fixed register that is dumped in.
347 /// This is the operand # in the AsmOperands list that this should be
349 unsigned AsmOperandNum;
351 /// TiedOperandNum - This is the (earlier) result operand that should be
353 unsigned TiedOperandNum;
355 /// ImmVal - This is the immediate value added to the instruction.
358 /// Register - This is the register record.
362 /// MINumOperands - The number of MCInst operands populated by this
364 unsigned MINumOperands;
366 static ResOperand getRenderedOp(unsigned AsmOpNum, unsigned NumOperands) {
368 X.Kind = RenderAsmOperand;
369 X.AsmOperandNum = AsmOpNum;
370 X.MINumOperands = NumOperands;
374 static ResOperand getTiedOp(unsigned TiedOperandNum) {
376 X.Kind = TiedOperand;
377 X.TiedOperandNum = TiedOperandNum;
382 static ResOperand getImmOp(int64_t Val) {
390 static ResOperand getRegOp(Record *Reg) {
399 /// AsmVariantID - Target's assembly syntax variant no.
402 /// TheDef - This is the definition of the instruction or InstAlias that this
403 /// matchable came from.
404 Record *const TheDef;
406 /// DefRec - This is the definition that it came from.
407 PointerUnion<const CodeGenInstruction*, const CodeGenInstAlias*> DefRec;
409 const CodeGenInstruction *getResultInst() const {
410 if (DefRec.is<const CodeGenInstruction*>())
411 return DefRec.get<const CodeGenInstruction*>();
412 return DefRec.get<const CodeGenInstAlias*>()->ResultInst;
415 /// ResOperands - This is the operand list that should be built for the result
417 SmallVector<ResOperand, 8> ResOperands;
419 /// AsmString - The assembly string for this instruction (with variants
420 /// removed), e.g. "movsx $src, $dst".
421 std::string AsmString;
423 /// Mnemonic - This is the first token of the matched instruction, its
427 /// AsmOperands - The textual operands that this instruction matches,
428 /// annotated with a class and where in the OperandList they were defined.
429 /// This directly corresponds to the tokenized AsmString after the mnemonic is
431 SmallVector<AsmOperand, 8> AsmOperands;
433 /// Predicates - The required subtarget features to match this instruction.
434 SmallVector<SubtargetFeatureInfo*, 4> RequiredFeatures;
436 /// ConversionFnKind - The enum value which is passed to the generated
437 /// convertToMCInst to convert parsed operands into an MCInst for this
439 std::string ConversionFnKind;
441 /// If this instruction is deprecated in some form.
444 MatchableInfo(const CodeGenInstruction &CGI)
445 : AsmVariantID(0), TheDef(CGI.TheDef), DefRec(&CGI),
446 AsmString(CGI.AsmString) {
449 MatchableInfo(const CodeGenInstAlias *Alias)
450 : AsmVariantID(0), TheDef(Alias->TheDef), DefRec(Alias),
451 AsmString(Alias->AsmString) {
454 // Two-operand aliases clone from the main matchable, but mark the second
455 // operand as a tied operand of the first for purposes of the assembler.
456 void formTwoOperandAlias(StringRef Constraint);
458 void initialize(const AsmMatcherInfo &Info,
459 SmallPtrSet<Record*, 16> &SingletonRegisters,
460 int AsmVariantNo, std::string &RegisterPrefix);
462 /// validate - Return true if this matchable is a valid thing to match against
463 /// and perform a bunch of validity checking.
464 bool validate(StringRef CommentDelimiter, bool Hack) const;
466 /// extractSingletonRegisterForAsmOperand - Extract singleton register,
467 /// if present, from specified token.
469 extractSingletonRegisterForAsmOperand(unsigned i, const AsmMatcherInfo &Info,
470 std::string &RegisterPrefix);
472 /// findAsmOperand - Find the AsmOperand with the specified name and
473 /// suboperand index.
474 int findAsmOperand(StringRef N, int SubOpIdx) const {
475 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
476 if (N == AsmOperands[i].SrcOpName &&
477 SubOpIdx == AsmOperands[i].SubOpIdx)
482 /// findAsmOperandNamed - Find the first AsmOperand with the specified name.
483 /// This does not check the suboperand index.
484 int findAsmOperandNamed(StringRef N) const {
485 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
486 if (N == AsmOperands[i].SrcOpName)
491 void buildInstructionResultOperands();
492 void buildAliasResultOperands();
494 /// operator< - Compare two matchables.
495 bool operator<(const MatchableInfo &RHS) const {
496 // The primary comparator is the instruction mnemonic.
497 if (Mnemonic != RHS.Mnemonic)
498 return Mnemonic < RHS.Mnemonic;
500 if (AsmOperands.size() != RHS.AsmOperands.size())
501 return AsmOperands.size() < RHS.AsmOperands.size();
503 // Compare lexicographically by operand. The matcher validates that other
504 // orderings wouldn't be ambiguous using \see couldMatchAmbiguouslyWith().
505 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
506 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
508 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
512 // Give matches that require more features higher precedence. This is useful
513 // because we cannot define AssemblerPredicates with the negation of
514 // processor features. For example, ARM v6 "nop" may be either a HINT or
515 // MOV. With v6, we want to match HINT. The assembler has no way to
516 // predicate MOV under "NoV6", but HINT will always match first because it
517 // requires V6 while MOV does not.
518 if (RequiredFeatures.size() != RHS.RequiredFeatures.size())
519 return RequiredFeatures.size() > RHS.RequiredFeatures.size();
524 /// couldMatchAmbiguouslyWith - Check whether this matchable could
525 /// ambiguously match the same set of operands as \p RHS (without being a
526 /// strictly superior match).
527 bool couldMatchAmbiguouslyWith(const MatchableInfo &RHS) {
528 // The primary comparator is the instruction mnemonic.
529 if (Mnemonic != RHS.Mnemonic)
532 // The number of operands is unambiguous.
533 if (AsmOperands.size() != RHS.AsmOperands.size())
536 // Otherwise, make sure the ordering of the two instructions is unambiguous
537 // by checking that either (a) a token or operand kind discriminates them,
538 // or (b) the ordering among equivalent kinds is consistent.
540 // Tokens and operand kinds are unambiguous (assuming a correct target
542 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
543 if (AsmOperands[i].Class->Kind != RHS.AsmOperands[i].Class->Kind ||
544 AsmOperands[i].Class->Kind == ClassInfo::Token)
545 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class ||
546 *RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
549 // Otherwise, this operand could commute if all operands are equivalent, or
550 // there is a pair of operands that compare less than and a pair that
551 // compare greater than.
552 bool HasLT = false, HasGT = false;
553 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
554 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
556 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
560 return !(HasLT ^ HasGT);
566 void tokenizeAsmString(const AsmMatcherInfo &Info);
569 /// SubtargetFeatureInfo - Helper class for storing information on a subtarget
570 /// feature which participates in instruction matching.
571 struct SubtargetFeatureInfo {
572 /// \brief The predicate record for this feature.
575 /// \brief An unique index assigned to represent this feature.
578 SubtargetFeatureInfo(Record *D, unsigned Idx) : TheDef(D), Index(Idx) {}
580 /// \brief The name of the enumerated constant identifying this feature.
581 std::string getEnumName() const {
582 return "Feature_" + TheDef->getName();
586 struct OperandMatchEntry {
587 unsigned OperandMask;
591 static OperandMatchEntry create(MatchableInfo* mi, ClassInfo *ci,
594 X.OperandMask = opMask;
602 class AsmMatcherInfo {
605 RecordKeeper &Records;
607 /// The tablegen AsmParser record.
610 /// Target - The target information.
611 CodeGenTarget &Target;
613 /// The classes which are needed for matching.
614 std::vector<ClassInfo*> Classes;
616 /// The information on the matchables to match.
617 std::vector<MatchableInfo*> Matchables;
619 /// Info for custom matching operands by user defined methods.
620 std::vector<OperandMatchEntry> OperandMatchInfo;
622 /// Map of Register records to their class information.
623 typedef std::map<Record*, ClassInfo*, LessRecordByID> RegisterClassesTy;
624 RegisterClassesTy RegisterClasses;
626 /// Map of Predicate records to their subtarget information.
627 std::map<Record*, SubtargetFeatureInfo*, LessRecordByID> SubtargetFeatures;
629 /// Map of AsmOperandClass records to their class information.
630 std::map<Record*, ClassInfo*> AsmOperandClasses;
633 /// Map of token to class information which has already been constructed.
634 std::map<std::string, ClassInfo*> TokenClasses;
636 /// Map of RegisterClass records to their class information.
637 std::map<Record*, ClassInfo*> RegisterClassClasses;
640 /// getTokenClass - Lookup or create the class for the given token.
641 ClassInfo *getTokenClass(StringRef Token);
643 /// getOperandClass - Lookup or create the class for the given operand.
644 ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI,
646 ClassInfo *getOperandClass(Record *Rec, int SubOpIdx);
648 /// buildRegisterClasses - Build the ClassInfo* instances for register
650 void buildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters);
652 /// buildOperandClasses - Build the ClassInfo* instances for user defined
654 void buildOperandClasses();
656 void buildInstructionOperandReference(MatchableInfo *II, StringRef OpName,
658 void buildAliasOperandReference(MatchableInfo *II, StringRef OpName,
659 MatchableInfo::AsmOperand &Op);
662 AsmMatcherInfo(Record *AsmParser,
663 CodeGenTarget &Target,
664 RecordKeeper &Records);
666 /// buildInfo - Construct the various tables used during matching.
669 /// buildOperandMatchInfo - Build the necessary information to handle user
670 /// defined operand parsing methods.
671 void buildOperandMatchInfo();
673 /// getSubtargetFeature - Lookup or create the subtarget feature info for the
675 SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const {
676 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
677 std::map<Record*, SubtargetFeatureInfo*, LessRecordByID>::const_iterator I =
678 SubtargetFeatures.find(Def);
679 return I == SubtargetFeatures.end() ? 0 : I->second;
682 RecordKeeper &getRecords() const {
687 } // End anonymous namespace
689 void MatchableInfo::dump() {
690 errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n";
692 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
693 AsmOperand &Op = AsmOperands[i];
694 errs() << " op[" << i << "] = " << Op.Class->ClassName << " - ";
695 errs() << '\"' << Op.Token << "\"\n";
699 static std::pair<StringRef, StringRef>
700 parseTwoOperandConstraint(StringRef S, ArrayRef<SMLoc> Loc) {
701 // Split via the '='.
702 std::pair<StringRef, StringRef> Ops = S.split('=');
703 if (Ops.second == "")
704 PrintFatalError(Loc, "missing '=' in two-operand alias constraint");
705 // Trim whitespace and the leading '$' on the operand names.
706 size_t start = Ops.first.find_first_of('$');
707 if (start == std::string::npos)
708 PrintFatalError(Loc, "expected '$' prefix on asm operand name");
709 Ops.first = Ops.first.slice(start + 1, std::string::npos);
710 size_t end = Ops.first.find_last_of(" \t");
711 Ops.first = Ops.first.slice(0, end);
712 // Now the second operand.
713 start = Ops.second.find_first_of('$');
714 if (start == std::string::npos)
715 PrintFatalError(Loc, "expected '$' prefix on asm operand name");
716 Ops.second = Ops.second.slice(start + 1, std::string::npos);
717 end = Ops.second.find_last_of(" \t");
718 Ops.first = Ops.first.slice(0, end);
722 void MatchableInfo::formTwoOperandAlias(StringRef Constraint) {
723 // Figure out which operands are aliased and mark them as tied.
724 std::pair<StringRef, StringRef> Ops =
725 parseTwoOperandConstraint(Constraint, TheDef->getLoc());
727 // Find the AsmOperands that refer to the operands we're aliasing.
728 int SrcAsmOperand = findAsmOperandNamed(Ops.first);
729 int DstAsmOperand = findAsmOperandNamed(Ops.second);
730 if (SrcAsmOperand == -1)
731 PrintFatalError(TheDef->getLoc(),
732 "unknown source two-operand alias operand '" +
733 Ops.first.str() + "'.");
734 if (DstAsmOperand == -1)
735 PrintFatalError(TheDef->getLoc(),
736 "unknown destination two-operand alias operand '" +
737 Ops.second.str() + "'.");
739 // Find the ResOperand that refers to the operand we're aliasing away
740 // and update it to refer to the combined operand instead.
741 for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) {
742 ResOperand &Op = ResOperands[i];
743 if (Op.Kind == ResOperand::RenderAsmOperand &&
744 Op.AsmOperandNum == (unsigned)SrcAsmOperand) {
745 Op.AsmOperandNum = DstAsmOperand;
749 // Remove the AsmOperand for the alias operand.
750 AsmOperands.erase(AsmOperands.begin() + SrcAsmOperand);
751 // Adjust the ResOperand references to any AsmOperands that followed
752 // the one we just deleted.
753 for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) {
754 ResOperand &Op = ResOperands[i];
757 // Nothing to do for operands that don't reference AsmOperands.
759 case ResOperand::RenderAsmOperand:
760 if (Op.AsmOperandNum > (unsigned)SrcAsmOperand)
763 case ResOperand::TiedOperand:
764 if (Op.TiedOperandNum > (unsigned)SrcAsmOperand)
771 void MatchableInfo::initialize(const AsmMatcherInfo &Info,
772 SmallPtrSet<Record*, 16> &SingletonRegisters,
773 int AsmVariantNo, std::string &RegisterPrefix) {
774 AsmVariantID = AsmVariantNo;
776 CodeGenInstruction::FlattenAsmStringVariants(AsmString, AsmVariantNo);
778 tokenizeAsmString(Info);
780 // Compute the require features.
781 std::vector<Record*> Predicates =TheDef->getValueAsListOfDefs("Predicates");
782 for (unsigned i = 0, e = Predicates.size(); i != e; ++i)
783 if (SubtargetFeatureInfo *Feature =
784 Info.getSubtargetFeature(Predicates[i]))
785 RequiredFeatures.push_back(Feature);
787 // Collect singleton registers, if used.
788 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
789 extractSingletonRegisterForAsmOperand(i, Info, RegisterPrefix);
790 if (Record *Reg = AsmOperands[i].SingletonReg)
791 SingletonRegisters.insert(Reg);
794 const RecordVal *DepMask = TheDef->getValue("DeprecatedFeatureMask");
796 DepMask = TheDef->getValue("ComplexDeprecationPredicate");
799 DepMask ? !DepMask->getValue()->getAsUnquotedString().empty() : false;
802 /// tokenizeAsmString - Tokenize a simplified assembly string.
803 void MatchableInfo::tokenizeAsmString(const AsmMatcherInfo &Info) {
804 StringRef String = AsmString;
807 for (unsigned i = 0, e = String.size(); i != e; ++i) {
817 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
820 if (!isspace(String[i]) && String[i] != ',')
821 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
827 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
831 assert(i != String.size() && "Invalid quoted character");
832 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
838 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
842 // If this isn't "${", treat like a normal token.
843 if (i + 1 == String.size() || String[i + 1] != '{') {
848 StringRef::iterator End = std::find(String.begin() + i, String.end(),'}');
849 assert(End != String.end() && "Missing brace in operand reference!");
850 size_t EndPos = End - String.begin();
851 AsmOperands.push_back(AsmOperand(String.slice(i, EndPos+1)));
858 if (!Info.AsmParser->getValueAsBit("MnemonicContainsDot")) {
860 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
870 if (InTok && Prev != String.size())
871 AsmOperands.push_back(AsmOperand(String.substr(Prev)));
873 // The first token of the instruction is the mnemonic, which must be a
874 // simple string, not a $foo variable or a singleton register.
875 if (AsmOperands.empty())
876 PrintFatalError(TheDef->getLoc(),
877 "Instruction '" + TheDef->getName() + "' has no tokens");
878 Mnemonic = AsmOperands[0].Token;
879 if (Mnemonic.empty())
880 PrintFatalError(TheDef->getLoc(),
881 "Missing instruction mnemonic");
882 // FIXME : Check and raise an error if it is a register.
883 if (Mnemonic[0] == '$')
884 PrintFatalError(TheDef->getLoc(),
885 "Invalid instruction mnemonic '" + Mnemonic.str() + "'!");
887 // Remove the first operand, it is tracked in the mnemonic field.
888 AsmOperands.erase(AsmOperands.begin());
891 bool MatchableInfo::validate(StringRef CommentDelimiter, bool Hack) const {
892 // Reject matchables with no .s string.
893 if (AsmString.empty())
894 PrintFatalError(TheDef->getLoc(), "instruction with empty asm string");
896 // Reject any matchables with a newline in them, they should be marked
897 // isCodeGenOnly if they are pseudo instructions.
898 if (AsmString.find('\n') != std::string::npos)
899 PrintFatalError(TheDef->getLoc(),
900 "multiline instruction is not valid for the asmparser, "
901 "mark it isCodeGenOnly");
903 // Remove comments from the asm string. We know that the asmstring only
905 if (!CommentDelimiter.empty() &&
906 StringRef(AsmString).find(CommentDelimiter) != StringRef::npos)
907 PrintFatalError(TheDef->getLoc(),
908 "asmstring for instruction has comment character in it, "
909 "mark it isCodeGenOnly");
911 // Reject matchables with operand modifiers, these aren't something we can
912 // handle, the target should be refactored to use operands instead of
915 // Also, check for instructions which reference the operand multiple times;
916 // this implies a constraint we would not honor.
917 std::set<std::string> OperandNames;
918 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
919 StringRef Tok = AsmOperands[i].Token;
920 if (Tok[0] == '$' && Tok.find(':') != StringRef::npos)
921 PrintFatalError(TheDef->getLoc(),
922 "matchable with operand modifier '" + Tok.str() +
923 "' not supported by asm matcher. Mark isCodeGenOnly!");
925 // Verify that any operand is only mentioned once.
926 // We reject aliases and ignore instructions for now.
927 if (Tok[0] == '$' && !OperandNames.insert(Tok).second) {
929 PrintFatalError(TheDef->getLoc(),
930 "ERROR: matchable with tied operand '" + Tok.str() +
931 "' can never be matched!");
932 // FIXME: Should reject these. The ARM backend hits this with $lane in a
933 // bunch of instructions. It is unclear what the right answer is.
935 errs() << "warning: '" << TheDef->getName() << "': "
936 << "ignoring instruction with tied operand '"
937 << Tok.str() << "'\n";
946 /// extractSingletonRegisterForAsmOperand - Extract singleton register,
947 /// if present, from specified token.
949 extractSingletonRegisterForAsmOperand(unsigned OperandNo,
950 const AsmMatcherInfo &Info,
951 std::string &RegisterPrefix) {
952 StringRef Tok = AsmOperands[OperandNo].Token;
953 if (RegisterPrefix.empty()) {
954 std::string LoweredTok = Tok.lower();
955 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(LoweredTok))
956 AsmOperands[OperandNo].SingletonReg = Reg->TheDef;
960 if (!Tok.startswith(RegisterPrefix))
963 StringRef RegName = Tok.substr(RegisterPrefix.size());
964 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName))
965 AsmOperands[OperandNo].SingletonReg = Reg->TheDef;
967 // If there is no register prefix (i.e. "%" in "%eax"), then this may
968 // be some random non-register token, just ignore it.
972 static std::string getEnumNameForToken(StringRef Str) {
975 for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) {
977 case '*': Res += "_STAR_"; break;
978 case '%': Res += "_PCT_"; break;
979 case ':': Res += "_COLON_"; break;
980 case '!': Res += "_EXCLAIM_"; break;
981 case '.': Res += "_DOT_"; break;
982 case '<': Res += "_LT_"; break;
983 case '>': Res += "_GT_"; break;
985 if ((*it >= 'A' && *it <= 'Z') ||
986 (*it >= 'a' && *it <= 'z') ||
987 (*it >= '0' && *it <= '9'))
990 Res += "_" + utostr((unsigned) *it) + "_";
997 ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) {
998 ClassInfo *&Entry = TokenClasses[Token];
1001 Entry = new ClassInfo();
1002 Entry->Kind = ClassInfo::Token;
1003 Entry->ClassName = "Token";
1004 Entry->Name = "MCK_" + getEnumNameForToken(Token);
1005 Entry->ValueName = Token;
1006 Entry->PredicateMethod = "<invalid>";
1007 Entry->RenderMethod = "<invalid>";
1008 Entry->ParserMethod = "";
1009 Entry->DiagnosticType = "";
1010 Classes.push_back(Entry);
1017 AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI,
1019 Record *Rec = OI.Rec;
1021 Rec = cast<DefInit>(OI.MIOperandInfo->getArg(SubOpIdx))->getDef();
1022 return getOperandClass(Rec, SubOpIdx);
1026 AsmMatcherInfo::getOperandClass(Record *Rec, int SubOpIdx) {
1027 if (Rec->isSubClassOf("RegisterOperand")) {
1028 // RegisterOperand may have an associated ParserMatchClass. If it does,
1029 // use it, else just fall back to the underlying register class.
1030 const RecordVal *R = Rec->getValue("ParserMatchClass");
1031 if (R == 0 || R->getValue() == 0)
1032 PrintFatalError("Record `" + Rec->getName() +
1033 "' does not have a ParserMatchClass!\n");
1035 if (DefInit *DI= dyn_cast<DefInit>(R->getValue())) {
1036 Record *MatchClass = DI->getDef();
1037 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1041 // No custom match class. Just use the register class.
1042 Record *ClassRec = Rec->getValueAsDef("RegClass");
1044 PrintFatalError(Rec->getLoc(), "RegisterOperand `" + Rec->getName() +
1045 "' has no associated register class!\n");
1046 if (ClassInfo *CI = RegisterClassClasses[ClassRec])
1048 PrintFatalError(Rec->getLoc(), "register class has no class info!");
1052 if (Rec->isSubClassOf("RegisterClass")) {
1053 if (ClassInfo *CI = RegisterClassClasses[Rec])
1055 PrintFatalError(Rec->getLoc(), "register class has no class info!");
1058 if (!Rec->isSubClassOf("Operand"))
1059 PrintFatalError(Rec->getLoc(), "Operand `" + Rec->getName() +
1060 "' does not derive from class Operand!\n");
1061 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1062 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1065 PrintFatalError(Rec->getLoc(), "operand has no match class!");
1068 struct LessRegisterSet {
1069 bool operator() (const RegisterSet &LHS, const RegisterSet & RHS) const {
1070 // std::set<T> defines its own compariso "operator<", but it
1071 // performs a lexicographical comparison by T's innate comparison
1072 // for some reason. We don't want non-deterministic pointer
1073 // comparisons so use this instead.
1074 return std::lexicographical_compare(LHS.begin(), LHS.end(),
1075 RHS.begin(), RHS.end(),
1080 void AsmMatcherInfo::
1081 buildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters) {
1082 const std::vector<CodeGenRegister*> &Registers =
1083 Target.getRegBank().getRegisters();
1084 ArrayRef<CodeGenRegisterClass*> RegClassList =
1085 Target.getRegBank().getRegClasses();
1087 typedef std::set<RegisterSet, LessRegisterSet> RegisterSetSet;
1089 // The register sets used for matching.
1090 RegisterSetSet RegisterSets;
1092 // Gather the defined sets.
1093 for (ArrayRef<CodeGenRegisterClass*>::const_iterator it =
1094 RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it)
1095 RegisterSets.insert(RegisterSet(
1096 (*it)->getOrder().begin(), (*it)->getOrder().end()));
1098 // Add any required singleton sets.
1099 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
1100 ie = SingletonRegisters.end(); it != ie; ++it) {
1102 RegisterSets.insert(RegisterSet(&Rec, &Rec + 1));
1105 // Introduce derived sets where necessary (when a register does not determine
1106 // a unique register set class), and build the mapping of registers to the set
1107 // they should classify to.
1108 std::map<Record*, RegisterSet> RegisterMap;
1109 for (std::vector<CodeGenRegister*>::const_iterator it = Registers.begin(),
1110 ie = Registers.end(); it != ie; ++it) {
1111 const CodeGenRegister &CGR = **it;
1112 // Compute the intersection of all sets containing this register.
1113 RegisterSet ContainingSet;
1115 for (RegisterSetSet::iterator it = RegisterSets.begin(),
1116 ie = RegisterSets.end(); it != ie; ++it) {
1117 if (!it->count(CGR.TheDef))
1120 if (ContainingSet.empty()) {
1121 ContainingSet = *it;
1126 std::swap(Tmp, ContainingSet);
1127 std::insert_iterator<RegisterSet> II(ContainingSet,
1128 ContainingSet.begin());
1129 std::set_intersection(Tmp.begin(), Tmp.end(), it->begin(), it->end(), II,
1133 if (!ContainingSet.empty()) {
1134 RegisterSets.insert(ContainingSet);
1135 RegisterMap.insert(std::make_pair(CGR.TheDef, ContainingSet));
1139 // Construct the register classes.
1140 std::map<RegisterSet, ClassInfo*, LessRegisterSet> RegisterSetClasses;
1142 for (RegisterSetSet::iterator it = RegisterSets.begin(),
1143 ie = RegisterSets.end(); it != ie; ++it, ++Index) {
1144 ClassInfo *CI = new ClassInfo();
1145 CI->Kind = ClassInfo::RegisterClass0 + Index;
1146 CI->ClassName = "Reg" + utostr(Index);
1147 CI->Name = "MCK_Reg" + utostr(Index);
1149 CI->PredicateMethod = ""; // unused
1150 CI->RenderMethod = "addRegOperands";
1151 CI->Registers = *it;
1152 // FIXME: diagnostic type.
1153 CI->DiagnosticType = "";
1154 Classes.push_back(CI);
1155 RegisterSetClasses.insert(std::make_pair(*it, CI));
1158 // Find the superclasses; we could compute only the subgroup lattice edges,
1159 // but there isn't really a point.
1160 for (RegisterSetSet::iterator it = RegisterSets.begin(),
1161 ie = RegisterSets.end(); it != ie; ++it) {
1162 ClassInfo *CI = RegisterSetClasses[*it];
1163 for (RegisterSetSet::iterator it2 = RegisterSets.begin(),
1164 ie2 = RegisterSets.end(); it2 != ie2; ++it2)
1166 std::includes(it2->begin(), it2->end(), it->begin(), it->end(),
1168 CI->SuperClasses.push_back(RegisterSetClasses[*it2]);
1171 // Name the register classes which correspond to a user defined RegisterClass.
1172 for (ArrayRef<CodeGenRegisterClass*>::const_iterator
1173 it = RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it) {
1174 const CodeGenRegisterClass &RC = **it;
1175 // Def will be NULL for non-user defined register classes.
1176 Record *Def = RC.getDef();
1179 ClassInfo *CI = RegisterSetClasses[RegisterSet(RC.getOrder().begin(),
1180 RC.getOrder().end())];
1181 if (CI->ValueName.empty()) {
1182 CI->ClassName = RC.getName();
1183 CI->Name = "MCK_" + RC.getName();
1184 CI->ValueName = RC.getName();
1186 CI->ValueName = CI->ValueName + "," + RC.getName();
1188 RegisterClassClasses.insert(std::make_pair(Def, CI));
1191 // Populate the map for individual registers.
1192 for (std::map<Record*, RegisterSet>::iterator it = RegisterMap.begin(),
1193 ie = RegisterMap.end(); it != ie; ++it)
1194 RegisterClasses[it->first] = RegisterSetClasses[it->second];
1196 // Name the register classes which correspond to singleton registers.
1197 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
1198 ie = SingletonRegisters.end(); it != ie; ++it) {
1200 ClassInfo *CI = RegisterClasses[Rec];
1201 assert(CI && "Missing singleton register class info!");
1203 if (CI->ValueName.empty()) {
1204 CI->ClassName = Rec->getName();
1205 CI->Name = "MCK_" + Rec->getName();
1206 CI->ValueName = Rec->getName();
1208 CI->ValueName = CI->ValueName + "," + Rec->getName();
1212 void AsmMatcherInfo::buildOperandClasses() {
1213 std::vector<Record*> AsmOperands =
1214 Records.getAllDerivedDefinitions("AsmOperandClass");
1216 // Pre-populate AsmOperandClasses map.
1217 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
1218 ie = AsmOperands.end(); it != ie; ++it)
1219 AsmOperandClasses[*it] = new ClassInfo();
1222 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
1223 ie = AsmOperands.end(); it != ie; ++it, ++Index) {
1224 ClassInfo *CI = AsmOperandClasses[*it];
1225 CI->Kind = ClassInfo::UserClass0 + Index;
1227 ListInit *Supers = (*it)->getValueAsListInit("SuperClasses");
1228 for (unsigned i = 0, e = Supers->getSize(); i != e; ++i) {
1229 DefInit *DI = dyn_cast<DefInit>(Supers->getElement(i));
1231 PrintError((*it)->getLoc(), "Invalid super class reference!");
1235 ClassInfo *SC = AsmOperandClasses[DI->getDef()];
1237 PrintError((*it)->getLoc(), "Invalid super class reference!");
1239 CI->SuperClasses.push_back(SC);
1241 CI->ClassName = (*it)->getValueAsString("Name");
1242 CI->Name = "MCK_" + CI->ClassName;
1243 CI->ValueName = (*it)->getName();
1245 // Get or construct the predicate method name.
1246 Init *PMName = (*it)->getValueInit("PredicateMethod");
1247 if (StringInit *SI = dyn_cast<StringInit>(PMName)) {
1248 CI->PredicateMethod = SI->getValue();
1250 assert(isa<UnsetInit>(PMName) && "Unexpected PredicateMethod field!");
1251 CI->PredicateMethod = "is" + CI->ClassName;
1254 // Get or construct the render method name.
1255 Init *RMName = (*it)->getValueInit("RenderMethod");
1256 if (StringInit *SI = dyn_cast<StringInit>(RMName)) {
1257 CI->RenderMethod = SI->getValue();
1259 assert(isa<UnsetInit>(RMName) && "Unexpected RenderMethod field!");
1260 CI->RenderMethod = "add" + CI->ClassName + "Operands";
1263 // Get the parse method name or leave it as empty.
1264 Init *PRMName = (*it)->getValueInit("ParserMethod");
1265 if (StringInit *SI = dyn_cast<StringInit>(PRMName))
1266 CI->ParserMethod = SI->getValue();
1268 // Get the diagnostic type or leave it as empty.
1269 // Get the parse method name or leave it as empty.
1270 Init *DiagnosticType = (*it)->getValueInit("DiagnosticType");
1271 if (StringInit *SI = dyn_cast<StringInit>(DiagnosticType))
1272 CI->DiagnosticType = SI->getValue();
1274 AsmOperandClasses[*it] = CI;
1275 Classes.push_back(CI);
1279 AsmMatcherInfo::AsmMatcherInfo(Record *asmParser,
1280 CodeGenTarget &target,
1281 RecordKeeper &records)
1282 : Records(records), AsmParser(asmParser), Target(target) {
1285 /// buildOperandMatchInfo - Build the necessary information to handle user
1286 /// defined operand parsing methods.
1287 void AsmMatcherInfo::buildOperandMatchInfo() {
1289 /// Map containing a mask with all operands indices that can be found for
1290 /// that class inside a instruction.
1291 typedef std::map<ClassInfo*, unsigned, LessClassInfoPtr> OpClassMaskTy;
1292 OpClassMaskTy OpClassMask;
1294 for (std::vector<MatchableInfo*>::const_iterator it =
1295 Matchables.begin(), ie = Matchables.end();
1297 MatchableInfo &II = **it;
1298 OpClassMask.clear();
1300 // Keep track of all operands of this instructions which belong to the
1302 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) {
1303 MatchableInfo::AsmOperand &Op = II.AsmOperands[i];
1304 if (Op.Class->ParserMethod.empty())
1306 unsigned &OperandMask = OpClassMask[Op.Class];
1307 OperandMask |= (1 << i);
1310 // Generate operand match info for each mnemonic/operand class pair.
1311 for (OpClassMaskTy::iterator iit = OpClassMask.begin(),
1312 iie = OpClassMask.end(); iit != iie; ++iit) {
1313 unsigned OpMask = iit->second;
1314 ClassInfo *CI = iit->first;
1315 OperandMatchInfo.push_back(OperandMatchEntry::create(&II, CI, OpMask));
1320 void AsmMatcherInfo::buildInfo() {
1321 // Build information about all of the AssemblerPredicates.
1322 std::vector<Record*> AllPredicates =
1323 Records.getAllDerivedDefinitions("Predicate");
1324 for (unsigned i = 0, e = AllPredicates.size(); i != e; ++i) {
1325 Record *Pred = AllPredicates[i];
1326 // Ignore predicates that are not intended for the assembler.
1327 if (!Pred->getValueAsBit("AssemblerMatcherPredicate"))
1330 if (Pred->getName().empty())
1331 PrintFatalError(Pred->getLoc(), "Predicate has no name!");
1333 unsigned FeatureNo = SubtargetFeatures.size();
1334 SubtargetFeatures[Pred] = new SubtargetFeatureInfo(Pred, FeatureNo);
1335 assert(FeatureNo < 32 && "Too many subtarget features!");
1338 // Parse the instructions; we need to do this first so that we can gather the
1339 // singleton register classes.
1340 SmallPtrSet<Record*, 16> SingletonRegisters;
1341 unsigned VariantCount = Target.getAsmParserVariantCount();
1342 for (unsigned VC = 0; VC != VariantCount; ++VC) {
1343 Record *AsmVariant = Target.getAsmParserVariant(VC);
1344 std::string CommentDelimiter =
1345 AsmVariant->getValueAsString("CommentDelimiter");
1346 std::string RegisterPrefix = AsmVariant->getValueAsString("RegisterPrefix");
1347 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
1349 for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
1350 E = Target.inst_end(); I != E; ++I) {
1351 const CodeGenInstruction &CGI = **I;
1353 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1354 // filter the set of instructions we consider.
1355 if (!StringRef(CGI.TheDef->getName()).startswith(MatchPrefix))
1358 // Ignore "codegen only" instructions.
1359 if (CGI.TheDef->getValueAsBit("isCodeGenOnly"))
1362 OwningPtr<MatchableInfo> II(new MatchableInfo(CGI));
1364 II->initialize(*this, SingletonRegisters, AsmVariantNo, RegisterPrefix);
1366 // Ignore instructions which shouldn't be matched and diagnose invalid
1367 // instruction definitions with an error.
1368 if (!II->validate(CommentDelimiter, true))
1371 // Ignore "Int_*" and "*_Int" instructions, which are internal aliases.
1373 // FIXME: This is a total hack.
1374 if (StringRef(II->TheDef->getName()).startswith("Int_") ||
1375 StringRef(II->TheDef->getName()).endswith("_Int"))
1378 Matchables.push_back(II.take());
1381 // Parse all of the InstAlias definitions and stick them in the list of
1383 std::vector<Record*> AllInstAliases =
1384 Records.getAllDerivedDefinitions("InstAlias");
1385 for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) {
1386 CodeGenInstAlias *Alias = new CodeGenInstAlias(AllInstAliases[i], Target);
1388 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1389 // filter the set of instruction aliases we consider, based on the target
1391 if (!StringRef(Alias->ResultInst->TheDef->getName())
1392 .startswith( MatchPrefix))
1395 OwningPtr<MatchableInfo> II(new MatchableInfo(Alias));
1397 II->initialize(*this, SingletonRegisters, AsmVariantNo, RegisterPrefix);
1399 // Validate the alias definitions.
1400 II->validate(CommentDelimiter, false);
1402 Matchables.push_back(II.take());
1406 // Build info for the register classes.
1407 buildRegisterClasses(SingletonRegisters);
1409 // Build info for the user defined assembly operand classes.
1410 buildOperandClasses();
1412 // Build the information about matchables, now that we have fully formed
1414 std::vector<MatchableInfo*> NewMatchables;
1415 for (std::vector<MatchableInfo*>::iterator it = Matchables.begin(),
1416 ie = Matchables.end(); it != ie; ++it) {
1417 MatchableInfo *II = *it;
1419 // Parse the tokens after the mnemonic.
1420 // Note: buildInstructionOperandReference may insert new AsmOperands, so
1421 // don't precompute the loop bound.
1422 for (unsigned i = 0; i != II->AsmOperands.size(); ++i) {
1423 MatchableInfo::AsmOperand &Op = II->AsmOperands[i];
1424 StringRef Token = Op.Token;
1426 // Check for singleton registers.
1427 if (Record *RegRecord = II->AsmOperands[i].SingletonReg) {
1428 Op.Class = RegisterClasses[RegRecord];
1429 assert(Op.Class && Op.Class->Registers.size() == 1 &&
1430 "Unexpected class for singleton register");
1434 // Check for simple tokens.
1435 if (Token[0] != '$') {
1436 Op.Class = getTokenClass(Token);
1440 if (Token.size() > 1 && isdigit(Token[1])) {
1441 Op.Class = getTokenClass(Token);
1445 // Otherwise this is an operand reference.
1446 StringRef OperandName;
1447 if (Token[1] == '{')
1448 OperandName = Token.substr(2, Token.size() - 3);
1450 OperandName = Token.substr(1);
1452 if (II->DefRec.is<const CodeGenInstruction*>())
1453 buildInstructionOperandReference(II, OperandName, i);
1455 buildAliasOperandReference(II, OperandName, Op);
1458 if (II->DefRec.is<const CodeGenInstruction*>()) {
1459 II->buildInstructionResultOperands();
1460 // If the instruction has a two-operand alias, build up the
1461 // matchable here. We'll add them in bulk at the end to avoid
1462 // confusing this loop.
1463 std::string Constraint =
1464 II->TheDef->getValueAsString("TwoOperandAliasConstraint");
1465 if (Constraint != "") {
1466 // Start by making a copy of the original matchable.
1467 OwningPtr<MatchableInfo> AliasII(new MatchableInfo(*II));
1469 // Adjust it to be a two-operand alias.
1470 AliasII->formTwoOperandAlias(Constraint);
1472 // Add the alias to the matchables list.
1473 NewMatchables.push_back(AliasII.take());
1476 II->buildAliasResultOperands();
1478 if (!NewMatchables.empty())
1479 Matchables.insert(Matchables.end(), NewMatchables.begin(),
1480 NewMatchables.end());
1482 // Process token alias definitions and set up the associated superclass
1484 std::vector<Record*> AllTokenAliases =
1485 Records.getAllDerivedDefinitions("TokenAlias");
1486 for (unsigned i = 0, e = AllTokenAliases.size(); i != e; ++i) {
1487 Record *Rec = AllTokenAliases[i];
1488 ClassInfo *FromClass = getTokenClass(Rec->getValueAsString("FromToken"));
1489 ClassInfo *ToClass = getTokenClass(Rec->getValueAsString("ToToken"));
1490 if (FromClass == ToClass)
1491 PrintFatalError(Rec->getLoc(),
1492 "error: Destination value identical to source value.");
1493 FromClass->SuperClasses.push_back(ToClass);
1496 // Reorder classes so that classes precede super classes.
1497 std::sort(Classes.begin(), Classes.end(), less_ptr<ClassInfo>());
1500 /// buildInstructionOperandReference - The specified operand is a reference to a
1501 /// named operand such as $src. Resolve the Class and OperandInfo pointers.
1502 void AsmMatcherInfo::
1503 buildInstructionOperandReference(MatchableInfo *II,
1504 StringRef OperandName,
1505 unsigned AsmOpIdx) {
1506 const CodeGenInstruction &CGI = *II->DefRec.get<const CodeGenInstruction*>();
1507 const CGIOperandList &Operands = CGI.Operands;
1508 MatchableInfo::AsmOperand *Op = &II->AsmOperands[AsmOpIdx];
1510 // Map this token to an operand.
1512 if (!Operands.hasOperandNamed(OperandName, Idx))
1513 PrintFatalError(II->TheDef->getLoc(), "error: unable to find operand: '" +
1514 OperandName.str() + "'");
1516 // If the instruction operand has multiple suboperands, but the parser
1517 // match class for the asm operand is still the default "ImmAsmOperand",
1518 // then handle each suboperand separately.
1519 if (Op->SubOpIdx == -1 && Operands[Idx].MINumOperands > 1) {
1520 Record *Rec = Operands[Idx].Rec;
1521 assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
1522 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1523 if (MatchClass && MatchClass->getValueAsString("Name") == "Imm") {
1524 // Insert remaining suboperands after AsmOpIdx in II->AsmOperands.
1525 StringRef Token = Op->Token; // save this in case Op gets moved
1526 for (unsigned SI = 1, SE = Operands[Idx].MINumOperands; SI != SE; ++SI) {
1527 MatchableInfo::AsmOperand NewAsmOp(Token);
1528 NewAsmOp.SubOpIdx = SI;
1529 II->AsmOperands.insert(II->AsmOperands.begin()+AsmOpIdx+SI, NewAsmOp);
1531 // Replace Op with first suboperand.
1532 Op = &II->AsmOperands[AsmOpIdx]; // update the pointer in case it moved
1537 // Set up the operand class.
1538 Op->Class = getOperandClass(Operands[Idx], Op->SubOpIdx);
1540 // If the named operand is tied, canonicalize it to the untied operand.
1541 // For example, something like:
1542 // (outs GPR:$dst), (ins GPR:$src)
1543 // with an asmstring of
1545 // we want to canonicalize to:
1547 // so that we know how to provide the $dst operand when filling in the result.
1549 if (Operands[Idx].MINumOperands == 1)
1550 OITied = Operands[Idx].getTiedRegister();
1552 // The tied operand index is an MIOperand index, find the operand that
1554 std::pair<unsigned, unsigned> Idx = Operands.getSubOperandNumber(OITied);
1555 OperandName = Operands[Idx.first].Name;
1556 Op->SubOpIdx = Idx.second;
1559 Op->SrcOpName = OperandName;
1562 /// buildAliasOperandReference - When parsing an operand reference out of the
1563 /// matching string (e.g. "movsx $src, $dst"), determine what the class of the
1564 /// operand reference is by looking it up in the result pattern definition.
1565 void AsmMatcherInfo::buildAliasOperandReference(MatchableInfo *II,
1566 StringRef OperandName,
1567 MatchableInfo::AsmOperand &Op) {
1568 const CodeGenInstAlias &CGA = *II->DefRec.get<const CodeGenInstAlias*>();
1570 // Set up the operand class.
1571 for (unsigned i = 0, e = CGA.ResultOperands.size(); i != e; ++i)
1572 if (CGA.ResultOperands[i].isRecord() &&
1573 CGA.ResultOperands[i].getName() == OperandName) {
1574 // It's safe to go with the first one we find, because CodeGenInstAlias
1575 // validates that all operands with the same name have the same record.
1576 Op.SubOpIdx = CGA.ResultInstOperandIndex[i].second;
1577 // Use the match class from the Alias definition, not the
1578 // destination instruction, as we may have an immediate that's
1579 // being munged by the match class.
1580 Op.Class = getOperandClass(CGA.ResultOperands[i].getRecord(),
1582 Op.SrcOpName = OperandName;
1586 PrintFatalError(II->TheDef->getLoc(), "error: unable to find operand: '" +
1587 OperandName.str() + "'");
1590 void MatchableInfo::buildInstructionResultOperands() {
1591 const CodeGenInstruction *ResultInst = getResultInst();
1593 // Loop over all operands of the result instruction, determining how to
1595 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1596 const CGIOperandList::OperandInfo &OpInfo = ResultInst->Operands[i];
1598 // If this is a tied operand, just copy from the previously handled operand.
1600 if (OpInfo.MINumOperands == 1)
1601 TiedOp = OpInfo.getTiedRegister();
1603 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1607 // Find out what operand from the asmparser this MCInst operand comes from.
1608 int SrcOperand = findAsmOperandNamed(OpInfo.Name);
1609 if (OpInfo.Name.empty() || SrcOperand == -1) {
1610 // This may happen for operands that are tied to a suboperand of a
1611 // complex operand. Simply use a dummy value here; nobody should
1612 // use this operand slot.
1613 // FIXME: The long term goal is for the MCOperand list to not contain
1614 // tied operands at all.
1615 ResOperands.push_back(ResOperand::getImmOp(0));
1619 // Check if the one AsmOperand populates the entire operand.
1620 unsigned NumOperands = OpInfo.MINumOperands;
1621 if (AsmOperands[SrcOperand].SubOpIdx == -1) {
1622 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, NumOperands));
1626 // Add a separate ResOperand for each suboperand.
1627 for (unsigned AI = 0; AI < NumOperands; ++AI) {
1628 assert(AsmOperands[SrcOperand+AI].SubOpIdx == (int)AI &&
1629 AsmOperands[SrcOperand+AI].SrcOpName == OpInfo.Name &&
1630 "unexpected AsmOperands for suboperands");
1631 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand + AI, 1));
1636 void MatchableInfo::buildAliasResultOperands() {
1637 const CodeGenInstAlias &CGA = *DefRec.get<const CodeGenInstAlias*>();
1638 const CodeGenInstruction *ResultInst = getResultInst();
1640 // Loop over all operands of the result instruction, determining how to
1642 unsigned AliasOpNo = 0;
1643 unsigned LastOpNo = CGA.ResultInstOperandIndex.size();
1644 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1645 const CGIOperandList::OperandInfo *OpInfo = &ResultInst->Operands[i];
1647 // If this is a tied operand, just copy from the previously handled operand.
1649 if (OpInfo->MINumOperands == 1)
1650 TiedOp = OpInfo->getTiedRegister();
1652 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1656 // Handle all the suboperands for this operand.
1657 const std::string &OpName = OpInfo->Name;
1658 for ( ; AliasOpNo < LastOpNo &&
1659 CGA.ResultInstOperandIndex[AliasOpNo].first == i; ++AliasOpNo) {
1660 int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second;
1662 // Find out what operand from the asmparser that this MCInst operand
1664 switch (CGA.ResultOperands[AliasOpNo].Kind) {
1665 case CodeGenInstAlias::ResultOperand::K_Record: {
1666 StringRef Name = CGA.ResultOperands[AliasOpNo].getName();
1667 int SrcOperand = findAsmOperand(Name, SubIdx);
1668 if (SrcOperand == -1)
1669 PrintFatalError(TheDef->getLoc(), "Instruction '" +
1670 TheDef->getName() + "' has operand '" + OpName +
1671 "' that doesn't appear in asm string!");
1672 unsigned NumOperands = (SubIdx == -1 ? OpInfo->MINumOperands : 1);
1673 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand,
1677 case CodeGenInstAlias::ResultOperand::K_Imm: {
1678 int64_t ImmVal = CGA.ResultOperands[AliasOpNo].getImm();
1679 ResOperands.push_back(ResOperand::getImmOp(ImmVal));
1682 case CodeGenInstAlias::ResultOperand::K_Reg: {
1683 Record *Reg = CGA.ResultOperands[AliasOpNo].getRegister();
1684 ResOperands.push_back(ResOperand::getRegOp(Reg));
1692 static unsigned getConverterOperandID(const std::string &Name,
1693 SetVector<std::string> &Table,
1695 IsNew = Table.insert(Name);
1697 unsigned ID = IsNew ? Table.size() - 1 :
1698 std::find(Table.begin(), Table.end(), Name) - Table.begin();
1700 assert(ID < Table.size());
1706 static void emitConvertFuncs(CodeGenTarget &Target, StringRef ClassName,
1707 std::vector<MatchableInfo*> &Infos,
1709 SetVector<std::string> OperandConversionKinds;
1710 SetVector<std::string> InstructionConversionKinds;
1711 std::vector<std::vector<uint8_t> > ConversionTable;
1712 size_t MaxRowLength = 2; // minimum is custom converter plus terminator.
1714 // TargetOperandClass - This is the target's operand class, like X86Operand.
1715 std::string TargetOperandClass = Target.getName() + "Operand";
1717 // Write the convert function to a separate stream, so we can drop it after
1718 // the enum. We'll build up the conversion handlers for the individual
1719 // operand types opportunistically as we encounter them.
1720 std::string ConvertFnBody;
1721 raw_string_ostream CvtOS(ConvertFnBody);
1722 // Start the unified conversion function.
1723 CvtOS << "void " << Target.getName() << ClassName << "::\n"
1724 << "convertToMCInst(unsigned Kind, MCInst &Inst, "
1725 << "unsigned Opcode,\n"
1726 << " const SmallVectorImpl<MCParsedAsmOperand*"
1727 << "> &Operands) {\n"
1728 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
1729 << " const uint8_t *Converter = ConversionTable[Kind];\n"
1730 << " Inst.setOpcode(Opcode);\n"
1731 << " for (const uint8_t *p = Converter; *p; p+= 2) {\n"
1732 << " switch (*p) {\n"
1733 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
1734 << " case CVT_Reg:\n"
1735 << " static_cast<" << TargetOperandClass
1736 << "*>(Operands[*(p + 1)])->addRegOperands(Inst, 1);\n"
1738 << " case CVT_Tied:\n"
1739 << " Inst.addOperand(Inst.getOperand(*(p + 1)));\n"
1742 std::string OperandFnBody;
1743 raw_string_ostream OpOS(OperandFnBody);
1744 // Start the operand number lookup function.
1745 OpOS << "void " << Target.getName() << ClassName << "::\n"
1746 << "convertToMapAndConstraints(unsigned Kind,\n";
1748 OpOS << "const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {\n"
1749 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
1750 << " unsigned NumMCOperands = 0;\n"
1751 << " const uint8_t *Converter = ConversionTable[Kind];\n"
1752 << " for (const uint8_t *p = Converter; *p; p+= 2) {\n"
1753 << " switch (*p) {\n"
1754 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
1755 << " case CVT_Reg:\n"
1756 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1757 << " Operands[*(p + 1)]->setConstraint(\"r\");\n"
1758 << " ++NumMCOperands;\n"
1760 << " case CVT_Tied:\n"
1761 << " ++NumMCOperands;\n"
1764 // Pre-populate the operand conversion kinds with the standard always
1765 // available entries.
1766 OperandConversionKinds.insert("CVT_Done");
1767 OperandConversionKinds.insert("CVT_Reg");
1768 OperandConversionKinds.insert("CVT_Tied");
1769 enum { CVT_Done, CVT_Reg, CVT_Tied };
1771 for (std::vector<MatchableInfo*>::const_iterator it = Infos.begin(),
1772 ie = Infos.end(); it != ie; ++it) {
1773 MatchableInfo &II = **it;
1775 // Check if we have a custom match function.
1776 std::string AsmMatchConverter =
1777 II.getResultInst()->TheDef->getValueAsString("AsmMatchConverter");
1778 if (!AsmMatchConverter.empty()) {
1779 std::string Signature = "ConvertCustom_" + AsmMatchConverter;
1780 II.ConversionFnKind = Signature;
1782 // Check if we have already generated this signature.
1783 if (!InstructionConversionKinds.insert(Signature))
1786 // Remember this converter for the kind enum.
1787 unsigned KindID = OperandConversionKinds.size();
1788 OperandConversionKinds.insert("CVT_" +
1789 getEnumNameForToken(AsmMatchConverter));
1791 // Add the converter row for this instruction.
1792 ConversionTable.push_back(std::vector<uint8_t>());
1793 ConversionTable.back().push_back(KindID);
1794 ConversionTable.back().push_back(CVT_Done);
1796 // Add the handler to the conversion driver function.
1797 CvtOS << " case CVT_"
1798 << getEnumNameForToken(AsmMatchConverter) << ":\n"
1799 << " " << AsmMatchConverter << "(Inst, Operands);\n"
1802 // FIXME: Handle the operand number lookup for custom match functions.
1806 // Build the conversion function signature.
1807 std::string Signature = "Convert";
1809 std::vector<uint8_t> ConversionRow;
1811 // Compute the convert enum and the case body.
1812 MaxRowLength = std::max(MaxRowLength, II.ResOperands.size()*2 + 1 );
1814 for (unsigned i = 0, e = II.ResOperands.size(); i != e; ++i) {
1815 const MatchableInfo::ResOperand &OpInfo = II.ResOperands[i];
1817 // Generate code to populate each result operand.
1818 switch (OpInfo.Kind) {
1819 case MatchableInfo::ResOperand::RenderAsmOperand: {
1820 // This comes from something we parsed.
1821 MatchableInfo::AsmOperand &Op = II.AsmOperands[OpInfo.AsmOperandNum];
1823 // Registers are always converted the same, don't duplicate the
1824 // conversion function based on them.
1827 Class = Op.Class->isRegisterClass() ? "Reg" : Op.Class->ClassName;
1829 Signature += utostr(OpInfo.MINumOperands);
1830 Signature += "_" + itostr(OpInfo.AsmOperandNum);
1832 // Add the conversion kind, if necessary, and get the associated ID
1833 // the index of its entry in the vector).
1834 std::string Name = "CVT_" + (Op.Class->isRegisterClass() ? "Reg" :
1835 Op.Class->RenderMethod);
1836 Name = getEnumNameForToken(Name);
1838 bool IsNewConverter = false;
1839 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1842 // Add the operand entry to the instruction kind conversion row.
1843 ConversionRow.push_back(ID);
1844 ConversionRow.push_back(OpInfo.AsmOperandNum + 1);
1846 if (!IsNewConverter)
1849 // This is a new operand kind. Add a handler for it to the
1850 // converter driver.
1851 CvtOS << " case " << Name << ":\n"
1852 << " static_cast<" << TargetOperandClass
1853 << "*>(Operands[*(p + 1)])->"
1854 << Op.Class->RenderMethod << "(Inst, " << OpInfo.MINumOperands
1858 // Add a handler for the operand number lookup.
1859 OpOS << " case " << Name << ":\n"
1860 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n";
1862 if (Op.Class->isRegisterClass())
1863 OpOS << " Operands[*(p + 1)]->setConstraint(\"r\");\n";
1865 OpOS << " Operands[*(p + 1)]->setConstraint(\"m\");\n";
1866 OpOS << " NumMCOperands += " << OpInfo.MINumOperands << ";\n"
1870 case MatchableInfo::ResOperand::TiedOperand: {
1871 // If this operand is tied to a previous one, just copy the MCInst
1872 // operand from the earlier one.We can only tie single MCOperand values.
1873 assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand");
1874 unsigned TiedOp = OpInfo.TiedOperandNum;
1875 assert(i > TiedOp && "Tied operand precedes its target!");
1876 Signature += "__Tie" + utostr(TiedOp);
1877 ConversionRow.push_back(CVT_Tied);
1878 ConversionRow.push_back(TiedOp);
1881 case MatchableInfo::ResOperand::ImmOperand: {
1882 int64_t Val = OpInfo.ImmVal;
1883 std::string Ty = "imm_" + itostr(Val);
1884 Signature += "__" + Ty;
1886 std::string Name = "CVT_" + Ty;
1887 bool IsNewConverter = false;
1888 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1890 // Add the operand entry to the instruction kind conversion row.
1891 ConversionRow.push_back(ID);
1892 ConversionRow.push_back(0);
1894 if (!IsNewConverter)
1897 CvtOS << " case " << Name << ":\n"
1898 << " Inst.addOperand(MCOperand::CreateImm(" << Val << "));\n"
1901 OpOS << " case " << Name << ":\n"
1902 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1903 << " Operands[*(p + 1)]->setConstraint(\"\");\n"
1904 << " ++NumMCOperands;\n"
1908 case MatchableInfo::ResOperand::RegOperand: {
1909 std::string Reg, Name;
1910 if (OpInfo.Register == 0) {
1914 Reg = getQualifiedName(OpInfo.Register);
1915 Name = "reg" + OpInfo.Register->getName();
1917 Signature += "__" + Name;
1918 Name = "CVT_" + Name;
1919 bool IsNewConverter = false;
1920 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1922 // Add the operand entry to the instruction kind conversion row.
1923 ConversionRow.push_back(ID);
1924 ConversionRow.push_back(0);
1926 if (!IsNewConverter)
1928 CvtOS << " case " << Name << ":\n"
1929 << " Inst.addOperand(MCOperand::CreateReg(" << Reg << "));\n"
1932 OpOS << " case " << Name << ":\n"
1933 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1934 << " Operands[*(p + 1)]->setConstraint(\"m\");\n"
1935 << " ++NumMCOperands;\n"
1941 // If there were no operands, add to the signature to that effect
1942 if (Signature == "Convert")
1943 Signature += "_NoOperands";
1945 II.ConversionFnKind = Signature;
1947 // Save the signature. If we already have it, don't add a new row
1949 if (!InstructionConversionKinds.insert(Signature))
1952 // Add the row to the table.
1953 ConversionTable.push_back(ConversionRow);
1956 // Finish up the converter driver function.
1957 CvtOS << " }\n }\n}\n\n";
1959 // Finish up the operand number lookup function.
1960 OpOS << " }\n }\n}\n\n";
1962 OS << "namespace {\n";
1964 // Output the operand conversion kind enum.
1965 OS << "enum OperatorConversionKind {\n";
1966 for (unsigned i = 0, e = OperandConversionKinds.size(); i != e; ++i)
1967 OS << " " << OperandConversionKinds[i] << ",\n";
1968 OS << " CVT_NUM_CONVERTERS\n";
1971 // Output the instruction conversion kind enum.
1972 OS << "enum InstructionConversionKind {\n";
1973 for (SetVector<std::string>::const_iterator
1974 i = InstructionConversionKinds.begin(),
1975 e = InstructionConversionKinds.end(); i != e; ++i)
1976 OS << " " << *i << ",\n";
1977 OS << " CVT_NUM_SIGNATURES\n";
1981 OS << "} // end anonymous namespace\n\n";
1983 // Output the conversion table.
1984 OS << "static const uint8_t ConversionTable[CVT_NUM_SIGNATURES]["
1985 << MaxRowLength << "] = {\n";
1987 for (unsigned Row = 0, ERow = ConversionTable.size(); Row != ERow; ++Row) {
1988 assert(ConversionTable[Row].size() % 2 == 0 && "bad conversion row!");
1989 OS << " // " << InstructionConversionKinds[Row] << "\n";
1991 for (unsigned i = 0, e = ConversionTable[Row].size(); i != e; i += 2)
1992 OS << OperandConversionKinds[ConversionTable[Row][i]] << ", "
1993 << (unsigned)(ConversionTable[Row][i + 1]) << ", ";
1994 OS << "CVT_Done },\n";
1999 // Spit out the conversion driver function.
2002 // Spit out the operand number lookup function.
2006 /// emitMatchClassEnumeration - Emit the enumeration for match class kinds.
2007 static void emitMatchClassEnumeration(CodeGenTarget &Target,
2008 std::vector<ClassInfo*> &Infos,
2010 OS << "namespace {\n\n";
2012 OS << "/// MatchClassKind - The kinds of classes which participate in\n"
2013 << "/// instruction matching.\n";
2014 OS << "enum MatchClassKind {\n";
2015 OS << " InvalidMatchClass = 0,\n";
2016 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
2017 ie = Infos.end(); it != ie; ++it) {
2018 ClassInfo &CI = **it;
2019 OS << " " << CI.Name << ", // ";
2020 if (CI.Kind == ClassInfo::Token) {
2021 OS << "'" << CI.ValueName << "'\n";
2022 } else if (CI.isRegisterClass()) {
2023 if (!CI.ValueName.empty())
2024 OS << "register class '" << CI.ValueName << "'\n";
2026 OS << "derived register class\n";
2028 OS << "user defined class '" << CI.ValueName << "'\n";
2031 OS << " NumMatchClassKinds\n";
2037 /// emitValidateOperandClass - Emit the function to validate an operand class.
2038 static void emitValidateOperandClass(AsmMatcherInfo &Info,
2040 OS << "static unsigned validateOperandClass(MCParsedAsmOperand *GOp, "
2041 << "MatchClassKind Kind) {\n";
2042 OS << " " << Info.Target.getName() << "Operand &Operand = *("
2043 << Info.Target.getName() << "Operand*)GOp;\n";
2045 // The InvalidMatchClass is not to match any operand.
2046 OS << " if (Kind == InvalidMatchClass)\n";
2047 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n\n";
2049 // Check for Token operands first.
2050 // FIXME: Use a more specific diagnostic type.
2051 OS << " if (Operand.isToken())\n";
2052 OS << " return isSubclass(matchTokenString(Operand.getToken()), Kind) ?\n"
2053 << " MCTargetAsmParser::Match_Success :\n"
2054 << " MCTargetAsmParser::Match_InvalidOperand;\n\n";
2056 // Check the user classes. We don't care what order since we're only
2057 // actually matching against one of them.
2058 for (std::vector<ClassInfo*>::iterator it = Info.Classes.begin(),
2059 ie = Info.Classes.end(); it != ie; ++it) {
2060 ClassInfo &CI = **it;
2062 if (!CI.isUserClass())
2065 OS << " // '" << CI.ClassName << "' class\n";
2066 OS << " if (Kind == " << CI.Name << ") {\n";
2067 OS << " if (Operand." << CI.PredicateMethod << "())\n";
2068 OS << " return MCTargetAsmParser::Match_Success;\n";
2069 if (!CI.DiagnosticType.empty())
2070 OS << " return " << Info.Target.getName() << "AsmParser::Match_"
2071 << CI.DiagnosticType << ";\n";
2075 // Check for register operands, including sub-classes.
2076 OS << " if (Operand.isReg()) {\n";
2077 OS << " MatchClassKind OpKind;\n";
2078 OS << " switch (Operand.getReg()) {\n";
2079 OS << " default: OpKind = InvalidMatchClass; break;\n";
2080 for (AsmMatcherInfo::RegisterClassesTy::iterator
2081 it = Info.RegisterClasses.begin(), ie = Info.RegisterClasses.end();
2083 OS << " case " << Info.Target.getName() << "::"
2084 << it->first->getName() << ": OpKind = " << it->second->Name
2087 OS << " return isSubclass(OpKind, Kind) ? "
2088 << "MCTargetAsmParser::Match_Success :\n "
2089 << " MCTargetAsmParser::Match_InvalidOperand;\n }\n\n";
2091 // Generic fallthrough match failure case for operands that don't have
2092 // specialized diagnostic types.
2093 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n";
2097 /// emitIsSubclass - Emit the subclass predicate function.
2098 static void emitIsSubclass(CodeGenTarget &Target,
2099 std::vector<ClassInfo*> &Infos,
2101 OS << "/// isSubclass - Compute whether \\p A is a subclass of \\p B.\n";
2102 OS << "static bool isSubclass(MatchClassKind A, MatchClassKind B) {\n";
2103 OS << " if (A == B)\n";
2104 OS << " return true;\n\n";
2107 raw_string_ostream SS(OStr);
2109 SS << " switch (A) {\n";
2110 SS << " default:\n";
2111 SS << " return false;\n";
2112 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
2113 ie = Infos.end(); it != ie; ++it) {
2114 ClassInfo &A = **it;
2116 std::vector<StringRef> SuperClasses;
2117 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
2118 ie = Infos.end(); it != ie; ++it) {
2119 ClassInfo &B = **it;
2121 if (&A != &B && A.isSubsetOf(B))
2122 SuperClasses.push_back(B.Name);
2125 if (SuperClasses.empty())
2129 SS << "\n case " << A.Name << ":\n";
2131 if (SuperClasses.size() == 1) {
2132 SS << " return B == " << SuperClasses.back().str() << ";\n";
2136 if (!SuperClasses.empty()) {
2137 SS << " switch (B) {\n";
2138 SS << " default: return false;\n";
2139 for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i)
2140 SS << " case " << SuperClasses[i].str() << ": return true;\n";
2143 // No case statement to emit
2144 SS << " return false;\n";
2149 // If there were case statements emitted into the string stream, write them
2150 // to the output stream, otherwise write the default.
2154 OS << " return false;\n";
2159 /// emitMatchTokenString - Emit the function to match a token string to the
2160 /// appropriate match class value.
2161 static void emitMatchTokenString(CodeGenTarget &Target,
2162 std::vector<ClassInfo*> &Infos,
2164 // Construct the match list.
2165 std::vector<StringMatcher::StringPair> Matches;
2166 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
2167 ie = Infos.end(); it != ie; ++it) {
2168 ClassInfo &CI = **it;
2170 if (CI.Kind == ClassInfo::Token)
2171 Matches.push_back(StringMatcher::StringPair(CI.ValueName,
2172 "return " + CI.Name + ";"));
2175 OS << "static MatchClassKind matchTokenString(StringRef Name) {\n";
2177 StringMatcher("Name", Matches, OS).Emit();
2179 OS << " return InvalidMatchClass;\n";
2183 /// emitMatchRegisterName - Emit the function to match a string to the target
2184 /// specific register enum.
2185 static void emitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
2187 // Construct the match list.
2188 std::vector<StringMatcher::StringPair> Matches;
2189 const std::vector<CodeGenRegister*> &Regs =
2190 Target.getRegBank().getRegisters();
2191 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
2192 const CodeGenRegister *Reg = Regs[i];
2193 if (Reg->TheDef->getValueAsString("AsmName").empty())
2196 Matches.push_back(StringMatcher::StringPair(
2197 Reg->TheDef->getValueAsString("AsmName"),
2198 "return " + utostr(Reg->EnumValue) + ";"));
2201 OS << "static unsigned MatchRegisterName(StringRef Name) {\n";
2203 StringMatcher("Name", Matches, OS).Emit();
2205 OS << " return 0;\n";
2209 /// emitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag
2211 static void emitSubtargetFeatureFlagEnumeration(AsmMatcherInfo &Info,
2213 OS << "// Flags for subtarget features that participate in "
2214 << "instruction matching.\n";
2215 OS << "enum SubtargetFeatureFlag {\n";
2216 for (std::map<Record*, SubtargetFeatureInfo*, LessRecordByID>::const_iterator
2217 it = Info.SubtargetFeatures.begin(),
2218 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
2219 SubtargetFeatureInfo &SFI = *it->second;
2220 OS << " " << SFI.getEnumName() << " = (1 << " << SFI.Index << "),\n";
2222 OS << " Feature_None = 0\n";
2226 /// emitOperandDiagnosticTypes - Emit the operand matching diagnostic types.
2227 static void emitOperandDiagnosticTypes(AsmMatcherInfo &Info, raw_ostream &OS) {
2228 // Get the set of diagnostic types from all of the operand classes.
2229 std::set<StringRef> Types;
2230 for (std::map<Record*, ClassInfo*>::const_iterator
2231 I = Info.AsmOperandClasses.begin(),
2232 E = Info.AsmOperandClasses.end(); I != E; ++I) {
2233 if (!I->second->DiagnosticType.empty())
2234 Types.insert(I->second->DiagnosticType);
2237 if (Types.empty()) return;
2239 // Now emit the enum entries.
2240 for (std::set<StringRef>::const_iterator I = Types.begin(), E = Types.end();
2242 OS << " Match_" << *I << ",\n";
2243 OS << " END_OPERAND_DIAGNOSTIC_TYPES\n";
2246 /// emitGetSubtargetFeatureName - Emit the helper function to get the
2247 /// user-level name for a subtarget feature.
2248 static void emitGetSubtargetFeatureName(AsmMatcherInfo &Info, raw_ostream &OS) {
2249 OS << "// User-level names for subtarget features that participate in\n"
2250 << "// instruction matching.\n"
2251 << "static const char *getSubtargetFeatureName(unsigned Val) {\n";
2252 if (!Info.SubtargetFeatures.empty()) {
2253 OS << " switch(Val) {\n";
2254 typedef std::map<Record*, SubtargetFeatureInfo*, LessRecordByID> RecFeatMap;
2255 for (RecFeatMap::const_iterator it = Info.SubtargetFeatures.begin(),
2256 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
2257 SubtargetFeatureInfo &SFI = *it->second;
2258 // FIXME: Totally just a placeholder name to get the algorithm working.
2259 OS << " case " << SFI.getEnumName() << ": return \""
2260 << SFI.TheDef->getValueAsString("PredicateName") << "\";\n";
2262 OS << " default: return \"(unknown)\";\n";
2265 // Nothing to emit, so skip the switch
2266 OS << " return \"(unknown)\";\n";
2271 /// emitComputeAvailableFeatures - Emit the function to compute the list of
2272 /// available features given a subtarget.
2273 static void emitComputeAvailableFeatures(AsmMatcherInfo &Info,
2275 std::string ClassName =
2276 Info.AsmParser->getValueAsString("AsmParserClassName");
2278 OS << "unsigned " << Info.Target.getName() << ClassName << "::\n"
2279 << "ComputeAvailableFeatures(uint64_t FB) const {\n";
2280 OS << " unsigned Features = 0;\n";
2281 for (std::map<Record*, SubtargetFeatureInfo*, LessRecordByID>::const_iterator
2282 it = Info.SubtargetFeatures.begin(),
2283 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
2284 SubtargetFeatureInfo &SFI = *it->second;
2287 std::string CondStorage =
2288 SFI.TheDef->getValueAsString("AssemblerCondString");
2289 StringRef Conds = CondStorage;
2290 std::pair<StringRef,StringRef> Comma = Conds.split(',');
2297 StringRef Cond = Comma.first;
2298 if (Cond[0] == '!') {
2300 Cond = Cond.substr(1);
2303 OS << "((FB & " << Info.Target.getName() << "::" << Cond << ")";
2310 if (Comma.second.empty())
2314 Comma = Comma.second.split(',');
2318 OS << " Features |= " << SFI.getEnumName() << ";\n";
2320 OS << " return Features;\n";
2324 static std::string GetAliasRequiredFeatures(Record *R,
2325 const AsmMatcherInfo &Info) {
2326 std::vector<Record*> ReqFeatures = R->getValueAsListOfDefs("Predicates");
2328 unsigned NumFeatures = 0;
2329 for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) {
2330 SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]);
2333 PrintFatalError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() +
2334 "' is not marked as an AssemblerPredicate!");
2339 Result += F->getEnumName();
2343 if (NumFeatures > 1)
2344 Result = '(' + Result + ')';
2348 static void emitMnemonicAliasVariant(raw_ostream &OS,const AsmMatcherInfo &Info,
2349 std::vector<Record*> &Aliases,
2350 unsigned Indent = 0,
2351 StringRef AsmParserVariantName = StringRef()){
2352 // Keep track of all the aliases from a mnemonic. Use an std::map so that the
2353 // iteration order of the map is stable.
2354 std::map<std::string, std::vector<Record*> > AliasesFromMnemonic;
2356 for (unsigned i = 0, e = Aliases.size(); i != e; ++i) {
2357 Record *R = Aliases[i];
2358 // FIXME: Allow AssemblerVariantName to be a comma separated list.
2359 std::string AsmVariantName = R->getValueAsString("AsmVariantName");
2360 if (AsmVariantName != AsmParserVariantName)
2362 AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R);
2364 if (AliasesFromMnemonic.empty())
2367 // Process each alias a "from" mnemonic at a time, building the code executed
2368 // by the string remapper.
2369 std::vector<StringMatcher::StringPair> Cases;
2370 for (std::map<std::string, std::vector<Record*> >::iterator
2371 I = AliasesFromMnemonic.begin(), E = AliasesFromMnemonic.end();
2373 const std::vector<Record*> &ToVec = I->second;
2375 // Loop through each alias and emit code that handles each case. If there
2376 // are two instructions without predicates, emit an error. If there is one,
2378 std::string MatchCode;
2379 int AliasWithNoPredicate = -1;
2381 for (unsigned i = 0, e = ToVec.size(); i != e; ++i) {
2382 Record *R = ToVec[i];
2383 std::string FeatureMask = GetAliasRequiredFeatures(R, Info);
2385 // If this unconditionally matches, remember it for later and diagnose
2387 if (FeatureMask.empty()) {
2388 if (AliasWithNoPredicate != -1) {
2389 // We can't have two aliases from the same mnemonic with no predicate.
2390 PrintError(ToVec[AliasWithNoPredicate]->getLoc(),
2391 "two MnemonicAliases with the same 'from' mnemonic!");
2392 PrintFatalError(R->getLoc(), "this is the other MnemonicAlias.");
2395 AliasWithNoPredicate = i;
2398 if (R->getValueAsString("ToMnemonic") == I->first)
2399 PrintFatalError(R->getLoc(), "MnemonicAlias to the same string");
2401 if (!MatchCode.empty())
2402 MatchCode += "else ";
2403 MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n";
2404 MatchCode += " Mnemonic = \"" +R->getValueAsString("ToMnemonic")+"\";\n";
2407 if (AliasWithNoPredicate != -1) {
2408 Record *R = ToVec[AliasWithNoPredicate];
2409 if (!MatchCode.empty())
2410 MatchCode += "else\n ";
2411 MatchCode += "Mnemonic = \"" + R->getValueAsString("ToMnemonic")+"\";\n";
2414 MatchCode += "return;";
2416 Cases.push_back(std::make_pair(I->first, MatchCode));
2418 StringMatcher("Mnemonic", Cases, OS).Emit(Indent);
2421 /// emitMnemonicAliases - If the target has any MnemonicAlias<> definitions,
2422 /// emit a function for them and return true, otherwise return false.
2423 static bool emitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info,
2424 CodeGenTarget &Target) {
2425 // Ignore aliases when match-prefix is set.
2426 if (!MatchPrefix.empty())
2429 std::vector<Record*> Aliases =
2430 Info.getRecords().getAllDerivedDefinitions("MnemonicAlias");
2431 if (Aliases.empty()) return false;
2433 OS << "static void applyMnemonicAliases(StringRef &Mnemonic, "
2434 "unsigned Features, unsigned VariantID) {\n";
2435 OS << " switch (VariantID) {\n";
2436 unsigned VariantCount = Target.getAsmParserVariantCount();
2437 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2438 Record *AsmVariant = Target.getAsmParserVariant(VC);
2439 int AsmParserVariantNo = AsmVariant->getValueAsInt("Variant");
2440 std::string AsmParserVariantName = AsmVariant->getValueAsString("Name");
2441 OS << " case " << AsmParserVariantNo << ":\n";
2442 emitMnemonicAliasVariant(OS, Info, Aliases, /*Indent=*/2,
2443 AsmParserVariantName);
2448 // Emit aliases that apply to all variants.
2449 emitMnemonicAliasVariant(OS, Info, Aliases);
2456 static const char *getMinimalTypeForRange(uint64_t Range) {
2457 assert(Range < 0xFFFFFFFFULL && "Enum too large");
2465 static void emitCustomOperandParsing(raw_ostream &OS, CodeGenTarget &Target,
2466 const AsmMatcherInfo &Info, StringRef ClassName,
2467 StringToOffsetTable &StringTable,
2468 unsigned MaxMnemonicIndex) {
2469 unsigned MaxMask = 0;
2470 for (std::vector<OperandMatchEntry>::const_iterator it =
2471 Info.OperandMatchInfo.begin(), ie = Info.OperandMatchInfo.end();
2473 MaxMask |= it->OperandMask;
2476 // Emit the static custom operand parsing table;
2477 OS << "namespace {\n";
2478 OS << " struct OperandMatchEntry {\n";
2479 OS << " " << getMinimalTypeForRange(1ULL << Info.SubtargetFeatures.size())
2480 << " RequiredFeatures;\n";
2481 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex)
2483 OS << " " << getMinimalTypeForRange(Info.Classes.size())
2485 OS << " " << getMinimalTypeForRange(MaxMask)
2486 << " OperandMask;\n\n";
2487 OS << " StringRef getMnemonic() const {\n";
2488 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2489 OS << " MnemonicTable[Mnemonic]);\n";
2493 OS << " // Predicate for searching for an opcode.\n";
2494 OS << " struct LessOpcodeOperand {\n";
2495 OS << " bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {\n";
2496 OS << " return LHS.getMnemonic() < RHS;\n";
2498 OS << " bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {\n";
2499 OS << " return LHS < RHS.getMnemonic();\n";
2501 OS << " bool operator()(const OperandMatchEntry &LHS,";
2502 OS << " const OperandMatchEntry &RHS) {\n";
2503 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2507 OS << "} // end anonymous namespace.\n\n";
2509 OS << "static const OperandMatchEntry OperandMatchTable["
2510 << Info.OperandMatchInfo.size() << "] = {\n";
2512 OS << " /* Operand List Mask, Mnemonic, Operand Class, Features */\n";
2513 for (std::vector<OperandMatchEntry>::const_iterator it =
2514 Info.OperandMatchInfo.begin(), ie = Info.OperandMatchInfo.end();
2516 const OperandMatchEntry &OMI = *it;
2517 const MatchableInfo &II = *OMI.MI;
2521 // Write the required features mask.
2522 if (!II.RequiredFeatures.empty()) {
2523 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
2525 OS << II.RequiredFeatures[i]->getEnumName();
2530 // Store a pascal-style length byte in the mnemonic.
2531 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2532 OS << ", " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2533 << " /* " << II.Mnemonic << " */, ";
2537 OS << ", " << OMI.OperandMask;
2539 bool printComma = false;
2540 for (int i = 0, e = 31; i !=e; ++i)
2541 if (OMI.OperandMask & (1 << i)) {
2553 // Emit the operand class switch to call the correct custom parser for
2554 // the found operand class.
2555 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
2556 << Target.getName() << ClassName << "::\n"
2557 << "tryCustomParseOperand(SmallVectorImpl<MCParsedAsmOperand*>"
2558 << " &Operands,\n unsigned MCK) {\n\n"
2559 << " switch(MCK) {\n";
2561 for (std::vector<ClassInfo*>::const_iterator it = Info.Classes.begin(),
2562 ie = Info.Classes.end(); it != ie; ++it) {
2563 ClassInfo *CI = *it;
2564 if (CI->ParserMethod.empty())
2566 OS << " case " << CI->Name << ":\n"
2567 << " return " << CI->ParserMethod << "(Operands);\n";
2570 OS << " default:\n";
2571 OS << " return MatchOperand_NoMatch;\n";
2573 OS << " return MatchOperand_NoMatch;\n";
2576 // Emit the static custom operand parser. This code is very similar with
2577 // the other matcher. Also use MatchResultTy here just in case we go for
2578 // a better error handling.
2579 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
2580 << Target.getName() << ClassName << "::\n"
2581 << "MatchOperandParserImpl(SmallVectorImpl<MCParsedAsmOperand*>"
2582 << " &Operands,\n StringRef Mnemonic) {\n";
2584 // Emit code to get the available features.
2585 OS << " // Get the current feature set.\n";
2586 OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n";
2588 OS << " // Get the next operand index.\n";
2589 OS << " unsigned NextOpNum = Operands.size()-1;\n";
2591 // Emit code to search the table.
2592 OS << " // Search the table.\n";
2593 OS << " std::pair<const OperandMatchEntry*, const OperandMatchEntry*>";
2594 OS << " MnemonicRange =\n";
2595 OS << " std::equal_range(OperandMatchTable, OperandMatchTable+"
2596 << Info.OperandMatchInfo.size() << ", Mnemonic,\n"
2597 << " LessOpcodeOperand());\n\n";
2599 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2600 OS << " return MatchOperand_NoMatch;\n\n";
2602 OS << " for (const OperandMatchEntry *it = MnemonicRange.first,\n"
2603 << " *ie = MnemonicRange.second; it != ie; ++it) {\n";
2605 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2606 OS << " assert(Mnemonic == it->getMnemonic());\n\n";
2608 // Emit check that the required features are available.
2609 OS << " // check if the available features match\n";
2610 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2611 << "!= it->RequiredFeatures) {\n";
2612 OS << " continue;\n";
2615 // Emit check to ensure the operand number matches.
2616 OS << " // check if the operand in question has a custom parser.\n";
2617 OS << " if (!(it->OperandMask & (1 << NextOpNum)))\n";
2618 OS << " continue;\n\n";
2620 // Emit call to the custom parser method
2621 OS << " // call custom parse method to handle the operand\n";
2622 OS << " OperandMatchResultTy Result = ";
2623 OS << "tryCustomParseOperand(Operands, it->Class);\n";
2624 OS << " if (Result != MatchOperand_NoMatch)\n";
2625 OS << " return Result;\n";
2628 OS << " // Okay, we had no match.\n";
2629 OS << " return MatchOperand_NoMatch;\n";
2633 void AsmMatcherEmitter::run(raw_ostream &OS) {
2634 CodeGenTarget Target(Records);
2635 Record *AsmParser = Target.getAsmParser();
2636 std::string ClassName = AsmParser->getValueAsString("AsmParserClassName");
2638 // Compute the information on the instructions to match.
2639 AsmMatcherInfo Info(AsmParser, Target, Records);
2642 // Sort the instruction table using the partial order on classes. We use
2643 // stable_sort to ensure that ambiguous instructions are still
2644 // deterministically ordered.
2645 std::stable_sort(Info.Matchables.begin(), Info.Matchables.end(),
2646 less_ptr<MatchableInfo>());
2648 DEBUG_WITH_TYPE("instruction_info", {
2649 for (std::vector<MatchableInfo*>::iterator
2650 it = Info.Matchables.begin(), ie = Info.Matchables.end();
2655 // Check for ambiguous matchables.
2656 DEBUG_WITH_TYPE("ambiguous_instrs", {
2657 unsigned NumAmbiguous = 0;
2658 for (unsigned i = 0, e = Info.Matchables.size(); i != e; ++i) {
2659 for (unsigned j = i + 1; j != e; ++j) {
2660 MatchableInfo &A = *Info.Matchables[i];
2661 MatchableInfo &B = *Info.Matchables[j];
2663 if (A.couldMatchAmbiguouslyWith(B)) {
2664 errs() << "warning: ambiguous matchables:\n";
2666 errs() << "\nis incomparable with:\n";
2674 errs() << "warning: " << NumAmbiguous
2675 << " ambiguous matchables!\n";
2678 // Compute the information on the custom operand parsing.
2679 Info.buildOperandMatchInfo();
2681 // Write the output.
2683 // Information for the class declaration.
2684 OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
2685 OS << "#undef GET_ASSEMBLER_HEADER\n";
2686 OS << " // This should be included into the middle of the declaration of\n";
2687 OS << " // your subclasses implementation of MCTargetAsmParser.\n";
2688 OS << " unsigned ComputeAvailableFeatures(uint64_t FeatureBits) const;\n";
2689 OS << " void convertToMCInst(unsigned Kind, MCInst &Inst, "
2690 << "unsigned Opcode,\n"
2691 << " const SmallVectorImpl<MCParsedAsmOperand*> "
2693 OS << " void convertToMapAndConstraints(unsigned Kind,\n ";
2694 OS << " const SmallVectorImpl<MCParsedAsmOperand*> &Operands);\n";
2695 OS << " bool mnemonicIsValid(StringRef Mnemonic, unsigned VariantID);\n";
2696 OS << " unsigned MatchInstructionImpl(\n";
2698 OS << "const SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n"
2699 << " MCInst &Inst,\n"
2700 << " unsigned &ErrorInfo,"
2701 << " bool matchingInlineAsm,\n"
2702 << " unsigned VariantID = 0);\n";
2704 if (Info.OperandMatchInfo.size()) {
2705 OS << "\n enum OperandMatchResultTy {\n";
2706 OS << " MatchOperand_Success, // operand matched successfully\n";
2707 OS << " MatchOperand_NoMatch, // operand did not match\n";
2708 OS << " MatchOperand_ParseFail // operand matched but had errors\n";
2710 OS << " OperandMatchResultTy MatchOperandParserImpl(\n";
2711 OS << " SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n";
2712 OS << " StringRef Mnemonic);\n";
2714 OS << " OperandMatchResultTy tryCustomParseOperand(\n";
2715 OS << " SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n";
2716 OS << " unsigned MCK);\n\n";
2719 OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n";
2721 // Emit the operand match diagnostic enum names.
2722 OS << "\n#ifdef GET_OPERAND_DIAGNOSTIC_TYPES\n";
2723 OS << "#undef GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
2724 emitOperandDiagnosticTypes(Info, OS);
2725 OS << "#endif // GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
2728 OS << "\n#ifdef GET_REGISTER_MATCHER\n";
2729 OS << "#undef GET_REGISTER_MATCHER\n\n";
2731 // Emit the subtarget feature enumeration.
2732 emitSubtargetFeatureFlagEnumeration(Info, OS);
2734 // Emit the function to match a register name to number.
2735 // This should be omitted for Mips target
2736 if (AsmParser->getValueAsBit("ShouldEmitMatchRegisterName"))
2737 emitMatchRegisterName(Target, AsmParser, OS);
2739 OS << "#endif // GET_REGISTER_MATCHER\n\n";
2741 OS << "\n#ifdef GET_SUBTARGET_FEATURE_NAME\n";
2742 OS << "#undef GET_SUBTARGET_FEATURE_NAME\n\n";
2744 // Generate the helper function to get the names for subtarget features.
2745 emitGetSubtargetFeatureName(Info, OS);
2747 OS << "#endif // GET_SUBTARGET_FEATURE_NAME\n\n";
2749 OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
2750 OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
2752 // Generate the function that remaps for mnemonic aliases.
2753 bool HasMnemonicAliases = emitMnemonicAliases(OS, Info, Target);
2755 // Generate the convertToMCInst function to convert operands into an MCInst.
2756 // Also, generate the convertToMapAndConstraints function for MS-style inline
2757 // assembly. The latter doesn't actually generate a MCInst.
2758 emitConvertFuncs(Target, ClassName, Info.Matchables, OS);
2760 // Emit the enumeration for classes which participate in matching.
2761 emitMatchClassEnumeration(Target, Info.Classes, OS);
2763 // Emit the routine to match token strings to their match class.
2764 emitMatchTokenString(Target, Info.Classes, OS);
2766 // Emit the subclass predicate routine.
2767 emitIsSubclass(Target, Info.Classes, OS);
2769 // Emit the routine to validate an operand against a match class.
2770 emitValidateOperandClass(Info, OS);
2772 // Emit the available features compute function.
2773 emitComputeAvailableFeatures(Info, OS);
2776 StringToOffsetTable StringTable;
2778 size_t MaxNumOperands = 0;
2779 unsigned MaxMnemonicIndex = 0;
2780 bool HasDeprecation = false;
2781 for (std::vector<MatchableInfo*>::const_iterator it =
2782 Info.Matchables.begin(), ie = Info.Matchables.end();
2784 MatchableInfo &II = **it;
2785 MaxNumOperands = std::max(MaxNumOperands, II.AsmOperands.size());
2786 HasDeprecation |= II.HasDeprecation;
2788 // Store a pascal-style length byte in the mnemonic.
2789 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2790 MaxMnemonicIndex = std::max(MaxMnemonicIndex,
2791 StringTable.GetOrAddStringOffset(LenMnemonic, false));
2794 OS << "static const char *const MnemonicTable =\n";
2795 StringTable.EmitString(OS);
2798 // Emit the static match table; unused classes get initalized to 0 which is
2799 // guaranteed to be InvalidMatchClass.
2801 // FIXME: We can reduce the size of this table very easily. First, we change
2802 // it so that store the kinds in separate bit-fields for each index, which
2803 // only needs to be the max width used for classes at that index (we also need
2804 // to reject based on this during classification). If we then make sure to
2805 // order the match kinds appropriately (putting mnemonics last), then we
2806 // should only end up using a few bits for each class, especially the ones
2807 // following the mnemonic.
2808 OS << "namespace {\n";
2809 OS << " struct MatchEntry {\n";
2810 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex)
2812 OS << " uint16_t Opcode;\n";
2813 OS << " " << getMinimalTypeForRange(Info.Matchables.size())
2815 OS << " " << getMinimalTypeForRange(1ULL << Info.SubtargetFeatures.size())
2816 << " RequiredFeatures;\n";
2817 OS << " " << getMinimalTypeForRange(Info.Classes.size())
2818 << " Classes[" << MaxNumOperands << "];\n";
2819 OS << " StringRef getMnemonic() const {\n";
2820 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2821 OS << " MnemonicTable[Mnemonic]);\n";
2825 OS << " // Predicate for searching for an opcode.\n";
2826 OS << " struct LessOpcode {\n";
2827 OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n";
2828 OS << " return LHS.getMnemonic() < RHS;\n";
2830 OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n";
2831 OS << " return LHS < RHS.getMnemonic();\n";
2833 OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n";
2834 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2838 OS << "} // end anonymous namespace.\n\n";
2840 unsigned VariantCount = Target.getAsmParserVariantCount();
2841 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2842 Record *AsmVariant = Target.getAsmParserVariant(VC);
2843 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2845 OS << "static const MatchEntry MatchTable" << VC << "[] = {\n";
2847 for (std::vector<MatchableInfo*>::const_iterator it =
2848 Info.Matchables.begin(), ie = Info.Matchables.end();
2850 MatchableInfo &II = **it;
2851 if (II.AsmVariantID != AsmVariantNo)
2854 // Store a pascal-style length byte in the mnemonic.
2855 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2856 OS << " { " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2857 << " /* " << II.Mnemonic << " */, "
2858 << Target.getName() << "::"
2859 << II.getResultInst()->TheDef->getName() << ", "
2860 << II.ConversionFnKind << ", ";
2862 // Write the required features mask.
2863 if (!II.RequiredFeatures.empty()) {
2864 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
2866 OS << II.RequiredFeatures[i]->getEnumName();
2872 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) {
2873 MatchableInfo::AsmOperand &Op = II.AsmOperands[i];
2876 OS << Op.Class->Name;
2884 // A method to determine if a mnemonic is in the list.
2885 OS << "bool " << Target.getName() << ClassName << "::\n"
2886 << "mnemonicIsValid(StringRef Mnemonic, unsigned VariantID) {\n";
2887 OS << " // Find the appropriate table for this asm variant.\n";
2888 OS << " const MatchEntry *Start, *End;\n";
2889 OS << " switch (VariantID) {\n";
2890 OS << " default: // unreachable\n";
2891 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2892 Record *AsmVariant = Target.getAsmParserVariant(VC);
2893 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2894 OS << " case " << AsmVariantNo << ": Start = MatchTable" << VC
2895 << "; End = array_endof(MatchTable" << VC << "); break;\n";
2898 OS << " // Search the table.\n";
2899 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
2900 OS << " std::equal_range(Start, End, Mnemonic, LessOpcode());\n";
2901 OS << " return MnemonicRange.first != MnemonicRange.second;\n";
2904 // Finally, build the match function.
2906 << Target.getName() << ClassName << "::\n"
2907 << "MatchInstructionImpl(const SmallVectorImpl<MCParsedAsmOperand*>"
2909 OS << " MCInst &Inst,\n"
2910 << "unsigned &ErrorInfo, bool matchingInlineAsm, unsigned VariantID) {\n";
2912 OS << " // Eliminate obvious mismatches.\n";
2913 OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n";
2914 OS << " ErrorInfo = " << (MaxNumOperands+1) << ";\n";
2915 OS << " return Match_InvalidOperand;\n";
2918 // Emit code to get the available features.
2919 OS << " // Get the current feature set.\n";
2920 OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n";
2922 OS << " // Get the instruction mnemonic, which is the first token.\n";
2923 OS << " StringRef Mnemonic = ((" << Target.getName()
2924 << "Operand*)Operands[0])->getToken();\n\n";
2926 if (HasMnemonicAliases) {
2927 OS << " // Process all MnemonicAliases to remap the mnemonic.\n";
2928 OS << " applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);\n\n";
2931 // Emit code to compute the class list for this operand vector.
2932 OS << " // Some state to try to produce better error messages.\n";
2933 OS << " bool HadMatchOtherThanFeatures = false;\n";
2934 OS << " bool HadMatchOtherThanPredicate = false;\n";
2935 OS << " unsigned RetCode = Match_InvalidOperand;\n";
2936 OS << " unsigned MissingFeatures = ~0U;\n";
2937 OS << " // Set ErrorInfo to the operand that mismatches if it is\n";
2938 OS << " // wrong for all instances of the instruction.\n";
2939 OS << " ErrorInfo = ~0U;\n";
2941 // Emit code to search the table.
2942 OS << " // Find the appropriate table for this asm variant.\n";
2943 OS << " const MatchEntry *Start, *End;\n";
2944 OS << " switch (VariantID) {\n";
2945 OS << " default: // unreachable\n";
2946 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2947 Record *AsmVariant = Target.getAsmParserVariant(VC);
2948 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2949 OS << " case " << AsmVariantNo << ": Start = MatchTable" << VC
2950 << "; End = array_endof(MatchTable" << VC << "); break;\n";
2953 OS << " // Search the table.\n";
2954 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
2955 OS << " std::equal_range(Start, End, Mnemonic, LessOpcode());\n\n";
2957 OS << " // Return a more specific error code if no mnemonics match.\n";
2958 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2959 OS << " return Match_MnemonicFail;\n\n";
2961 OS << " for (const MatchEntry *it = MnemonicRange.first, "
2962 << "*ie = MnemonicRange.second;\n";
2963 OS << " it != ie; ++it) {\n";
2965 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2966 OS << " assert(Mnemonic == it->getMnemonic());\n";
2968 // Emit check that the subclasses match.
2969 OS << " bool OperandsValid = true;\n";
2970 OS << " for (unsigned i = 0; i != " << MaxNumOperands << "; ++i) {\n";
2971 OS << " if (i + 1 >= Operands.size()) {\n";
2972 OS << " OperandsValid = (it->Classes[i] == " <<"InvalidMatchClass);\n";
2973 OS << " if (!OperandsValid) ErrorInfo = i + 1;\n";
2976 OS << " unsigned Diag = validateOperandClass(Operands[i+1],\n";
2978 OS << "(MatchClassKind)it->Classes[i]);\n";
2979 OS << " if (Diag == Match_Success)\n";
2980 OS << " continue;\n";
2981 OS << " // If the generic handler indicates an invalid operand\n";
2982 OS << " // failure, check for a special case.\n";
2983 OS << " if (Diag == Match_InvalidOperand) {\n";
2984 OS << " Diag = validateTargetOperandClass(Operands[i+1],\n";
2986 OS << "(MatchClassKind)it->Classes[i]);\n";
2987 OS << " if (Diag == Match_Success)\n";
2988 OS << " continue;\n";
2990 OS << " // If this operand is broken for all of the instances of this\n";
2991 OS << " // mnemonic, keep track of it so we can report loc info.\n";
2992 OS << " // If we already had a match that only failed due to a\n";
2993 OS << " // target predicate, that diagnostic is preferred.\n";
2994 OS << " if (!HadMatchOtherThanPredicate &&\n";
2995 OS << " (it == MnemonicRange.first || ErrorInfo <= i+1)) {\n";
2996 OS << " ErrorInfo = i+1;\n";
2997 OS << " // InvalidOperand is the default. Prefer specificity.\n";
2998 OS << " if (Diag != Match_InvalidOperand)\n";
2999 OS << " RetCode = Diag;\n";
3001 OS << " // Otherwise, just reject this instance of the mnemonic.\n";
3002 OS << " OperandsValid = false;\n";
3006 OS << " if (!OperandsValid) continue;\n";
3008 // Emit check that the required features are available.
3009 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
3010 << "!= it->RequiredFeatures) {\n";
3011 OS << " HadMatchOtherThanFeatures = true;\n";
3012 OS << " unsigned NewMissingFeatures = it->RequiredFeatures & "
3013 "~AvailableFeatures;\n";
3014 OS << " if (CountPopulation_32(NewMissingFeatures) <=\n"
3015 " CountPopulation_32(MissingFeatures))\n";
3016 OS << " MissingFeatures = NewMissingFeatures;\n";
3017 OS << " continue;\n";
3020 OS << " if (matchingInlineAsm) {\n";
3021 OS << " Inst.setOpcode(it->Opcode);\n";
3022 OS << " convertToMapAndConstraints(it->ConvertFn, Operands);\n";
3023 OS << " return Match_Success;\n";
3025 OS << " // We have selected a definite instruction, convert the parsed\n"
3026 << " // operands into the appropriate MCInst.\n";
3027 OS << " convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n";
3030 // Verify the instruction with the target-specific match predicate function.
3031 OS << " // We have a potential match. Check the target predicate to\n"
3032 << " // handle any context sensitive constraints.\n"
3033 << " unsigned MatchResult;\n"
3034 << " if ((MatchResult = checkTargetMatchPredicate(Inst)) !="
3035 << " Match_Success) {\n"
3036 << " Inst.clear();\n"
3037 << " RetCode = MatchResult;\n"
3038 << " HadMatchOtherThanPredicate = true;\n"
3042 // Call the post-processing function, if used.
3043 std::string InsnCleanupFn =
3044 AsmParser->getValueAsString("AsmParserInstCleanup");
3045 if (!InsnCleanupFn.empty())
3046 OS << " " << InsnCleanupFn << "(Inst);\n";
3048 if (HasDeprecation) {
3049 OS << " std::string Info;\n";
3050 OS << " if (MII.get(Inst.getOpcode()).getDeprecatedInfo(Inst, STI, Info)) {\n";
3051 OS << " SMLoc Loc = ((" << Target.getName() << "Operand*)Operands[0])->getStartLoc();\n";
3052 OS << " Parser.Warning(Loc, Info, None);\n";
3056 OS << " return Match_Success;\n";
3059 OS << " // Okay, we had no match. Try to return a useful error code.\n";
3060 OS << " if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)\n";
3061 OS << " return RetCode;\n\n";
3062 OS << " // Missing feature matches return which features were missing\n";
3063 OS << " ErrorInfo = MissingFeatures;\n";
3064 OS << " return Match_MissingFeature;\n";
3067 if (Info.OperandMatchInfo.size())
3068 emitCustomOperandParsing(OS, Target, Info, ClassName, StringTable,
3071 OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";
3076 void EmitAsmMatcher(RecordKeeper &RK, raw_ostream &OS) {
3077 emitSourceFileHeader("Assembly Matcher Source Fragment", OS);
3078 AsmMatcherEmitter(RK).run(OS);
3081 } // End llvm namespace