1 //===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits a target specifier matcher for converting parsed
11 // assembly operands in the MCInst structures. It also emits a matcher for
12 // custom operand parsing.
14 // Converting assembly operands into MCInst structures
15 // ---------------------------------------------------
17 // The input to the target specific matcher is a list of literal tokens and
18 // operands. The target specific parser should generally eliminate any syntax
19 // which is not relevant for matching; for example, comma tokens should have
20 // already been consumed and eliminated by the parser. Most instructions will
21 // end up with a single literal token (the instruction name) and some number of
24 // Some example inputs, for X86:
25 // 'addl' (immediate ...) (register ...)
26 // 'add' (immediate ...) (memory ...)
29 // The assembly matcher is responsible for converting this input into a precise
30 // machine instruction (i.e., an instruction with a well defined encoding). This
31 // mapping has several properties which complicate matching:
33 // - It may be ambiguous; many architectures can legally encode particular
34 // variants of an instruction in different ways (for example, using a smaller
35 // encoding for small immediates). Such ambiguities should never be
36 // arbitrarily resolved by the assembler, the assembler is always responsible
37 // for choosing the "best" available instruction.
39 // - It may depend on the subtarget or the assembler context. Instructions
40 // which are invalid for the current mode, but otherwise unambiguous (e.g.,
41 // an SSE instruction in a file being assembled for i486) should be accepted
42 // and rejected by the assembler front end. However, if the proper encoding
43 // for an instruction is dependent on the assembler context then the matcher
44 // is responsible for selecting the correct machine instruction for the
47 // The core matching algorithm attempts to exploit the regularity in most
48 // instruction sets to quickly determine the set of possibly matching
49 // instructions, and the simplify the generated code. Additionally, this helps
50 // to ensure that the ambiguities are intentionally resolved by the user.
52 // The matching is divided into two distinct phases:
54 // 1. Classification: Each operand is mapped to the unique set which (a)
55 // contains it, and (b) is the largest such subset for which a single
56 // instruction could match all members.
58 // For register classes, we can generate these subgroups automatically. For
59 // arbitrary operands, we expect the user to define the classes and their
60 // relations to one another (for example, 8-bit signed immediates as a
61 // subset of 32-bit immediates).
63 // By partitioning the operands in this way, we guarantee that for any
64 // tuple of classes, any single instruction must match either all or none
65 // of the sets of operands which could classify to that tuple.
67 // In addition, the subset relation amongst classes induces a partial order
68 // on such tuples, which we use to resolve ambiguities.
70 // 2. The input can now be treated as a tuple of classes (static tokens are
71 // simple singleton sets). Each such tuple should generally map to a single
72 // instruction (we currently ignore cases where this isn't true, whee!!!),
73 // which we can emit a simple matcher for.
75 // Custom Operand Parsing
76 // ----------------------
78 // Some targets need a custom way to parse operands, some specific instructions
79 // can contain arguments that can represent processor flags and other kinds of
80 // identifiers that need to be mapped to specific values in the final encoded
81 // instructions. The target specific custom operand parsing works in the
84 // 1. A operand match table is built, each entry contains a mnemonic, an
85 // operand class, a mask for all operand positions for that same
86 // class/mnemonic and target features to be checked while trying to match.
88 // 2. The operand matcher will try every possible entry with the same
89 // mnemonic and will check if the target feature for this mnemonic also
90 // matches. After that, if the operand to be matched has its index
91 // present in the mask, a successful match occurs. Otherwise, fallback
92 // to the regular operand parsing.
94 // 3. For a match success, each operand class that has a 'ParserMethod'
95 // becomes part of a switch from where the custom method is called.
97 //===----------------------------------------------------------------------===//
99 #include "CodeGenTarget.h"
100 #include "llvm/ADT/PointerUnion.h"
101 #include "llvm/ADT/STLExtras.h"
102 #include "llvm/ADT/SmallPtrSet.h"
103 #include "llvm/ADT/SmallVector.h"
104 #include "llvm/ADT/StringExtras.h"
105 #include "llvm/Support/CommandLine.h"
106 #include "llvm/Support/Debug.h"
107 #include "llvm/Support/ErrorHandling.h"
108 #include "llvm/TableGen/Error.h"
109 #include "llvm/TableGen/Record.h"
110 #include "llvm/TableGen/StringMatcher.h"
111 #include "llvm/TableGen/StringToOffsetTable.h"
112 #include "llvm/TableGen/TableGenBackend.h"
118 #include <forward_list>
119 using namespace llvm;
121 #define DEBUG_TYPE "asm-matcher-emitter"
123 static cl::opt<std::string>
124 MatchPrefix("match-prefix", cl::init(""),
125 cl::desc("Only match instructions with the given prefix"));
128 class AsmMatcherInfo;
129 struct SubtargetFeatureInfo;
131 // Register sets are used as keys in some second-order sets TableGen creates
132 // when generating its data structures. This means that the order of two
133 // RegisterSets can be seen in the outputted AsmMatcher tables occasionally, and
134 // can even affect compiler output (at least seen in diagnostics produced when
135 // all matches fail). So we use a type that sorts them consistently.
136 typedef std::set<Record*, LessRecordByID> RegisterSet;
138 class AsmMatcherEmitter {
139 RecordKeeper &Records;
141 AsmMatcherEmitter(RecordKeeper &R) : Records(R) {}
143 void run(raw_ostream &o);
146 /// ClassInfo - Helper class for storing the information about a particular
147 /// class of operands which can be matched.
150 /// Invalid kind, for use as a sentinel value.
153 /// The class for a particular token.
156 /// The (first) register class, subsequent register classes are
157 /// RegisterClass0+1, and so on.
160 /// The (first) user defined class, subsequent user defined classes are
161 /// UserClass0+1, and so on.
165 /// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
166 /// N) for the Nth user defined class.
169 /// SuperClasses - The super classes of this class. Note that for simplicities
170 /// sake user operands only record their immediate super class, while register
171 /// operands include all superclasses.
172 std::vector<ClassInfo*> SuperClasses;
174 /// Name - The full class name, suitable for use in an enum.
177 /// ClassName - The unadorned generic name for this class (e.g., Token).
178 std::string ClassName;
180 /// ValueName - The name of the value this class represents; for a token this
181 /// is the literal token string, for an operand it is the TableGen class (or
182 /// empty if this is a derived class).
183 std::string ValueName;
185 /// PredicateMethod - The name of the operand method to test whether the
186 /// operand matches this class; this is not valid for Token or register kinds.
187 std::string PredicateMethod;
189 /// RenderMethod - The name of the operand method to add this operand to an
190 /// MCInst; this is not valid for Token or register kinds.
191 std::string RenderMethod;
193 /// ParserMethod - The name of the operand method to do a target specific
194 /// parsing on the operand.
195 std::string ParserMethod;
197 /// For register classes: the records for all the registers in this class.
198 RegisterSet Registers;
200 /// For custom match classes: the diagnostic kind for when the predicate fails.
201 std::string DiagnosticType;
203 /// isRegisterClass() - Check if this is a register class.
204 bool isRegisterClass() const {
205 return Kind >= RegisterClass0 && Kind < UserClass0;
208 /// isUserClass() - Check if this is a user defined class.
209 bool isUserClass() const {
210 return Kind >= UserClass0;
213 /// isRelatedTo - Check whether this class is "related" to \p RHS. Classes
214 /// are related if they are in the same class hierarchy.
215 bool isRelatedTo(const ClassInfo &RHS) const {
216 // Tokens are only related to tokens.
217 if (Kind == Token || RHS.Kind == Token)
218 return Kind == Token && RHS.Kind == Token;
220 // Registers classes are only related to registers classes, and only if
221 // their intersection is non-empty.
222 if (isRegisterClass() || RHS.isRegisterClass()) {
223 if (!isRegisterClass() || !RHS.isRegisterClass())
227 std::insert_iterator<RegisterSet> II(Tmp, Tmp.begin());
228 std::set_intersection(Registers.begin(), Registers.end(),
229 RHS.Registers.begin(), RHS.Registers.end(),
230 II, LessRecordByID());
235 // Otherwise we have two users operands; they are related if they are in the
236 // same class hierarchy.
238 // FIXME: This is an oversimplification, they should only be related if they
239 // intersect, however we don't have that information.
240 assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");
241 const ClassInfo *Root = this;
242 while (!Root->SuperClasses.empty())
243 Root = Root->SuperClasses.front();
245 const ClassInfo *RHSRoot = &RHS;
246 while (!RHSRoot->SuperClasses.empty())
247 RHSRoot = RHSRoot->SuperClasses.front();
249 return Root == RHSRoot;
252 /// isSubsetOf - Test whether this class is a subset of \p RHS.
253 bool isSubsetOf(const ClassInfo &RHS) const {
254 // This is a subset of RHS if it is the same class...
258 // ... or if any of its super classes are a subset of RHS.
259 for (const ClassInfo *CI : SuperClasses)
260 if (CI->isSubsetOf(RHS))
266 /// operator< - Compare two classes.
267 bool operator<(const ClassInfo &RHS) const {
271 // Unrelated classes can be ordered by kind.
272 if (!isRelatedTo(RHS))
273 return Kind < RHS.Kind;
277 llvm_unreachable("Invalid kind!");
280 // This class precedes the RHS if it is a proper subset of the RHS.
283 if (RHS.isSubsetOf(*this))
286 // Otherwise, order by name to ensure we have a total ordering.
287 return ValueName < RHS.ValueName;
292 /// MatchableInfo - Helper class for storing the necessary information for an
293 /// instruction or alias which is capable of being matched.
294 struct MatchableInfo {
296 /// Token - This is the token that the operand came from.
299 /// The unique class instance this operand should match.
302 /// The operand name this is, if anything.
305 /// The suboperand index within SrcOpName, or -1 for the entire operand.
308 /// Register record if this token is singleton register.
309 Record *SingletonReg;
311 explicit AsmOperand(StringRef T) : Token(T), Class(nullptr), SubOpIdx(-1),
312 SingletonReg(nullptr) {}
315 /// ResOperand - This represents a single operand in the result instruction
316 /// generated by the match. In cases (like addressing modes) where a single
317 /// assembler operand expands to multiple MCOperands, this represents the
318 /// single assembler operand, not the MCOperand.
321 /// RenderAsmOperand - This represents an operand result that is
322 /// generated by calling the render method on the assembly operand. The
323 /// corresponding AsmOperand is specified by AsmOperandNum.
326 /// TiedOperand - This represents a result operand that is a duplicate of
327 /// a previous result operand.
330 /// ImmOperand - This represents an immediate value that is dumped into
334 /// RegOperand - This represents a fixed register that is dumped in.
339 /// This is the operand # in the AsmOperands list that this should be
341 unsigned AsmOperandNum;
343 /// TiedOperandNum - This is the (earlier) result operand that should be
345 unsigned TiedOperandNum;
347 /// ImmVal - This is the immediate value added to the instruction.
350 /// Register - This is the register record.
354 /// MINumOperands - The number of MCInst operands populated by this
356 unsigned MINumOperands;
358 static ResOperand getRenderedOp(unsigned AsmOpNum, unsigned NumOperands) {
360 X.Kind = RenderAsmOperand;
361 X.AsmOperandNum = AsmOpNum;
362 X.MINumOperands = NumOperands;
366 static ResOperand getTiedOp(unsigned TiedOperandNum) {
368 X.Kind = TiedOperand;
369 X.TiedOperandNum = TiedOperandNum;
374 static ResOperand getImmOp(int64_t Val) {
382 static ResOperand getRegOp(Record *Reg) {
391 /// AsmVariantID - Target's assembly syntax variant no.
394 /// TheDef - This is the definition of the instruction or InstAlias that this
395 /// matchable came from.
396 Record *const TheDef;
398 /// DefRec - This is the definition that it came from.
399 PointerUnion<const CodeGenInstruction*, const CodeGenInstAlias*> DefRec;
401 const CodeGenInstruction *getResultInst() const {
402 if (DefRec.is<const CodeGenInstruction*>())
403 return DefRec.get<const CodeGenInstruction*>();
404 return DefRec.get<const CodeGenInstAlias*>()->ResultInst;
407 /// ResOperands - This is the operand list that should be built for the result
409 SmallVector<ResOperand, 8> ResOperands;
411 /// AsmString - The assembly string for this instruction (with variants
412 /// removed), e.g. "movsx $src, $dst".
413 std::string AsmString;
415 /// Mnemonic - This is the first token of the matched instruction, its
419 /// AsmOperands - The textual operands that this instruction matches,
420 /// annotated with a class and where in the OperandList they were defined.
421 /// This directly corresponds to the tokenized AsmString after the mnemonic is
423 SmallVector<AsmOperand, 8> AsmOperands;
425 /// Predicates - The required subtarget features to match this instruction.
426 SmallVector<const SubtargetFeatureInfo *, 4> RequiredFeatures;
428 /// ConversionFnKind - The enum value which is passed to the generated
429 /// convertToMCInst to convert parsed operands into an MCInst for this
431 std::string ConversionFnKind;
433 /// If this instruction is deprecated in some form.
436 MatchableInfo(const CodeGenInstruction &CGI)
437 : AsmVariantID(0), TheDef(CGI.TheDef), DefRec(&CGI),
438 AsmString(CGI.AsmString) {
441 MatchableInfo(const CodeGenInstAlias *Alias)
442 : AsmVariantID(0), TheDef(Alias->TheDef), DefRec(Alias),
443 AsmString(Alias->AsmString) {
447 if (DefRec.is<const CodeGenInstAlias*>())
448 delete DefRec.get<const CodeGenInstAlias*>();
451 // Two-operand aliases clone from the main matchable, but mark the second
452 // operand as a tied operand of the first for purposes of the assembler.
453 void formTwoOperandAlias(StringRef Constraint);
455 void initialize(const AsmMatcherInfo &Info,
456 SmallPtrSetImpl<Record*> &SingletonRegisters,
457 int AsmVariantNo, std::string &RegisterPrefix);
459 /// validate - Return true if this matchable is a valid thing to match against
460 /// and perform a bunch of validity checking.
461 bool validate(StringRef CommentDelimiter, bool Hack) const;
463 /// extractSingletonRegisterForAsmOperand - Extract singleton register,
464 /// if present, from specified token.
466 extractSingletonRegisterForAsmOperand(unsigned i, const AsmMatcherInfo &Info,
467 std::string &RegisterPrefix);
469 /// findAsmOperand - Find the AsmOperand with the specified name and
470 /// suboperand index.
471 int findAsmOperand(StringRef N, int SubOpIdx) const {
472 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
473 if (N == AsmOperands[i].SrcOpName &&
474 SubOpIdx == AsmOperands[i].SubOpIdx)
479 /// findAsmOperandNamed - Find the first AsmOperand with the specified name.
480 /// This does not check the suboperand index.
481 int findAsmOperandNamed(StringRef N) const {
482 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
483 if (N == AsmOperands[i].SrcOpName)
488 void buildInstructionResultOperands();
489 void buildAliasResultOperands();
491 /// operator< - Compare two matchables.
492 bool operator<(const MatchableInfo &RHS) const {
493 // The primary comparator is the instruction mnemonic.
494 if (Mnemonic != RHS.Mnemonic)
495 return Mnemonic < RHS.Mnemonic;
497 if (AsmOperands.size() != RHS.AsmOperands.size())
498 return AsmOperands.size() < RHS.AsmOperands.size();
500 // Compare lexicographically by operand. The matcher validates that other
501 // orderings wouldn't be ambiguous using \see couldMatchAmbiguouslyWith().
502 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
503 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
505 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
509 // Give matches that require more features higher precedence. This is useful
510 // because we cannot define AssemblerPredicates with the negation of
511 // processor features. For example, ARM v6 "nop" may be either a HINT or
512 // MOV. With v6, we want to match HINT. The assembler has no way to
513 // predicate MOV under "NoV6", but HINT will always match first because it
514 // requires V6 while MOV does not.
515 if (RequiredFeatures.size() != RHS.RequiredFeatures.size())
516 return RequiredFeatures.size() > RHS.RequiredFeatures.size();
521 /// couldMatchAmbiguouslyWith - Check whether this matchable could
522 /// ambiguously match the same set of operands as \p RHS (without being a
523 /// strictly superior match).
524 bool couldMatchAmbiguouslyWith(const MatchableInfo &RHS) const {
525 // The primary comparator is the instruction mnemonic.
526 if (Mnemonic != RHS.Mnemonic)
529 // The number of operands is unambiguous.
530 if (AsmOperands.size() != RHS.AsmOperands.size())
533 // Otherwise, make sure the ordering of the two instructions is unambiguous
534 // by checking that either (a) a token or operand kind discriminates them,
535 // or (b) the ordering among equivalent kinds is consistent.
537 // Tokens and operand kinds are unambiguous (assuming a correct target
539 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
540 if (AsmOperands[i].Class->Kind != RHS.AsmOperands[i].Class->Kind ||
541 AsmOperands[i].Class->Kind == ClassInfo::Token)
542 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class ||
543 *RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
546 // Otherwise, this operand could commute if all operands are equivalent, or
547 // there is a pair of operands that compare less than and a pair that
548 // compare greater than.
549 bool HasLT = false, HasGT = false;
550 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
551 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
553 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
557 return !(HasLT ^ HasGT);
563 void tokenizeAsmString(const AsmMatcherInfo &Info);
566 /// SubtargetFeatureInfo - Helper class for storing information on a subtarget
567 /// feature which participates in instruction matching.
568 struct SubtargetFeatureInfo {
569 /// \brief The predicate record for this feature.
572 /// \brief An unique index assigned to represent this feature.
575 SubtargetFeatureInfo(Record *D, uint64_t Idx) : TheDef(D), Index(Idx) {}
577 /// \brief The name of the enumerated constant identifying this feature.
578 std::string getEnumName() const {
579 return "Feature_" + TheDef->getName();
583 errs() << getEnumName() << " " << Index << "\n";
588 struct OperandMatchEntry {
589 unsigned OperandMask;
590 const MatchableInfo* MI;
593 static OperandMatchEntry create(const MatchableInfo *mi, ClassInfo *ci,
596 X.OperandMask = opMask;
604 class AsmMatcherInfo {
607 RecordKeeper &Records;
609 /// The tablegen AsmParser record.
612 /// Target - The target information.
613 CodeGenTarget &Target;
615 /// The classes which are needed for matching.
616 std::forward_list<ClassInfo> Classes;
618 /// The information on the matchables to match.
619 std::vector<std::unique_ptr<MatchableInfo>> Matchables;
621 /// Info for custom matching operands by user defined methods.
622 std::vector<OperandMatchEntry> OperandMatchInfo;
624 /// Map of Register records to their class information.
625 typedef std::map<Record*, ClassInfo*, LessRecordByID> RegisterClassesTy;
626 RegisterClassesTy RegisterClasses;
628 /// Map of Predicate records to their subtarget information.
629 std::map<Record *, SubtargetFeatureInfo, LessRecordByID> SubtargetFeatures;
631 /// Map of AsmOperandClass records to their class information.
632 std::map<Record*, ClassInfo*> AsmOperandClasses;
635 /// Map of token to class information which has already been constructed.
636 std::map<std::string, ClassInfo*> TokenClasses;
638 /// Map of RegisterClass records to their class information.
639 std::map<Record*, ClassInfo*> RegisterClassClasses;
642 /// getTokenClass - Lookup or create the class for the given token.
643 ClassInfo *getTokenClass(StringRef Token);
645 /// getOperandClass - Lookup or create the class for the given operand.
646 ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI,
648 ClassInfo *getOperandClass(Record *Rec, int SubOpIdx);
650 /// buildRegisterClasses - Build the ClassInfo* instances for register
652 void buildRegisterClasses(SmallPtrSetImpl<Record*> &SingletonRegisters);
654 /// buildOperandClasses - Build the ClassInfo* instances for user defined
656 void buildOperandClasses();
658 void buildInstructionOperandReference(MatchableInfo *II, StringRef OpName,
660 void buildAliasOperandReference(MatchableInfo *II, StringRef OpName,
661 MatchableInfo::AsmOperand &Op);
664 AsmMatcherInfo(Record *AsmParser,
665 CodeGenTarget &Target,
666 RecordKeeper &Records);
668 /// buildInfo - Construct the various tables used during matching.
671 /// buildOperandMatchInfo - Build the necessary information to handle user
672 /// defined operand parsing methods.
673 void buildOperandMatchInfo();
675 /// getSubtargetFeature - Lookup or create the subtarget feature info for the
677 const SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const {
678 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
679 const auto &I = SubtargetFeatures.find(Def);
680 return I == SubtargetFeatures.end() ? nullptr : &I->second;
683 RecordKeeper &getRecords() const {
688 } // End anonymous namespace
690 void MatchableInfo::dump() const {
691 errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n";
693 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
694 const AsmOperand &Op = AsmOperands[i];
695 errs() << " op[" << i << "] = " << Op.Class->ClassName << " - ";
696 errs() << '\"' << Op.Token << "\"\n";
700 static std::pair<StringRef, StringRef>
701 parseTwoOperandConstraint(StringRef S, ArrayRef<SMLoc> Loc) {
702 // Split via the '='.
703 std::pair<StringRef, StringRef> Ops = S.split('=');
704 if (Ops.second == "")
705 PrintFatalError(Loc, "missing '=' in two-operand alias constraint");
706 // Trim whitespace and the leading '$' on the operand names.
707 size_t start = Ops.first.find_first_of('$');
708 if (start == std::string::npos)
709 PrintFatalError(Loc, "expected '$' prefix on asm operand name");
710 Ops.first = Ops.first.slice(start + 1, std::string::npos);
711 size_t end = Ops.first.find_last_of(" \t");
712 Ops.first = Ops.first.slice(0, end);
713 // Now the second operand.
714 start = Ops.second.find_first_of('$');
715 if (start == std::string::npos)
716 PrintFatalError(Loc, "expected '$' prefix on asm operand name");
717 Ops.second = Ops.second.slice(start + 1, std::string::npos);
718 end = Ops.second.find_last_of(" \t");
719 Ops.first = Ops.first.slice(0, end);
723 void MatchableInfo::formTwoOperandAlias(StringRef Constraint) {
724 // Figure out which operands are aliased and mark them as tied.
725 std::pair<StringRef, StringRef> Ops =
726 parseTwoOperandConstraint(Constraint, TheDef->getLoc());
728 // Find the AsmOperands that refer to the operands we're aliasing.
729 int SrcAsmOperand = findAsmOperandNamed(Ops.first);
730 int DstAsmOperand = findAsmOperandNamed(Ops.second);
731 if (SrcAsmOperand == -1)
732 PrintFatalError(TheDef->getLoc(),
733 "unknown source two-operand alias operand '" + Ops.first +
735 if (DstAsmOperand == -1)
736 PrintFatalError(TheDef->getLoc(),
737 "unknown destination two-operand alias operand '" +
740 // Find the ResOperand that refers to the operand we're aliasing away
741 // and update it to refer to the combined operand instead.
742 for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) {
743 ResOperand &Op = ResOperands[i];
744 if (Op.Kind == ResOperand::RenderAsmOperand &&
745 Op.AsmOperandNum == (unsigned)SrcAsmOperand) {
746 Op.AsmOperandNum = DstAsmOperand;
750 // Remove the AsmOperand for the alias operand.
751 AsmOperands.erase(AsmOperands.begin() + SrcAsmOperand);
752 // Adjust the ResOperand references to any AsmOperands that followed
753 // the one we just deleted.
754 for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) {
755 ResOperand &Op = ResOperands[i];
758 // Nothing to do for operands that don't reference AsmOperands.
760 case ResOperand::RenderAsmOperand:
761 if (Op.AsmOperandNum > (unsigned)SrcAsmOperand)
764 case ResOperand::TiedOperand:
765 if (Op.TiedOperandNum > (unsigned)SrcAsmOperand)
772 void MatchableInfo::initialize(const AsmMatcherInfo &Info,
773 SmallPtrSetImpl<Record*> &SingletonRegisters,
774 int AsmVariantNo, std::string &RegisterPrefix) {
775 AsmVariantID = AsmVariantNo;
777 CodeGenInstruction::FlattenAsmStringVariants(AsmString, AsmVariantNo);
779 tokenizeAsmString(Info);
781 // Compute the require features.
782 std::vector<Record*> Predicates =TheDef->getValueAsListOfDefs("Predicates");
783 for (unsigned i = 0, e = Predicates.size(); i != e; ++i)
784 if (const SubtargetFeatureInfo *Feature =
785 Info.getSubtargetFeature(Predicates[i]))
786 RequiredFeatures.push_back(Feature);
788 // Collect singleton registers, if used.
789 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
790 extractSingletonRegisterForAsmOperand(i, Info, RegisterPrefix);
791 if (Record *Reg = AsmOperands[i].SingletonReg)
792 SingletonRegisters.insert(Reg);
795 const RecordVal *DepMask = TheDef->getValue("DeprecatedFeatureMask");
797 DepMask = TheDef->getValue("ComplexDeprecationPredicate");
800 DepMask ? !DepMask->getValue()->getAsUnquotedString().empty() : false;
803 /// tokenizeAsmString - Tokenize a simplified assembly string.
804 void MatchableInfo::tokenizeAsmString(const AsmMatcherInfo &Info) {
805 StringRef String = AsmString;
808 for (unsigned i = 0, e = String.size(); i != e; ++i) {
818 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
821 if (!isspace(String[i]) && String[i] != ',')
822 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
828 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
832 assert(i != String.size() && "Invalid quoted character");
833 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
839 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
843 // If this isn't "${", treat like a normal token.
844 if (i + 1 == String.size() || String[i + 1] != '{') {
849 StringRef::iterator End = std::find(String.begin() + i, String.end(),'}');
850 assert(End != String.end() && "Missing brace in operand reference!");
851 size_t EndPos = End - String.begin();
852 AsmOperands.push_back(AsmOperand(String.slice(i, EndPos+1)));
859 if (!Info.AsmParser->getValueAsBit("MnemonicContainsDot")) {
861 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
871 if (InTok && Prev != String.size())
872 AsmOperands.push_back(AsmOperand(String.substr(Prev)));
874 // The first token of the instruction is the mnemonic, which must be a
875 // simple string, not a $foo variable or a singleton register.
876 if (AsmOperands.empty())
877 PrintFatalError(TheDef->getLoc(),
878 "Instruction '" + TheDef->getName() + "' has no tokens");
879 Mnemonic = AsmOperands[0].Token;
880 if (Mnemonic.empty())
881 PrintFatalError(TheDef->getLoc(),
882 "Missing instruction mnemonic");
883 // FIXME : Check and raise an error if it is a register.
884 if (Mnemonic[0] == '$')
885 PrintFatalError(TheDef->getLoc(),
886 "Invalid instruction mnemonic '" + Mnemonic + "'!");
888 // Remove the first operand, it is tracked in the mnemonic field.
889 AsmOperands.erase(AsmOperands.begin());
892 bool MatchableInfo::validate(StringRef CommentDelimiter, bool Hack) const {
893 // Reject matchables with no .s string.
894 if (AsmString.empty())
895 PrintFatalError(TheDef->getLoc(), "instruction with empty asm string");
897 // Reject any matchables with a newline in them, they should be marked
898 // isCodeGenOnly if they are pseudo instructions.
899 if (AsmString.find('\n') != std::string::npos)
900 PrintFatalError(TheDef->getLoc(),
901 "multiline instruction is not valid for the asmparser, "
902 "mark it isCodeGenOnly");
904 // Remove comments from the asm string. We know that the asmstring only
906 if (!CommentDelimiter.empty() &&
907 StringRef(AsmString).find(CommentDelimiter) != StringRef::npos)
908 PrintFatalError(TheDef->getLoc(),
909 "asmstring for instruction has comment character in it, "
910 "mark it isCodeGenOnly");
912 // Reject matchables with operand modifiers, these aren't something we can
913 // handle, the target should be refactored to use operands instead of
916 // Also, check for instructions which reference the operand multiple times;
917 // this implies a constraint we would not honor.
918 std::set<std::string> OperandNames;
919 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
920 StringRef Tok = AsmOperands[i].Token;
921 if (Tok[0] == '$' && Tok.find(':') != StringRef::npos)
922 PrintFatalError(TheDef->getLoc(),
923 "matchable with operand modifier '" + Tok +
924 "' not supported by asm matcher. Mark isCodeGenOnly!");
926 // Verify that any operand is only mentioned once.
927 // We reject aliases and ignore instructions for now.
928 if (Tok[0] == '$' && !OperandNames.insert(Tok).second) {
930 PrintFatalError(TheDef->getLoc(),
931 "ERROR: matchable with tied operand '" + Tok +
932 "' can never be matched!");
933 // FIXME: Should reject these. The ARM backend hits this with $lane in a
934 // bunch of instructions. It is unclear what the right answer is.
936 errs() << "warning: '" << TheDef->getName() << "': "
937 << "ignoring instruction with tied operand '"
947 /// extractSingletonRegisterForAsmOperand - Extract singleton register,
948 /// if present, from specified token.
950 extractSingletonRegisterForAsmOperand(unsigned OperandNo,
951 const AsmMatcherInfo &Info,
952 std::string &RegisterPrefix) {
953 StringRef Tok = AsmOperands[OperandNo].Token;
954 if (RegisterPrefix.empty()) {
955 std::string LoweredTok = Tok.lower();
956 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(LoweredTok))
957 AsmOperands[OperandNo].SingletonReg = Reg->TheDef;
961 if (!Tok.startswith(RegisterPrefix))
964 StringRef RegName = Tok.substr(RegisterPrefix.size());
965 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName))
966 AsmOperands[OperandNo].SingletonReg = Reg->TheDef;
968 // If there is no register prefix (i.e. "%" in "%eax"), then this may
969 // be some random non-register token, just ignore it.
973 static std::string getEnumNameForToken(StringRef Str) {
976 for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) {
978 case '*': Res += "_STAR_"; break;
979 case '%': Res += "_PCT_"; break;
980 case ':': Res += "_COLON_"; break;
981 case '!': Res += "_EXCLAIM_"; break;
982 case '.': Res += "_DOT_"; break;
983 case '<': Res += "_LT_"; break;
984 case '>': Res += "_GT_"; break;
986 if ((*it >= 'A' && *it <= 'Z') ||
987 (*it >= 'a' && *it <= 'z') ||
988 (*it >= '0' && *it <= '9'))
991 Res += "_" + utostr((unsigned) *it) + "_";
998 ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) {
999 ClassInfo *&Entry = TokenClasses[Token];
1002 Classes.emplace_front();
1003 Entry = &Classes.front();
1004 Entry->Kind = ClassInfo::Token;
1005 Entry->ClassName = "Token";
1006 Entry->Name = "MCK_" + getEnumNameForToken(Token);
1007 Entry->ValueName = Token;
1008 Entry->PredicateMethod = "<invalid>";
1009 Entry->RenderMethod = "<invalid>";
1010 Entry->ParserMethod = "";
1011 Entry->DiagnosticType = "";
1018 AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI,
1020 Record *Rec = OI.Rec;
1022 Rec = cast<DefInit>(OI.MIOperandInfo->getArg(SubOpIdx))->getDef();
1023 return getOperandClass(Rec, SubOpIdx);
1027 AsmMatcherInfo::getOperandClass(Record *Rec, int SubOpIdx) {
1028 if (Rec->isSubClassOf("RegisterOperand")) {
1029 // RegisterOperand may have an associated ParserMatchClass. If it does,
1030 // use it, else just fall back to the underlying register class.
1031 const RecordVal *R = Rec->getValue("ParserMatchClass");
1032 if (!R || !R->getValue())
1033 PrintFatalError("Record `" + Rec->getName() +
1034 "' does not have a ParserMatchClass!\n");
1036 if (DefInit *DI= dyn_cast<DefInit>(R->getValue())) {
1037 Record *MatchClass = DI->getDef();
1038 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1042 // No custom match class. Just use the register class.
1043 Record *ClassRec = Rec->getValueAsDef("RegClass");
1045 PrintFatalError(Rec->getLoc(), "RegisterOperand `" + Rec->getName() +
1046 "' has no associated register class!\n");
1047 if (ClassInfo *CI = RegisterClassClasses[ClassRec])
1049 PrintFatalError(Rec->getLoc(), "register class has no class info!");
1053 if (Rec->isSubClassOf("RegisterClass")) {
1054 if (ClassInfo *CI = RegisterClassClasses[Rec])
1056 PrintFatalError(Rec->getLoc(), "register class has no class info!");
1059 if (!Rec->isSubClassOf("Operand"))
1060 PrintFatalError(Rec->getLoc(), "Operand `" + Rec->getName() +
1061 "' does not derive from class Operand!\n");
1062 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1063 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1066 PrintFatalError(Rec->getLoc(), "operand has no match class!");
1069 struct LessRegisterSet {
1070 bool operator() (const RegisterSet &LHS, const RegisterSet & RHS) const {
1071 // std::set<T> defines its own compariso "operator<", but it
1072 // performs a lexicographical comparison by T's innate comparison
1073 // for some reason. We don't want non-deterministic pointer
1074 // comparisons so use this instead.
1075 return std::lexicographical_compare(LHS.begin(), LHS.end(),
1076 RHS.begin(), RHS.end(),
1081 void AsmMatcherInfo::
1082 buildRegisterClasses(SmallPtrSetImpl<Record*> &SingletonRegisters) {
1083 const auto &Registers = Target.getRegBank().getRegisters();
1084 ArrayRef<CodeGenRegisterClass*> RegClassList =
1085 Target.getRegBank().getRegClasses();
1087 typedef std::set<RegisterSet, LessRegisterSet> RegisterSetSet;
1089 // The register sets used for matching.
1090 RegisterSetSet RegisterSets;
1092 // Gather the defined sets.
1093 for (const CodeGenRegisterClass *RC : RegClassList)
1094 RegisterSets.insert(RegisterSet(RC->getOrder().begin(),
1095 RC->getOrder().end()));
1097 // Add any required singleton sets.
1098 for (Record *Rec : SingletonRegisters) {
1099 RegisterSets.insert(RegisterSet(&Rec, &Rec + 1));
1102 // Introduce derived sets where necessary (when a register does not determine
1103 // a unique register set class), and build the mapping of registers to the set
1104 // they should classify to.
1105 std::map<Record*, RegisterSet> RegisterMap;
1106 for (const CodeGenRegister &CGR : Registers) {
1107 // Compute the intersection of all sets containing this register.
1108 RegisterSet ContainingSet;
1110 for (const RegisterSet &RS : RegisterSets) {
1111 if (!RS.count(CGR.TheDef))
1114 if (ContainingSet.empty()) {
1120 std::swap(Tmp, ContainingSet);
1121 std::insert_iterator<RegisterSet> II(ContainingSet,
1122 ContainingSet.begin());
1123 std::set_intersection(Tmp.begin(), Tmp.end(), RS.begin(), RS.end(), II,
1127 if (!ContainingSet.empty()) {
1128 RegisterSets.insert(ContainingSet);
1129 RegisterMap.insert(std::make_pair(CGR.TheDef, ContainingSet));
1133 // Construct the register classes.
1134 std::map<RegisterSet, ClassInfo*, LessRegisterSet> RegisterSetClasses;
1136 for (const RegisterSet &RS : RegisterSets) {
1137 Classes.emplace_front();
1138 ClassInfo *CI = &Classes.front();
1139 CI->Kind = ClassInfo::RegisterClass0 + Index;
1140 CI->ClassName = "Reg" + utostr(Index);
1141 CI->Name = "MCK_Reg" + utostr(Index);
1143 CI->PredicateMethod = ""; // unused
1144 CI->RenderMethod = "addRegOperands";
1146 // FIXME: diagnostic type.
1147 CI->DiagnosticType = "";
1148 RegisterSetClasses.insert(std::make_pair(RS, CI));
1152 // Find the superclasses; we could compute only the subgroup lattice edges,
1153 // but there isn't really a point.
1154 for (const RegisterSet &RS : RegisterSets) {
1155 ClassInfo *CI = RegisterSetClasses[RS];
1156 for (const RegisterSet &RS2 : RegisterSets)
1158 std::includes(RS2.begin(), RS2.end(), RS.begin(), RS.end(),
1160 CI->SuperClasses.push_back(RegisterSetClasses[RS2]);
1163 // Name the register classes which correspond to a user defined RegisterClass.
1164 for (const CodeGenRegisterClass *RC : RegClassList) {
1165 // Def will be NULL for non-user defined register classes.
1166 Record *Def = RC->getDef();
1169 ClassInfo *CI = RegisterSetClasses[RegisterSet(RC->getOrder().begin(),
1170 RC->getOrder().end())];
1171 if (CI->ValueName.empty()) {
1172 CI->ClassName = RC->getName();
1173 CI->Name = "MCK_" + RC->getName();
1174 CI->ValueName = RC->getName();
1176 CI->ValueName = CI->ValueName + "," + RC->getName();
1178 RegisterClassClasses.insert(std::make_pair(Def, CI));
1181 // Populate the map for individual registers.
1182 for (std::map<Record*, RegisterSet>::iterator it = RegisterMap.begin(),
1183 ie = RegisterMap.end(); it != ie; ++it)
1184 RegisterClasses[it->first] = RegisterSetClasses[it->second];
1186 // Name the register classes which correspond to singleton registers.
1187 for (Record *Rec : SingletonRegisters) {
1188 ClassInfo *CI = RegisterClasses[Rec];
1189 assert(CI && "Missing singleton register class info!");
1191 if (CI->ValueName.empty()) {
1192 CI->ClassName = Rec->getName();
1193 CI->Name = "MCK_" + Rec->getName();
1194 CI->ValueName = Rec->getName();
1196 CI->ValueName = CI->ValueName + "," + Rec->getName();
1200 void AsmMatcherInfo::buildOperandClasses() {
1201 std::vector<Record*> AsmOperands =
1202 Records.getAllDerivedDefinitions("AsmOperandClass");
1204 // Pre-populate AsmOperandClasses map.
1205 for (Record *Rec : AsmOperands) {
1206 Classes.emplace_front();
1207 AsmOperandClasses[Rec] = &Classes.front();
1211 for (Record *Rec : AsmOperands) {
1212 ClassInfo *CI = AsmOperandClasses[Rec];
1213 CI->Kind = ClassInfo::UserClass0 + Index;
1215 ListInit *Supers = Rec->getValueAsListInit("SuperClasses");
1216 for (unsigned i = 0, e = Supers->getSize(); i != e; ++i) {
1217 DefInit *DI = dyn_cast<DefInit>(Supers->getElement(i));
1219 PrintError(Rec->getLoc(), "Invalid super class reference!");
1223 ClassInfo *SC = AsmOperandClasses[DI->getDef()];
1225 PrintError(Rec->getLoc(), "Invalid super class reference!");
1227 CI->SuperClasses.push_back(SC);
1229 CI->ClassName = Rec->getValueAsString("Name");
1230 CI->Name = "MCK_" + CI->ClassName;
1231 CI->ValueName = Rec->getName();
1233 // Get or construct the predicate method name.
1234 Init *PMName = Rec->getValueInit("PredicateMethod");
1235 if (StringInit *SI = dyn_cast<StringInit>(PMName)) {
1236 CI->PredicateMethod = SI->getValue();
1238 assert(isa<UnsetInit>(PMName) && "Unexpected PredicateMethod field!");
1239 CI->PredicateMethod = "is" + CI->ClassName;
1242 // Get or construct the render method name.
1243 Init *RMName = Rec->getValueInit("RenderMethod");
1244 if (StringInit *SI = dyn_cast<StringInit>(RMName)) {
1245 CI->RenderMethod = SI->getValue();
1247 assert(isa<UnsetInit>(RMName) && "Unexpected RenderMethod field!");
1248 CI->RenderMethod = "add" + CI->ClassName + "Operands";
1251 // Get the parse method name or leave it as empty.
1252 Init *PRMName = Rec->getValueInit("ParserMethod");
1253 if (StringInit *SI = dyn_cast<StringInit>(PRMName))
1254 CI->ParserMethod = SI->getValue();
1256 // Get the diagnostic type or leave it as empty.
1257 // Get the parse method name or leave it as empty.
1258 Init *DiagnosticType = Rec->getValueInit("DiagnosticType");
1259 if (StringInit *SI = dyn_cast<StringInit>(DiagnosticType))
1260 CI->DiagnosticType = SI->getValue();
1266 AsmMatcherInfo::AsmMatcherInfo(Record *asmParser,
1267 CodeGenTarget &target,
1268 RecordKeeper &records)
1269 : Records(records), AsmParser(asmParser), Target(target) {
1272 /// buildOperandMatchInfo - Build the necessary information to handle user
1273 /// defined operand parsing methods.
1274 void AsmMatcherInfo::buildOperandMatchInfo() {
1276 /// Map containing a mask with all operands indices that can be found for
1277 /// that class inside a instruction.
1278 typedef std::map<ClassInfo *, unsigned, less_ptr<ClassInfo>> OpClassMaskTy;
1279 OpClassMaskTy OpClassMask;
1281 for (const auto &MI : Matchables) {
1282 OpClassMask.clear();
1284 // Keep track of all operands of this instructions which belong to the
1286 for (unsigned i = 0, e = MI->AsmOperands.size(); i != e; ++i) {
1287 const MatchableInfo::AsmOperand &Op = MI->AsmOperands[i];
1288 if (Op.Class->ParserMethod.empty())
1290 unsigned &OperandMask = OpClassMask[Op.Class];
1291 OperandMask |= (1 << i);
1294 // Generate operand match info for each mnemonic/operand class pair.
1295 for (const auto &OCM : OpClassMask) {
1296 unsigned OpMask = OCM.second;
1297 ClassInfo *CI = OCM.first;
1298 OperandMatchInfo.push_back(OperandMatchEntry::create(MI.get(), CI,
1304 void AsmMatcherInfo::buildInfo() {
1305 // Build information about all of the AssemblerPredicates.
1306 std::vector<Record*> AllPredicates =
1307 Records.getAllDerivedDefinitions("Predicate");
1308 for (unsigned i = 0, e = AllPredicates.size(); i != e; ++i) {
1309 Record *Pred = AllPredicates[i];
1310 // Ignore predicates that are not intended for the assembler.
1311 if (!Pred->getValueAsBit("AssemblerMatcherPredicate"))
1314 if (Pred->getName().empty())
1315 PrintFatalError(Pred->getLoc(), "Predicate has no name!");
1317 SubtargetFeatures.insert(std::make_pair(
1318 Pred, SubtargetFeatureInfo(Pred, SubtargetFeatures.size())));
1319 DEBUG(SubtargetFeatures.find(Pred)->second.dump());
1320 assert(SubtargetFeatures.size() <= 64 && "Too many subtarget features!");
1323 // Parse the instructions; we need to do this first so that we can gather the
1324 // singleton register classes.
1325 SmallPtrSet<Record*, 16> SingletonRegisters;
1326 unsigned VariantCount = Target.getAsmParserVariantCount();
1327 for (unsigned VC = 0; VC != VariantCount; ++VC) {
1328 Record *AsmVariant = Target.getAsmParserVariant(VC);
1329 std::string CommentDelimiter =
1330 AsmVariant->getValueAsString("CommentDelimiter");
1331 std::string RegisterPrefix = AsmVariant->getValueAsString("RegisterPrefix");
1332 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
1334 for (const CodeGenInstruction *CGI : Target.instructions()) {
1336 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1337 // filter the set of instructions we consider.
1338 if (!StringRef(CGI->TheDef->getName()).startswith(MatchPrefix))
1341 // Ignore "codegen only" instructions.
1342 if (CGI->TheDef->getValueAsBit("isCodeGenOnly"))
1345 std::unique_ptr<MatchableInfo> II(new MatchableInfo(*CGI));
1347 II->initialize(*this, SingletonRegisters, AsmVariantNo, RegisterPrefix);
1349 // Ignore instructions which shouldn't be matched and diagnose invalid
1350 // instruction definitions with an error.
1351 if (!II->validate(CommentDelimiter, true))
1354 Matchables.push_back(std::move(II));
1357 // Parse all of the InstAlias definitions and stick them in the list of
1359 std::vector<Record*> AllInstAliases =
1360 Records.getAllDerivedDefinitions("InstAlias");
1361 for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) {
1362 CodeGenInstAlias *Alias =
1363 new CodeGenInstAlias(AllInstAliases[i], AsmVariantNo, Target);
1365 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1366 // filter the set of instruction aliases we consider, based on the target
1368 if (!StringRef(Alias->ResultInst->TheDef->getName())
1369 .startswith( MatchPrefix))
1372 std::unique_ptr<MatchableInfo> II(new MatchableInfo(Alias));
1374 II->initialize(*this, SingletonRegisters, AsmVariantNo, RegisterPrefix);
1376 // Validate the alias definitions.
1377 II->validate(CommentDelimiter, false);
1379 Matchables.push_back(std::move(II));
1383 // Build info for the register classes.
1384 buildRegisterClasses(SingletonRegisters);
1386 // Build info for the user defined assembly operand classes.
1387 buildOperandClasses();
1389 // Build the information about matchables, now that we have fully formed
1391 std::vector<std::unique_ptr<MatchableInfo>> NewMatchables;
1392 for (auto &II : Matchables) {
1393 // Parse the tokens after the mnemonic.
1394 // Note: buildInstructionOperandReference may insert new AsmOperands, so
1395 // don't precompute the loop bound.
1396 for (unsigned i = 0; i != II->AsmOperands.size(); ++i) {
1397 MatchableInfo::AsmOperand &Op = II->AsmOperands[i];
1398 StringRef Token = Op.Token;
1400 // Check for singleton registers.
1401 if (Record *RegRecord = II->AsmOperands[i].SingletonReg) {
1402 Op.Class = RegisterClasses[RegRecord];
1403 assert(Op.Class && Op.Class->Registers.size() == 1 &&
1404 "Unexpected class for singleton register");
1408 // Check for simple tokens.
1409 if (Token[0] != '$') {
1410 Op.Class = getTokenClass(Token);
1414 if (Token.size() > 1 && isdigit(Token[1])) {
1415 Op.Class = getTokenClass(Token);
1419 // Otherwise this is an operand reference.
1420 StringRef OperandName;
1421 if (Token[1] == '{')
1422 OperandName = Token.substr(2, Token.size() - 3);
1424 OperandName = Token.substr(1);
1426 if (II->DefRec.is<const CodeGenInstruction*>())
1427 buildInstructionOperandReference(II.get(), OperandName, i);
1429 buildAliasOperandReference(II.get(), OperandName, Op);
1432 if (II->DefRec.is<const CodeGenInstruction*>()) {
1433 II->buildInstructionResultOperands();
1434 // If the instruction has a two-operand alias, build up the
1435 // matchable here. We'll add them in bulk at the end to avoid
1436 // confusing this loop.
1437 std::string Constraint =
1438 II->TheDef->getValueAsString("TwoOperandAliasConstraint");
1439 if (Constraint != "") {
1440 // Start by making a copy of the original matchable.
1441 std::unique_ptr<MatchableInfo> AliasII(new MatchableInfo(*II));
1443 // Adjust it to be a two-operand alias.
1444 AliasII->formTwoOperandAlias(Constraint);
1446 // Add the alias to the matchables list.
1447 NewMatchables.push_back(std::move(AliasII));
1450 II->buildAliasResultOperands();
1452 if (!NewMatchables.empty())
1453 std::move(NewMatchables.begin(), NewMatchables.end(),
1454 std::back_inserter(Matchables));
1456 // Process token alias definitions and set up the associated superclass
1458 std::vector<Record*> AllTokenAliases =
1459 Records.getAllDerivedDefinitions("TokenAlias");
1460 for (unsigned i = 0, e = AllTokenAliases.size(); i != e; ++i) {
1461 Record *Rec = AllTokenAliases[i];
1462 ClassInfo *FromClass = getTokenClass(Rec->getValueAsString("FromToken"));
1463 ClassInfo *ToClass = getTokenClass(Rec->getValueAsString("ToToken"));
1464 if (FromClass == ToClass)
1465 PrintFatalError(Rec->getLoc(),
1466 "error: Destination value identical to source value.");
1467 FromClass->SuperClasses.push_back(ToClass);
1470 // Reorder classes so that classes precede super classes.
1474 /// buildInstructionOperandReference - The specified operand is a reference to a
1475 /// named operand such as $src. Resolve the Class and OperandInfo pointers.
1476 void AsmMatcherInfo::
1477 buildInstructionOperandReference(MatchableInfo *II,
1478 StringRef OperandName,
1479 unsigned AsmOpIdx) {
1480 const CodeGenInstruction &CGI = *II->DefRec.get<const CodeGenInstruction*>();
1481 const CGIOperandList &Operands = CGI.Operands;
1482 MatchableInfo::AsmOperand *Op = &II->AsmOperands[AsmOpIdx];
1484 // Map this token to an operand.
1486 if (!Operands.hasOperandNamed(OperandName, Idx))
1487 PrintFatalError(II->TheDef->getLoc(),
1488 "error: unable to find operand: '" + OperandName + "'");
1490 // If the instruction operand has multiple suboperands, but the parser
1491 // match class for the asm operand is still the default "ImmAsmOperand",
1492 // then handle each suboperand separately.
1493 if (Op->SubOpIdx == -1 && Operands[Idx].MINumOperands > 1) {
1494 Record *Rec = Operands[Idx].Rec;
1495 assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
1496 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1497 if (MatchClass && MatchClass->getValueAsString("Name") == "Imm") {
1498 // Insert remaining suboperands after AsmOpIdx in II->AsmOperands.
1499 StringRef Token = Op->Token; // save this in case Op gets moved
1500 for (unsigned SI = 1, SE = Operands[Idx].MINumOperands; SI != SE; ++SI) {
1501 MatchableInfo::AsmOperand NewAsmOp(Token);
1502 NewAsmOp.SubOpIdx = SI;
1503 II->AsmOperands.insert(II->AsmOperands.begin()+AsmOpIdx+SI, NewAsmOp);
1505 // Replace Op with first suboperand.
1506 Op = &II->AsmOperands[AsmOpIdx]; // update the pointer in case it moved
1511 // Set up the operand class.
1512 Op->Class = getOperandClass(Operands[Idx], Op->SubOpIdx);
1514 // If the named operand is tied, canonicalize it to the untied operand.
1515 // For example, something like:
1516 // (outs GPR:$dst), (ins GPR:$src)
1517 // with an asmstring of
1519 // we want to canonicalize to:
1521 // so that we know how to provide the $dst operand when filling in the result.
1523 if (Operands[Idx].MINumOperands == 1)
1524 OITied = Operands[Idx].getTiedRegister();
1526 // The tied operand index is an MIOperand index, find the operand that
1528 std::pair<unsigned, unsigned> Idx = Operands.getSubOperandNumber(OITied);
1529 OperandName = Operands[Idx.first].Name;
1530 Op->SubOpIdx = Idx.second;
1533 Op->SrcOpName = OperandName;
1536 /// buildAliasOperandReference - When parsing an operand reference out of the
1537 /// matching string (e.g. "movsx $src, $dst"), determine what the class of the
1538 /// operand reference is by looking it up in the result pattern definition.
1539 void AsmMatcherInfo::buildAliasOperandReference(MatchableInfo *II,
1540 StringRef OperandName,
1541 MatchableInfo::AsmOperand &Op) {
1542 const CodeGenInstAlias &CGA = *II->DefRec.get<const CodeGenInstAlias*>();
1544 // Set up the operand class.
1545 for (unsigned i = 0, e = CGA.ResultOperands.size(); i != e; ++i)
1546 if (CGA.ResultOperands[i].isRecord() &&
1547 CGA.ResultOperands[i].getName() == OperandName) {
1548 // It's safe to go with the first one we find, because CodeGenInstAlias
1549 // validates that all operands with the same name have the same record.
1550 Op.SubOpIdx = CGA.ResultInstOperandIndex[i].second;
1551 // Use the match class from the Alias definition, not the
1552 // destination instruction, as we may have an immediate that's
1553 // being munged by the match class.
1554 Op.Class = getOperandClass(CGA.ResultOperands[i].getRecord(),
1556 Op.SrcOpName = OperandName;
1560 PrintFatalError(II->TheDef->getLoc(),
1561 "error: unable to find operand: '" + OperandName + "'");
1564 void MatchableInfo::buildInstructionResultOperands() {
1565 const CodeGenInstruction *ResultInst = getResultInst();
1567 // Loop over all operands of the result instruction, determining how to
1569 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1570 const CGIOperandList::OperandInfo &OpInfo = ResultInst->Operands[i];
1572 // If this is a tied operand, just copy from the previously handled operand.
1574 if (OpInfo.MINumOperands == 1)
1575 TiedOp = OpInfo.getTiedRegister();
1577 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1581 // Find out what operand from the asmparser this MCInst operand comes from.
1582 int SrcOperand = findAsmOperandNamed(OpInfo.Name);
1583 if (OpInfo.Name.empty() || SrcOperand == -1) {
1584 // This may happen for operands that are tied to a suboperand of a
1585 // complex operand. Simply use a dummy value here; nobody should
1586 // use this operand slot.
1587 // FIXME: The long term goal is for the MCOperand list to not contain
1588 // tied operands at all.
1589 ResOperands.push_back(ResOperand::getImmOp(0));
1593 // Check if the one AsmOperand populates the entire operand.
1594 unsigned NumOperands = OpInfo.MINumOperands;
1595 if (AsmOperands[SrcOperand].SubOpIdx == -1) {
1596 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, NumOperands));
1600 // Add a separate ResOperand for each suboperand.
1601 for (unsigned AI = 0; AI < NumOperands; ++AI) {
1602 assert(AsmOperands[SrcOperand+AI].SubOpIdx == (int)AI &&
1603 AsmOperands[SrcOperand+AI].SrcOpName == OpInfo.Name &&
1604 "unexpected AsmOperands for suboperands");
1605 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand + AI, 1));
1610 void MatchableInfo::buildAliasResultOperands() {
1611 const CodeGenInstAlias &CGA = *DefRec.get<const CodeGenInstAlias*>();
1612 const CodeGenInstruction *ResultInst = getResultInst();
1614 // Loop over all operands of the result instruction, determining how to
1616 unsigned AliasOpNo = 0;
1617 unsigned LastOpNo = CGA.ResultInstOperandIndex.size();
1618 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1619 const CGIOperandList::OperandInfo *OpInfo = &ResultInst->Operands[i];
1621 // If this is a tied operand, just copy from the previously handled operand.
1623 if (OpInfo->MINumOperands == 1)
1624 TiedOp = OpInfo->getTiedRegister();
1626 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1630 // Handle all the suboperands for this operand.
1631 const std::string &OpName = OpInfo->Name;
1632 for ( ; AliasOpNo < LastOpNo &&
1633 CGA.ResultInstOperandIndex[AliasOpNo].first == i; ++AliasOpNo) {
1634 int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second;
1636 // Find out what operand from the asmparser that this MCInst operand
1638 switch (CGA.ResultOperands[AliasOpNo].Kind) {
1639 case CodeGenInstAlias::ResultOperand::K_Record: {
1640 StringRef Name = CGA.ResultOperands[AliasOpNo].getName();
1641 int SrcOperand = findAsmOperand(Name, SubIdx);
1642 if (SrcOperand == -1)
1643 PrintFatalError(TheDef->getLoc(), "Instruction '" +
1644 TheDef->getName() + "' has operand '" + OpName +
1645 "' that doesn't appear in asm string!");
1646 unsigned NumOperands = (SubIdx == -1 ? OpInfo->MINumOperands : 1);
1647 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand,
1651 case CodeGenInstAlias::ResultOperand::K_Imm: {
1652 int64_t ImmVal = CGA.ResultOperands[AliasOpNo].getImm();
1653 ResOperands.push_back(ResOperand::getImmOp(ImmVal));
1656 case CodeGenInstAlias::ResultOperand::K_Reg: {
1657 Record *Reg = CGA.ResultOperands[AliasOpNo].getRegister();
1658 ResOperands.push_back(ResOperand::getRegOp(Reg));
1666 static unsigned getConverterOperandID(const std::string &Name,
1667 SetVector<std::string> &Table,
1669 IsNew = Table.insert(Name);
1671 unsigned ID = IsNew ? Table.size() - 1 :
1672 std::find(Table.begin(), Table.end(), Name) - Table.begin();
1674 assert(ID < Table.size());
1680 static void emitConvertFuncs(CodeGenTarget &Target, StringRef ClassName,
1681 std::vector<std::unique_ptr<MatchableInfo>> &Infos,
1683 SetVector<std::string> OperandConversionKinds;
1684 SetVector<std::string> InstructionConversionKinds;
1685 std::vector<std::vector<uint8_t> > ConversionTable;
1686 size_t MaxRowLength = 2; // minimum is custom converter plus terminator.
1688 // TargetOperandClass - This is the target's operand class, like X86Operand.
1689 std::string TargetOperandClass = Target.getName() + "Operand";
1691 // Write the convert function to a separate stream, so we can drop it after
1692 // the enum. We'll build up the conversion handlers for the individual
1693 // operand types opportunistically as we encounter them.
1694 std::string ConvertFnBody;
1695 raw_string_ostream CvtOS(ConvertFnBody);
1696 // Start the unified conversion function.
1697 CvtOS << "void " << Target.getName() << ClassName << "::\n"
1698 << "convertToMCInst(unsigned Kind, MCInst &Inst, "
1699 << "unsigned Opcode,\n"
1700 << " const OperandVector"
1701 << " &Operands) {\n"
1702 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
1703 << " const uint8_t *Converter = ConversionTable[Kind];\n"
1704 << " Inst.setOpcode(Opcode);\n"
1705 << " for (const uint8_t *p = Converter; *p; p+= 2) {\n"
1706 << " switch (*p) {\n"
1707 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
1708 << " case CVT_Reg:\n"
1709 << " static_cast<" << TargetOperandClass
1710 << "&>(*Operands[*(p + 1)]).addRegOperands(Inst, 1);\n"
1712 << " case CVT_Tied:\n"
1713 << " Inst.addOperand(Inst.getOperand(*(p + 1)));\n"
1716 std::string OperandFnBody;
1717 raw_string_ostream OpOS(OperandFnBody);
1718 // Start the operand number lookup function.
1719 OpOS << "void " << Target.getName() << ClassName << "::\n"
1720 << "convertToMapAndConstraints(unsigned Kind,\n";
1722 OpOS << "const OperandVector &Operands) {\n"
1723 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
1724 << " unsigned NumMCOperands = 0;\n"
1725 << " const uint8_t *Converter = ConversionTable[Kind];\n"
1726 << " for (const uint8_t *p = Converter; *p; p+= 2) {\n"
1727 << " switch (*p) {\n"
1728 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
1729 << " case CVT_Reg:\n"
1730 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1731 << " Operands[*(p + 1)]->setConstraint(\"r\");\n"
1732 << " ++NumMCOperands;\n"
1734 << " case CVT_Tied:\n"
1735 << " ++NumMCOperands;\n"
1738 // Pre-populate the operand conversion kinds with the standard always
1739 // available entries.
1740 OperandConversionKinds.insert("CVT_Done");
1741 OperandConversionKinds.insert("CVT_Reg");
1742 OperandConversionKinds.insert("CVT_Tied");
1743 enum { CVT_Done, CVT_Reg, CVT_Tied };
1745 for (auto &II : Infos) {
1746 // Check if we have a custom match function.
1747 std::string AsmMatchConverter =
1748 II->getResultInst()->TheDef->getValueAsString("AsmMatchConverter");
1749 if (!AsmMatchConverter.empty()) {
1750 std::string Signature = "ConvertCustom_" + AsmMatchConverter;
1751 II->ConversionFnKind = Signature;
1753 // Check if we have already generated this signature.
1754 if (!InstructionConversionKinds.insert(Signature))
1757 // Remember this converter for the kind enum.
1758 unsigned KindID = OperandConversionKinds.size();
1759 OperandConversionKinds.insert("CVT_" +
1760 getEnumNameForToken(AsmMatchConverter));
1762 // Add the converter row for this instruction.
1763 ConversionTable.push_back(std::vector<uint8_t>());
1764 ConversionTable.back().push_back(KindID);
1765 ConversionTable.back().push_back(CVT_Done);
1767 // Add the handler to the conversion driver function.
1768 CvtOS << " case CVT_"
1769 << getEnumNameForToken(AsmMatchConverter) << ":\n"
1770 << " " << AsmMatchConverter << "(Inst, Operands);\n"
1773 // FIXME: Handle the operand number lookup for custom match functions.
1777 // Build the conversion function signature.
1778 std::string Signature = "Convert";
1780 std::vector<uint8_t> ConversionRow;
1782 // Compute the convert enum and the case body.
1783 MaxRowLength = std::max(MaxRowLength, II->ResOperands.size()*2 + 1 );
1785 for (unsigned i = 0, e = II->ResOperands.size(); i != e; ++i) {
1786 const MatchableInfo::ResOperand &OpInfo = II->ResOperands[i];
1788 // Generate code to populate each result operand.
1789 switch (OpInfo.Kind) {
1790 case MatchableInfo::ResOperand::RenderAsmOperand: {
1791 // This comes from something we parsed.
1792 const MatchableInfo::AsmOperand &Op =
1793 II->AsmOperands[OpInfo.AsmOperandNum];
1795 // Registers are always converted the same, don't duplicate the
1796 // conversion function based on them.
1799 Class = Op.Class->isRegisterClass() ? "Reg" : Op.Class->ClassName;
1801 Signature += utostr(OpInfo.MINumOperands);
1802 Signature += "_" + itostr(OpInfo.AsmOperandNum);
1804 // Add the conversion kind, if necessary, and get the associated ID
1805 // the index of its entry in the vector).
1806 std::string Name = "CVT_" + (Op.Class->isRegisterClass() ? "Reg" :
1807 Op.Class->RenderMethod);
1808 Name = getEnumNameForToken(Name);
1810 bool IsNewConverter = false;
1811 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1814 // Add the operand entry to the instruction kind conversion row.
1815 ConversionRow.push_back(ID);
1816 ConversionRow.push_back(OpInfo.AsmOperandNum + 1);
1818 if (!IsNewConverter)
1821 // This is a new operand kind. Add a handler for it to the
1822 // converter driver.
1823 CvtOS << " case " << Name << ":\n"
1824 << " static_cast<" << TargetOperandClass
1825 << "&>(*Operands[*(p + 1)])." << Op.Class->RenderMethod
1826 << "(Inst, " << OpInfo.MINumOperands << ");\n"
1829 // Add a handler for the operand number lookup.
1830 OpOS << " case " << Name << ":\n"
1831 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n";
1833 if (Op.Class->isRegisterClass())
1834 OpOS << " Operands[*(p + 1)]->setConstraint(\"r\");\n";
1836 OpOS << " Operands[*(p + 1)]->setConstraint(\"m\");\n";
1837 OpOS << " NumMCOperands += " << OpInfo.MINumOperands << ";\n"
1841 case MatchableInfo::ResOperand::TiedOperand: {
1842 // If this operand is tied to a previous one, just copy the MCInst
1843 // operand from the earlier one.We can only tie single MCOperand values.
1844 assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand");
1845 unsigned TiedOp = OpInfo.TiedOperandNum;
1846 assert(i > TiedOp && "Tied operand precedes its target!");
1847 Signature += "__Tie" + utostr(TiedOp);
1848 ConversionRow.push_back(CVT_Tied);
1849 ConversionRow.push_back(TiedOp);
1852 case MatchableInfo::ResOperand::ImmOperand: {
1853 int64_t Val = OpInfo.ImmVal;
1854 std::string Ty = "imm_" + itostr(Val);
1855 Signature += "__" + Ty;
1857 std::string Name = "CVT_" + Ty;
1858 bool IsNewConverter = false;
1859 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1861 // Add the operand entry to the instruction kind conversion row.
1862 ConversionRow.push_back(ID);
1863 ConversionRow.push_back(0);
1865 if (!IsNewConverter)
1868 CvtOS << " case " << Name << ":\n"
1869 << " Inst.addOperand(MCOperand::CreateImm(" << Val << "));\n"
1872 OpOS << " case " << Name << ":\n"
1873 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1874 << " Operands[*(p + 1)]->setConstraint(\"\");\n"
1875 << " ++NumMCOperands;\n"
1879 case MatchableInfo::ResOperand::RegOperand: {
1880 std::string Reg, Name;
1881 if (!OpInfo.Register) {
1885 Reg = getQualifiedName(OpInfo.Register);
1886 Name = "reg" + OpInfo.Register->getName();
1888 Signature += "__" + Name;
1889 Name = "CVT_" + Name;
1890 bool IsNewConverter = false;
1891 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1893 // Add the operand entry to the instruction kind conversion row.
1894 ConversionRow.push_back(ID);
1895 ConversionRow.push_back(0);
1897 if (!IsNewConverter)
1899 CvtOS << " case " << Name << ":\n"
1900 << " Inst.addOperand(MCOperand::CreateReg(" << Reg << "));\n"
1903 OpOS << " case " << Name << ":\n"
1904 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1905 << " Operands[*(p + 1)]->setConstraint(\"m\");\n"
1906 << " ++NumMCOperands;\n"
1912 // If there were no operands, add to the signature to that effect
1913 if (Signature == "Convert")
1914 Signature += "_NoOperands";
1916 II->ConversionFnKind = Signature;
1918 // Save the signature. If we already have it, don't add a new row
1920 if (!InstructionConversionKinds.insert(Signature))
1923 // Add the row to the table.
1924 ConversionTable.push_back(ConversionRow);
1927 // Finish up the converter driver function.
1928 CvtOS << " }\n }\n}\n\n";
1930 // Finish up the operand number lookup function.
1931 OpOS << " }\n }\n}\n\n";
1933 OS << "namespace {\n";
1935 // Output the operand conversion kind enum.
1936 OS << "enum OperatorConversionKind {\n";
1937 for (unsigned i = 0, e = OperandConversionKinds.size(); i != e; ++i)
1938 OS << " " << OperandConversionKinds[i] << ",\n";
1939 OS << " CVT_NUM_CONVERTERS\n";
1942 // Output the instruction conversion kind enum.
1943 OS << "enum InstructionConversionKind {\n";
1944 for (SetVector<std::string>::const_iterator
1945 i = InstructionConversionKinds.begin(),
1946 e = InstructionConversionKinds.end(); i != e; ++i)
1947 OS << " " << *i << ",\n";
1948 OS << " CVT_NUM_SIGNATURES\n";
1952 OS << "} // end anonymous namespace\n\n";
1954 // Output the conversion table.
1955 OS << "static const uint8_t ConversionTable[CVT_NUM_SIGNATURES]["
1956 << MaxRowLength << "] = {\n";
1958 for (unsigned Row = 0, ERow = ConversionTable.size(); Row != ERow; ++Row) {
1959 assert(ConversionTable[Row].size() % 2 == 0 && "bad conversion row!");
1960 OS << " // " << InstructionConversionKinds[Row] << "\n";
1962 for (unsigned i = 0, e = ConversionTable[Row].size(); i != e; i += 2)
1963 OS << OperandConversionKinds[ConversionTable[Row][i]] << ", "
1964 << (unsigned)(ConversionTable[Row][i + 1]) << ", ";
1965 OS << "CVT_Done },\n";
1970 // Spit out the conversion driver function.
1973 // Spit out the operand number lookup function.
1977 /// emitMatchClassEnumeration - Emit the enumeration for match class kinds.
1978 static void emitMatchClassEnumeration(CodeGenTarget &Target,
1979 std::forward_list<ClassInfo> &Infos,
1981 OS << "namespace {\n\n";
1983 OS << "/// MatchClassKind - The kinds of classes which participate in\n"
1984 << "/// instruction matching.\n";
1985 OS << "enum MatchClassKind {\n";
1986 OS << " InvalidMatchClass = 0,\n";
1987 for (const auto &CI : Infos) {
1988 OS << " " << CI.Name << ", // ";
1989 if (CI.Kind == ClassInfo::Token) {
1990 OS << "'" << CI.ValueName << "'\n";
1991 } else if (CI.isRegisterClass()) {
1992 if (!CI.ValueName.empty())
1993 OS << "register class '" << CI.ValueName << "'\n";
1995 OS << "derived register class\n";
1997 OS << "user defined class '" << CI.ValueName << "'\n";
2000 OS << " NumMatchClassKinds\n";
2006 /// emitValidateOperandClass - Emit the function to validate an operand class.
2007 static void emitValidateOperandClass(AsmMatcherInfo &Info,
2009 OS << "static unsigned validateOperandClass(MCParsedAsmOperand &GOp, "
2010 << "MatchClassKind Kind) {\n";
2011 OS << " " << Info.Target.getName() << "Operand &Operand = ("
2012 << Info.Target.getName() << "Operand&)GOp;\n";
2014 // The InvalidMatchClass is not to match any operand.
2015 OS << " if (Kind == InvalidMatchClass)\n";
2016 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n\n";
2018 // Check for Token operands first.
2019 // FIXME: Use a more specific diagnostic type.
2020 OS << " if (Operand.isToken())\n";
2021 OS << " return isSubclass(matchTokenString(Operand.getToken()), Kind) ?\n"
2022 << " MCTargetAsmParser::Match_Success :\n"
2023 << " MCTargetAsmParser::Match_InvalidOperand;\n\n";
2025 // Check the user classes. We don't care what order since we're only
2026 // actually matching against one of them.
2027 for (const auto &CI : Info.Classes) {
2028 if (!CI.isUserClass())
2031 OS << " // '" << CI.ClassName << "' class\n";
2032 OS << " if (Kind == " << CI.Name << ") {\n";
2033 OS << " if (Operand." << CI.PredicateMethod << "())\n";
2034 OS << " return MCTargetAsmParser::Match_Success;\n";
2035 if (!CI.DiagnosticType.empty())
2036 OS << " return " << Info.Target.getName() << "AsmParser::Match_"
2037 << CI.DiagnosticType << ";\n";
2041 // Check for register operands, including sub-classes.
2042 OS << " if (Operand.isReg()) {\n";
2043 OS << " MatchClassKind OpKind;\n";
2044 OS << " switch (Operand.getReg()) {\n";
2045 OS << " default: OpKind = InvalidMatchClass; break;\n";
2046 for (const auto &RC : Info.RegisterClasses)
2047 OS << " case " << Info.Target.getName() << "::"
2048 << RC.first->getName() << ": OpKind = " << RC.second->Name
2051 OS << " return isSubclass(OpKind, Kind) ? "
2052 << "MCTargetAsmParser::Match_Success :\n "
2053 << " MCTargetAsmParser::Match_InvalidOperand;\n }\n\n";
2055 // Generic fallthrough match failure case for operands that don't have
2056 // specialized diagnostic types.
2057 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n";
2061 /// emitIsSubclass - Emit the subclass predicate function.
2062 static void emitIsSubclass(CodeGenTarget &Target,
2063 std::forward_list<ClassInfo> &Infos,
2065 OS << "/// isSubclass - Compute whether \\p A is a subclass of \\p B.\n";
2066 OS << "static bool isSubclass(MatchClassKind A, MatchClassKind B) {\n";
2067 OS << " if (A == B)\n";
2068 OS << " return true;\n\n";
2071 raw_string_ostream SS(OStr);
2073 SS << " switch (A) {\n";
2074 SS << " default:\n";
2075 SS << " return false;\n";
2076 for (const auto &A : Infos) {
2077 std::vector<StringRef> SuperClasses;
2078 for (const auto &B : Infos) {
2079 if (&A != &B && A.isSubsetOf(B))
2080 SuperClasses.push_back(B.Name);
2083 if (SuperClasses.empty())
2087 SS << "\n case " << A.Name << ":\n";
2089 if (SuperClasses.size() == 1) {
2090 SS << " return B == " << SuperClasses.back().str() << ";\n";
2094 if (!SuperClasses.empty()) {
2095 SS << " switch (B) {\n";
2096 SS << " default: return false;\n";
2097 for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i)
2098 SS << " case " << SuperClasses[i].str() << ": return true;\n";
2101 // No case statement to emit
2102 SS << " return false;\n";
2107 // If there were case statements emitted into the string stream, write them
2108 // to the output stream, otherwise write the default.
2112 OS << " return false;\n";
2117 /// emitMatchTokenString - Emit the function to match a token string to the
2118 /// appropriate match class value.
2119 static void emitMatchTokenString(CodeGenTarget &Target,
2120 std::forward_list<ClassInfo> &Infos,
2122 // Construct the match list.
2123 std::vector<StringMatcher::StringPair> Matches;
2124 for (const auto &CI : Infos) {
2125 if (CI.Kind == ClassInfo::Token)
2127 StringMatcher::StringPair(CI.ValueName, "return " + CI.Name + ";"));
2130 OS << "static MatchClassKind matchTokenString(StringRef Name) {\n";
2132 StringMatcher("Name", Matches, OS).Emit();
2134 OS << " return InvalidMatchClass;\n";
2138 /// emitMatchRegisterName - Emit the function to match a string to the target
2139 /// specific register enum.
2140 static void emitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
2142 // Construct the match list.
2143 std::vector<StringMatcher::StringPair> Matches;
2144 const auto &Regs = Target.getRegBank().getRegisters();
2145 for (const CodeGenRegister &Reg : Regs) {
2146 if (Reg.TheDef->getValueAsString("AsmName").empty())
2150 StringMatcher::StringPair(Reg.TheDef->getValueAsString("AsmName"),
2151 "return " + utostr(Reg.EnumValue) + ";"));
2154 OS << "static unsigned MatchRegisterName(StringRef Name) {\n";
2156 StringMatcher("Name", Matches, OS).Emit();
2158 OS << " return 0;\n";
2162 static const char *getMinimalTypeForRange(uint64_t Range) {
2163 assert(Range <= 0xFFFFFFFFFFFFFFFFULL && "Enum too large");
2164 if (Range > 0xFFFFFFFFULL)
2173 static const char *getMinimalRequiredFeaturesType(const AsmMatcherInfo &Info) {
2174 uint64_t MaxIndex = Info.SubtargetFeatures.size();
2177 return getMinimalTypeForRange(1ULL << MaxIndex);
2180 /// emitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag
2182 static void emitSubtargetFeatureFlagEnumeration(AsmMatcherInfo &Info,
2184 OS << "// Flags for subtarget features that participate in "
2185 << "instruction matching.\n";
2186 OS << "enum SubtargetFeatureFlag : " << getMinimalRequiredFeaturesType(Info)
2188 for (const auto &SF : Info.SubtargetFeatures) {
2189 const SubtargetFeatureInfo &SFI = SF.second;
2190 OS << " " << SFI.getEnumName() << " = (1ULL << " << SFI.Index << "),\n";
2192 OS << " Feature_None = 0\n";
2196 /// emitOperandDiagnosticTypes - Emit the operand matching diagnostic types.
2197 static void emitOperandDiagnosticTypes(AsmMatcherInfo &Info, raw_ostream &OS) {
2198 // Get the set of diagnostic types from all of the operand classes.
2199 std::set<StringRef> Types;
2200 for (std::map<Record*, ClassInfo*>::const_iterator
2201 I = Info.AsmOperandClasses.begin(),
2202 E = Info.AsmOperandClasses.end(); I != E; ++I) {
2203 if (!I->second->DiagnosticType.empty())
2204 Types.insert(I->second->DiagnosticType);
2207 if (Types.empty()) return;
2209 // Now emit the enum entries.
2210 for (std::set<StringRef>::const_iterator I = Types.begin(), E = Types.end();
2212 OS << " Match_" << *I << ",\n";
2213 OS << " END_OPERAND_DIAGNOSTIC_TYPES\n";
2216 /// emitGetSubtargetFeatureName - Emit the helper function to get the
2217 /// user-level name for a subtarget feature.
2218 static void emitGetSubtargetFeatureName(AsmMatcherInfo &Info, raw_ostream &OS) {
2219 OS << "// User-level names for subtarget features that participate in\n"
2220 << "// instruction matching.\n"
2221 << "static const char *getSubtargetFeatureName(uint64_t Val) {\n";
2222 if (!Info.SubtargetFeatures.empty()) {
2223 OS << " switch(Val) {\n";
2224 for (const auto &SF : Info.SubtargetFeatures) {
2225 const SubtargetFeatureInfo &SFI = SF.second;
2226 // FIXME: Totally just a placeholder name to get the algorithm working.
2227 OS << " case " << SFI.getEnumName() << ": return \""
2228 << SFI.TheDef->getValueAsString("PredicateName") << "\";\n";
2230 OS << " default: return \"(unknown)\";\n";
2233 // Nothing to emit, so skip the switch
2234 OS << " return \"(unknown)\";\n";
2239 /// emitComputeAvailableFeatures - Emit the function to compute the list of
2240 /// available features given a subtarget.
2241 static void emitComputeAvailableFeatures(AsmMatcherInfo &Info,
2243 std::string ClassName =
2244 Info.AsmParser->getValueAsString("AsmParserClassName");
2246 OS << "uint64_t " << Info.Target.getName() << ClassName << "::\n"
2247 << "ComputeAvailableFeatures(uint64_t FB) const {\n";
2248 OS << " uint64_t Features = 0;\n";
2249 for (const auto &SF : Info.SubtargetFeatures) {
2250 const SubtargetFeatureInfo &SFI = SF.second;
2253 std::string CondStorage =
2254 SFI.TheDef->getValueAsString("AssemblerCondString");
2255 StringRef Conds = CondStorage;
2256 std::pair<StringRef,StringRef> Comma = Conds.split(',');
2263 StringRef Cond = Comma.first;
2264 if (Cond[0] == '!') {
2266 Cond = Cond.substr(1);
2269 OS << "((FB & " << Info.Target.getName() << "::" << Cond << ")";
2276 if (Comma.second.empty())
2280 Comma = Comma.second.split(',');
2284 OS << " Features |= " << SFI.getEnumName() << ";\n";
2286 OS << " return Features;\n";
2290 static std::string GetAliasRequiredFeatures(Record *R,
2291 const AsmMatcherInfo &Info) {
2292 std::vector<Record*> ReqFeatures = R->getValueAsListOfDefs("Predicates");
2294 unsigned NumFeatures = 0;
2295 for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) {
2296 const SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]);
2299 PrintFatalError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() +
2300 "' is not marked as an AssemblerPredicate!");
2305 Result += F->getEnumName();
2309 if (NumFeatures > 1)
2310 Result = '(' + Result + ')';
2314 static void emitMnemonicAliasVariant(raw_ostream &OS,const AsmMatcherInfo &Info,
2315 std::vector<Record*> &Aliases,
2316 unsigned Indent = 0,
2317 StringRef AsmParserVariantName = StringRef()){
2318 // Keep track of all the aliases from a mnemonic. Use an std::map so that the
2319 // iteration order of the map is stable.
2320 std::map<std::string, std::vector<Record*> > AliasesFromMnemonic;
2322 for (unsigned i = 0, e = Aliases.size(); i != e; ++i) {
2323 Record *R = Aliases[i];
2324 // FIXME: Allow AssemblerVariantName to be a comma separated list.
2325 std::string AsmVariantName = R->getValueAsString("AsmVariantName");
2326 if (AsmVariantName != AsmParserVariantName)
2328 AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R);
2330 if (AliasesFromMnemonic.empty())
2333 // Process each alias a "from" mnemonic at a time, building the code executed
2334 // by the string remapper.
2335 std::vector<StringMatcher::StringPair> Cases;
2336 for (std::map<std::string, std::vector<Record*> >::iterator
2337 I = AliasesFromMnemonic.begin(), E = AliasesFromMnemonic.end();
2339 const std::vector<Record*> &ToVec = I->second;
2341 // Loop through each alias and emit code that handles each case. If there
2342 // are two instructions without predicates, emit an error. If there is one,
2344 std::string MatchCode;
2345 int AliasWithNoPredicate = -1;
2347 for (unsigned i = 0, e = ToVec.size(); i != e; ++i) {
2348 Record *R = ToVec[i];
2349 std::string FeatureMask = GetAliasRequiredFeatures(R, Info);
2351 // If this unconditionally matches, remember it for later and diagnose
2353 if (FeatureMask.empty()) {
2354 if (AliasWithNoPredicate != -1) {
2355 // We can't have two aliases from the same mnemonic with no predicate.
2356 PrintError(ToVec[AliasWithNoPredicate]->getLoc(),
2357 "two MnemonicAliases with the same 'from' mnemonic!");
2358 PrintFatalError(R->getLoc(), "this is the other MnemonicAlias.");
2361 AliasWithNoPredicate = i;
2364 if (R->getValueAsString("ToMnemonic") == I->first)
2365 PrintFatalError(R->getLoc(), "MnemonicAlias to the same string");
2367 if (!MatchCode.empty())
2368 MatchCode += "else ";
2369 MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n";
2370 MatchCode += " Mnemonic = \"" +R->getValueAsString("ToMnemonic")+"\";\n";
2373 if (AliasWithNoPredicate != -1) {
2374 Record *R = ToVec[AliasWithNoPredicate];
2375 if (!MatchCode.empty())
2376 MatchCode += "else\n ";
2377 MatchCode += "Mnemonic = \"" + R->getValueAsString("ToMnemonic")+"\";\n";
2380 MatchCode += "return;";
2382 Cases.push_back(std::make_pair(I->first, MatchCode));
2384 StringMatcher("Mnemonic", Cases, OS).Emit(Indent);
2387 /// emitMnemonicAliases - If the target has any MnemonicAlias<> definitions,
2388 /// emit a function for them and return true, otherwise return false.
2389 static bool emitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info,
2390 CodeGenTarget &Target) {
2391 // Ignore aliases when match-prefix is set.
2392 if (!MatchPrefix.empty())
2395 std::vector<Record*> Aliases =
2396 Info.getRecords().getAllDerivedDefinitions("MnemonicAlias");
2397 if (Aliases.empty()) return false;
2399 OS << "static void applyMnemonicAliases(StringRef &Mnemonic, "
2400 "uint64_t Features, unsigned VariantID) {\n";
2401 OS << " switch (VariantID) {\n";
2402 unsigned VariantCount = Target.getAsmParserVariantCount();
2403 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2404 Record *AsmVariant = Target.getAsmParserVariant(VC);
2405 int AsmParserVariantNo = AsmVariant->getValueAsInt("Variant");
2406 std::string AsmParserVariantName = AsmVariant->getValueAsString("Name");
2407 OS << " case " << AsmParserVariantNo << ":\n";
2408 emitMnemonicAliasVariant(OS, Info, Aliases, /*Indent=*/2,
2409 AsmParserVariantName);
2414 // Emit aliases that apply to all variants.
2415 emitMnemonicAliasVariant(OS, Info, Aliases);
2422 static void emitCustomOperandParsing(raw_ostream &OS, CodeGenTarget &Target,
2423 const AsmMatcherInfo &Info, StringRef ClassName,
2424 StringToOffsetTable &StringTable,
2425 unsigned MaxMnemonicIndex) {
2426 unsigned MaxMask = 0;
2427 for (std::vector<OperandMatchEntry>::const_iterator it =
2428 Info.OperandMatchInfo.begin(), ie = Info.OperandMatchInfo.end();
2430 MaxMask |= it->OperandMask;
2433 // Emit the static custom operand parsing table;
2434 OS << "namespace {\n";
2435 OS << " struct OperandMatchEntry {\n";
2436 OS << " " << getMinimalRequiredFeaturesType(Info)
2437 << " RequiredFeatures;\n";
2438 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex)
2440 OS << " " << getMinimalTypeForRange(std::distance(
2441 Info.Classes.begin(), Info.Classes.end())) << " Class;\n";
2442 OS << " " << getMinimalTypeForRange(MaxMask)
2443 << " OperandMask;\n\n";
2444 OS << " StringRef getMnemonic() const {\n";
2445 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2446 OS << " MnemonicTable[Mnemonic]);\n";
2450 OS << " // Predicate for searching for an opcode.\n";
2451 OS << " struct LessOpcodeOperand {\n";
2452 OS << " bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {\n";
2453 OS << " return LHS.getMnemonic() < RHS;\n";
2455 OS << " bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {\n";
2456 OS << " return LHS < RHS.getMnemonic();\n";
2458 OS << " bool operator()(const OperandMatchEntry &LHS,";
2459 OS << " const OperandMatchEntry &RHS) {\n";
2460 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2464 OS << "} // end anonymous namespace.\n\n";
2466 OS << "static const OperandMatchEntry OperandMatchTable["
2467 << Info.OperandMatchInfo.size() << "] = {\n";
2469 OS << " /* Operand List Mask, Mnemonic, Operand Class, Features */\n";
2470 for (std::vector<OperandMatchEntry>::const_iterator it =
2471 Info.OperandMatchInfo.begin(), ie = Info.OperandMatchInfo.end();
2473 const OperandMatchEntry &OMI = *it;
2474 const MatchableInfo &II = *OMI.MI;
2478 // Write the required features mask.
2479 if (!II.RequiredFeatures.empty()) {
2480 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
2482 OS << II.RequiredFeatures[i]->getEnumName();
2487 // Store a pascal-style length byte in the mnemonic.
2488 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2489 OS << ", " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2490 << " /* " << II.Mnemonic << " */, ";
2494 OS << ", " << OMI.OperandMask;
2496 bool printComma = false;
2497 for (int i = 0, e = 31; i !=e; ++i)
2498 if (OMI.OperandMask & (1 << i)) {
2510 // Emit the operand class switch to call the correct custom parser for
2511 // the found operand class.
2512 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
2513 << Target.getName() << ClassName << "::\n"
2514 << "tryCustomParseOperand(OperandVector"
2515 << " &Operands,\n unsigned MCK) {\n\n"
2516 << " switch(MCK) {\n";
2518 for (const auto &CI : Info.Classes) {
2519 if (CI.ParserMethod.empty())
2521 OS << " case " << CI.Name << ":\n"
2522 << " return " << CI.ParserMethod << "(Operands);\n";
2525 OS << " default:\n";
2526 OS << " return MatchOperand_NoMatch;\n";
2528 OS << " return MatchOperand_NoMatch;\n";
2531 // Emit the static custom operand parser. This code is very similar with
2532 // the other matcher. Also use MatchResultTy here just in case we go for
2533 // a better error handling.
2534 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
2535 << Target.getName() << ClassName << "::\n"
2536 << "MatchOperandParserImpl(OperandVector"
2537 << " &Operands,\n StringRef Mnemonic) {\n";
2539 // Emit code to get the available features.
2540 OS << " // Get the current feature set.\n";
2541 OS << " uint64_t AvailableFeatures = getAvailableFeatures();\n\n";
2543 OS << " // Get the next operand index.\n";
2544 OS << " unsigned NextOpNum = Operands.size()-1;\n";
2546 // Emit code to search the table.
2547 OS << " // Search the table.\n";
2548 OS << " std::pair<const OperandMatchEntry*, const OperandMatchEntry*>";
2549 OS << " MnemonicRange =\n";
2550 OS << " std::equal_range(OperandMatchTable, OperandMatchTable+"
2551 << Info.OperandMatchInfo.size() << ", Mnemonic,\n"
2552 << " LessOpcodeOperand());\n\n";
2554 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2555 OS << " return MatchOperand_NoMatch;\n\n";
2557 OS << " for (const OperandMatchEntry *it = MnemonicRange.first,\n"
2558 << " *ie = MnemonicRange.second; it != ie; ++it) {\n";
2560 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2561 OS << " assert(Mnemonic == it->getMnemonic());\n\n";
2563 // Emit check that the required features are available.
2564 OS << " // check if the available features match\n";
2565 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2566 << "!= it->RequiredFeatures) {\n";
2567 OS << " continue;\n";
2570 // Emit check to ensure the operand number matches.
2571 OS << " // check if the operand in question has a custom parser.\n";
2572 OS << " if (!(it->OperandMask & (1 << NextOpNum)))\n";
2573 OS << " continue;\n\n";
2575 // Emit call to the custom parser method
2576 OS << " // call custom parse method to handle the operand\n";
2577 OS << " OperandMatchResultTy Result = ";
2578 OS << "tryCustomParseOperand(Operands, it->Class);\n";
2579 OS << " if (Result != MatchOperand_NoMatch)\n";
2580 OS << " return Result;\n";
2583 OS << " // Okay, we had no match.\n";
2584 OS << " return MatchOperand_NoMatch;\n";
2588 void AsmMatcherEmitter::run(raw_ostream &OS) {
2589 CodeGenTarget Target(Records);
2590 Record *AsmParser = Target.getAsmParser();
2591 std::string ClassName = AsmParser->getValueAsString("AsmParserClassName");
2593 // Compute the information on the instructions to match.
2594 AsmMatcherInfo Info(AsmParser, Target, Records);
2597 // Sort the instruction table using the partial order on classes. We use
2598 // stable_sort to ensure that ambiguous instructions are still
2599 // deterministically ordered.
2600 std::stable_sort(Info.Matchables.begin(), Info.Matchables.end(),
2601 [](const std::unique_ptr<MatchableInfo> &a,
2602 const std::unique_ptr<MatchableInfo> &b){
2605 DEBUG_WITH_TYPE("instruction_info", {
2606 for (const auto &MI : Info.Matchables)
2610 // Check for ambiguous matchables.
2611 DEBUG_WITH_TYPE("ambiguous_instrs", {
2612 unsigned NumAmbiguous = 0;
2613 for (unsigned i = 0, e = Info.Matchables.size(); i != e; ++i) {
2614 for (unsigned j = i + 1; j != e; ++j) {
2615 const MatchableInfo &A = *Info.Matchables[i];
2616 const MatchableInfo &B = *Info.Matchables[j];
2618 if (A.couldMatchAmbiguouslyWith(B)) {
2619 errs() << "warning: ambiguous matchables:\n";
2621 errs() << "\nis incomparable with:\n";
2629 errs() << "warning: " << NumAmbiguous
2630 << " ambiguous matchables!\n";
2633 // Compute the information on the custom operand parsing.
2634 Info.buildOperandMatchInfo();
2636 // Write the output.
2638 // Information for the class declaration.
2639 OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
2640 OS << "#undef GET_ASSEMBLER_HEADER\n";
2641 OS << " // This should be included into the middle of the declaration of\n";
2642 OS << " // your subclasses implementation of MCTargetAsmParser.\n";
2643 OS << " uint64_t ComputeAvailableFeatures(uint64_t FeatureBits) const;\n";
2644 OS << " void convertToMCInst(unsigned Kind, MCInst &Inst, "
2645 << "unsigned Opcode,\n"
2646 << " const OperandVector "
2648 OS << " void convertToMapAndConstraints(unsigned Kind,\n ";
2649 OS << " const OperandVector &Operands) override;\n";
2650 OS << " bool mnemonicIsValid(StringRef Mnemonic, unsigned VariantID) override;\n";
2651 OS << " unsigned MatchInstructionImpl(\n";
2653 OS << "const OperandVector &Operands,\n"
2654 << " MCInst &Inst,\n"
2655 << " uint64_t &ErrorInfo,"
2656 << " bool matchingInlineAsm,\n"
2657 << " unsigned VariantID = 0);\n";
2659 if (Info.OperandMatchInfo.size()) {
2660 OS << "\n enum OperandMatchResultTy {\n";
2661 OS << " MatchOperand_Success, // operand matched successfully\n";
2662 OS << " MatchOperand_NoMatch, // operand did not match\n";
2663 OS << " MatchOperand_ParseFail // operand matched but had errors\n";
2665 OS << " OperandMatchResultTy MatchOperandParserImpl(\n";
2666 OS << " OperandVector &Operands,\n";
2667 OS << " StringRef Mnemonic);\n";
2669 OS << " OperandMatchResultTy tryCustomParseOperand(\n";
2670 OS << " OperandVector &Operands,\n";
2671 OS << " unsigned MCK);\n\n";
2674 OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n";
2676 // Emit the operand match diagnostic enum names.
2677 OS << "\n#ifdef GET_OPERAND_DIAGNOSTIC_TYPES\n";
2678 OS << "#undef GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
2679 emitOperandDiagnosticTypes(Info, OS);
2680 OS << "#endif // GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
2683 OS << "\n#ifdef GET_REGISTER_MATCHER\n";
2684 OS << "#undef GET_REGISTER_MATCHER\n\n";
2686 // Emit the subtarget feature enumeration.
2687 emitSubtargetFeatureFlagEnumeration(Info, OS);
2689 // Emit the function to match a register name to number.
2690 // This should be omitted for Mips target
2691 if (AsmParser->getValueAsBit("ShouldEmitMatchRegisterName"))
2692 emitMatchRegisterName(Target, AsmParser, OS);
2694 OS << "#endif // GET_REGISTER_MATCHER\n\n";
2696 OS << "\n#ifdef GET_SUBTARGET_FEATURE_NAME\n";
2697 OS << "#undef GET_SUBTARGET_FEATURE_NAME\n\n";
2699 // Generate the helper function to get the names for subtarget features.
2700 emitGetSubtargetFeatureName(Info, OS);
2702 OS << "#endif // GET_SUBTARGET_FEATURE_NAME\n\n";
2704 OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
2705 OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
2707 // Generate the function that remaps for mnemonic aliases.
2708 bool HasMnemonicAliases = emitMnemonicAliases(OS, Info, Target);
2710 // Generate the convertToMCInst function to convert operands into an MCInst.
2711 // Also, generate the convertToMapAndConstraints function for MS-style inline
2712 // assembly. The latter doesn't actually generate a MCInst.
2713 emitConvertFuncs(Target, ClassName, Info.Matchables, OS);
2715 // Emit the enumeration for classes which participate in matching.
2716 emitMatchClassEnumeration(Target, Info.Classes, OS);
2718 // Emit the routine to match token strings to their match class.
2719 emitMatchTokenString(Target, Info.Classes, OS);
2721 // Emit the subclass predicate routine.
2722 emitIsSubclass(Target, Info.Classes, OS);
2724 // Emit the routine to validate an operand against a match class.
2725 emitValidateOperandClass(Info, OS);
2727 // Emit the available features compute function.
2728 emitComputeAvailableFeatures(Info, OS);
2731 StringToOffsetTable StringTable;
2733 size_t MaxNumOperands = 0;
2734 unsigned MaxMnemonicIndex = 0;
2735 bool HasDeprecation = false;
2736 for (const auto &MI : Info.Matchables) {
2737 MaxNumOperands = std::max(MaxNumOperands, MI->AsmOperands.size());
2738 HasDeprecation |= MI->HasDeprecation;
2740 // Store a pascal-style length byte in the mnemonic.
2741 std::string LenMnemonic = char(MI->Mnemonic.size()) + MI->Mnemonic.str();
2742 MaxMnemonicIndex = std::max(MaxMnemonicIndex,
2743 StringTable.GetOrAddStringOffset(LenMnemonic, false));
2746 OS << "static const char *const MnemonicTable =\n";
2747 StringTable.EmitString(OS);
2750 // Emit the static match table; unused classes get initalized to 0 which is
2751 // guaranteed to be InvalidMatchClass.
2753 // FIXME: We can reduce the size of this table very easily. First, we change
2754 // it so that store the kinds in separate bit-fields for each index, which
2755 // only needs to be the max width used for classes at that index (we also need
2756 // to reject based on this during classification). If we then make sure to
2757 // order the match kinds appropriately (putting mnemonics last), then we
2758 // should only end up using a few bits for each class, especially the ones
2759 // following the mnemonic.
2760 OS << "namespace {\n";
2761 OS << " struct MatchEntry {\n";
2762 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex)
2764 OS << " uint16_t Opcode;\n";
2765 OS << " " << getMinimalTypeForRange(Info.Matchables.size())
2767 OS << " " << getMinimalRequiredFeaturesType(Info)
2768 << " RequiredFeatures;\n";
2769 OS << " " << getMinimalTypeForRange(
2770 std::distance(Info.Classes.begin(), Info.Classes.end()))
2771 << " Classes[" << MaxNumOperands << "];\n";
2772 OS << " StringRef getMnemonic() const {\n";
2773 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2774 OS << " MnemonicTable[Mnemonic]);\n";
2778 OS << " // Predicate for searching for an opcode.\n";
2779 OS << " struct LessOpcode {\n";
2780 OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n";
2781 OS << " return LHS.getMnemonic() < RHS;\n";
2783 OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n";
2784 OS << " return LHS < RHS.getMnemonic();\n";
2786 OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n";
2787 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2791 OS << "} // end anonymous namespace.\n\n";
2793 unsigned VariantCount = Target.getAsmParserVariantCount();
2794 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2795 Record *AsmVariant = Target.getAsmParserVariant(VC);
2796 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2798 OS << "static const MatchEntry MatchTable" << VC << "[] = {\n";
2800 for (const auto &MI : Info.Matchables) {
2801 if (MI->AsmVariantID != AsmVariantNo)
2804 // Store a pascal-style length byte in the mnemonic.
2805 std::string LenMnemonic = char(MI->Mnemonic.size()) + MI->Mnemonic.str();
2806 OS << " { " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2807 << " /* " << MI->Mnemonic << " */, "
2808 << Target.getName() << "::"
2809 << MI->getResultInst()->TheDef->getName() << ", "
2810 << MI->ConversionFnKind << ", ";
2812 // Write the required features mask.
2813 if (!MI->RequiredFeatures.empty()) {
2814 for (unsigned i = 0, e = MI->RequiredFeatures.size(); i != e; ++i) {
2816 OS << MI->RequiredFeatures[i]->getEnumName();
2822 for (unsigned i = 0, e = MI->AsmOperands.size(); i != e; ++i) {
2823 const MatchableInfo::AsmOperand &Op = MI->AsmOperands[i];
2826 OS << Op.Class->Name;
2834 // A method to determine if a mnemonic is in the list.
2835 OS << "bool " << Target.getName() << ClassName << "::\n"
2836 << "mnemonicIsValid(StringRef Mnemonic, unsigned VariantID) {\n";
2837 OS << " // Find the appropriate table for this asm variant.\n";
2838 OS << " const MatchEntry *Start, *End;\n";
2839 OS << " switch (VariantID) {\n";
2840 OS << " default: // unreachable\n";
2841 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2842 Record *AsmVariant = Target.getAsmParserVariant(VC);
2843 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2844 OS << " case " << AsmVariantNo << ": Start = std::begin(MatchTable" << VC
2845 << "); End = std::end(MatchTable" << VC << "); break;\n";
2848 OS << " // Search the table.\n";
2849 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
2850 OS << " std::equal_range(Start, End, Mnemonic, LessOpcode());\n";
2851 OS << " return MnemonicRange.first != MnemonicRange.second;\n";
2854 // Finally, build the match function.
2855 OS << "unsigned " << Target.getName() << ClassName << "::\n"
2856 << "MatchInstructionImpl(const OperandVector"
2858 OS << " MCInst &Inst,\n"
2859 << "uint64_t &ErrorInfo, bool matchingInlineAsm, unsigned VariantID) {\n";
2861 OS << " // Eliminate obvious mismatches.\n";
2862 OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n";
2863 OS << " ErrorInfo = " << (MaxNumOperands+1) << ";\n";
2864 OS << " return Match_InvalidOperand;\n";
2867 // Emit code to get the available features.
2868 OS << " // Get the current feature set.\n";
2869 OS << " uint64_t AvailableFeatures = getAvailableFeatures();\n\n";
2871 OS << " // Get the instruction mnemonic, which is the first token.\n";
2872 OS << " StringRef Mnemonic = ((" << Target.getName()
2873 << "Operand&)*Operands[0]).getToken();\n\n";
2875 if (HasMnemonicAliases) {
2876 OS << " // Process all MnemonicAliases to remap the mnemonic.\n";
2877 OS << " applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);\n\n";
2880 // Emit code to compute the class list for this operand vector.
2881 OS << " // Some state to try to produce better error messages.\n";
2882 OS << " bool HadMatchOtherThanFeatures = false;\n";
2883 OS << " bool HadMatchOtherThanPredicate = false;\n";
2884 OS << " unsigned RetCode = Match_InvalidOperand;\n";
2885 OS << " uint64_t MissingFeatures = ~0ULL;\n";
2886 OS << " // Set ErrorInfo to the operand that mismatches if it is\n";
2887 OS << " // wrong for all instances of the instruction.\n";
2888 OS << " ErrorInfo = ~0U;\n";
2890 // Emit code to search the table.
2891 OS << " // Find the appropriate table for this asm variant.\n";
2892 OS << " const MatchEntry *Start, *End;\n";
2893 OS << " switch (VariantID) {\n";
2894 OS << " default: // unreachable\n";
2895 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2896 Record *AsmVariant = Target.getAsmParserVariant(VC);
2897 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2898 OS << " case " << AsmVariantNo << ": Start = std::begin(MatchTable" << VC
2899 << "); End = std::end(MatchTable" << VC << "); break;\n";
2902 OS << " // Search the table.\n";
2903 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
2904 OS << " std::equal_range(Start, End, Mnemonic, LessOpcode());\n\n";
2906 OS << " // Return a more specific error code if no mnemonics match.\n";
2907 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2908 OS << " return Match_MnemonicFail;\n\n";
2910 OS << " for (const MatchEntry *it = MnemonicRange.first, "
2911 << "*ie = MnemonicRange.second;\n";
2912 OS << " it != ie; ++it) {\n";
2914 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2915 OS << " assert(Mnemonic == it->getMnemonic());\n";
2917 // Emit check that the subclasses match.
2918 OS << " bool OperandsValid = true;\n";
2919 OS << " for (unsigned i = 0; i != " << MaxNumOperands << "; ++i) {\n";
2920 OS << " if (i + 1 >= Operands.size()) {\n";
2921 OS << " OperandsValid = (it->Classes[i] == " <<"InvalidMatchClass);\n";
2922 OS << " if (!OperandsValid) ErrorInfo = i + 1;\n";
2925 OS << " unsigned Diag = validateOperandClass(*Operands[i+1],\n";
2927 OS << "(MatchClassKind)it->Classes[i]);\n";
2928 OS << " if (Diag == Match_Success)\n";
2929 OS << " continue;\n";
2930 OS << " // If the generic handler indicates an invalid operand\n";
2931 OS << " // failure, check for a special case.\n";
2932 OS << " if (Diag == Match_InvalidOperand) {\n";
2933 OS << " Diag = validateTargetOperandClass(*Operands[i+1],\n";
2935 OS << "(MatchClassKind)it->Classes[i]);\n";
2936 OS << " if (Diag == Match_Success)\n";
2937 OS << " continue;\n";
2939 OS << " // If this operand is broken for all of the instances of this\n";
2940 OS << " // mnemonic, keep track of it so we can report loc info.\n";
2941 OS << " // If we already had a match that only failed due to a\n";
2942 OS << " // target predicate, that diagnostic is preferred.\n";
2943 OS << " if (!HadMatchOtherThanPredicate &&\n";
2944 OS << " (it == MnemonicRange.first || ErrorInfo <= i+1)) {\n";
2945 OS << " ErrorInfo = i+1;\n";
2946 OS << " // InvalidOperand is the default. Prefer specificity.\n";
2947 OS << " if (Diag != Match_InvalidOperand)\n";
2948 OS << " RetCode = Diag;\n";
2950 OS << " // Otherwise, just reject this instance of the mnemonic.\n";
2951 OS << " OperandsValid = false;\n";
2955 OS << " if (!OperandsValid) continue;\n";
2957 // Emit check that the required features are available.
2958 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2959 << "!= it->RequiredFeatures) {\n";
2960 OS << " HadMatchOtherThanFeatures = true;\n";
2961 OS << " uint64_t NewMissingFeatures = it->RequiredFeatures & "
2962 "~AvailableFeatures;\n";
2963 OS << " if (CountPopulation_64(NewMissingFeatures) <=\n"
2964 " CountPopulation_64(MissingFeatures))\n";
2965 OS << " MissingFeatures = NewMissingFeatures;\n";
2966 OS << " continue;\n";
2969 OS << " if (matchingInlineAsm) {\n";
2970 OS << " Inst.setOpcode(it->Opcode);\n";
2971 OS << " convertToMapAndConstraints(it->ConvertFn, Operands);\n";
2972 OS << " return Match_Success;\n";
2974 OS << " // We have selected a definite instruction, convert the parsed\n"
2975 << " // operands into the appropriate MCInst.\n";
2976 OS << " convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n";
2979 // Verify the instruction with the target-specific match predicate function.
2980 OS << " // We have a potential match. Check the target predicate to\n"
2981 << " // handle any context sensitive constraints.\n"
2982 << " unsigned MatchResult;\n"
2983 << " if ((MatchResult = checkTargetMatchPredicate(Inst)) !="
2984 << " Match_Success) {\n"
2985 << " Inst.clear();\n"
2986 << " RetCode = MatchResult;\n"
2987 << " HadMatchOtherThanPredicate = true;\n"
2991 // Call the post-processing function, if used.
2992 std::string InsnCleanupFn =
2993 AsmParser->getValueAsString("AsmParserInstCleanup");
2994 if (!InsnCleanupFn.empty())
2995 OS << " " << InsnCleanupFn << "(Inst);\n";
2997 if (HasDeprecation) {
2998 OS << " std::string Info;\n";
2999 OS << " if (MII.get(Inst.getOpcode()).getDeprecatedInfo(Inst, STI, Info)) {\n";
3000 OS << " SMLoc Loc = ((" << Target.getName()
3001 << "Operand&)*Operands[0]).getStartLoc();\n";
3002 OS << " getParser().Warning(Loc, Info, None);\n";
3006 OS << " return Match_Success;\n";
3009 OS << " // Okay, we had no match. Try to return a useful error code.\n";
3010 OS << " if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)\n";
3011 OS << " return RetCode;\n\n";
3012 OS << " // Missing feature matches return which features were missing\n";
3013 OS << " ErrorInfo = MissingFeatures;\n";
3014 OS << " return Match_MissingFeature;\n";
3017 if (Info.OperandMatchInfo.size())
3018 emitCustomOperandParsing(OS, Target, Info, ClassName, StringTable,
3021 OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";
3026 void EmitAsmMatcher(RecordKeeper &RK, raw_ostream &OS) {
3027 emitSourceFileHeader("Assembly Matcher Source Fragment", OS);
3028 AsmMatcherEmitter(RK).run(OS);
3031 } // End llvm namespace