1 //===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits a target specifier matcher for converting parsed
11 // assembly operands in the MCInst structures.
13 // The input to the target specific matcher is a list of literal tokens and
14 // operands. The target specific parser should generally eliminate any syntax
15 // which is not relevant for matching; for example, comma tokens should have
16 // already been consumed and eliminated by the parser. Most instructions will
17 // end up with a single literal token (the instruction name) and some number of
20 // Some example inputs, for X86:
21 // 'addl' (immediate ...) (register ...)
22 // 'add' (immediate ...) (memory ...)
25 // The assembly matcher is responsible for converting this input into a precise
26 // machine instruction (i.e., an instruction with a well defined encoding). This
27 // mapping has several properties which complicate matching:
29 // - It may be ambiguous; many architectures can legally encode particular
30 // variants of an instruction in different ways (for example, using a smaller
31 // encoding for small immediates). Such ambiguities should never be
32 // arbitrarily resolved by the assembler, the assembler is always responsible
33 // for choosing the "best" available instruction.
35 // - It may depend on the subtarget or the assembler context. Instructions
36 // which are invalid for the current mode, but otherwise unambiguous (e.g.,
37 // an SSE instruction in a file being assembled for i486) should be accepted
38 // and rejected by the assembler front end. However, if the proper encoding
39 // for an instruction is dependent on the assembler context then the matcher
40 // is responsible for selecting the correct machine instruction for the
43 // The core matching algorithm attempts to exploit the regularity in most
44 // instruction sets to quickly determine the set of possibly matching
45 // instructions, and the simplify the generated code. Additionally, this helps
46 // to ensure that the ambiguities are intentionally resolved by the user.
48 // The matching is divided into two distinct phases:
50 // 1. Classification: Each operand is mapped to the unique set which (a)
51 // contains it, and (b) is the largest such subset for which a single
52 // instruction could match all members.
54 // For register classes, we can generate these subgroups automatically. For
55 // arbitrary operands, we expect the user to define the classes and their
56 // relations to one another (for example, 8-bit signed immediates as a
57 // subset of 32-bit immediates).
59 // By partitioning the operands in this way, we guarantee that for any
60 // tuple of classes, any single instruction must match either all or none
61 // of the sets of operands which could classify to that tuple.
63 // In addition, the subset relation amongst classes induces a partial order
64 // on such tuples, which we use to resolve ambiguities.
66 // FIXME: What do we do if a crazy case shows up where this is the wrong
69 // 2. The input can now be treated as a tuple of classes (static tokens are
70 // simple singleton sets). Each such tuple should generally map to a single
71 // instruction (we currently ignore cases where this isn't true, whee!!!),
72 // which we can emit a simple matcher for.
74 //===----------------------------------------------------------------------===//
76 #include "AsmMatcherEmitter.h"
77 #include "CodeGenTarget.h"
79 #include "StringMatcher.h"
80 #include "llvm/ADT/OwningPtr.h"
81 #include "llvm/ADT/SmallVector.h"
82 #include "llvm/ADT/STLExtras.h"
83 #include "llvm/ADT/StringExtras.h"
84 #include "llvm/Support/CommandLine.h"
85 #include "llvm/Support/Debug.h"
91 static cl::opt<std::string>
92 MatchPrefix("match-prefix", cl::init(""),
93 cl::desc("Only match instructions with the given prefix"));
95 /// TokenizeAsmString - Tokenize a simplified assembly string.
96 static void TokenizeAsmString(StringRef AsmString,
97 SmallVectorImpl<StringRef> &Tokens) {
100 for (unsigned i = 0, e = AsmString.size(); i != e; ++i) {
101 switch (AsmString[i]) {
110 Tokens.push_back(AsmString.slice(Prev, i));
113 if (!isspace(AsmString[i]) && AsmString[i] != ',')
114 Tokens.push_back(AsmString.substr(i, 1));
120 Tokens.push_back(AsmString.slice(Prev, i));
124 assert(i != AsmString.size() && "Invalid quoted character");
125 Tokens.push_back(AsmString.substr(i, 1));
130 // If this isn't "${", treat like a normal token.
131 if (i + 1 == AsmString.size() || AsmString[i + 1] != '{') {
133 Tokens.push_back(AsmString.slice(Prev, i));
141 Tokens.push_back(AsmString.slice(Prev, i));
145 StringRef::iterator End =
146 std::find(AsmString.begin() + i, AsmString.end(), '}');
147 assert(End != AsmString.end() && "Missing brace in operand reference!");
148 size_t EndPos = End - AsmString.begin();
149 Tokens.push_back(AsmString.slice(i, EndPos+1));
157 Tokens.push_back(AsmString.slice(Prev, i));
167 if (InTok && Prev != AsmString.size())
168 Tokens.push_back(AsmString.substr(Prev));
171 static bool IsAssemblerInstruction(StringRef Name,
172 const CodeGenInstruction &CGI,
173 const SmallVectorImpl<StringRef> &Tokens) {
174 // Ignore "codegen only" instructions.
175 if (CGI.TheDef->getValueAsBit("isCodeGenOnly"))
178 // Ignore "Int_*" and "*_Int" instructions, which are internal aliases.
180 // FIXME: This is a total hack.
181 if (StringRef(Name).startswith("Int_") || StringRef(Name).endswith("_Int"))
184 // Reject instructions with no .s string.
185 if (CGI.AsmString.empty()) {
186 PrintError(CGI.TheDef->getLoc(),
187 "instruction with empty asm string");
188 throw std::string("ERROR: Invalid instruction for asm matcher");
191 // Reject any instructions with a newline in them, they should be marked
192 // isCodeGenOnly if they are pseudo instructions.
193 if (CGI.AsmString.find('\n') != std::string::npos) {
194 PrintError(CGI.TheDef->getLoc(),
195 "multiline instruction is not valid for the asmparser, "
196 "mark it isCodeGenOnly");
197 throw std::string("ERROR: Invalid instruction");
200 // Reject instructions with attributes, these aren't something we can handle,
201 // the target should be refactored to use operands instead of modifiers.
203 // Also, check for instructions which reference the operand multiple times;
204 // this implies a constraint we would not honor.
205 std::set<std::string> OperandNames;
206 for (unsigned i = 1, e = Tokens.size(); i < e; ++i) {
207 if (Tokens[i][0] == '$' &&
208 Tokens[i].find(':') != StringRef::npos) {
209 PrintError(CGI.TheDef->getLoc(),
210 "instruction with operand modifier '" + Tokens[i].str() +
211 "' not supported by asm matcher. Mark isCodeGenOnly!");
212 throw std::string("ERROR: Invalid instruction");
215 // FIXME: Should reject these. The ARM backend hits this with $lane in a
216 // bunch of instructions. It is unclear what the right answer is for this.
217 if (Tokens[i][0] == '$' && !OperandNames.insert(Tokens[i]).second) {
219 errs() << "warning: '" << Name << "': "
220 << "ignoring instruction with tied operand '"
221 << Tokens[i].str() << "'\n";
231 class AsmMatcherInfo;
232 struct SubtargetFeatureInfo;
234 /// ClassInfo - Helper class for storing the information about a particular
235 /// class of operands which can be matched.
238 /// Invalid kind, for use as a sentinel value.
241 /// The class for a particular token.
244 /// The (first) register class, subsequent register classes are
245 /// RegisterClass0+1, and so on.
248 /// The (first) user defined class, subsequent user defined classes are
249 /// UserClass0+1, and so on.
253 /// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
254 /// N) for the Nth user defined class.
257 /// SuperClasses - The super classes of this class. Note that for simplicities
258 /// sake user operands only record their immediate super class, while register
259 /// operands include all superclasses.
260 std::vector<ClassInfo*> SuperClasses;
262 /// Name - The full class name, suitable for use in an enum.
265 /// ClassName - The unadorned generic name for this class (e.g., Token).
266 std::string ClassName;
268 /// ValueName - The name of the value this class represents; for a token this
269 /// is the literal token string, for an operand it is the TableGen class (or
270 /// empty if this is a derived class).
271 std::string ValueName;
273 /// PredicateMethod - The name of the operand method to test whether the
274 /// operand matches this class; this is not valid for Token or register kinds.
275 std::string PredicateMethod;
277 /// RenderMethod - The name of the operand method to add this operand to an
278 /// MCInst; this is not valid for Token or register kinds.
279 std::string RenderMethod;
281 /// For register classes, the records for all the registers in this class.
282 std::set<Record*> Registers;
285 /// isRegisterClass() - Check if this is a register class.
286 bool isRegisterClass() const {
287 return Kind >= RegisterClass0 && Kind < UserClass0;
290 /// isUserClass() - Check if this is a user defined class.
291 bool isUserClass() const {
292 return Kind >= UserClass0;
295 /// isRelatedTo - Check whether this class is "related" to \arg RHS. Classes
296 /// are related if they are in the same class hierarchy.
297 bool isRelatedTo(const ClassInfo &RHS) const {
298 // Tokens are only related to tokens.
299 if (Kind == Token || RHS.Kind == Token)
300 return Kind == Token && RHS.Kind == Token;
302 // Registers classes are only related to registers classes, and only if
303 // their intersection is non-empty.
304 if (isRegisterClass() || RHS.isRegisterClass()) {
305 if (!isRegisterClass() || !RHS.isRegisterClass())
308 std::set<Record*> Tmp;
309 std::insert_iterator< std::set<Record*> > II(Tmp, Tmp.begin());
310 std::set_intersection(Registers.begin(), Registers.end(),
311 RHS.Registers.begin(), RHS.Registers.end(),
317 // Otherwise we have two users operands; they are related if they are in the
318 // same class hierarchy.
320 // FIXME: This is an oversimplification, they should only be related if they
321 // intersect, however we don't have that information.
322 assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");
323 const ClassInfo *Root = this;
324 while (!Root->SuperClasses.empty())
325 Root = Root->SuperClasses.front();
327 const ClassInfo *RHSRoot = &RHS;
328 while (!RHSRoot->SuperClasses.empty())
329 RHSRoot = RHSRoot->SuperClasses.front();
331 return Root == RHSRoot;
334 /// isSubsetOf - Test whether this class is a subset of \arg RHS;
335 bool isSubsetOf(const ClassInfo &RHS) const {
336 // This is a subset of RHS if it is the same class...
340 // ... or if any of its super classes are a subset of RHS.
341 for (std::vector<ClassInfo*>::const_iterator it = SuperClasses.begin(),
342 ie = SuperClasses.end(); it != ie; ++it)
343 if ((*it)->isSubsetOf(RHS))
349 /// operator< - Compare two classes.
350 bool operator<(const ClassInfo &RHS) const {
354 // Unrelated classes can be ordered by kind.
355 if (!isRelatedTo(RHS))
356 return Kind < RHS.Kind;
360 assert(0 && "Invalid kind!");
362 // Tokens are comparable by value.
364 // FIXME: Compare by enum value.
365 return ValueName < RHS.ValueName;
368 // This class preceeds the RHS if it is a proper subset of the RHS.
371 if (RHS.isSubsetOf(*this))
374 // Otherwise, order by name to ensure we have a total ordering.
375 return ValueName < RHS.ValueName;
380 /// InstructionInfo - Helper class for storing the necessary information for an
381 /// instruction which is capable of being matched.
382 struct InstructionInfo {
384 /// The unique class instance this operand should match.
387 /// The original operand this corresponds to, if any.
388 const CodeGenInstruction::OperandInfo *OperandInfo;
391 /// InstrName - The target name for this instruction.
392 std::string InstrName;
394 /// Instr - The instruction this matches.
395 const CodeGenInstruction *Instr;
397 /// AsmString - The assembly string for this instruction (with variants
399 std::string AsmString;
401 /// Tokens - The tokenized assembly pattern that this instruction matches.
402 SmallVector<StringRef, 4> Tokens;
404 /// Operands - The operands that this instruction matches.
405 SmallVector<Operand, 4> Operands;
407 /// Predicates - The required subtarget features to match this instruction.
408 SmallVector<SubtargetFeatureInfo*, 4> RequiredFeatures;
410 /// ConversionFnKind - The enum value which is passed to the generated
411 /// ConvertToMCInst to convert parsed operands into an MCInst for this
413 std::string ConversionFnKind;
415 /// getSingletonRegisterForToken - If the specified token is a singleton
416 /// register, return the register name, otherwise return a null StringRef.
417 StringRef getSingletonRegisterForToken(unsigned i,
418 const AsmMatcherInfo &Info) const;
420 /// operator< - Compare two instructions.
421 bool operator<(const InstructionInfo &RHS) const {
422 // The primary comparator is the instruction mnemonic.
423 if (Tokens[0] != RHS.Tokens[0])
424 return Tokens[0] < RHS.Tokens[0];
426 if (Operands.size() != RHS.Operands.size())
427 return Operands.size() < RHS.Operands.size();
429 // Compare lexicographically by operand. The matcher validates that other
430 // orderings wouldn't be ambiguous using \see CouldMatchAmiguouslyWith().
431 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
432 if (*Operands[i].Class < *RHS.Operands[i].Class)
434 if (*RHS.Operands[i].Class < *Operands[i].Class)
441 /// CouldMatchAmiguouslyWith - Check whether this instruction could
442 /// ambiguously match the same set of operands as \arg RHS (without being a
443 /// strictly superior match).
444 bool CouldMatchAmiguouslyWith(const InstructionInfo &RHS) {
445 // The number of operands is unambiguous.
446 if (Operands.size() != RHS.Operands.size())
449 // Otherwise, make sure the ordering of the two instructions is unambiguous
450 // by checking that either (a) a token or operand kind discriminates them,
451 // or (b) the ordering among equivalent kinds is consistent.
453 // Tokens and operand kinds are unambiguous (assuming a correct target
455 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
456 if (Operands[i].Class->Kind != RHS.Operands[i].Class->Kind ||
457 Operands[i].Class->Kind == ClassInfo::Token)
458 if (*Operands[i].Class < *RHS.Operands[i].Class ||
459 *RHS.Operands[i].Class < *Operands[i].Class)
462 // Otherwise, this operand could commute if all operands are equivalent, or
463 // there is a pair of operands that compare less than and a pair that
464 // compare greater than.
465 bool HasLT = false, HasGT = false;
466 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
467 if (*Operands[i].Class < *RHS.Operands[i].Class)
469 if (*RHS.Operands[i].Class < *Operands[i].Class)
473 return !(HasLT ^ HasGT);
479 /// SubtargetFeatureInfo - Helper class for storing information on a subtarget
480 /// feature which participates in instruction matching.
481 struct SubtargetFeatureInfo {
482 /// \brief The predicate record for this feature.
485 /// \brief An unique index assigned to represent this feature.
488 SubtargetFeatureInfo(Record *D, unsigned Idx) : TheDef(D), Index(Idx) {}
490 /// \brief The name of the enumerated constant identifying this feature.
491 std::string getEnumName() const {
492 return "Feature_" + TheDef->getName();
496 class AsmMatcherInfo {
498 /// The tablegen AsmParser record.
501 /// Target - The target information.
502 CodeGenTarget &Target;
504 /// The AsmParser "CommentDelimiter" value.
505 std::string CommentDelimiter;
507 /// The AsmParser "RegisterPrefix" value.
508 std::string RegisterPrefix;
510 /// The classes which are needed for matching.
511 std::vector<ClassInfo*> Classes;
513 /// The information on the instruction to match.
514 std::vector<InstructionInfo*> Instructions;
516 /// Map of Register records to their class information.
517 std::map<Record*, ClassInfo*> RegisterClasses;
519 /// Map of Predicate records to their subtarget information.
520 std::map<Record*, SubtargetFeatureInfo*> SubtargetFeatures;
523 /// Map of token to class information which has already been constructed.
524 std::map<std::string, ClassInfo*> TokenClasses;
526 /// Map of RegisterClass records to their class information.
527 std::map<Record*, ClassInfo*> RegisterClassClasses;
529 /// Map of AsmOperandClass records to their class information.
530 std::map<Record*, ClassInfo*> AsmOperandClasses;
533 /// getTokenClass - Lookup or create the class for the given token.
534 ClassInfo *getTokenClass(StringRef Token);
536 /// getOperandClass - Lookup or create the class for the given operand.
537 ClassInfo *getOperandClass(StringRef Token,
538 const CodeGenInstruction::OperandInfo &OI);
540 /// BuildRegisterClasses - Build the ClassInfo* instances for register
542 void BuildRegisterClasses(std::set<std::string> &SingletonRegisterNames);
544 /// BuildOperandClasses - Build the ClassInfo* instances for user defined
546 void BuildOperandClasses();
549 AsmMatcherInfo(Record *AsmParser, CodeGenTarget &Target);
551 /// BuildInfo - Construct the various tables used during matching.
554 /// getSubtargetFeature - Lookup or create the subtarget feature info for the
556 SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const {
557 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
558 std::map<Record*, SubtargetFeatureInfo*>::const_iterator I =
559 SubtargetFeatures.find(Def);
560 return I == SubtargetFeatures.end() ? 0 : I->second;
566 void InstructionInfo::dump() {
567 errs() << InstrName << " -- " << "flattened:\"" << AsmString << '\"'
569 for (unsigned i = 0, e = Tokens.size(); i != e; ++i) {
576 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
577 Operand &Op = Operands[i];
578 errs() << " op[" << i << "] = " << Op.Class->ClassName << " - ";
579 if (Op.Class->Kind == ClassInfo::Token) {
580 errs() << '\"' << Tokens[i] << "\"\n";
584 if (!Op.OperandInfo) {
585 errs() << "(singleton register)\n";
589 const CodeGenInstruction::OperandInfo &OI = *Op.OperandInfo;
590 errs() << OI.Name << " " << OI.Rec->getName()
591 << " (" << OI.MIOperandNo << ", " << OI.MINumOperands << ")\n";
595 /// getRegisterRecord - Get the register record for \arg name, or 0.
596 static Record *getRegisterRecord(CodeGenTarget &Target, StringRef Name) {
597 for (unsigned i = 0, e = Target.getRegisters().size(); i != e; ++i) {
598 const CodeGenRegister &Reg = Target.getRegisters()[i];
599 if (Name == Reg.TheDef->getValueAsString("AsmName"))
606 /// getSingletonRegisterForToken - If the specified token is a singleton
607 /// register, return the register name, otherwise return a null StringRef.
608 StringRef InstructionInfo::
609 getSingletonRegisterForToken(unsigned i, const AsmMatcherInfo &Info) const {
610 StringRef Tok = Tokens[i];
611 if (!Tok.startswith(Info.RegisterPrefix))
614 StringRef RegName = Tok.substr(Info.RegisterPrefix.size());
615 Record *Rec = getRegisterRecord(Info.Target, RegName);
618 // If there is no register prefix (i.e. "%" in "%eax"), then this may
619 // be some random non-register token, just ignore it.
620 if (Info.RegisterPrefix.empty())
623 std::string Err = "unable to find register for '" + RegName.str() +
624 "' (which matches register prefix)";
625 throw TGError(Instr->TheDef->getLoc(), Err);
632 static std::string getEnumNameForToken(StringRef Str) {
635 for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) {
637 case '*': Res += "_STAR_"; break;
638 case '%': Res += "_PCT_"; break;
639 case ':': Res += "_COLON_"; break;
644 Res += "_" + utostr((unsigned) *it) + "_";
651 ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) {
652 ClassInfo *&Entry = TokenClasses[Token];
655 Entry = new ClassInfo();
656 Entry->Kind = ClassInfo::Token;
657 Entry->ClassName = "Token";
658 Entry->Name = "MCK_" + getEnumNameForToken(Token);
659 Entry->ValueName = Token;
660 Entry->PredicateMethod = "<invalid>";
661 Entry->RenderMethod = "<invalid>";
662 Classes.push_back(Entry);
669 AsmMatcherInfo::getOperandClass(StringRef Token,
670 const CodeGenInstruction::OperandInfo &OI) {
671 if (OI.Rec->isSubClassOf("RegisterClass")) {
672 ClassInfo *CI = RegisterClassClasses[OI.Rec];
675 PrintError(OI.Rec->getLoc(), "register class has no class info!");
676 throw std::string("ERROR: Missing register class!");
682 assert(OI.Rec->isSubClassOf("Operand") && "Unexpected operand!");
683 Record *MatchClass = OI.Rec->getValueAsDef("ParserMatchClass");
684 ClassInfo *CI = AsmOperandClasses[MatchClass];
687 PrintError(OI.Rec->getLoc(), "operand has no match class!");
688 throw std::string("ERROR: Missing match class!");
694 void AsmMatcherInfo::BuildRegisterClasses(std::set<std::string>
695 &SingletonRegisterNames) {
696 std::vector<CodeGenRegisterClass> RegisterClasses;
697 std::vector<CodeGenRegister> Registers;
699 RegisterClasses = Target.getRegisterClasses();
700 Registers = Target.getRegisters();
702 // The register sets used for matching.
703 std::set< std::set<Record*> > RegisterSets;
705 // Gather the defined sets.
706 for (std::vector<CodeGenRegisterClass>::iterator it = RegisterClasses.begin(),
707 ie = RegisterClasses.end(); it != ie; ++it)
708 RegisterSets.insert(std::set<Record*>(it->Elements.begin(),
709 it->Elements.end()));
711 // Add any required singleton sets.
712 for (std::set<std::string>::iterator it = SingletonRegisterNames.begin(),
713 ie = SingletonRegisterNames.end(); it != ie; ++it)
714 if (Record *Rec = getRegisterRecord(Target, *it))
715 RegisterSets.insert(std::set<Record*>(&Rec, &Rec + 1));
717 // Introduce derived sets where necessary (when a register does not determine
718 // a unique register set class), and build the mapping of registers to the set
719 // they should classify to.
720 std::map<Record*, std::set<Record*> > RegisterMap;
721 for (std::vector<CodeGenRegister>::iterator it = Registers.begin(),
722 ie = Registers.end(); it != ie; ++it) {
723 CodeGenRegister &CGR = *it;
724 // Compute the intersection of all sets containing this register.
725 std::set<Record*> ContainingSet;
727 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
728 ie = RegisterSets.end(); it != ie; ++it) {
729 if (!it->count(CGR.TheDef))
732 if (ContainingSet.empty()) {
735 std::set<Record*> Tmp;
736 std::swap(Tmp, ContainingSet);
737 std::insert_iterator< std::set<Record*> > II(ContainingSet,
738 ContainingSet.begin());
739 std::set_intersection(Tmp.begin(), Tmp.end(), it->begin(), it->end(),
744 if (!ContainingSet.empty()) {
745 RegisterSets.insert(ContainingSet);
746 RegisterMap.insert(std::make_pair(CGR.TheDef, ContainingSet));
750 // Construct the register classes.
751 std::map<std::set<Record*>, ClassInfo*> RegisterSetClasses;
753 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
754 ie = RegisterSets.end(); it != ie; ++it, ++Index) {
755 ClassInfo *CI = new ClassInfo();
756 CI->Kind = ClassInfo::RegisterClass0 + Index;
757 CI->ClassName = "Reg" + utostr(Index);
758 CI->Name = "MCK_Reg" + utostr(Index);
760 CI->PredicateMethod = ""; // unused
761 CI->RenderMethod = "addRegOperands";
763 Classes.push_back(CI);
764 RegisterSetClasses.insert(std::make_pair(*it, CI));
767 // Find the superclasses; we could compute only the subgroup lattice edges,
768 // but there isn't really a point.
769 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
770 ie = RegisterSets.end(); it != ie; ++it) {
771 ClassInfo *CI = RegisterSetClasses[*it];
772 for (std::set< std::set<Record*> >::iterator it2 = RegisterSets.begin(),
773 ie2 = RegisterSets.end(); it2 != ie2; ++it2)
775 std::includes(it2->begin(), it2->end(), it->begin(), it->end()))
776 CI->SuperClasses.push_back(RegisterSetClasses[*it2]);
779 // Name the register classes which correspond to a user defined RegisterClass.
780 for (std::vector<CodeGenRegisterClass>::iterator it = RegisterClasses.begin(),
781 ie = RegisterClasses.end(); it != ie; ++it) {
782 ClassInfo *CI = RegisterSetClasses[std::set<Record*>(it->Elements.begin(),
783 it->Elements.end())];
784 if (CI->ValueName.empty()) {
785 CI->ClassName = it->getName();
786 CI->Name = "MCK_" + it->getName();
787 CI->ValueName = it->getName();
789 CI->ValueName = CI->ValueName + "," + it->getName();
791 RegisterClassClasses.insert(std::make_pair(it->TheDef, CI));
794 // Populate the map for individual registers.
795 for (std::map<Record*, std::set<Record*> >::iterator it = RegisterMap.begin(),
796 ie = RegisterMap.end(); it != ie; ++it)
797 this->RegisterClasses[it->first] = RegisterSetClasses[it->second];
799 // Name the register classes which correspond to singleton registers.
800 for (std::set<std::string>::iterator it = SingletonRegisterNames.begin(),
801 ie = SingletonRegisterNames.end(); it != ie; ++it) {
802 if (Record *Rec = getRegisterRecord(Target, *it)) {
803 ClassInfo *CI = this->RegisterClasses[Rec];
804 assert(CI && "Missing singleton register class info!");
806 if (CI->ValueName.empty()) {
807 CI->ClassName = Rec->getName();
808 CI->Name = "MCK_" + Rec->getName();
809 CI->ValueName = Rec->getName();
811 CI->ValueName = CI->ValueName + "," + Rec->getName();
816 void AsmMatcherInfo::BuildOperandClasses() {
817 std::vector<Record*> AsmOperands;
818 AsmOperands = Records.getAllDerivedDefinitions("AsmOperandClass");
820 // Pre-populate AsmOperandClasses map.
821 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
822 ie = AsmOperands.end(); it != ie; ++it)
823 AsmOperandClasses[*it] = new ClassInfo();
826 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
827 ie = AsmOperands.end(); it != ie; ++it, ++Index) {
828 ClassInfo *CI = AsmOperandClasses[*it];
829 CI->Kind = ClassInfo::UserClass0 + Index;
831 ListInit *Supers = (*it)->getValueAsListInit("SuperClasses");
832 for (unsigned i = 0, e = Supers->getSize(); i != e; ++i) {
833 DefInit *DI = dynamic_cast<DefInit*>(Supers->getElement(i));
835 PrintError((*it)->getLoc(), "Invalid super class reference!");
839 ClassInfo *SC = AsmOperandClasses[DI->getDef()];
841 PrintError((*it)->getLoc(), "Invalid super class reference!");
843 CI->SuperClasses.push_back(SC);
845 CI->ClassName = (*it)->getValueAsString("Name");
846 CI->Name = "MCK_" + CI->ClassName;
847 CI->ValueName = (*it)->getName();
849 // Get or construct the predicate method name.
850 Init *PMName = (*it)->getValueInit("PredicateMethod");
851 if (StringInit *SI = dynamic_cast<StringInit*>(PMName)) {
852 CI->PredicateMethod = SI->getValue();
854 assert(dynamic_cast<UnsetInit*>(PMName) &&
855 "Unexpected PredicateMethod field!");
856 CI->PredicateMethod = "is" + CI->ClassName;
859 // Get or construct the render method name.
860 Init *RMName = (*it)->getValueInit("RenderMethod");
861 if (StringInit *SI = dynamic_cast<StringInit*>(RMName)) {
862 CI->RenderMethod = SI->getValue();
864 assert(dynamic_cast<UnsetInit*>(RMName) &&
865 "Unexpected RenderMethod field!");
866 CI->RenderMethod = "add" + CI->ClassName + "Operands";
869 AsmOperandClasses[*it] = CI;
870 Classes.push_back(CI);
874 AsmMatcherInfo::AsmMatcherInfo(Record *asmParser, CodeGenTarget &target)
875 : AsmParser(asmParser), Target(target),
876 CommentDelimiter(AsmParser->getValueAsString("CommentDelimiter")),
877 RegisterPrefix(AsmParser->getValueAsString("RegisterPrefix"))
881 void AsmMatcherInfo::BuildInfo() {
882 // Build information about all of the AssemblerPredicates.
883 std::vector<Record*> AllPredicates =
884 Records.getAllDerivedDefinitions("Predicate");
885 for (unsigned i = 0, e = AllPredicates.size(); i != e; ++i) {
886 Record *Pred = AllPredicates[i];
887 // Ignore predicates that are not intended for the assembler.
888 if (!Pred->getValueAsBit("AssemblerMatcherPredicate"))
891 if (Pred->getName().empty()) {
892 PrintError(Pred->getLoc(), "Predicate has no name!");
893 throw std::string("ERROR: Predicate defs must be named");
896 unsigned FeatureNo = SubtargetFeatures.size();
897 SubtargetFeatures[Pred] = new SubtargetFeatureInfo(Pred, FeatureNo);
898 assert(FeatureNo < 32 && "Too many subtarget features!");
901 // Parse the instructions; we need to do this first so that we can gather the
902 // singleton register classes.
903 std::set<std::string> SingletonRegisterNames;
904 for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
905 E = Target.inst_end(); I != E; ++I) {
906 const CodeGenInstruction &CGI = **I;
908 // If the tblgen -match-prefix option is specified (for tblgen hackers),
909 // filter the set of instructions we consider.
910 if (!StringRef(CGI.TheDef->getName()).startswith(MatchPrefix))
913 OwningPtr<InstructionInfo> II(new InstructionInfo());
915 II->InstrName = CGI.TheDef->getName();
917 // TODO: Eventually support asmparser for Variant != 0.
918 II->AsmString = CGI.FlattenAsmStringVariants(CGI.AsmString, 0);
920 // Remove comments from the asm string. We know that the asmstring only
922 if (!CommentDelimiter.empty()) {
923 size_t Idx = StringRef(II->AsmString).find(CommentDelimiter);
924 if (Idx != StringRef::npos)
925 II->AsmString = II->AsmString.substr(0, Idx);
928 TokenizeAsmString(II->AsmString, II->Tokens);
930 // Ignore instructions which shouldn't be matched and diagnose invalid
931 // instruction definitions with an error.
932 if (!IsAssemblerInstruction(CGI.TheDef->getName(), CGI, II->Tokens))
935 // Collect singleton registers, if used.
936 for (unsigned i = 0, e = II->Tokens.size(); i != e; ++i) {
937 StringRef RegName = II->getSingletonRegisterForToken(i, *this);
939 if (RegName != StringRef())
940 SingletonRegisterNames.insert(RegName);
943 // Compute the require features.
944 std::vector<Record*> Predicates =
945 CGI.TheDef->getValueAsListOfDefs("Predicates");
946 for (unsigned i = 0, e = Predicates.size(); i != e; ++i)
947 if (SubtargetFeatureInfo *Feature = getSubtargetFeature(Predicates[i]))
948 II->RequiredFeatures.push_back(Feature);
950 Instructions.push_back(II.take());
953 // Build info for the register classes.
954 BuildRegisterClasses(SingletonRegisterNames);
956 // Build info for the user defined assembly operand classes.
957 BuildOperandClasses();
959 // Build the instruction information.
960 for (std::vector<InstructionInfo*>::iterator it = Instructions.begin(),
961 ie = Instructions.end(); it != ie; ++it) {
962 InstructionInfo *II = *it;
964 // The first token of the instruction is the mnemonic, which must be a
965 // simple string, not a $foo variable or a singleton register.
966 assert(!II->Tokens.empty() && "Instruction has no tokens?");
967 StringRef Mnemonic = II->Tokens[0];
968 if (Mnemonic[0] == '$' ||
969 II->getSingletonRegisterForToken(0, *this) != StringRef())
970 throw TGError(II->Instr->TheDef->getLoc(),
971 "Invalid instruction mnemonic '" + Mnemonic.str() + "'!");
973 // Parse the tokens after the mnemonic.
974 for (unsigned i = 1, e = II->Tokens.size(); i != e; ++i) {
975 StringRef Token = II->Tokens[i];
977 // Check for singleton registers.
978 StringRef RegName = II->getSingletonRegisterForToken(i, *this);
979 if (RegName != StringRef()) {
980 Record *RegRecord = getRegisterRecord(Target, RegName);
981 InstructionInfo::Operand Op;
982 Op.Class = RegisterClasses[RegRecord];
984 assert(Op.Class && Op.Class->Registers.size() == 1 &&
985 "Unexpected class for singleton register");
986 II->Operands.push_back(Op);
990 // Check for simple tokens.
991 if (Token[0] != '$') {
992 InstructionInfo::Operand Op;
993 Op.Class = getTokenClass(Token);
995 II->Operands.push_back(Op);
999 // Otherwise this is an operand reference.
1000 StringRef OperandName;
1001 if (Token[1] == '{')
1002 OperandName = Token.substr(2, Token.size() - 3);
1004 OperandName = Token.substr(1);
1006 // Map this token to an operand. FIXME: Move elsewhere.
1009 Idx = II->Instr->getOperandNamed(OperandName);
1011 throw std::string("error: unable to find operand: '" +
1012 OperandName.str() + "'");
1015 // FIXME: This is annoying, the named operand may be tied (e.g.,
1016 // XCHG8rm). What we want is the untied operand, which we now have to
1017 // grovel for. Only worry about this for single entry operands, we have to
1018 // clean this up anyway.
1019 const CodeGenInstruction::OperandInfo *OI = &II->Instr->OperandList[Idx];
1020 if (OI->Constraints[0].isTied()) {
1021 unsigned TiedOp = OI->Constraints[0].getTiedOperand();
1023 // The tied operand index is an MIOperand index, find the operand that
1025 for (unsigned i = 0, e = II->Instr->OperandList.size(); i != e; ++i) {
1026 if (II->Instr->OperandList[i].MIOperandNo == TiedOp) {
1027 OI = &II->Instr->OperandList[i];
1032 assert(OI && "Unable to find tied operand target!");
1035 InstructionInfo::Operand Op;
1036 Op.Class = getOperandClass(Token, *OI);
1037 Op.OperandInfo = OI;
1038 II->Operands.push_back(Op);
1042 // Reorder classes so that classes preceed super classes.
1043 std::sort(Classes.begin(), Classes.end(), less_ptr<ClassInfo>());
1046 static std::pair<unsigned, unsigned> *
1047 GetTiedOperandAtIndex(SmallVectorImpl<std::pair<unsigned, unsigned> > &List,
1049 for (unsigned i = 0, e = List.size(); i != e; ++i)
1050 if (Index == List[i].first)
1056 static void EmitConvertToMCInst(CodeGenTarget &Target,
1057 std::vector<InstructionInfo*> &Infos,
1059 // Write the convert function to a separate stream, so we can drop it after
1061 std::string ConvertFnBody;
1062 raw_string_ostream CvtOS(ConvertFnBody);
1064 // Function we have already generated.
1065 std::set<std::string> GeneratedFns;
1067 // Start the unified conversion function.
1069 CvtOS << "static void ConvertToMCInst(ConversionKind Kind, MCInst &Inst, "
1070 << "unsigned Opcode,\n"
1071 << " const SmallVectorImpl<MCParsedAsmOperand*"
1072 << "> &Operands) {\n";
1073 CvtOS << " Inst.setOpcode(Opcode);\n";
1074 CvtOS << " switch (Kind) {\n";
1075 CvtOS << " default:\n";
1077 // Start the enum, which we will generate inline.
1079 OS << "// Unified function for converting operants to MCInst instances.\n\n";
1080 OS << "enum ConversionKind {\n";
1082 // TargetOperandClass - This is the target's operand class, like X86Operand.
1083 std::string TargetOperandClass = Target.getName() + "Operand";
1085 for (std::vector<InstructionInfo*>::const_iterator it = Infos.begin(),
1086 ie = Infos.end(); it != ie; ++it) {
1087 InstructionInfo &II = **it;
1089 // Order the (class) operands by the order to convert them into an MCInst.
1090 SmallVector<std::pair<unsigned, unsigned>, 4> MIOperandList;
1091 for (unsigned i = 0, e = II.Operands.size(); i != e; ++i) {
1092 InstructionInfo::Operand &Op = II.Operands[i];
1094 MIOperandList.push_back(std::make_pair(Op.OperandInfo->MIOperandNo, i));
1097 // Find any tied operands.
1098 SmallVector<std::pair<unsigned, unsigned>, 4> TiedOperands;
1099 for (unsigned i = 0, e = II.Instr->OperandList.size(); i != e; ++i) {
1100 const CodeGenInstruction::OperandInfo &OpInfo = II.Instr->OperandList[i];
1101 for (unsigned j = 0, e = OpInfo.Constraints.size(); j != e; ++j) {
1102 const CodeGenInstruction::ConstraintInfo &CI = OpInfo.Constraints[j];
1104 TiedOperands.push_back(std::make_pair(OpInfo.MIOperandNo + j,
1105 CI.getTiedOperand()));
1109 std::sort(MIOperandList.begin(), MIOperandList.end());
1111 // Compute the total number of operands.
1112 unsigned NumMIOperands = 0;
1113 for (unsigned i = 0, e = II.Instr->OperandList.size(); i != e; ++i) {
1114 const CodeGenInstruction::OperandInfo &OI = II.Instr->OperandList[i];
1115 NumMIOperands = std::max(NumMIOperands,
1116 OI.MIOperandNo + OI.MINumOperands);
1119 // Build the conversion function signature.
1120 std::string Signature = "Convert";
1121 unsigned CurIndex = 0;
1122 for (unsigned i = 0, e = MIOperandList.size(); i != e; ++i) {
1123 InstructionInfo::Operand &Op = II.Operands[MIOperandList[i].second];
1124 assert(CurIndex <= Op.OperandInfo->MIOperandNo &&
1125 "Duplicate match for instruction operand!");
1127 // Skip operands which weren't matched by anything, this occurs when the
1128 // .td file encodes "implicit" operands as explicit ones.
1130 // FIXME: This should be removed from the MCInst structure.
1131 for (; CurIndex != Op.OperandInfo->MIOperandNo; ++CurIndex) {
1132 std::pair<unsigned, unsigned> *Tie = GetTiedOperandAtIndex(TiedOperands,
1135 Signature += "__Imp";
1137 Signature += "__Tie" + utostr(Tie->second);
1142 // Registers are always converted the same, don't duplicate the conversion
1143 // function based on them.
1145 // FIXME: We could generalize this based on the render method, if it
1147 if (Op.Class->isRegisterClass())
1150 Signature += Op.Class->ClassName;
1151 Signature += utostr(Op.OperandInfo->MINumOperands);
1152 Signature += "_" + utostr(MIOperandList[i].second);
1154 CurIndex += Op.OperandInfo->MINumOperands;
1157 // Add any trailing implicit operands.
1158 for (; CurIndex != NumMIOperands; ++CurIndex) {
1159 std::pair<unsigned, unsigned> *Tie = GetTiedOperandAtIndex(TiedOperands,
1162 Signature += "__Imp";
1164 Signature += "__Tie" + utostr(Tie->second);
1167 II.ConversionFnKind = Signature;
1169 // Check if we have already generated this signature.
1170 if (!GeneratedFns.insert(Signature).second)
1173 // If not, emit it now.
1175 // Add to the enum list.
1176 OS << " " << Signature << ",\n";
1178 // And to the convert function.
1179 CvtOS << " case " << Signature << ":\n";
1181 for (unsigned i = 0, e = MIOperandList.size(); i != e; ++i) {
1182 InstructionInfo::Operand &Op = II.Operands[MIOperandList[i].second];
1184 // Add the implicit operands.
1185 for (; CurIndex != Op.OperandInfo->MIOperandNo; ++CurIndex) {
1186 // See if this is a tied operand.
1187 std::pair<unsigned, unsigned> *Tie = GetTiedOperandAtIndex(TiedOperands,
1191 // If not, this is some implicit operand. Just assume it is a register
1193 CvtOS << " Inst.addOperand(MCOperand::CreateReg(0));\n";
1195 // Copy the tied operand.
1196 assert(Tie->first>Tie->second && "Tied operand preceeds its target!");
1197 CvtOS << " Inst.addOperand(Inst.getOperand("
1198 << Tie->second << "));\n";
1202 CvtOS << " ((" << TargetOperandClass << "*)Operands["
1203 << MIOperandList[i].second
1204 << "+1])->" << Op.Class->RenderMethod
1205 << "(Inst, " << Op.OperandInfo->MINumOperands << ");\n";
1206 CurIndex += Op.OperandInfo->MINumOperands;
1209 // And add trailing implicit operands.
1210 for (; CurIndex != NumMIOperands; ++CurIndex) {
1211 std::pair<unsigned, unsigned> *Tie = GetTiedOperandAtIndex(TiedOperands,
1215 // If not, this is some implicit operand. Just assume it is a register
1217 CvtOS << " Inst.addOperand(MCOperand::CreateReg(0));\n";
1219 // Copy the tied operand.
1220 assert(Tie->first>Tie->second && "Tied operand preceeds its target!");
1221 CvtOS << " Inst.addOperand(Inst.getOperand("
1222 << Tie->second << "));\n";
1226 CvtOS << " return;\n";
1229 // Finish the convert function.
1234 // Finish the enum, and drop the convert function after it.
1236 OS << " NumConversionVariants\n";
1242 /// EmitMatchClassEnumeration - Emit the enumeration for match class kinds.
1243 static void EmitMatchClassEnumeration(CodeGenTarget &Target,
1244 std::vector<ClassInfo*> &Infos,
1246 OS << "namespace {\n\n";
1248 OS << "/// MatchClassKind - The kinds of classes which participate in\n"
1249 << "/// instruction matching.\n";
1250 OS << "enum MatchClassKind {\n";
1251 OS << " InvalidMatchClass = 0,\n";
1252 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1253 ie = Infos.end(); it != ie; ++it) {
1254 ClassInfo &CI = **it;
1255 OS << " " << CI.Name << ", // ";
1256 if (CI.Kind == ClassInfo::Token) {
1257 OS << "'" << CI.ValueName << "'\n";
1258 } else if (CI.isRegisterClass()) {
1259 if (!CI.ValueName.empty())
1260 OS << "register class '" << CI.ValueName << "'\n";
1262 OS << "derived register class\n";
1264 OS << "user defined class '" << CI.ValueName << "'\n";
1267 OS << " NumMatchClassKinds\n";
1273 /// EmitClassifyOperand - Emit the function to classify an operand.
1274 static void EmitClassifyOperand(AsmMatcherInfo &Info,
1276 OS << "static MatchClassKind ClassifyOperand(MCParsedAsmOperand *GOp) {\n"
1277 << " " << Info.Target.getName() << "Operand &Operand = *("
1278 << Info.Target.getName() << "Operand*)GOp;\n";
1281 OS << " if (Operand.isToken())\n";
1282 OS << " return MatchTokenString(Operand.getToken());\n\n";
1284 // Classify registers.
1286 // FIXME: Don't hardcode isReg, getReg.
1287 OS << " if (Operand.isReg()) {\n";
1288 OS << " switch (Operand.getReg()) {\n";
1289 OS << " default: return InvalidMatchClass;\n";
1290 for (std::map<Record*, ClassInfo*>::iterator
1291 it = Info.RegisterClasses.begin(), ie = Info.RegisterClasses.end();
1293 OS << " case " << Info.Target.getName() << "::"
1294 << it->first->getName() << ": return " << it->second->Name << ";\n";
1298 // Classify user defined operands.
1299 for (std::vector<ClassInfo*>::iterator it = Info.Classes.begin(),
1300 ie = Info.Classes.end(); it != ie; ++it) {
1301 ClassInfo &CI = **it;
1303 if (!CI.isUserClass())
1306 OS << " // '" << CI.ClassName << "' class";
1307 if (!CI.SuperClasses.empty()) {
1308 OS << ", subclass of ";
1309 for (unsigned i = 0, e = CI.SuperClasses.size(); i != e; ++i) {
1311 OS << "'" << CI.SuperClasses[i]->ClassName << "'";
1312 assert(CI < *CI.SuperClasses[i] && "Invalid class relation!");
1317 OS << " if (Operand." << CI.PredicateMethod << "()) {\n";
1319 // Validate subclass relationships.
1320 if (!CI.SuperClasses.empty()) {
1321 for (unsigned i = 0, e = CI.SuperClasses.size(); i != e; ++i)
1322 OS << " assert(Operand." << CI.SuperClasses[i]->PredicateMethod
1323 << "() && \"Invalid class relationship!\");\n";
1326 OS << " return " << CI.Name << ";\n";
1329 OS << " return InvalidMatchClass;\n";
1333 /// EmitIsSubclass - Emit the subclass predicate function.
1334 static void EmitIsSubclass(CodeGenTarget &Target,
1335 std::vector<ClassInfo*> &Infos,
1337 OS << "/// IsSubclass - Compute whether \\arg A is a subclass of \\arg B.\n";
1338 OS << "static bool IsSubclass(MatchClassKind A, MatchClassKind B) {\n";
1339 OS << " if (A == B)\n";
1340 OS << " return true;\n\n";
1342 OS << " switch (A) {\n";
1343 OS << " default:\n";
1344 OS << " return false;\n";
1345 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1346 ie = Infos.end(); it != ie; ++it) {
1347 ClassInfo &A = **it;
1349 if (A.Kind != ClassInfo::Token) {
1350 std::vector<StringRef> SuperClasses;
1351 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1352 ie = Infos.end(); it != ie; ++it) {
1353 ClassInfo &B = **it;
1355 if (&A != &B && A.isSubsetOf(B))
1356 SuperClasses.push_back(B.Name);
1359 if (SuperClasses.empty())
1362 OS << "\n case " << A.Name << ":\n";
1364 if (SuperClasses.size() == 1) {
1365 OS << " return B == " << SuperClasses.back() << ";\n";
1369 OS << " switch (B) {\n";
1370 OS << " default: return false;\n";
1371 for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i)
1372 OS << " case " << SuperClasses[i] << ": return true;\n";
1382 /// EmitMatchTokenString - Emit the function to match a token string to the
1383 /// appropriate match class value.
1384 static void EmitMatchTokenString(CodeGenTarget &Target,
1385 std::vector<ClassInfo*> &Infos,
1387 // Construct the match list.
1388 std::vector<StringMatcher::StringPair> Matches;
1389 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1390 ie = Infos.end(); it != ie; ++it) {
1391 ClassInfo &CI = **it;
1393 if (CI.Kind == ClassInfo::Token)
1394 Matches.push_back(StringMatcher::StringPair(CI.ValueName,
1395 "return " + CI.Name + ";"));
1398 OS << "static MatchClassKind MatchTokenString(StringRef Name) {\n";
1400 StringMatcher("Name", Matches, OS).Emit();
1402 OS << " return InvalidMatchClass;\n";
1406 /// EmitMatchRegisterName - Emit the function to match a string to the target
1407 /// specific register enum.
1408 static void EmitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
1410 // Construct the match list.
1411 std::vector<StringMatcher::StringPair> Matches;
1412 for (unsigned i = 0, e = Target.getRegisters().size(); i != e; ++i) {
1413 const CodeGenRegister &Reg = Target.getRegisters()[i];
1414 if (Reg.TheDef->getValueAsString("AsmName").empty())
1417 Matches.push_back(StringMatcher::StringPair(
1418 Reg.TheDef->getValueAsString("AsmName"),
1419 "return " + utostr(i + 1) + ";"));
1422 OS << "static unsigned MatchRegisterName(StringRef Name) {\n";
1424 StringMatcher("Name", Matches, OS).Emit();
1426 OS << " return 0;\n";
1430 /// EmitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag
1432 static void EmitSubtargetFeatureFlagEnumeration(AsmMatcherInfo &Info,
1434 OS << "// Flags for subtarget features that participate in "
1435 << "instruction matching.\n";
1436 OS << "enum SubtargetFeatureFlag {\n";
1437 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
1438 it = Info.SubtargetFeatures.begin(),
1439 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
1440 SubtargetFeatureInfo &SFI = *it->second;
1441 OS << " " << SFI.getEnumName() << " = (1 << " << SFI.Index << "),\n";
1443 OS << " Feature_None = 0\n";
1447 /// EmitComputeAvailableFeatures - Emit the function to compute the list of
1448 /// available features given a subtarget.
1449 static void EmitComputeAvailableFeatures(AsmMatcherInfo &Info,
1451 std::string ClassName =
1452 Info.AsmParser->getValueAsString("AsmParserClassName");
1454 OS << "unsigned " << Info.Target.getName() << ClassName << "::\n"
1455 << "ComputeAvailableFeatures(const " << Info.Target.getName()
1456 << "Subtarget *Subtarget) const {\n";
1457 OS << " unsigned Features = 0;\n";
1458 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
1459 it = Info.SubtargetFeatures.begin(),
1460 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
1461 SubtargetFeatureInfo &SFI = *it->second;
1462 OS << " if (" << SFI.TheDef->getValueAsString("CondString")
1464 OS << " Features |= " << SFI.getEnumName() << ";\n";
1466 OS << " return Features;\n";
1470 static std::string GetAliasRequiredFeatures(Record *R,
1471 const AsmMatcherInfo &Info) {
1472 std::vector<Record*> ReqFeatures = R->getValueAsListOfDefs("Predicates");
1474 unsigned NumFeatures = 0;
1475 for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) {
1476 if (SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i])) {
1480 Result += F->getEnumName();
1485 if (NumFeatures > 1)
1486 Result = '(' + Result + ')';
1490 /// EmitMnemonicAliases - If the target has any MnemonicAlias<> definitions,
1491 /// emit a function for them and return true, otherwise return false.
1492 static bool EmitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info) {
1493 std::vector<Record*> Aliases =
1494 Records.getAllDerivedDefinitions("MnemonicAlias");
1495 if (Aliases.empty()) return false;
1497 OS << "static void ApplyMnemonicAliases(StringRef &Mnemonic, "
1498 "unsigned Features) {\n";
1500 // Keep track of all the aliases from a mnemonic. Use an std::map so that the
1501 // iteration order of the map is stable.
1502 std::map<std::string, std::vector<Record*> > AliasesFromMnemonic;
1504 for (unsigned i = 0, e = Aliases.size(); i != e; ++i) {
1505 Record *R = Aliases[i];
1506 AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R);
1509 // Process each alias a "from" mnemonic at a time, building the code executed
1510 // by the string remapper.
1511 std::vector<StringMatcher::StringPair> Cases;
1512 for (std::map<std::string, std::vector<Record*> >::iterator
1513 I = AliasesFromMnemonic.begin(), E = AliasesFromMnemonic.end();
1515 const std::vector<Record*> &ToVec = I->second;
1517 // Loop through each alias and emit code that handles each case. If there
1518 // are two instructions without predicates, emit an error. If there is one,
1520 std::string MatchCode;
1521 int AliasWithNoPredicate = -1;
1523 for (unsigned i = 0, e = ToVec.size(); i != e; ++i) {
1524 Record *R = ToVec[i];
1525 std::string FeatureMask = GetAliasRequiredFeatures(R, Info);
1527 // If this unconditionally matches, remember it for later and diagnose
1529 if (FeatureMask.empty()) {
1530 if (AliasWithNoPredicate != -1) {
1531 // We can't have two aliases from the same mnemonic with no predicate.
1532 PrintError(ToVec[AliasWithNoPredicate]->getLoc(),
1533 "two MnemonicAliases with the same 'from' mnemonic!");
1534 PrintError(R->getLoc(), "this is the other MnemonicAlias.");
1535 throw std::string("ERROR: Invalid MnemonicAlias definitions!");
1538 AliasWithNoPredicate = i;
1542 if (!MatchCode.empty())
1543 MatchCode += "else ";
1544 MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n";
1545 MatchCode += " Mnemonic = \"" +R->getValueAsString("ToMnemonic")+"\";\n";
1548 if (AliasWithNoPredicate != -1) {
1549 Record *R = ToVec[AliasWithNoPredicate];
1550 if (!MatchCode.empty())
1551 MatchCode += "else\n ";
1552 MatchCode += "Mnemonic = \"" + R->getValueAsString("ToMnemonic")+"\";\n";
1555 MatchCode += "return;";
1557 Cases.push_back(std::make_pair(I->first, MatchCode));
1561 StringMatcher("Mnemonic", Cases, OS).Emit();
1567 void AsmMatcherEmitter::run(raw_ostream &OS) {
1568 CodeGenTarget Target;
1569 Record *AsmParser = Target.getAsmParser();
1570 std::string ClassName = AsmParser->getValueAsString("AsmParserClassName");
1572 // Compute the information on the instructions to match.
1573 AsmMatcherInfo Info(AsmParser, Target);
1576 // Sort the instruction table using the partial order on classes. We use
1577 // stable_sort to ensure that ambiguous instructions are still
1578 // deterministically ordered.
1579 std::stable_sort(Info.Instructions.begin(), Info.Instructions.end(),
1580 less_ptr<InstructionInfo>());
1582 DEBUG_WITH_TYPE("instruction_info", {
1583 for (std::vector<InstructionInfo*>::iterator
1584 it = Info.Instructions.begin(), ie = Info.Instructions.end();
1589 // Check for ambiguous instructions.
1590 DEBUG_WITH_TYPE("ambiguous_instrs", {
1591 unsigned NumAmbiguous = 0;
1592 for (unsigned i = 0, e = Info.Instructions.size(); i != e; ++i) {
1593 for (unsigned j = i + 1; j != e; ++j) {
1594 InstructionInfo &A = *Info.Instructions[i];
1595 InstructionInfo &B = *Info.Instructions[j];
1597 if (A.CouldMatchAmiguouslyWith(B)) {
1598 errs() << "warning: ambiguous instruction match:\n";
1600 errs() << "\nis incomparable with:\n";
1608 errs() << "warning: " << NumAmbiguous
1609 << " ambiguous instructions!\n";
1612 // Write the output.
1614 EmitSourceFileHeader("Assembly Matcher Source Fragment", OS);
1616 // Information for the class declaration.
1617 OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
1618 OS << "#undef GET_ASSEMBLER_HEADER\n";
1619 OS << " // This should be included into the middle of the declaration of \n";
1620 OS << " // your subclasses implementation of TargetAsmParser.\n";
1621 OS << " unsigned ComputeAvailableFeatures(const " <<
1622 Target.getName() << "Subtarget *Subtarget) const;\n";
1623 OS << " enum MatchResultTy {\n";
1624 OS << " Match_Success, Match_MnemonicFail, Match_InvalidOperand,\n";
1625 OS << " Match_MissingFeature\n";
1627 OS << " MatchResultTy MatchInstructionImpl(const "
1628 << "SmallVectorImpl<MCParsedAsmOperand*>"
1629 << " &Operands, MCInst &Inst, unsigned &ErrorInfo);\n\n";
1630 OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n";
1635 OS << "\n#ifdef GET_REGISTER_MATCHER\n";
1636 OS << "#undef GET_REGISTER_MATCHER\n\n";
1638 // Emit the subtarget feature enumeration.
1639 EmitSubtargetFeatureFlagEnumeration(Info, OS);
1641 // Emit the function to match a register name to number.
1642 EmitMatchRegisterName(Target, AsmParser, OS);
1644 OS << "#endif // GET_REGISTER_MATCHER\n\n";
1647 OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
1648 OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
1650 // Generate the function that remaps for mnemonic aliases.
1651 bool HasMnemonicAliases = EmitMnemonicAliases(OS, Info);
1653 // Generate the unified function to convert operands into an MCInst.
1654 EmitConvertToMCInst(Target, Info.Instructions, OS);
1656 // Emit the enumeration for classes which participate in matching.
1657 EmitMatchClassEnumeration(Target, Info.Classes, OS);
1659 // Emit the routine to match token strings to their match class.
1660 EmitMatchTokenString(Target, Info.Classes, OS);
1662 // Emit the routine to classify an operand.
1663 EmitClassifyOperand(Info, OS);
1665 // Emit the subclass predicate routine.
1666 EmitIsSubclass(Target, Info.Classes, OS);
1668 // Emit the available features compute function.
1669 EmitComputeAvailableFeatures(Info, OS);
1672 size_t MaxNumOperands = 0;
1673 for (std::vector<InstructionInfo*>::const_iterator it =
1674 Info.Instructions.begin(), ie = Info.Instructions.end();
1676 MaxNumOperands = std::max(MaxNumOperands, (*it)->Operands.size());
1679 // Emit the static match table; unused classes get initalized to 0 which is
1680 // guaranteed to be InvalidMatchClass.
1682 // FIXME: We can reduce the size of this table very easily. First, we change
1683 // it so that store the kinds in separate bit-fields for each index, which
1684 // only needs to be the max width used for classes at that index (we also need
1685 // to reject based on this during classification). If we then make sure to
1686 // order the match kinds appropriately (putting mnemonics last), then we
1687 // should only end up using a few bits for each class, especially the ones
1688 // following the mnemonic.
1689 OS << "namespace {\n";
1690 OS << " struct MatchEntry {\n";
1691 OS << " unsigned Opcode;\n";
1692 OS << " const char *Mnemonic;\n";
1693 OS << " ConversionKind ConvertFn;\n";
1694 OS << " MatchClassKind Classes[" << MaxNumOperands << "];\n";
1695 OS << " unsigned RequiredFeatures;\n";
1698 OS << "// Predicate for searching for an opcode.\n";
1699 OS << " struct LessOpcode {\n";
1700 OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n";
1701 OS << " return StringRef(LHS.Mnemonic) < RHS;\n";
1703 OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n";
1704 OS << " return LHS < StringRef(RHS.Mnemonic);\n";
1706 OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n";
1707 OS << " return StringRef(LHS.Mnemonic) < StringRef(RHS.Mnemonic);\n";
1711 OS << "} // end anonymous namespace.\n\n";
1713 OS << "static const MatchEntry MatchTable["
1714 << Info.Instructions.size() << "] = {\n";
1716 for (std::vector<InstructionInfo*>::const_iterator it =
1717 Info.Instructions.begin(), ie = Info.Instructions.end();
1719 InstructionInfo &II = **it;
1721 OS << " { " << Target.getName() << "::" << II.InstrName
1722 << ", \"" << II.Tokens[0] << "\""
1723 << ", " << II.ConversionFnKind << ", { ";
1724 for (unsigned i = 0, e = II.Operands.size(); i != e; ++i) {
1725 InstructionInfo::Operand &Op = II.Operands[i];
1728 OS << Op.Class->Name;
1732 // Write the required features mask.
1733 if (!II.RequiredFeatures.empty()) {
1734 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
1736 OS << II.RequiredFeatures[i]->getEnumName();
1746 // Finally, build the match function.
1747 OS << Target.getName() << ClassName << "::MatchResultTy "
1748 << Target.getName() << ClassName << "::\n"
1749 << "MatchInstructionImpl(const SmallVectorImpl<MCParsedAsmOperand*>"
1751 OS << " MCInst &Inst, unsigned &ErrorInfo) {\n";
1753 // Emit code to get the available features.
1754 OS << " // Get the current feature set.\n";
1755 OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n";
1757 OS << " // Get the instruction mnemonic, which is the first token.\n";
1758 OS << " StringRef Mnemonic = ((" << Target.getName()
1759 << "Operand*)Operands[0])->getToken();\n\n";
1761 if (HasMnemonicAliases) {
1762 OS << " // Process all MnemonicAliases to remap the mnemonic.\n";
1763 OS << " ApplyMnemonicAliases(Mnemonic, AvailableFeatures);\n\n";
1766 // Emit code to compute the class list for this operand vector.
1767 OS << " // Eliminate obvious mismatches.\n";
1768 OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n";
1769 OS << " ErrorInfo = " << (MaxNumOperands+1) << ";\n";
1770 OS << " return Match_InvalidOperand;\n";
1773 OS << " // Compute the class list for this operand vector.\n";
1774 OS << " MatchClassKind Classes[" << MaxNumOperands << "];\n";
1775 OS << " for (unsigned i = 1, e = Operands.size(); i != e; ++i) {\n";
1776 OS << " Classes[i-1] = ClassifyOperand(Operands[i]);\n\n";
1778 OS << " // Check for invalid operands before matching.\n";
1779 OS << " if (Classes[i-1] == InvalidMatchClass) {\n";
1780 OS << " ErrorInfo = i;\n";
1781 OS << " return Match_InvalidOperand;\n";
1785 OS << " // Mark unused classes.\n";
1786 OS << " for (unsigned i = Operands.size()-1, e = " << MaxNumOperands << "; "
1787 << "i != e; ++i)\n";
1788 OS << " Classes[i] = InvalidMatchClass;\n\n";
1790 OS << " // Some state to try to produce better error messages.\n";
1791 OS << " bool HadMatchOtherThanFeatures = false;\n\n";
1792 OS << " // Set ErrorInfo to the operand that mismatches if it is \n";
1793 OS << " // wrong for all instances of the instruction.\n";
1794 OS << " ErrorInfo = ~0U;\n";
1796 // Emit code to search the table.
1797 OS << " // Search the table.\n";
1798 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
1799 OS << " std::equal_range(MatchTable, MatchTable+"
1800 << Info.Instructions.size() << ", Mnemonic, LessOpcode());\n\n";
1802 OS << " // Return a more specific error code if no mnemonics match.\n";
1803 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
1804 OS << " return Match_MnemonicFail;\n\n";
1806 OS << " for (const MatchEntry *it = MnemonicRange.first, "
1807 << "*ie = MnemonicRange.second;\n";
1808 OS << " it != ie; ++it) {\n";
1810 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
1811 OS << " assert(Mnemonic == it->Mnemonic);\n";
1813 // Emit check that the subclasses match.
1814 OS << " bool OperandsValid = true;\n";
1815 OS << " for (unsigned i = 0; i != " << MaxNumOperands << "; ++i) {\n";
1816 OS << " if (IsSubclass(Classes[i], it->Classes[i]))\n";
1817 OS << " continue;\n";
1818 OS << " // If this operand is broken for all of the instances of this\n";
1819 OS << " // mnemonic, keep track of it so we can report loc info.\n";
1820 OS << " if (it == MnemonicRange.first || ErrorInfo == i+1)\n";
1821 OS << " ErrorInfo = i+1;\n";
1823 OS << " ErrorInfo = ~0U;";
1824 OS << " // Otherwise, just reject this instance of the mnemonic.\n";
1825 OS << " OperandsValid = false;\n";
1829 OS << " if (!OperandsValid) continue;\n";
1831 // Emit check that the required features are available.
1832 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
1833 << "!= it->RequiredFeatures) {\n";
1834 OS << " HadMatchOtherThanFeatures = true;\n";
1835 OS << " continue;\n";
1839 OS << " ConvertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n";
1841 // Call the post-processing function, if used.
1842 std::string InsnCleanupFn =
1843 AsmParser->getValueAsString("AsmParserInstCleanup");
1844 if (!InsnCleanupFn.empty())
1845 OS << " " << InsnCleanupFn << "(Inst);\n";
1847 OS << " return Match_Success;\n";
1850 OS << " // Okay, we had no match. Try to return a useful error code.\n";
1851 OS << " if (HadMatchOtherThanFeatures) return Match_MissingFeature;\n";
1852 OS << " return Match_InvalidOperand;\n";
1855 OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";