1 //===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits a target specifier matcher for converting parsed
11 // assembly operands in the MCInst structures.
13 // The input to the target specific matcher is a list of literal tokens and
14 // operands. The target specific parser should generally eliminate any syntax
15 // which is not relevant for matching; for example, comma tokens should have
16 // already been consumed and eliminated by the parser. Most instructions will
17 // end up with a single literal token (the instruction name) and some number of
20 // Some example inputs, for X86:
21 // 'addl' (immediate ...) (register ...)
22 // 'add' (immediate ...) (memory ...)
25 // The assembly matcher is responsible for converting this input into a precise
26 // machine instruction (i.e., an instruction with a well defined encoding). This
27 // mapping has several properties which complicate matching:
29 // - It may be ambiguous; many architectures can legally encode particular
30 // variants of an instruction in different ways (for example, using a smaller
31 // encoding for small immediates). Such ambiguities should never be
32 // arbitrarily resolved by the assembler, the assembler is always responsible
33 // for choosing the "best" available instruction.
35 // - It may depend on the subtarget or the assembler context. Instructions
36 // which are invalid for the current mode, but otherwise unambiguous (e.g.,
37 // an SSE instruction in a file being assembled for i486) should be accepted
38 // and rejected by the assembler front end. However, if the proper encoding
39 // for an instruction is dependent on the assembler context then the matcher
40 // is responsible for selecting the correct machine instruction for the
43 // The core matching algorithm attempts to exploit the regularity in most
44 // instruction sets to quickly determine the set of possibly matching
45 // instructions, and the simplify the generated code. Additionally, this helps
46 // to ensure that the ambiguities are intentionally resolved by the user.
48 // The matching is divided into two distinct phases:
50 // 1. Classification: Each operand is mapped to the unique set which (a)
51 // contains it, and (b) is the largest such subset for which a single
52 // instruction could match all members.
54 // For register classes, we can generate these subgroups automatically. For
55 // arbitrary operands, we expect the user to define the classes and their
56 // relations to one another (for example, 8-bit signed immediates as a
57 // subset of 32-bit immediates).
59 // By partitioning the operands in this way, we guarantee that for any
60 // tuple of classes, any single instruction must match either all or none
61 // of the sets of operands which could classify to that tuple.
63 // In addition, the subset relation amongst classes induces a partial order
64 // on such tuples, which we use to resolve ambiguities.
66 // 2. The input can now be treated as a tuple of classes (static tokens are
67 // simple singleton sets). Each such tuple should generally map to a single
68 // instruction (we currently ignore cases where this isn't true, whee!!!),
69 // which we can emit a simple matcher for.
71 //===----------------------------------------------------------------------===//
73 #include "AsmMatcherEmitter.h"
74 #include "CodeGenTarget.h"
76 #include "StringMatcher.h"
77 #include "llvm/ADT/OwningPtr.h"
78 #include "llvm/ADT/SmallPtrSet.h"
79 #include "llvm/ADT/SmallVector.h"
80 #include "llvm/ADT/STLExtras.h"
81 #include "llvm/ADT/StringExtras.h"
82 #include "llvm/Support/CommandLine.h"
83 #include "llvm/Support/Debug.h"
88 static cl::opt<std::string>
89 MatchPrefix("match-prefix", cl::init(""),
90 cl::desc("Only match instructions with the given prefix"));
95 struct SubtargetFeatureInfo;
97 /// ClassInfo - Helper class for storing the information about a particular
98 /// class of operands which can be matched.
101 /// Invalid kind, for use as a sentinel value.
104 /// The class for a particular token.
107 /// The (first) register class, subsequent register classes are
108 /// RegisterClass0+1, and so on.
111 /// The (first) user defined class, subsequent user defined classes are
112 /// UserClass0+1, and so on.
116 /// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
117 /// N) for the Nth user defined class.
120 /// SuperClasses - The super classes of this class. Note that for simplicities
121 /// sake user operands only record their immediate super class, while register
122 /// operands include all superclasses.
123 std::vector<ClassInfo*> SuperClasses;
125 /// Name - The full class name, suitable for use in an enum.
128 /// ClassName - The unadorned generic name for this class (e.g., Token).
129 std::string ClassName;
131 /// ValueName - The name of the value this class represents; for a token this
132 /// is the literal token string, for an operand it is the TableGen class (or
133 /// empty if this is a derived class).
134 std::string ValueName;
136 /// PredicateMethod - The name of the operand method to test whether the
137 /// operand matches this class; this is not valid for Token or register kinds.
138 std::string PredicateMethod;
140 /// RenderMethod - The name of the operand method to add this operand to an
141 /// MCInst; this is not valid for Token or register kinds.
142 std::string RenderMethod;
144 /// For register classes, the records for all the registers in this class.
145 std::set<Record*> Registers;
148 /// isRegisterClass() - Check if this is a register class.
149 bool isRegisterClass() const {
150 return Kind >= RegisterClass0 && Kind < UserClass0;
153 /// isUserClass() - Check if this is a user defined class.
154 bool isUserClass() const {
155 return Kind >= UserClass0;
158 /// isRelatedTo - Check whether this class is "related" to \arg RHS. Classes
159 /// are related if they are in the same class hierarchy.
160 bool isRelatedTo(const ClassInfo &RHS) const {
161 // Tokens are only related to tokens.
162 if (Kind == Token || RHS.Kind == Token)
163 return Kind == Token && RHS.Kind == Token;
165 // Registers classes are only related to registers classes, and only if
166 // their intersection is non-empty.
167 if (isRegisterClass() || RHS.isRegisterClass()) {
168 if (!isRegisterClass() || !RHS.isRegisterClass())
171 std::set<Record*> Tmp;
172 std::insert_iterator< std::set<Record*> > II(Tmp, Tmp.begin());
173 std::set_intersection(Registers.begin(), Registers.end(),
174 RHS.Registers.begin(), RHS.Registers.end(),
180 // Otherwise we have two users operands; they are related if they are in the
181 // same class hierarchy.
183 // FIXME: This is an oversimplification, they should only be related if they
184 // intersect, however we don't have that information.
185 assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");
186 const ClassInfo *Root = this;
187 while (!Root->SuperClasses.empty())
188 Root = Root->SuperClasses.front();
190 const ClassInfo *RHSRoot = &RHS;
191 while (!RHSRoot->SuperClasses.empty())
192 RHSRoot = RHSRoot->SuperClasses.front();
194 return Root == RHSRoot;
197 /// isSubsetOf - Test whether this class is a subset of \arg RHS;
198 bool isSubsetOf(const ClassInfo &RHS) const {
199 // This is a subset of RHS if it is the same class...
203 // ... or if any of its super classes are a subset of RHS.
204 for (std::vector<ClassInfo*>::const_iterator it = SuperClasses.begin(),
205 ie = SuperClasses.end(); it != ie; ++it)
206 if ((*it)->isSubsetOf(RHS))
212 /// operator< - Compare two classes.
213 bool operator<(const ClassInfo &RHS) const {
217 // Unrelated classes can be ordered by kind.
218 if (!isRelatedTo(RHS))
219 return Kind < RHS.Kind;
223 assert(0 && "Invalid kind!");
225 // Tokens are comparable by value.
227 // FIXME: Compare by enum value.
228 return ValueName < RHS.ValueName;
231 // This class preceeds the RHS if it is a proper subset of the RHS.
234 if (RHS.isSubsetOf(*this))
237 // Otherwise, order by name to ensure we have a total ordering.
238 return ValueName < RHS.ValueName;
243 /// MatchableInfo - Helper class for storing the necessary information for an
244 /// instruction or alias which is capable of being matched.
245 struct MatchableInfo {
247 /// Token - This is the token that the operand came from.
250 /// The unique class instance this operand should match.
253 /// The original operand this corresponds to. This is unset for singleton
254 /// registers and tokens, because they don't have a list in the ins/outs
255 /// list. If an operand is tied ($a=$b), this refers to source operand: $b.
256 const CGIOperandList::OperandInfo *OperandInfo;
258 explicit AsmOperand(StringRef T) : Token(T), Class(0), OperandInfo(0) {}
261 /// ResOperand - This represents a single operand in the result instruction
262 /// generated by the match. In cases (like addressing modes) where a single
263 /// assembler operand expands to multiple MCOperands, this represents the
264 /// single assembler operand, not the MCOperand.
267 /// RenderAsmOperand - This represents an operand result that is
268 /// generated by calling the render method on the assembly operand. The
269 /// corresponding AsmOperand is specified by AsmOperandNum.
272 /// TiedOperand - This represents a result operand that is a duplicate of
273 /// a previous result operand.
278 /// This is the operand # in the AsmOperands list that this should be
280 unsigned AsmOperandNum;
282 /// TiedOperandNum - This is the (earlier) result operand that should be
284 unsigned TiedOperandNum;
287 /// OpInfo - This is the information about the instruction operand that is
289 const CGIOperandList::OperandInfo *OpInfo;
291 static ResOperand getRenderedOp(unsigned AsmOpNum,
292 const CGIOperandList::OperandInfo *Op) {
294 X.Kind = RenderAsmOperand;
295 X.AsmOperandNum = AsmOpNum;
300 static ResOperand getTiedOp(unsigned TiedOperandNum,
301 const CGIOperandList::OperandInfo *Op) {
303 X.Kind = TiedOperand;
304 X.TiedOperandNum = TiedOperandNum;
310 /// InstrName - The target name for this instruction.
311 std::string InstrName;
313 /// TheDef - This is the definition of the instruction or InstAlias that this
314 /// matchable came from.
315 Record *const TheDef;
318 const CGIOperandList &TheOperandList;
321 /// ResOperands - This is the operand list that should be built for the result
323 std::vector<ResOperand> ResOperands;
325 /// AsmString - The assembly string for this instruction (with variants
326 /// removed), e.g. "movsx $src, $dst".
327 std::string AsmString;
329 /// Mnemonic - This is the first token of the matched instruction, its
333 /// AsmOperands - The textual operands that this instruction matches,
334 /// annotated with a class and where in the OperandList they were defined.
335 /// This directly corresponds to the tokenized AsmString after the mnemonic is
337 SmallVector<AsmOperand, 4> AsmOperands;
339 /// Predicates - The required subtarget features to match this instruction.
340 SmallVector<SubtargetFeatureInfo*, 4> RequiredFeatures;
342 /// ConversionFnKind - The enum value which is passed to the generated
343 /// ConvertToMCInst to convert parsed operands into an MCInst for this
345 std::string ConversionFnKind;
347 MatchableInfo(const CodeGenInstruction &CGI)
348 : TheDef(CGI.TheDef), TheOperandList(CGI.Operands), AsmString(CGI.AsmString) {
349 InstrName = TheDef->getName();
352 MatchableInfo(const CodeGenInstAlias *Alias)
353 : TheDef(Alias->TheDef), TheOperandList(Alias->Operands),
354 AsmString(Alias->AsmString) {
357 DefInit *DI = dynamic_cast<DefInit*>(Alias->Result->getOperator());
360 InstrName = DI->getDef()->getName();
363 void Initialize(const AsmMatcherInfo &Info,
364 SmallPtrSet<Record*, 16> &SingletonRegisters);
366 /// Validate - Return true if this matchable is a valid thing to match against
367 /// and perform a bunch of validity checking.
368 bool Validate(StringRef CommentDelimiter, bool Hack) const;
370 /// getSingletonRegisterForAsmOperand - If the specified token is a singleton
371 /// register, return the Record for it, otherwise return null.
372 Record *getSingletonRegisterForAsmOperand(unsigned i,
373 const AsmMatcherInfo &Info) const;
375 void BuildResultOperands();
377 /// operator< - Compare two matchables.
378 bool operator<(const MatchableInfo &RHS) const {
379 // The primary comparator is the instruction mnemonic.
380 if (Mnemonic != RHS.Mnemonic)
381 return Mnemonic < RHS.Mnemonic;
383 if (AsmOperands.size() != RHS.AsmOperands.size())
384 return AsmOperands.size() < RHS.AsmOperands.size();
386 // Compare lexicographically by operand. The matcher validates that other
387 // orderings wouldn't be ambiguous using \see CouldMatchAmiguouslyWith().
388 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
389 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
391 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
398 /// CouldMatchAmiguouslyWith - Check whether this matchable could
399 /// ambiguously match the same set of operands as \arg RHS (without being a
400 /// strictly superior match).
401 bool CouldMatchAmiguouslyWith(const MatchableInfo &RHS) {
402 // The primary comparator is the instruction mnemonic.
403 if (Mnemonic != RHS.Mnemonic)
406 // The number of operands is unambiguous.
407 if (AsmOperands.size() != RHS.AsmOperands.size())
410 // Otherwise, make sure the ordering of the two instructions is unambiguous
411 // by checking that either (a) a token or operand kind discriminates them,
412 // or (b) the ordering among equivalent kinds is consistent.
414 // Tokens and operand kinds are unambiguous (assuming a correct target
416 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
417 if (AsmOperands[i].Class->Kind != RHS.AsmOperands[i].Class->Kind ||
418 AsmOperands[i].Class->Kind == ClassInfo::Token)
419 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class ||
420 *RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
423 // Otherwise, this operand could commute if all operands are equivalent, or
424 // there is a pair of operands that compare less than and a pair that
425 // compare greater than.
426 bool HasLT = false, HasGT = false;
427 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
428 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
430 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
434 return !(HasLT ^ HasGT);
440 void TokenizeAsmString(const AsmMatcherInfo &Info);
443 /// SubtargetFeatureInfo - Helper class for storing information on a subtarget
444 /// feature which participates in instruction matching.
445 struct SubtargetFeatureInfo {
446 /// \brief The predicate record for this feature.
449 /// \brief An unique index assigned to represent this feature.
452 SubtargetFeatureInfo(Record *D, unsigned Idx) : TheDef(D), Index(Idx) {}
454 /// \brief The name of the enumerated constant identifying this feature.
455 std::string getEnumName() const {
456 return "Feature_" + TheDef->getName();
460 class AsmMatcherInfo {
462 /// The tablegen AsmParser record.
465 /// Target - The target information.
466 CodeGenTarget &Target;
468 /// The AsmParser "RegisterPrefix" value.
469 std::string RegisterPrefix;
471 /// The classes which are needed for matching.
472 std::vector<ClassInfo*> Classes;
474 /// The information on the matchables to match.
475 std::vector<MatchableInfo*> Matchables;
477 /// Map of Register records to their class information.
478 std::map<Record*, ClassInfo*> RegisterClasses;
480 /// Map of Predicate records to their subtarget information.
481 std::map<Record*, SubtargetFeatureInfo*> SubtargetFeatures;
484 /// Map of token to class information which has already been constructed.
485 std::map<std::string, ClassInfo*> TokenClasses;
487 /// Map of RegisterClass records to their class information.
488 std::map<Record*, ClassInfo*> RegisterClassClasses;
490 /// Map of AsmOperandClass records to their class information.
491 std::map<Record*, ClassInfo*> AsmOperandClasses;
494 /// getTokenClass - Lookup or create the class for the given token.
495 ClassInfo *getTokenClass(StringRef Token);
497 /// getOperandClass - Lookup or create the class for the given operand.
498 ClassInfo *getOperandClass(StringRef Token,
499 const CGIOperandList::OperandInfo &OI);
501 /// BuildRegisterClasses - Build the ClassInfo* instances for register
503 void BuildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters);
505 /// BuildOperandClasses - Build the ClassInfo* instances for user defined
507 void BuildOperandClasses();
509 void BuildInstructionOperandReference(MatchableInfo *II,
510 MatchableInfo::AsmOperand &Op);
513 AsmMatcherInfo(Record *AsmParser, CodeGenTarget &Target);
515 /// BuildInfo - Construct the various tables used during matching.
518 /// getSubtargetFeature - Lookup or create the subtarget feature info for the
520 SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const {
521 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
522 std::map<Record*, SubtargetFeatureInfo*>::const_iterator I =
523 SubtargetFeatures.find(Def);
524 return I == SubtargetFeatures.end() ? 0 : I->second;
530 void MatchableInfo::dump() {
531 errs() << InstrName << " -- " << "flattened:\"" << AsmString << "\"\n";
533 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
534 AsmOperand &Op = AsmOperands[i];
535 errs() << " op[" << i << "] = " << Op.Class->ClassName << " - ";
536 if (Op.Class->Kind == ClassInfo::Token) {
537 errs() << '\"' << Op.Token << "\"\n";
541 if (!Op.OperandInfo) {
542 errs() << "(singleton register)\n";
546 const CGIOperandList::OperandInfo &OI = *Op.OperandInfo;
547 errs() << OI.Name << " " << OI.Rec->getName()
548 << " (" << OI.MIOperandNo << ", " << OI.MINumOperands << ")\n";
552 void MatchableInfo::Initialize(const AsmMatcherInfo &Info,
553 SmallPtrSet<Record*, 16> &SingletonRegisters) {
554 // TODO: Eventually support asmparser for Variant != 0.
555 AsmString = CodeGenInstruction::FlattenAsmStringVariants(AsmString, 0);
557 TokenizeAsmString(Info);
559 // Compute the require features.
560 std::vector<Record*> Predicates =TheDef->getValueAsListOfDefs("Predicates");
561 for (unsigned i = 0, e = Predicates.size(); i != e; ++i)
562 if (SubtargetFeatureInfo *Feature =
563 Info.getSubtargetFeature(Predicates[i]))
564 RequiredFeatures.push_back(Feature);
566 // Collect singleton registers, if used.
567 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
568 if (Record *Reg = getSingletonRegisterForAsmOperand(i, Info))
569 SingletonRegisters.insert(Reg);
573 /// TokenizeAsmString - Tokenize a simplified assembly string.
574 void MatchableInfo::TokenizeAsmString(const AsmMatcherInfo &Info) {
575 StringRef String = AsmString;
578 for (unsigned i = 0, e = String.size(); i != e; ++i) {
588 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
591 if (!isspace(String[i]) && String[i] != ',')
592 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
598 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
602 assert(i != String.size() && "Invalid quoted character");
603 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
608 // If this isn't "${", treat like a normal token.
609 if (i + 1 == String.size() || String[i + 1] != '{') {
611 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
619 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
623 StringRef::iterator End = std::find(String.begin() + i, String.end(),'}');
624 assert(End != String.end() && "Missing brace in operand reference!");
625 size_t EndPos = End - String.begin();
626 AsmOperands.push_back(AsmOperand(String.slice(i, EndPos+1)));
634 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
643 if (InTok && Prev != String.size())
644 AsmOperands.push_back(AsmOperand(String.substr(Prev)));
646 // The first token of the instruction is the mnemonic, which must be a
647 // simple string, not a $foo variable or a singleton register.
648 assert(!AsmOperands.empty() && "Instruction has no tokens?");
649 Mnemonic = AsmOperands[0].Token;
650 if (Mnemonic[0] == '$' || getSingletonRegisterForAsmOperand(0, Info))
651 throw TGError(TheDef->getLoc(),
652 "Invalid instruction mnemonic '" + Mnemonic.str() + "'!");
654 // Remove the first operand, it is tracked in the mnemonic field.
655 AsmOperands.erase(AsmOperands.begin());
660 bool MatchableInfo::Validate(StringRef CommentDelimiter, bool Hack) const {
661 // Reject matchables with no .s string.
662 if (AsmString.empty())
663 throw TGError(TheDef->getLoc(), "instruction with empty asm string");
665 // Reject any matchables with a newline in them, they should be marked
666 // isCodeGenOnly if they are pseudo instructions.
667 if (AsmString.find('\n') != std::string::npos)
668 throw TGError(TheDef->getLoc(),
669 "multiline instruction is not valid for the asmparser, "
670 "mark it isCodeGenOnly");
672 // Remove comments from the asm string. We know that the asmstring only
674 if (!CommentDelimiter.empty() &&
675 StringRef(AsmString).find(CommentDelimiter) != StringRef::npos)
676 throw TGError(TheDef->getLoc(),
677 "asmstring for instruction has comment character in it, "
678 "mark it isCodeGenOnly");
680 // Reject matchables with operand modifiers, these aren't something we can
681 /// handle, the target should be refactored to use operands instead of
684 // Also, check for instructions which reference the operand multiple times;
685 // this implies a constraint we would not honor.
686 std::set<std::string> OperandNames;
687 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
688 StringRef Tok = AsmOperands[i].Token;
689 if (Tok[0] == '$' && Tok.find(':') != StringRef::npos)
690 throw TGError(TheDef->getLoc(),
691 "matchable with operand modifier '" + Tok.str() +
692 "' not supported by asm matcher. Mark isCodeGenOnly!");
694 // Verify that any operand is only mentioned once.
695 // We reject aliases and ignore instructions for now.
696 if (Tok[0] == '$' && !OperandNames.insert(Tok).second) {
698 throw TGError(TheDef->getLoc(),
699 "ERROR: matchable with tied operand '" + Tok.str() +
700 "' can never be matched!");
701 // FIXME: Should reject these. The ARM backend hits this with $lane in a
702 // bunch of instructions. It is unclear what the right answer is.
704 errs() << "warning: '" << InstrName << "': "
705 << "ignoring instruction with tied operand '"
706 << Tok.str() << "'\n";
716 /// getSingletonRegisterForAsmOperand - If the specified token is a singleton
717 /// register, return the register name, otherwise return a null StringRef.
718 Record *MatchableInfo::
719 getSingletonRegisterForAsmOperand(unsigned i, const AsmMatcherInfo &Info) const{
720 StringRef Tok = AsmOperands[i].Token;
721 if (!Tok.startswith(Info.RegisterPrefix))
724 StringRef RegName = Tok.substr(Info.RegisterPrefix.size());
725 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName))
728 // If there is no register prefix (i.e. "%" in "%eax"), then this may
729 // be some random non-register token, just ignore it.
730 if (Info.RegisterPrefix.empty())
733 // Otherwise, we have something invalid prefixed with the register prefix,
735 std::string Err = "unable to find register for '" + RegName.str() +
736 "' (which matches register prefix)";
737 throw TGError(TheDef->getLoc(), Err);
741 static std::string getEnumNameForToken(StringRef Str) {
744 for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) {
746 case '*': Res += "_STAR_"; break;
747 case '%': Res += "_PCT_"; break;
748 case ':': Res += "_COLON_"; break;
753 Res += "_" + utostr((unsigned) *it) + "_";
760 ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) {
761 ClassInfo *&Entry = TokenClasses[Token];
764 Entry = new ClassInfo();
765 Entry->Kind = ClassInfo::Token;
766 Entry->ClassName = "Token";
767 Entry->Name = "MCK_" + getEnumNameForToken(Token);
768 Entry->ValueName = Token;
769 Entry->PredicateMethod = "<invalid>";
770 Entry->RenderMethod = "<invalid>";
771 Classes.push_back(Entry);
778 AsmMatcherInfo::getOperandClass(StringRef Token,
779 const CGIOperandList::OperandInfo &OI) {
780 if (OI.Rec->isSubClassOf("RegisterClass")) {
781 if (ClassInfo *CI = RegisterClassClasses[OI.Rec])
783 throw TGError(OI.Rec->getLoc(), "register class has no class info!");
786 assert(OI.Rec->isSubClassOf("Operand") && "Unexpected operand!");
787 Record *MatchClass = OI.Rec->getValueAsDef("ParserMatchClass");
788 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
791 throw TGError(OI.Rec->getLoc(), "operand has no match class!");
794 void AsmMatcherInfo::
795 BuildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters) {
796 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
797 const std::vector<CodeGenRegisterClass> &RegClassList =
798 Target.getRegisterClasses();
800 // The register sets used for matching.
801 std::set< std::set<Record*> > RegisterSets;
803 // Gather the defined sets.
804 for (std::vector<CodeGenRegisterClass>::const_iterator it =
805 RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it)
806 RegisterSets.insert(std::set<Record*>(it->Elements.begin(),
807 it->Elements.end()));
809 // Add any required singleton sets.
810 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
811 ie = SingletonRegisters.end(); it != ie; ++it) {
813 RegisterSets.insert(std::set<Record*>(&Rec, &Rec + 1));
816 // Introduce derived sets where necessary (when a register does not determine
817 // a unique register set class), and build the mapping of registers to the set
818 // they should classify to.
819 std::map<Record*, std::set<Record*> > RegisterMap;
820 for (std::vector<CodeGenRegister>::const_iterator it = Registers.begin(),
821 ie = Registers.end(); it != ie; ++it) {
822 const CodeGenRegister &CGR = *it;
823 // Compute the intersection of all sets containing this register.
824 std::set<Record*> ContainingSet;
826 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
827 ie = RegisterSets.end(); it != ie; ++it) {
828 if (!it->count(CGR.TheDef))
831 if (ContainingSet.empty()) {
836 std::set<Record*> Tmp;
837 std::swap(Tmp, ContainingSet);
838 std::insert_iterator< std::set<Record*> > II(ContainingSet,
839 ContainingSet.begin());
840 std::set_intersection(Tmp.begin(), Tmp.end(), it->begin(), it->end(), II);
843 if (!ContainingSet.empty()) {
844 RegisterSets.insert(ContainingSet);
845 RegisterMap.insert(std::make_pair(CGR.TheDef, ContainingSet));
849 // Construct the register classes.
850 std::map<std::set<Record*>, ClassInfo*> RegisterSetClasses;
852 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
853 ie = RegisterSets.end(); it != ie; ++it, ++Index) {
854 ClassInfo *CI = new ClassInfo();
855 CI->Kind = ClassInfo::RegisterClass0 + Index;
856 CI->ClassName = "Reg" + utostr(Index);
857 CI->Name = "MCK_Reg" + utostr(Index);
859 CI->PredicateMethod = ""; // unused
860 CI->RenderMethod = "addRegOperands";
862 Classes.push_back(CI);
863 RegisterSetClasses.insert(std::make_pair(*it, CI));
866 // Find the superclasses; we could compute only the subgroup lattice edges,
867 // but there isn't really a point.
868 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
869 ie = RegisterSets.end(); it != ie; ++it) {
870 ClassInfo *CI = RegisterSetClasses[*it];
871 for (std::set< std::set<Record*> >::iterator it2 = RegisterSets.begin(),
872 ie2 = RegisterSets.end(); it2 != ie2; ++it2)
874 std::includes(it2->begin(), it2->end(), it->begin(), it->end()))
875 CI->SuperClasses.push_back(RegisterSetClasses[*it2]);
878 // Name the register classes which correspond to a user defined RegisterClass.
879 for (std::vector<CodeGenRegisterClass>::const_iterator
880 it = RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it) {
881 ClassInfo *CI = RegisterSetClasses[std::set<Record*>(it->Elements.begin(),
882 it->Elements.end())];
883 if (CI->ValueName.empty()) {
884 CI->ClassName = it->getName();
885 CI->Name = "MCK_" + it->getName();
886 CI->ValueName = it->getName();
888 CI->ValueName = CI->ValueName + "," + it->getName();
890 RegisterClassClasses.insert(std::make_pair(it->TheDef, CI));
893 // Populate the map for individual registers.
894 for (std::map<Record*, std::set<Record*> >::iterator it = RegisterMap.begin(),
895 ie = RegisterMap.end(); it != ie; ++it)
896 RegisterClasses[it->first] = RegisterSetClasses[it->second];
898 // Name the register classes which correspond to singleton registers.
899 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
900 ie = SingletonRegisters.end(); it != ie; ++it) {
902 ClassInfo *CI = RegisterClasses[Rec];
903 assert(CI && "Missing singleton register class info!");
905 if (CI->ValueName.empty()) {
906 CI->ClassName = Rec->getName();
907 CI->Name = "MCK_" + Rec->getName();
908 CI->ValueName = Rec->getName();
910 CI->ValueName = CI->ValueName + "," + Rec->getName();
914 void AsmMatcherInfo::BuildOperandClasses() {
915 std::vector<Record*> AsmOperands =
916 Records.getAllDerivedDefinitions("AsmOperandClass");
918 // Pre-populate AsmOperandClasses map.
919 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
920 ie = AsmOperands.end(); it != ie; ++it)
921 AsmOperandClasses[*it] = new ClassInfo();
924 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
925 ie = AsmOperands.end(); it != ie; ++it, ++Index) {
926 ClassInfo *CI = AsmOperandClasses[*it];
927 CI->Kind = ClassInfo::UserClass0 + Index;
929 ListInit *Supers = (*it)->getValueAsListInit("SuperClasses");
930 for (unsigned i = 0, e = Supers->getSize(); i != e; ++i) {
931 DefInit *DI = dynamic_cast<DefInit*>(Supers->getElement(i));
933 PrintError((*it)->getLoc(), "Invalid super class reference!");
937 ClassInfo *SC = AsmOperandClasses[DI->getDef()];
939 PrintError((*it)->getLoc(), "Invalid super class reference!");
941 CI->SuperClasses.push_back(SC);
943 CI->ClassName = (*it)->getValueAsString("Name");
944 CI->Name = "MCK_" + CI->ClassName;
945 CI->ValueName = (*it)->getName();
947 // Get or construct the predicate method name.
948 Init *PMName = (*it)->getValueInit("PredicateMethod");
949 if (StringInit *SI = dynamic_cast<StringInit*>(PMName)) {
950 CI->PredicateMethod = SI->getValue();
952 assert(dynamic_cast<UnsetInit*>(PMName) &&
953 "Unexpected PredicateMethod field!");
954 CI->PredicateMethod = "is" + CI->ClassName;
957 // Get or construct the render method name.
958 Init *RMName = (*it)->getValueInit("RenderMethod");
959 if (StringInit *SI = dynamic_cast<StringInit*>(RMName)) {
960 CI->RenderMethod = SI->getValue();
962 assert(dynamic_cast<UnsetInit*>(RMName) &&
963 "Unexpected RenderMethod field!");
964 CI->RenderMethod = "add" + CI->ClassName + "Operands";
967 AsmOperandClasses[*it] = CI;
968 Classes.push_back(CI);
972 AsmMatcherInfo::AsmMatcherInfo(Record *asmParser, CodeGenTarget &target)
973 : AsmParser(asmParser), Target(target),
974 RegisterPrefix(AsmParser->getValueAsString("RegisterPrefix")) {
977 /// BuildInstructionOperandReference - The specified operand is a reference to a
978 /// named operand such as $src. Resolve the Class and OperandInfo pointers.
979 void AsmMatcherInfo::
980 BuildInstructionOperandReference(MatchableInfo *II,
981 MatchableInfo::AsmOperand &Op) {
982 StringRef Token = Op.Token;
983 assert(Token[0] == '$' && "Not an operand name ref");
985 StringRef OperandName;
987 OperandName = Token.substr(2, Token.size() - 3);
989 OperandName = Token.substr(1);
991 const CGIOperandList &Operands = II->TheOperandList;
994 // Map this token to an operand. FIXME: Move elsewhere.
996 if (!Operands.hasOperandNamed(OperandName, Idx))
997 throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" +
998 OperandName.str() + "'");
1000 // FIXME: This is annoying, the named operand may be tied (e.g.,
1001 // XCHG8rm). What we want is the untied operand, which we now have to
1002 // grovel for. Only worry about this for single entry operands, we have to
1003 // clean this up anyway.
1004 const CGIOperandList::OperandInfo *OI = &Operands[Idx];
1005 int OITied = OI->getTiedRegister();
1007 // The tied operand index is an MIOperand index, find the operand that
1009 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
1010 if (Operands[i].MIOperandNo == unsigned(OITied)) {
1016 assert(OI && "Unable to find tied operand target!");
1019 Op.Class = getOperandClass(Token, *OI);
1020 Op.OperandInfo = OI;
1024 void AsmMatcherInfo::BuildInfo() {
1025 // Build information about all of the AssemblerPredicates.
1026 std::vector<Record*> AllPredicates =
1027 Records.getAllDerivedDefinitions("Predicate");
1028 for (unsigned i = 0, e = AllPredicates.size(); i != e; ++i) {
1029 Record *Pred = AllPredicates[i];
1030 // Ignore predicates that are not intended for the assembler.
1031 if (!Pred->getValueAsBit("AssemblerMatcherPredicate"))
1034 if (Pred->getName().empty())
1035 throw TGError(Pred->getLoc(), "Predicate has no name!");
1037 unsigned FeatureNo = SubtargetFeatures.size();
1038 SubtargetFeatures[Pred] = new SubtargetFeatureInfo(Pred, FeatureNo);
1039 assert(FeatureNo < 32 && "Too many subtarget features!");
1042 StringRef CommentDelimiter = AsmParser->getValueAsString("CommentDelimiter");
1044 // Parse the instructions; we need to do this first so that we can gather the
1045 // singleton register classes.
1046 SmallPtrSet<Record*, 16> SingletonRegisters;
1047 for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
1048 E = Target.inst_end(); I != E; ++I) {
1049 const CodeGenInstruction &CGI = **I;
1051 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1052 // filter the set of instructions we consider.
1053 if (!StringRef(CGI.TheDef->getName()).startswith(MatchPrefix))
1056 // Ignore "codegen only" instructions.
1057 if (CGI.TheDef->getValueAsBit("isCodeGenOnly"))
1060 // Validate the operand list to ensure we can handle this instruction.
1061 for (unsigned i = 0, e = CGI.Operands.size(); i != e; ++i) {
1062 const CGIOperandList::OperandInfo &OI = CGI.Operands[i];
1064 // Validate tied operands.
1065 if (OI.getTiedRegister() != -1) {
1066 // If we have a tied operand that consists of multiple MCOperands, reject
1067 // it. We reject aliases and ignore instructions for now.
1068 if (OI.MINumOperands != 1) {
1069 // FIXME: Should reject these. The ARM backend hits this with $lane
1070 // in a bunch of instructions. It is unclear what the right answer is.
1072 errs() << "warning: '" << CGI.TheDef->getName() << "': "
1073 << "ignoring instruction with multi-operand tied operand '"
1074 << OI.Name << "'\n";
1081 OwningPtr<MatchableInfo> II(new MatchableInfo(CGI));
1083 II->Initialize(*this, SingletonRegisters);
1085 // Ignore instructions which shouldn't be matched and diagnose invalid
1086 // instruction definitions with an error.
1087 if (!II->Validate(CommentDelimiter, true))
1090 // Ignore "Int_*" and "*_Int" instructions, which are internal aliases.
1092 // FIXME: This is a total hack.
1093 if (StringRef(II->InstrName).startswith("Int_") ||
1094 StringRef(II->InstrName).endswith("_Int"))
1097 Matchables.push_back(II.take());
1100 // Parse all of the InstAlias definitions and stick them in the list of
1102 std::vector<Record*> AllInstAliases =
1103 Records.getAllDerivedDefinitions("InstAlias");
1104 for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) {
1105 CodeGenInstAlias *Alias = new CodeGenInstAlias(AllInstAliases[i]);
1107 OwningPtr<MatchableInfo> II(new MatchableInfo(Alias));
1109 II->Initialize(*this, SingletonRegisters);
1111 // Validate the alias definitions.
1112 II->Validate(CommentDelimiter, false);
1114 Matchables.push_back(II.take());
1117 // Build info for the register classes.
1118 BuildRegisterClasses(SingletonRegisters);
1120 // Build info for the user defined assembly operand classes.
1121 BuildOperandClasses();
1123 // Build the information about matchables.
1124 for (std::vector<MatchableInfo*>::iterator it = Matchables.begin(),
1125 ie = Matchables.end(); it != ie; ++it) {
1126 MatchableInfo *II = *it;
1128 // Parse the tokens after the mnemonic.
1129 for (unsigned i = 0, e = II->AsmOperands.size(); i != e; ++i) {
1130 MatchableInfo::AsmOperand &Op = II->AsmOperands[i];
1131 StringRef Token = Op.Token;
1133 // Check for singleton registers.
1134 if (Record *RegRecord = II->getSingletonRegisterForAsmOperand(i, *this)) {
1135 Op.Class = RegisterClasses[RegRecord];
1136 assert(Op.Class && Op.Class->Registers.size() == 1 &&
1137 "Unexpected class for singleton register");
1141 // Check for simple tokens.
1142 if (Token[0] != '$') {
1143 Op.Class = getTokenClass(Token);
1147 // Otherwise this is an operand reference.
1148 BuildInstructionOperandReference(II, Op);
1151 II->BuildResultOperands();
1154 // Reorder classes so that classes preceed super classes.
1155 std::sort(Classes.begin(), Classes.end(), less_ptr<ClassInfo>());
1158 void MatchableInfo::BuildResultOperands() {
1159 /// OperandMap - This is a mapping from the MCInst operands (specified by the
1160 /// II.OperandList operands) to the AsmOperands that they are filled in from.
1161 SmallVector<int, 16> OperandMap(TheOperandList.size(), -1);
1163 // Order the (class) operands by the order to convert them into an MCInst.
1164 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
1165 MatchableInfo::AsmOperand &Op = AsmOperands[i];
1166 if (!Op.OperandInfo) continue;
1169 // FIXME: eliminate the mapping+unmapping.
1170 unsigned LogicalOpNum = Op.OperandInfo - &TheOperandList[0];
1171 assert(LogicalOpNum < OperandMap.size() && "Invalid operand number");
1172 OperandMap[LogicalOpNum] = i;
1175 for (unsigned i = 0, e = TheOperandList.size(); i != e; ++i) {
1176 const CGIOperandList::OperandInfo &OpInfo = TheOperandList[i];
1178 // Find out what operand from the asmparser that this MCInst operand comes
1180 int SrcOperand = OperandMap[i];
1181 if (SrcOperand != -1) {
1182 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, &OpInfo));
1186 // Otherwise, this must be a tied operand.
1187 int TiedOp = OpInfo.getTiedRegister();
1189 throw TGError(TheDef->getLoc(), "Instruction '" +
1190 TheDef->getName() + "' has operand '" + OpInfo.Name +
1191 "' that doesn't appear in asm string!");
1193 ResOperands.push_back(ResOperand::getTiedOp(TiedOp, &OpInfo));
1198 static void EmitConvertToMCInst(CodeGenTarget &Target,
1199 std::vector<MatchableInfo*> &Infos,
1201 // Write the convert function to a separate stream, so we can drop it after
1203 std::string ConvertFnBody;
1204 raw_string_ostream CvtOS(ConvertFnBody);
1206 // Function we have already generated.
1207 std::set<std::string> GeneratedFns;
1209 // Start the unified conversion function.
1210 CvtOS << "static void ConvertToMCInst(ConversionKind Kind, MCInst &Inst, "
1211 << "unsigned Opcode,\n"
1212 << " const SmallVectorImpl<MCParsedAsmOperand*"
1213 << "> &Operands) {\n";
1214 CvtOS << " Inst.setOpcode(Opcode);\n";
1215 CvtOS << " switch (Kind) {\n";
1216 CvtOS << " default:\n";
1218 // Start the enum, which we will generate inline.
1220 OS << "// Unified function for converting operands to MCInst instances.\n\n";
1221 OS << "enum ConversionKind {\n";
1223 // TargetOperandClass - This is the target's operand class, like X86Operand.
1224 std::string TargetOperandClass = Target.getName() + "Operand";
1226 for (std::vector<MatchableInfo*>::const_iterator it = Infos.begin(),
1227 ie = Infos.end(); it != ie; ++it) {
1228 MatchableInfo &II = **it;
1230 // Build the conversion function signature.
1231 std::string Signature = "Convert";
1232 std::string CaseBody;
1233 raw_string_ostream CaseOS(CaseBody);
1235 // Compute the convert enum and the case body.
1236 for (unsigned i = 0, e = II.ResOperands.size(); i != e; ++i) {
1237 const MatchableInfo::ResOperand &OpInfo = II.ResOperands[i];
1239 // Generate code to populate each result operand.
1240 switch (OpInfo.Kind) {
1241 default: assert(0 && "Unknown result operand kind");
1242 case MatchableInfo::ResOperand::RenderAsmOperand: {
1243 // This comes from something we parsed.
1244 MatchableInfo::AsmOperand &Op = II.AsmOperands[OpInfo.AsmOperandNum];
1246 // Registers are always converted the same, don't duplicate the
1247 // conversion function based on them.
1249 if (Op.Class->isRegisterClass())
1252 Signature += Op.Class->ClassName;
1253 Signature += utostr(Op.OperandInfo->MINumOperands);
1254 Signature += "_" + itostr(OpInfo.AsmOperandNum);
1256 CaseOS << " ((" << TargetOperandClass << "*)Operands["
1257 << (OpInfo.AsmOperandNum+1) << "])->" << Op.Class->RenderMethod
1258 << "(Inst, " << Op.OperandInfo->MINumOperands << ");\n";
1262 case MatchableInfo::ResOperand::TiedOperand: {
1263 // If this operand is tied to a previous one, just copy the MCInst
1264 // operand from the earlier one.We can only tie single MCOperand values.
1265 //assert(OpInfo.OpInfo->MINumOperands == 1 && "Not a singular MCOperand");
1266 unsigned TiedOp = OpInfo.TiedOperandNum;
1267 assert(i > TiedOp && "Tied operand preceeds its target!");
1268 CaseOS << " Inst.addOperand(Inst.getOperand(" << TiedOp << "));\n";
1269 Signature += "__Tie" + utostr(TiedOp);
1275 II.ConversionFnKind = Signature;
1277 // Check if we have already generated this signature.
1278 if (!GeneratedFns.insert(Signature).second)
1281 // If not, emit it now. Add to the enum list.
1282 OS << " " << Signature << ",\n";
1284 CvtOS << " case " << Signature << ":\n";
1285 CvtOS << CaseOS.str();
1286 CvtOS << " return;\n";
1289 // Finish the convert function.
1294 // Finish the enum, and drop the convert function after it.
1296 OS << " NumConversionVariants\n";
1302 /// EmitMatchClassEnumeration - Emit the enumeration for match class kinds.
1303 static void EmitMatchClassEnumeration(CodeGenTarget &Target,
1304 std::vector<ClassInfo*> &Infos,
1306 OS << "namespace {\n\n";
1308 OS << "/// MatchClassKind - The kinds of classes which participate in\n"
1309 << "/// instruction matching.\n";
1310 OS << "enum MatchClassKind {\n";
1311 OS << " InvalidMatchClass = 0,\n";
1312 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1313 ie = Infos.end(); it != ie; ++it) {
1314 ClassInfo &CI = **it;
1315 OS << " " << CI.Name << ", // ";
1316 if (CI.Kind == ClassInfo::Token) {
1317 OS << "'" << CI.ValueName << "'\n";
1318 } else if (CI.isRegisterClass()) {
1319 if (!CI.ValueName.empty())
1320 OS << "register class '" << CI.ValueName << "'\n";
1322 OS << "derived register class\n";
1324 OS << "user defined class '" << CI.ValueName << "'\n";
1327 OS << " NumMatchClassKinds\n";
1333 /// EmitClassifyOperand - Emit the function to classify an operand.
1334 static void EmitClassifyOperand(AsmMatcherInfo &Info,
1336 OS << "static MatchClassKind ClassifyOperand(MCParsedAsmOperand *GOp) {\n"
1337 << " " << Info.Target.getName() << "Operand &Operand = *("
1338 << Info.Target.getName() << "Operand*)GOp;\n";
1341 OS << " if (Operand.isToken())\n";
1342 OS << " return MatchTokenString(Operand.getToken());\n\n";
1344 // Classify registers.
1346 // FIXME: Don't hardcode isReg, getReg.
1347 OS << " if (Operand.isReg()) {\n";
1348 OS << " switch (Operand.getReg()) {\n";
1349 OS << " default: return InvalidMatchClass;\n";
1350 for (std::map<Record*, ClassInfo*>::iterator
1351 it = Info.RegisterClasses.begin(), ie = Info.RegisterClasses.end();
1353 OS << " case " << Info.Target.getName() << "::"
1354 << it->first->getName() << ": return " << it->second->Name << ";\n";
1358 // Classify user defined operands.
1359 for (std::vector<ClassInfo*>::iterator it = Info.Classes.begin(),
1360 ie = Info.Classes.end(); it != ie; ++it) {
1361 ClassInfo &CI = **it;
1363 if (!CI.isUserClass())
1366 OS << " // '" << CI.ClassName << "' class";
1367 if (!CI.SuperClasses.empty()) {
1368 OS << ", subclass of ";
1369 for (unsigned i = 0, e = CI.SuperClasses.size(); i != e; ++i) {
1371 OS << "'" << CI.SuperClasses[i]->ClassName << "'";
1372 assert(CI < *CI.SuperClasses[i] && "Invalid class relation!");
1377 OS << " if (Operand." << CI.PredicateMethod << "()) {\n";
1379 // Validate subclass relationships.
1380 if (!CI.SuperClasses.empty()) {
1381 for (unsigned i = 0, e = CI.SuperClasses.size(); i != e; ++i)
1382 OS << " assert(Operand." << CI.SuperClasses[i]->PredicateMethod
1383 << "() && \"Invalid class relationship!\");\n";
1386 OS << " return " << CI.Name << ";\n";
1389 OS << " return InvalidMatchClass;\n";
1393 /// EmitIsSubclass - Emit the subclass predicate function.
1394 static void EmitIsSubclass(CodeGenTarget &Target,
1395 std::vector<ClassInfo*> &Infos,
1397 OS << "/// IsSubclass - Compute whether \\arg A is a subclass of \\arg B.\n";
1398 OS << "static bool IsSubclass(MatchClassKind A, MatchClassKind B) {\n";
1399 OS << " if (A == B)\n";
1400 OS << " return true;\n\n";
1402 OS << " switch (A) {\n";
1403 OS << " default:\n";
1404 OS << " return false;\n";
1405 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1406 ie = Infos.end(); it != ie; ++it) {
1407 ClassInfo &A = **it;
1409 if (A.Kind != ClassInfo::Token) {
1410 std::vector<StringRef> SuperClasses;
1411 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1412 ie = Infos.end(); it != ie; ++it) {
1413 ClassInfo &B = **it;
1415 if (&A != &B && A.isSubsetOf(B))
1416 SuperClasses.push_back(B.Name);
1419 if (SuperClasses.empty())
1422 OS << "\n case " << A.Name << ":\n";
1424 if (SuperClasses.size() == 1) {
1425 OS << " return B == " << SuperClasses.back() << ";\n";
1429 OS << " switch (B) {\n";
1430 OS << " default: return false;\n";
1431 for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i)
1432 OS << " case " << SuperClasses[i] << ": return true;\n";
1442 /// EmitMatchTokenString - Emit the function to match a token string to the
1443 /// appropriate match class value.
1444 static void EmitMatchTokenString(CodeGenTarget &Target,
1445 std::vector<ClassInfo*> &Infos,
1447 // Construct the match list.
1448 std::vector<StringMatcher::StringPair> Matches;
1449 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1450 ie = Infos.end(); it != ie; ++it) {
1451 ClassInfo &CI = **it;
1453 if (CI.Kind == ClassInfo::Token)
1454 Matches.push_back(StringMatcher::StringPair(CI.ValueName,
1455 "return " + CI.Name + ";"));
1458 OS << "static MatchClassKind MatchTokenString(StringRef Name) {\n";
1460 StringMatcher("Name", Matches, OS).Emit();
1462 OS << " return InvalidMatchClass;\n";
1466 /// EmitMatchRegisterName - Emit the function to match a string to the target
1467 /// specific register enum.
1468 static void EmitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
1470 // Construct the match list.
1471 std::vector<StringMatcher::StringPair> Matches;
1472 for (unsigned i = 0, e = Target.getRegisters().size(); i != e; ++i) {
1473 const CodeGenRegister &Reg = Target.getRegisters()[i];
1474 if (Reg.TheDef->getValueAsString("AsmName").empty())
1477 Matches.push_back(StringMatcher::StringPair(
1478 Reg.TheDef->getValueAsString("AsmName"),
1479 "return " + utostr(i + 1) + ";"));
1482 OS << "static unsigned MatchRegisterName(StringRef Name) {\n";
1484 StringMatcher("Name", Matches, OS).Emit();
1486 OS << " return 0;\n";
1490 /// EmitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag
1492 static void EmitSubtargetFeatureFlagEnumeration(AsmMatcherInfo &Info,
1494 OS << "// Flags for subtarget features that participate in "
1495 << "instruction matching.\n";
1496 OS << "enum SubtargetFeatureFlag {\n";
1497 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
1498 it = Info.SubtargetFeatures.begin(),
1499 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
1500 SubtargetFeatureInfo &SFI = *it->second;
1501 OS << " " << SFI.getEnumName() << " = (1 << " << SFI.Index << "),\n";
1503 OS << " Feature_None = 0\n";
1507 /// EmitComputeAvailableFeatures - Emit the function to compute the list of
1508 /// available features given a subtarget.
1509 static void EmitComputeAvailableFeatures(AsmMatcherInfo &Info,
1511 std::string ClassName =
1512 Info.AsmParser->getValueAsString("AsmParserClassName");
1514 OS << "unsigned " << Info.Target.getName() << ClassName << "::\n"
1515 << "ComputeAvailableFeatures(const " << Info.Target.getName()
1516 << "Subtarget *Subtarget) const {\n";
1517 OS << " unsigned Features = 0;\n";
1518 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
1519 it = Info.SubtargetFeatures.begin(),
1520 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
1521 SubtargetFeatureInfo &SFI = *it->second;
1522 OS << " if (" << SFI.TheDef->getValueAsString("CondString")
1524 OS << " Features |= " << SFI.getEnumName() << ";\n";
1526 OS << " return Features;\n";
1530 static std::string GetAliasRequiredFeatures(Record *R,
1531 const AsmMatcherInfo &Info) {
1532 std::vector<Record*> ReqFeatures = R->getValueAsListOfDefs("Predicates");
1534 unsigned NumFeatures = 0;
1535 for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) {
1536 SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]);
1539 throw TGError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() +
1540 "' is not marked as an AssemblerPredicate!");
1545 Result += F->getEnumName();
1549 if (NumFeatures > 1)
1550 Result = '(' + Result + ')';
1554 /// EmitMnemonicAliases - If the target has any MnemonicAlias<> definitions,
1555 /// emit a function for them and return true, otherwise return false.
1556 static bool EmitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info) {
1557 std::vector<Record*> Aliases =
1558 Records.getAllDerivedDefinitions("MnemonicAlias");
1559 if (Aliases.empty()) return false;
1561 OS << "static void ApplyMnemonicAliases(StringRef &Mnemonic, "
1562 "unsigned Features) {\n";
1564 // Keep track of all the aliases from a mnemonic. Use an std::map so that the
1565 // iteration order of the map is stable.
1566 std::map<std::string, std::vector<Record*> > AliasesFromMnemonic;
1568 for (unsigned i = 0, e = Aliases.size(); i != e; ++i) {
1569 Record *R = Aliases[i];
1570 AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R);
1573 // Process each alias a "from" mnemonic at a time, building the code executed
1574 // by the string remapper.
1575 std::vector<StringMatcher::StringPair> Cases;
1576 for (std::map<std::string, std::vector<Record*> >::iterator
1577 I = AliasesFromMnemonic.begin(), E = AliasesFromMnemonic.end();
1579 const std::vector<Record*> &ToVec = I->second;
1581 // Loop through each alias and emit code that handles each case. If there
1582 // are two instructions without predicates, emit an error. If there is one,
1584 std::string MatchCode;
1585 int AliasWithNoPredicate = -1;
1587 for (unsigned i = 0, e = ToVec.size(); i != e; ++i) {
1588 Record *R = ToVec[i];
1589 std::string FeatureMask = GetAliasRequiredFeatures(R, Info);
1591 // If this unconditionally matches, remember it for later and diagnose
1593 if (FeatureMask.empty()) {
1594 if (AliasWithNoPredicate != -1) {
1595 // We can't have two aliases from the same mnemonic with no predicate.
1596 PrintError(ToVec[AliasWithNoPredicate]->getLoc(),
1597 "two MnemonicAliases with the same 'from' mnemonic!");
1598 throw TGError(R->getLoc(), "this is the other MnemonicAlias.");
1601 AliasWithNoPredicate = i;
1605 if (!MatchCode.empty())
1606 MatchCode += "else ";
1607 MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n";
1608 MatchCode += " Mnemonic = \"" +R->getValueAsString("ToMnemonic")+"\";\n";
1611 if (AliasWithNoPredicate != -1) {
1612 Record *R = ToVec[AliasWithNoPredicate];
1613 if (!MatchCode.empty())
1614 MatchCode += "else\n ";
1615 MatchCode += "Mnemonic = \"" + R->getValueAsString("ToMnemonic")+"\";\n";
1618 MatchCode += "return;";
1620 Cases.push_back(std::make_pair(I->first, MatchCode));
1624 StringMatcher("Mnemonic", Cases, OS).Emit();
1630 void AsmMatcherEmitter::run(raw_ostream &OS) {
1631 CodeGenTarget Target;
1632 Record *AsmParser = Target.getAsmParser();
1633 std::string ClassName = AsmParser->getValueAsString("AsmParserClassName");
1635 // Compute the information on the instructions to match.
1636 AsmMatcherInfo Info(AsmParser, Target);
1639 // Sort the instruction table using the partial order on classes. We use
1640 // stable_sort to ensure that ambiguous instructions are still
1641 // deterministically ordered.
1642 std::stable_sort(Info.Matchables.begin(), Info.Matchables.end(),
1643 less_ptr<MatchableInfo>());
1645 DEBUG_WITH_TYPE("instruction_info", {
1646 for (std::vector<MatchableInfo*>::iterator
1647 it = Info.Matchables.begin(), ie = Info.Matchables.end();
1652 // Check for ambiguous matchables.
1653 DEBUG_WITH_TYPE("ambiguous_instrs", {
1654 unsigned NumAmbiguous = 0;
1655 for (unsigned i = 0, e = Info.Matchables.size(); i != e; ++i) {
1656 for (unsigned j = i + 1; j != e; ++j) {
1657 MatchableInfo &A = *Info.Matchables[i];
1658 MatchableInfo &B = *Info.Matchables[j];
1660 if (A.CouldMatchAmiguouslyWith(B)) {
1661 errs() << "warning: ambiguous matchables:\n";
1663 errs() << "\nis incomparable with:\n";
1671 errs() << "warning: " << NumAmbiguous
1672 << " ambiguous matchables!\n";
1675 // Write the output.
1677 EmitSourceFileHeader("Assembly Matcher Source Fragment", OS);
1679 // Information for the class declaration.
1680 OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
1681 OS << "#undef GET_ASSEMBLER_HEADER\n";
1682 OS << " // This should be included into the middle of the declaration of \n";
1683 OS << " // your subclasses implementation of TargetAsmParser.\n";
1684 OS << " unsigned ComputeAvailableFeatures(const " <<
1685 Target.getName() << "Subtarget *Subtarget) const;\n";
1686 OS << " enum MatchResultTy {\n";
1687 OS << " Match_Success, Match_MnemonicFail, Match_InvalidOperand,\n";
1688 OS << " Match_MissingFeature\n";
1690 OS << " MatchResultTy MatchInstructionImpl(const "
1691 << "SmallVectorImpl<MCParsedAsmOperand*>"
1692 << " &Operands, MCInst &Inst, unsigned &ErrorInfo);\n\n";
1693 OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n";
1698 OS << "\n#ifdef GET_REGISTER_MATCHER\n";
1699 OS << "#undef GET_REGISTER_MATCHER\n\n";
1701 // Emit the subtarget feature enumeration.
1702 EmitSubtargetFeatureFlagEnumeration(Info, OS);
1704 // Emit the function to match a register name to number.
1705 EmitMatchRegisterName(Target, AsmParser, OS);
1707 OS << "#endif // GET_REGISTER_MATCHER\n\n";
1710 OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
1711 OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
1713 // Generate the function that remaps for mnemonic aliases.
1714 bool HasMnemonicAliases = EmitMnemonicAliases(OS, Info);
1716 // Generate the unified function to convert operands into an MCInst.
1717 EmitConvertToMCInst(Target, Info.Matchables, OS);
1719 // Emit the enumeration for classes which participate in matching.
1720 EmitMatchClassEnumeration(Target, Info.Classes, OS);
1722 // Emit the routine to match token strings to their match class.
1723 EmitMatchTokenString(Target, Info.Classes, OS);
1725 // Emit the routine to classify an operand.
1726 EmitClassifyOperand(Info, OS);
1728 // Emit the subclass predicate routine.
1729 EmitIsSubclass(Target, Info.Classes, OS);
1731 // Emit the available features compute function.
1732 EmitComputeAvailableFeatures(Info, OS);
1735 size_t MaxNumOperands = 0;
1736 for (std::vector<MatchableInfo*>::const_iterator it =
1737 Info.Matchables.begin(), ie = Info.Matchables.end();
1739 MaxNumOperands = std::max(MaxNumOperands, (*it)->AsmOperands.size());
1742 // Emit the static match table; unused classes get initalized to 0 which is
1743 // guaranteed to be InvalidMatchClass.
1745 // FIXME: We can reduce the size of this table very easily. First, we change
1746 // it so that store the kinds in separate bit-fields for each index, which
1747 // only needs to be the max width used for classes at that index (we also need
1748 // to reject based on this during classification). If we then make sure to
1749 // order the match kinds appropriately (putting mnemonics last), then we
1750 // should only end up using a few bits for each class, especially the ones
1751 // following the mnemonic.
1752 OS << "namespace {\n";
1753 OS << " struct MatchEntry {\n";
1754 OS << " unsigned Opcode;\n";
1755 OS << " const char *Mnemonic;\n";
1756 OS << " ConversionKind ConvertFn;\n";
1757 OS << " MatchClassKind Classes[" << MaxNumOperands << "];\n";
1758 OS << " unsigned RequiredFeatures;\n";
1761 OS << "// Predicate for searching for an opcode.\n";
1762 OS << " struct LessOpcode {\n";
1763 OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n";
1764 OS << " return StringRef(LHS.Mnemonic) < RHS;\n";
1766 OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n";
1767 OS << " return LHS < StringRef(RHS.Mnemonic);\n";
1769 OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n";
1770 OS << " return StringRef(LHS.Mnemonic) < StringRef(RHS.Mnemonic);\n";
1774 OS << "} // end anonymous namespace.\n\n";
1776 OS << "static const MatchEntry MatchTable["
1777 << Info.Matchables.size() << "] = {\n";
1779 for (std::vector<MatchableInfo*>::const_iterator it =
1780 Info.Matchables.begin(), ie = Info.Matchables.end();
1782 MatchableInfo &II = **it;
1784 OS << " { " << Target.getName() << "::" << II.InstrName
1785 << ", \"" << II.Mnemonic << "\""
1786 << ", " << II.ConversionFnKind << ", { ";
1787 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) {
1788 MatchableInfo::AsmOperand &Op = II.AsmOperands[i];
1791 OS << Op.Class->Name;
1795 // Write the required features mask.
1796 if (!II.RequiredFeatures.empty()) {
1797 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
1799 OS << II.RequiredFeatures[i]->getEnumName();
1809 // Finally, build the match function.
1810 OS << Target.getName() << ClassName << "::MatchResultTy "
1811 << Target.getName() << ClassName << "::\n"
1812 << "MatchInstructionImpl(const SmallVectorImpl<MCParsedAsmOperand*>"
1814 OS << " MCInst &Inst, unsigned &ErrorInfo) {\n";
1816 // Emit code to get the available features.
1817 OS << " // Get the current feature set.\n";
1818 OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n";
1820 OS << " // Get the instruction mnemonic, which is the first token.\n";
1821 OS << " StringRef Mnemonic = ((" << Target.getName()
1822 << "Operand*)Operands[0])->getToken();\n\n";
1824 if (HasMnemonicAliases) {
1825 OS << " // Process all MnemonicAliases to remap the mnemonic.\n";
1826 OS << " ApplyMnemonicAliases(Mnemonic, AvailableFeatures);\n\n";
1829 // Emit code to compute the class list for this operand vector.
1830 OS << " // Eliminate obvious mismatches.\n";
1831 OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n";
1832 OS << " ErrorInfo = " << (MaxNumOperands+1) << ";\n";
1833 OS << " return Match_InvalidOperand;\n";
1836 OS << " // Compute the class list for this operand vector.\n";
1837 OS << " MatchClassKind Classes[" << MaxNumOperands << "];\n";
1838 OS << " for (unsigned i = 1, e = Operands.size(); i != e; ++i) {\n";
1839 OS << " Classes[i-1] = ClassifyOperand(Operands[i]);\n\n";
1841 OS << " // Check for invalid operands before matching.\n";
1842 OS << " if (Classes[i-1] == InvalidMatchClass) {\n";
1843 OS << " ErrorInfo = i;\n";
1844 OS << " return Match_InvalidOperand;\n";
1848 OS << " // Mark unused classes.\n";
1849 OS << " for (unsigned i = Operands.size()-1, e = " << MaxNumOperands << "; "
1850 << "i != e; ++i)\n";
1851 OS << " Classes[i] = InvalidMatchClass;\n\n";
1853 OS << " // Some state to try to produce better error messages.\n";
1854 OS << " bool HadMatchOtherThanFeatures = false;\n\n";
1855 OS << " // Set ErrorInfo to the operand that mismatches if it is \n";
1856 OS << " // wrong for all instances of the instruction.\n";
1857 OS << " ErrorInfo = ~0U;\n";
1859 // Emit code to search the table.
1860 OS << " // Search the table.\n";
1861 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
1862 OS << " std::equal_range(MatchTable, MatchTable+"
1863 << Info.Matchables.size() << ", Mnemonic, LessOpcode());\n\n";
1865 OS << " // Return a more specific error code if no mnemonics match.\n";
1866 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
1867 OS << " return Match_MnemonicFail;\n\n";
1869 OS << " for (const MatchEntry *it = MnemonicRange.first, "
1870 << "*ie = MnemonicRange.second;\n";
1871 OS << " it != ie; ++it) {\n";
1873 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
1874 OS << " assert(Mnemonic == it->Mnemonic);\n";
1876 // Emit check that the subclasses match.
1877 OS << " bool OperandsValid = true;\n";
1878 OS << " for (unsigned i = 0; i != " << MaxNumOperands << "; ++i) {\n";
1879 OS << " if (IsSubclass(Classes[i], it->Classes[i]))\n";
1880 OS << " continue;\n";
1881 OS << " // If this operand is broken for all of the instances of this\n";
1882 OS << " // mnemonic, keep track of it so we can report loc info.\n";
1883 OS << " if (it == MnemonicRange.first || ErrorInfo == i+1)\n";
1884 OS << " ErrorInfo = i+1;\n";
1886 OS << " ErrorInfo = ~0U;";
1887 OS << " // Otherwise, just reject this instance of the mnemonic.\n";
1888 OS << " OperandsValid = false;\n";
1892 OS << " if (!OperandsValid) continue;\n";
1894 // Emit check that the required features are available.
1895 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
1896 << "!= it->RequiredFeatures) {\n";
1897 OS << " HadMatchOtherThanFeatures = true;\n";
1898 OS << " continue;\n";
1902 OS << " ConvertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n";
1904 // Call the post-processing function, if used.
1905 std::string InsnCleanupFn =
1906 AsmParser->getValueAsString("AsmParserInstCleanup");
1907 if (!InsnCleanupFn.empty())
1908 OS << " " << InsnCleanupFn << "(Inst);\n";
1910 OS << " return Match_Success;\n";
1913 OS << " // Okay, we had no match. Try to return a useful error code.\n";
1914 OS << " if (HadMatchOtherThanFeatures) return Match_MissingFeature;\n";
1915 OS << " return Match_InvalidOperand;\n";
1918 OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";