1 //===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits a target specifier matcher for converting parsed
11 // assembly operands in the MCInst structures. It also emits a matcher for
12 // custom operand parsing.
14 // Converting assembly operands into MCInst structures
15 // ---------------------------------------------------
17 // The input to the target specific matcher is a list of literal tokens and
18 // operands. The target specific parser should generally eliminate any syntax
19 // which is not relevant for matching; for example, comma tokens should have
20 // already been consumed and eliminated by the parser. Most instructions will
21 // end up with a single literal token (the instruction name) and some number of
24 // Some example inputs, for X86:
25 // 'addl' (immediate ...) (register ...)
26 // 'add' (immediate ...) (memory ...)
29 // The assembly matcher is responsible for converting this input into a precise
30 // machine instruction (i.e., an instruction with a well defined encoding). This
31 // mapping has several properties which complicate matching:
33 // - It may be ambiguous; many architectures can legally encode particular
34 // variants of an instruction in different ways (for example, using a smaller
35 // encoding for small immediates). Such ambiguities should never be
36 // arbitrarily resolved by the assembler, the assembler is always responsible
37 // for choosing the "best" available instruction.
39 // - It may depend on the subtarget or the assembler context. Instructions
40 // which are invalid for the current mode, but otherwise unambiguous (e.g.,
41 // an SSE instruction in a file being assembled for i486) should be accepted
42 // and rejected by the assembler front end. However, if the proper encoding
43 // for an instruction is dependent on the assembler context then the matcher
44 // is responsible for selecting the correct machine instruction for the
47 // The core matching algorithm attempts to exploit the regularity in most
48 // instruction sets to quickly determine the set of possibly matching
49 // instructions, and the simplify the generated code. Additionally, this helps
50 // to ensure that the ambiguities are intentionally resolved by the user.
52 // The matching is divided into two distinct phases:
54 // 1. Classification: Each operand is mapped to the unique set which (a)
55 // contains it, and (b) is the largest such subset for which a single
56 // instruction could match all members.
58 // For register classes, we can generate these subgroups automatically. For
59 // arbitrary operands, we expect the user to define the classes and their
60 // relations to one another (for example, 8-bit signed immediates as a
61 // subset of 32-bit immediates).
63 // By partitioning the operands in this way, we guarantee that for any
64 // tuple of classes, any single instruction must match either all or none
65 // of the sets of operands which could classify to that tuple.
67 // In addition, the subset relation amongst classes induces a partial order
68 // on such tuples, which we use to resolve ambiguities.
70 // 2. The input can now be treated as a tuple of classes (static tokens are
71 // simple singleton sets). Each such tuple should generally map to a single
72 // instruction (we currently ignore cases where this isn't true, whee!!!),
73 // which we can emit a simple matcher for.
75 // Custom Operand Parsing
76 // ----------------------
78 // Some targets need a custom way to parse operands, some specific instructions
79 // can contain arguments that can represent processor flags and other kinds of
80 // identifiers that need to be mapped to specific values in the final encoded
81 // instructions. The target specific custom operand parsing works in the
84 // 1. A operand match table is built, each entry contains a mnemonic, an
85 // operand class, a mask for all operand positions for that same
86 // class/mnemonic and target features to be checked while trying to match.
88 // 2. The operand matcher will try every possible entry with the same
89 // mnemonic and will check if the target feature for this mnemonic also
90 // matches. After that, if the operand to be matched has its index
91 // present in the mask, a successful match occurs. Otherwise, fallback
92 // to the regular operand parsing.
94 // 3. For a match success, each operand class that has a 'ParserMethod'
95 // becomes part of a switch from where the custom method is called.
97 //===----------------------------------------------------------------------===//
99 #include "CodeGenTarget.h"
100 #include "llvm/ADT/OwningPtr.h"
101 #include "llvm/ADT/PointerUnion.h"
102 #include "llvm/ADT/STLExtras.h"
103 #include "llvm/ADT/SmallPtrSet.h"
104 #include "llvm/ADT/SmallVector.h"
105 #include "llvm/ADT/StringExtras.h"
106 #include "llvm/Support/CommandLine.h"
107 #include "llvm/Support/Debug.h"
108 #include "llvm/Support/ErrorHandling.h"
109 #include "llvm/TableGen/Error.h"
110 #include "llvm/TableGen/Record.h"
111 #include "llvm/TableGen/StringMatcher.h"
112 #include "llvm/TableGen/StringToOffsetTable.h"
113 #include "llvm/TableGen/TableGenBackend.h"
118 using namespace llvm;
120 static cl::opt<std::string>
121 MatchPrefix("match-prefix", cl::init(""),
122 cl::desc("Only match instructions with the given prefix"));
125 class AsmMatcherInfo;
126 struct SubtargetFeatureInfo;
128 class AsmMatcherEmitter {
129 RecordKeeper &Records;
131 AsmMatcherEmitter(RecordKeeper &R) : Records(R) {}
133 void run(raw_ostream &o);
136 /// ClassInfo - Helper class for storing the information about a particular
137 /// class of operands which can be matched.
140 /// Invalid kind, for use as a sentinel value.
143 /// The class for a particular token.
146 /// The (first) register class, subsequent register classes are
147 /// RegisterClass0+1, and so on.
150 /// The (first) user defined class, subsequent user defined classes are
151 /// UserClass0+1, and so on.
155 /// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
156 /// N) for the Nth user defined class.
159 /// SuperClasses - The super classes of this class. Note that for simplicities
160 /// sake user operands only record their immediate super class, while register
161 /// operands include all superclasses.
162 std::vector<ClassInfo*> SuperClasses;
164 /// Name - The full class name, suitable for use in an enum.
167 /// ClassName - The unadorned generic name for this class (e.g., Token).
168 std::string ClassName;
170 /// ValueName - The name of the value this class represents; for a token this
171 /// is the literal token string, for an operand it is the TableGen class (or
172 /// empty if this is a derived class).
173 std::string ValueName;
175 /// PredicateMethod - The name of the operand method to test whether the
176 /// operand matches this class; this is not valid for Token or register kinds.
177 std::string PredicateMethod;
179 /// RenderMethod - The name of the operand method to add this operand to an
180 /// MCInst; this is not valid for Token or register kinds.
181 std::string RenderMethod;
183 /// ParserMethod - The name of the operand method to do a target specific
184 /// parsing on the operand.
185 std::string ParserMethod;
187 /// For register classes, the records for all the registers in this class.
188 std::set<Record*> Registers;
190 /// For custom match classes, he diagnostic kind for when the predicate fails.
191 std::string DiagnosticType;
193 /// isRegisterClass() - Check if this is a register class.
194 bool isRegisterClass() const {
195 return Kind >= RegisterClass0 && Kind < UserClass0;
198 /// isUserClass() - Check if this is a user defined class.
199 bool isUserClass() const {
200 return Kind >= UserClass0;
203 /// isRelatedTo - Check whether this class is "related" to \p RHS. Classes
204 /// are related if they are in the same class hierarchy.
205 bool isRelatedTo(const ClassInfo &RHS) const {
206 // Tokens are only related to tokens.
207 if (Kind == Token || RHS.Kind == Token)
208 return Kind == Token && RHS.Kind == Token;
210 // Registers classes are only related to registers classes, and only if
211 // their intersection is non-empty.
212 if (isRegisterClass() || RHS.isRegisterClass()) {
213 if (!isRegisterClass() || !RHS.isRegisterClass())
216 std::set<Record*> Tmp;
217 std::insert_iterator< std::set<Record*> > II(Tmp, Tmp.begin());
218 std::set_intersection(Registers.begin(), Registers.end(),
219 RHS.Registers.begin(), RHS.Registers.end(),
225 // Otherwise we have two users operands; they are related if they are in the
226 // same class hierarchy.
228 // FIXME: This is an oversimplification, they should only be related if they
229 // intersect, however we don't have that information.
230 assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");
231 const ClassInfo *Root = this;
232 while (!Root->SuperClasses.empty())
233 Root = Root->SuperClasses.front();
235 const ClassInfo *RHSRoot = &RHS;
236 while (!RHSRoot->SuperClasses.empty())
237 RHSRoot = RHSRoot->SuperClasses.front();
239 return Root == RHSRoot;
242 /// isSubsetOf - Test whether this class is a subset of \p RHS.
243 bool isSubsetOf(const ClassInfo &RHS) const {
244 // This is a subset of RHS if it is the same class...
248 // ... or if any of its super classes are a subset of RHS.
249 for (std::vector<ClassInfo*>::const_iterator it = SuperClasses.begin(),
250 ie = SuperClasses.end(); it != ie; ++it)
251 if ((*it)->isSubsetOf(RHS))
257 /// operator< - Compare two classes.
258 bool operator<(const ClassInfo &RHS) const {
262 // Unrelated classes can be ordered by kind.
263 if (!isRelatedTo(RHS))
264 return Kind < RHS.Kind;
268 llvm_unreachable("Invalid kind!");
271 // This class precedes the RHS if it is a proper subset of the RHS.
274 if (RHS.isSubsetOf(*this))
277 // Otherwise, order by name to ensure we have a total ordering.
278 return ValueName < RHS.ValueName;
284 /// Sort ClassInfo pointers independently of pointer value.
285 struct LessClassInfoPtr {
286 bool operator()(const ClassInfo *LHS, const ClassInfo *RHS) const {
292 /// MatchableInfo - Helper class for storing the necessary information for an
293 /// instruction or alias which is capable of being matched.
294 struct MatchableInfo {
296 /// Token - This is the token that the operand came from.
299 /// The unique class instance this operand should match.
302 /// The operand name this is, if anything.
305 /// The suboperand index within SrcOpName, or -1 for the entire operand.
308 /// Register record if this token is singleton register.
309 Record *SingletonReg;
311 explicit AsmOperand(StringRef T) : Token(T), Class(0), SubOpIdx(-1),
315 /// ResOperand - This represents a single operand in the result instruction
316 /// generated by the match. In cases (like addressing modes) where a single
317 /// assembler operand expands to multiple MCOperands, this represents the
318 /// single assembler operand, not the MCOperand.
321 /// RenderAsmOperand - This represents an operand result that is
322 /// generated by calling the render method on the assembly operand. The
323 /// corresponding AsmOperand is specified by AsmOperandNum.
326 /// TiedOperand - This represents a result operand that is a duplicate of
327 /// a previous result operand.
330 /// ImmOperand - This represents an immediate value that is dumped into
334 /// RegOperand - This represents a fixed register that is dumped in.
339 /// This is the operand # in the AsmOperands list that this should be
341 unsigned AsmOperandNum;
343 /// TiedOperandNum - This is the (earlier) result operand that should be
345 unsigned TiedOperandNum;
347 /// ImmVal - This is the immediate value added to the instruction.
350 /// Register - This is the register record.
354 /// MINumOperands - The number of MCInst operands populated by this
356 unsigned MINumOperands;
358 static ResOperand getRenderedOp(unsigned AsmOpNum, unsigned NumOperands) {
360 X.Kind = RenderAsmOperand;
361 X.AsmOperandNum = AsmOpNum;
362 X.MINumOperands = NumOperands;
366 static ResOperand getTiedOp(unsigned TiedOperandNum) {
368 X.Kind = TiedOperand;
369 X.TiedOperandNum = TiedOperandNum;
374 static ResOperand getImmOp(int64_t Val) {
382 static ResOperand getRegOp(Record *Reg) {
391 /// AsmVariantID - Target's assembly syntax variant no.
394 /// TheDef - This is the definition of the instruction or InstAlias that this
395 /// matchable came from.
396 Record *const TheDef;
398 /// DefRec - This is the definition that it came from.
399 PointerUnion<const CodeGenInstruction*, const CodeGenInstAlias*> DefRec;
401 const CodeGenInstruction *getResultInst() const {
402 if (DefRec.is<const CodeGenInstruction*>())
403 return DefRec.get<const CodeGenInstruction*>();
404 return DefRec.get<const CodeGenInstAlias*>()->ResultInst;
407 /// ResOperands - This is the operand list that should be built for the result
409 SmallVector<ResOperand, 8> ResOperands;
411 /// AsmString - The assembly string for this instruction (with variants
412 /// removed), e.g. "movsx $src, $dst".
413 std::string AsmString;
415 /// Mnemonic - This is the first token of the matched instruction, its
419 /// AsmOperands - The textual operands that this instruction matches,
420 /// annotated with a class and where in the OperandList they were defined.
421 /// This directly corresponds to the tokenized AsmString after the mnemonic is
423 SmallVector<AsmOperand, 8> AsmOperands;
425 /// Predicates - The required subtarget features to match this instruction.
426 SmallVector<SubtargetFeatureInfo*, 4> RequiredFeatures;
428 /// ConversionFnKind - The enum value which is passed to the generated
429 /// convertToMCInst to convert parsed operands into an MCInst for this
431 std::string ConversionFnKind;
433 /// If this instruction is deprecated in some form.
436 MatchableInfo(const CodeGenInstruction &CGI)
437 : AsmVariantID(0), TheDef(CGI.TheDef), DefRec(&CGI),
438 AsmString(CGI.AsmString) {
441 MatchableInfo(const CodeGenInstAlias *Alias)
442 : AsmVariantID(0), TheDef(Alias->TheDef), DefRec(Alias),
443 AsmString(Alias->AsmString) {
446 // Two-operand aliases clone from the main matchable, but mark the second
447 // operand as a tied operand of the first for purposes of the assembler.
448 void formTwoOperandAlias(StringRef Constraint);
450 void initialize(const AsmMatcherInfo &Info,
451 SmallPtrSet<Record*, 16> &SingletonRegisters,
452 int AsmVariantNo, std::string &RegisterPrefix);
454 /// validate - Return true if this matchable is a valid thing to match against
455 /// and perform a bunch of validity checking.
456 bool validate(StringRef CommentDelimiter, bool Hack) const;
458 /// extractSingletonRegisterForAsmOperand - Extract singleton register,
459 /// if present, from specified token.
461 extractSingletonRegisterForAsmOperand(unsigned i, const AsmMatcherInfo &Info,
462 std::string &RegisterPrefix);
464 /// findAsmOperand - Find the AsmOperand with the specified name and
465 /// suboperand index.
466 int findAsmOperand(StringRef N, int SubOpIdx) const {
467 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
468 if (N == AsmOperands[i].SrcOpName &&
469 SubOpIdx == AsmOperands[i].SubOpIdx)
474 /// findAsmOperandNamed - Find the first AsmOperand with the specified name.
475 /// This does not check the suboperand index.
476 int findAsmOperandNamed(StringRef N) const {
477 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
478 if (N == AsmOperands[i].SrcOpName)
483 void buildInstructionResultOperands();
484 void buildAliasResultOperands();
486 /// operator< - Compare two matchables.
487 bool operator<(const MatchableInfo &RHS) const {
488 // The primary comparator is the instruction mnemonic.
489 if (Mnemonic != RHS.Mnemonic)
490 return Mnemonic < RHS.Mnemonic;
492 if (AsmOperands.size() != RHS.AsmOperands.size())
493 return AsmOperands.size() < RHS.AsmOperands.size();
495 // Compare lexicographically by operand. The matcher validates that other
496 // orderings wouldn't be ambiguous using \see couldMatchAmbiguouslyWith().
497 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
498 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
500 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
504 // Give matches that require more features higher precedence. This is useful
505 // because we cannot define AssemblerPredicates with the negation of
506 // processor features. For example, ARM v6 "nop" may be either a HINT or
507 // MOV. With v6, we want to match HINT. The assembler has no way to
508 // predicate MOV under "NoV6", but HINT will always match first because it
509 // requires V6 while MOV does not.
510 if (RequiredFeatures.size() != RHS.RequiredFeatures.size())
511 return RequiredFeatures.size() > RHS.RequiredFeatures.size();
516 /// couldMatchAmbiguouslyWith - Check whether this matchable could
517 /// ambiguously match the same set of operands as \p RHS (without being a
518 /// strictly superior match).
519 bool couldMatchAmbiguouslyWith(const MatchableInfo &RHS) {
520 // The primary comparator is the instruction mnemonic.
521 if (Mnemonic != RHS.Mnemonic)
524 // The number of operands is unambiguous.
525 if (AsmOperands.size() != RHS.AsmOperands.size())
528 // Otherwise, make sure the ordering of the two instructions is unambiguous
529 // by checking that either (a) a token or operand kind discriminates them,
530 // or (b) the ordering among equivalent kinds is consistent.
532 // Tokens and operand kinds are unambiguous (assuming a correct target
534 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
535 if (AsmOperands[i].Class->Kind != RHS.AsmOperands[i].Class->Kind ||
536 AsmOperands[i].Class->Kind == ClassInfo::Token)
537 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class ||
538 *RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
541 // Otherwise, this operand could commute if all operands are equivalent, or
542 // there is a pair of operands that compare less than and a pair that
543 // compare greater than.
544 bool HasLT = false, HasGT = false;
545 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
546 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
548 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
552 return !(HasLT ^ HasGT);
558 void tokenizeAsmString(const AsmMatcherInfo &Info);
561 /// SubtargetFeatureInfo - Helper class for storing information on a subtarget
562 /// feature which participates in instruction matching.
563 struct SubtargetFeatureInfo {
564 /// \brief The predicate record for this feature.
567 /// \brief An unique index assigned to represent this feature.
570 SubtargetFeatureInfo(Record *D, unsigned Idx) : TheDef(D), Index(Idx) {}
572 /// \brief The name of the enumerated constant identifying this feature.
573 std::string getEnumName() const {
574 return "Feature_" + TheDef->getName();
578 struct OperandMatchEntry {
579 unsigned OperandMask;
583 static OperandMatchEntry create(MatchableInfo* mi, ClassInfo *ci,
586 X.OperandMask = opMask;
594 class AsmMatcherInfo {
597 RecordKeeper &Records;
599 /// The tablegen AsmParser record.
602 /// Target - The target information.
603 CodeGenTarget &Target;
605 /// The classes which are needed for matching.
606 std::vector<ClassInfo*> Classes;
608 /// The information on the matchables to match.
609 std::vector<MatchableInfo*> Matchables;
611 /// Info for custom matching operands by user defined methods.
612 std::vector<OperandMatchEntry> OperandMatchInfo;
614 /// Map of Register records to their class information.
615 typedef std::map<Record*, ClassInfo*, LessRecordByID> RegisterClassesTy;
616 RegisterClassesTy RegisterClasses;
618 /// Map of Predicate records to their subtarget information.
619 std::map<Record*, SubtargetFeatureInfo*, LessRecordByID> SubtargetFeatures;
621 /// Map of AsmOperandClass records to their class information.
622 std::map<Record*, ClassInfo*> AsmOperandClasses;
625 /// Map of token to class information which has already been constructed.
626 std::map<std::string, ClassInfo*> TokenClasses;
628 /// Map of RegisterClass records to their class information.
629 std::map<Record*, ClassInfo*> RegisterClassClasses;
632 /// getTokenClass - Lookup or create the class for the given token.
633 ClassInfo *getTokenClass(StringRef Token);
635 /// getOperandClass - Lookup or create the class for the given operand.
636 ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI,
638 ClassInfo *getOperandClass(Record *Rec, int SubOpIdx);
640 /// buildRegisterClasses - Build the ClassInfo* instances for register
642 void buildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters);
644 /// buildOperandClasses - Build the ClassInfo* instances for user defined
646 void buildOperandClasses();
648 void buildInstructionOperandReference(MatchableInfo *II, StringRef OpName,
650 void buildAliasOperandReference(MatchableInfo *II, StringRef OpName,
651 MatchableInfo::AsmOperand &Op);
654 AsmMatcherInfo(Record *AsmParser,
655 CodeGenTarget &Target,
656 RecordKeeper &Records);
658 /// buildInfo - Construct the various tables used during matching.
661 /// buildOperandMatchInfo - Build the necessary information to handle user
662 /// defined operand parsing methods.
663 void buildOperandMatchInfo();
665 /// getSubtargetFeature - Lookup or create the subtarget feature info for the
667 SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const {
668 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
669 std::map<Record*, SubtargetFeatureInfo*, LessRecordByID>::const_iterator I =
670 SubtargetFeatures.find(Def);
671 return I == SubtargetFeatures.end() ? 0 : I->second;
674 RecordKeeper &getRecords() const {
679 } // End anonymous namespace
681 void MatchableInfo::dump() {
682 errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n";
684 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
685 AsmOperand &Op = AsmOperands[i];
686 errs() << " op[" << i << "] = " << Op.Class->ClassName << " - ";
687 errs() << '\"' << Op.Token << "\"\n";
691 static std::pair<StringRef, StringRef>
692 parseTwoOperandConstraint(StringRef S, ArrayRef<SMLoc> Loc) {
693 // Split via the '='.
694 std::pair<StringRef, StringRef> Ops = S.split('=');
695 if (Ops.second == "")
696 PrintFatalError(Loc, "missing '=' in two-operand alias constraint");
697 // Trim whitespace and the leading '$' on the operand names.
698 size_t start = Ops.first.find_first_of('$');
699 if (start == std::string::npos)
700 PrintFatalError(Loc, "expected '$' prefix on asm operand name");
701 Ops.first = Ops.first.slice(start + 1, std::string::npos);
702 size_t end = Ops.first.find_last_of(" \t");
703 Ops.first = Ops.first.slice(0, end);
704 // Now the second operand.
705 start = Ops.second.find_first_of('$');
706 if (start == std::string::npos)
707 PrintFatalError(Loc, "expected '$' prefix on asm operand name");
708 Ops.second = Ops.second.slice(start + 1, std::string::npos);
709 end = Ops.second.find_last_of(" \t");
710 Ops.first = Ops.first.slice(0, end);
714 void MatchableInfo::formTwoOperandAlias(StringRef Constraint) {
715 // Figure out which operands are aliased and mark them as tied.
716 std::pair<StringRef, StringRef> Ops =
717 parseTwoOperandConstraint(Constraint, TheDef->getLoc());
719 // Find the AsmOperands that refer to the operands we're aliasing.
720 int SrcAsmOperand = findAsmOperandNamed(Ops.first);
721 int DstAsmOperand = findAsmOperandNamed(Ops.second);
722 if (SrcAsmOperand == -1)
723 PrintFatalError(TheDef->getLoc(),
724 "unknown source two-operand alias operand '" +
725 Ops.first.str() + "'.");
726 if (DstAsmOperand == -1)
727 PrintFatalError(TheDef->getLoc(),
728 "unknown destination two-operand alias operand '" +
729 Ops.second.str() + "'.");
731 // Find the ResOperand that refers to the operand we're aliasing away
732 // and update it to refer to the combined operand instead.
733 for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) {
734 ResOperand &Op = ResOperands[i];
735 if (Op.Kind == ResOperand::RenderAsmOperand &&
736 Op.AsmOperandNum == (unsigned)SrcAsmOperand) {
737 Op.AsmOperandNum = DstAsmOperand;
741 // Remove the AsmOperand for the alias operand.
742 AsmOperands.erase(AsmOperands.begin() + SrcAsmOperand);
743 // Adjust the ResOperand references to any AsmOperands that followed
744 // the one we just deleted.
745 for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) {
746 ResOperand &Op = ResOperands[i];
749 // Nothing to do for operands that don't reference AsmOperands.
751 case ResOperand::RenderAsmOperand:
752 if (Op.AsmOperandNum > (unsigned)SrcAsmOperand)
755 case ResOperand::TiedOperand:
756 if (Op.TiedOperandNum > (unsigned)SrcAsmOperand)
763 void MatchableInfo::initialize(const AsmMatcherInfo &Info,
764 SmallPtrSet<Record*, 16> &SingletonRegisters,
765 int AsmVariantNo, std::string &RegisterPrefix) {
766 AsmVariantID = AsmVariantNo;
768 CodeGenInstruction::FlattenAsmStringVariants(AsmString, AsmVariantNo);
770 tokenizeAsmString(Info);
772 // Compute the require features.
773 std::vector<Record*> Predicates =TheDef->getValueAsListOfDefs("Predicates");
774 for (unsigned i = 0, e = Predicates.size(); i != e; ++i)
775 if (SubtargetFeatureInfo *Feature =
776 Info.getSubtargetFeature(Predicates[i]))
777 RequiredFeatures.push_back(Feature);
779 // Collect singleton registers, if used.
780 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
781 extractSingletonRegisterForAsmOperand(i, Info, RegisterPrefix);
782 if (Record *Reg = AsmOperands[i].SingletonReg)
783 SingletonRegisters.insert(Reg);
786 const RecordVal *DepMask = TheDef->getValue("DeprecatedFeatureMask");
788 DepMask = TheDef->getValue("ComplexDeprecationPredicate");
791 DepMask ? !DepMask->getValue()->getAsUnquotedString().empty() : false;
794 /// tokenizeAsmString - Tokenize a simplified assembly string.
795 void MatchableInfo::tokenizeAsmString(const AsmMatcherInfo &Info) {
796 StringRef String = AsmString;
799 for (unsigned i = 0, e = String.size(); i != e; ++i) {
809 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
812 if (!isspace(String[i]) && String[i] != ',')
813 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
819 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
823 assert(i != String.size() && "Invalid quoted character");
824 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
830 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
834 // If this isn't "${", treat like a normal token.
835 if (i + 1 == String.size() || String[i + 1] != '{') {
840 StringRef::iterator End = std::find(String.begin() + i, String.end(),'}');
841 assert(End != String.end() && "Missing brace in operand reference!");
842 size_t EndPos = End - String.begin();
843 AsmOperands.push_back(AsmOperand(String.slice(i, EndPos+1)));
850 if (!Info.AsmParser->getValueAsBit("MnemonicContainsDot")) {
852 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
862 if (InTok && Prev != String.size())
863 AsmOperands.push_back(AsmOperand(String.substr(Prev)));
865 // The first token of the instruction is the mnemonic, which must be a
866 // simple string, not a $foo variable or a singleton register.
867 if (AsmOperands.empty())
868 PrintFatalError(TheDef->getLoc(),
869 "Instruction '" + TheDef->getName() + "' has no tokens");
870 Mnemonic = AsmOperands[0].Token;
871 if (Mnemonic.empty())
872 PrintFatalError(TheDef->getLoc(),
873 "Missing instruction mnemonic");
874 // FIXME : Check and raise an error if it is a register.
875 if (Mnemonic[0] == '$')
876 PrintFatalError(TheDef->getLoc(),
877 "Invalid instruction mnemonic '" + Mnemonic.str() + "'!");
879 // Remove the first operand, it is tracked in the mnemonic field.
880 AsmOperands.erase(AsmOperands.begin());
883 bool MatchableInfo::validate(StringRef CommentDelimiter, bool Hack) const {
884 // Reject matchables with no .s string.
885 if (AsmString.empty())
886 PrintFatalError(TheDef->getLoc(), "instruction with empty asm string");
888 // Reject any matchables with a newline in them, they should be marked
889 // isCodeGenOnly if they are pseudo instructions.
890 if (AsmString.find('\n') != std::string::npos)
891 PrintFatalError(TheDef->getLoc(),
892 "multiline instruction is not valid for the asmparser, "
893 "mark it isCodeGenOnly");
895 // Remove comments from the asm string. We know that the asmstring only
897 if (!CommentDelimiter.empty() &&
898 StringRef(AsmString).find(CommentDelimiter) != StringRef::npos)
899 PrintFatalError(TheDef->getLoc(),
900 "asmstring for instruction has comment character in it, "
901 "mark it isCodeGenOnly");
903 // Reject matchables with operand modifiers, these aren't something we can
904 // handle, the target should be refactored to use operands instead of
907 // Also, check for instructions which reference the operand multiple times;
908 // this implies a constraint we would not honor.
909 std::set<std::string> OperandNames;
910 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
911 StringRef Tok = AsmOperands[i].Token;
912 if (Tok[0] == '$' && Tok.find(':') != StringRef::npos)
913 PrintFatalError(TheDef->getLoc(),
914 "matchable with operand modifier '" + Tok.str() +
915 "' not supported by asm matcher. Mark isCodeGenOnly!");
917 // Verify that any operand is only mentioned once.
918 // We reject aliases and ignore instructions for now.
919 if (Tok[0] == '$' && !OperandNames.insert(Tok).second) {
921 PrintFatalError(TheDef->getLoc(),
922 "ERROR: matchable with tied operand '" + Tok.str() +
923 "' can never be matched!");
924 // FIXME: Should reject these. The ARM backend hits this with $lane in a
925 // bunch of instructions. It is unclear what the right answer is.
927 errs() << "warning: '" << TheDef->getName() << "': "
928 << "ignoring instruction with tied operand '"
929 << Tok.str() << "'\n";
938 /// extractSingletonRegisterForAsmOperand - Extract singleton register,
939 /// if present, from specified token.
941 extractSingletonRegisterForAsmOperand(unsigned OperandNo,
942 const AsmMatcherInfo &Info,
943 std::string &RegisterPrefix) {
944 StringRef Tok = AsmOperands[OperandNo].Token;
945 if (RegisterPrefix.empty()) {
946 std::string LoweredTok = Tok.lower();
947 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(LoweredTok))
948 AsmOperands[OperandNo].SingletonReg = Reg->TheDef;
952 if (!Tok.startswith(RegisterPrefix))
955 StringRef RegName = Tok.substr(RegisterPrefix.size());
956 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName))
957 AsmOperands[OperandNo].SingletonReg = Reg->TheDef;
959 // If there is no register prefix (i.e. "%" in "%eax"), then this may
960 // be some random non-register token, just ignore it.
964 static std::string getEnumNameForToken(StringRef Str) {
967 for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) {
969 case '*': Res += "_STAR_"; break;
970 case '%': Res += "_PCT_"; break;
971 case ':': Res += "_COLON_"; break;
972 case '!': Res += "_EXCLAIM_"; break;
973 case '.': Res += "_DOT_"; break;
974 case '<': Res += "_LT_"; break;
975 case '>': Res += "_GT_"; break;
977 if ((*it >= 'A' && *it <= 'Z') ||
978 (*it >= 'a' && *it <= 'z') ||
979 (*it >= '0' && *it <= '9'))
982 Res += "_" + utostr((unsigned) *it) + "_";
989 ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) {
990 ClassInfo *&Entry = TokenClasses[Token];
993 Entry = new ClassInfo();
994 Entry->Kind = ClassInfo::Token;
995 Entry->ClassName = "Token";
996 Entry->Name = "MCK_" + getEnumNameForToken(Token);
997 Entry->ValueName = Token;
998 Entry->PredicateMethod = "<invalid>";
999 Entry->RenderMethod = "<invalid>";
1000 Entry->ParserMethod = "";
1001 Entry->DiagnosticType = "";
1002 Classes.push_back(Entry);
1009 AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI,
1011 Record *Rec = OI.Rec;
1013 Rec = cast<DefInit>(OI.MIOperandInfo->getArg(SubOpIdx))->getDef();
1014 return getOperandClass(Rec, SubOpIdx);
1018 AsmMatcherInfo::getOperandClass(Record *Rec, int SubOpIdx) {
1019 if (Rec->isSubClassOf("RegisterOperand")) {
1020 // RegisterOperand may have an associated ParserMatchClass. If it does,
1021 // use it, else just fall back to the underlying register class.
1022 const RecordVal *R = Rec->getValue("ParserMatchClass");
1023 if (R == 0 || R->getValue() == 0)
1024 PrintFatalError("Record `" + Rec->getName() +
1025 "' does not have a ParserMatchClass!\n");
1027 if (DefInit *DI= dyn_cast<DefInit>(R->getValue())) {
1028 Record *MatchClass = DI->getDef();
1029 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1033 // No custom match class. Just use the register class.
1034 Record *ClassRec = Rec->getValueAsDef("RegClass");
1036 PrintFatalError(Rec->getLoc(), "RegisterOperand `" + Rec->getName() +
1037 "' has no associated register class!\n");
1038 if (ClassInfo *CI = RegisterClassClasses[ClassRec])
1040 PrintFatalError(Rec->getLoc(), "register class has no class info!");
1044 if (Rec->isSubClassOf("RegisterClass")) {
1045 if (ClassInfo *CI = RegisterClassClasses[Rec])
1047 PrintFatalError(Rec->getLoc(), "register class has no class info!");
1050 if (!Rec->isSubClassOf("Operand"))
1051 PrintFatalError(Rec->getLoc(), "Operand `" + Rec->getName() +
1052 "' does not derive from class Operand!\n");
1053 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1054 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1057 PrintFatalError(Rec->getLoc(), "operand has no match class!");
1060 void AsmMatcherInfo::
1061 buildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters) {
1062 const std::vector<CodeGenRegister*> &Registers =
1063 Target.getRegBank().getRegisters();
1064 ArrayRef<CodeGenRegisterClass*> RegClassList =
1065 Target.getRegBank().getRegClasses();
1067 // The register sets used for matching.
1068 std::set< std::set<Record*> > RegisterSets;
1070 // Gather the defined sets.
1071 for (ArrayRef<CodeGenRegisterClass*>::const_iterator it =
1072 RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it)
1073 RegisterSets.insert(std::set<Record*>(
1074 (*it)->getOrder().begin(), (*it)->getOrder().end()));
1076 // Add any required singleton sets.
1077 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
1078 ie = SingletonRegisters.end(); it != ie; ++it) {
1080 RegisterSets.insert(std::set<Record*>(&Rec, &Rec + 1));
1083 // Introduce derived sets where necessary (when a register does not determine
1084 // a unique register set class), and build the mapping of registers to the set
1085 // they should classify to.
1086 std::map<Record*, std::set<Record*> > RegisterMap;
1087 for (std::vector<CodeGenRegister*>::const_iterator it = Registers.begin(),
1088 ie = Registers.end(); it != ie; ++it) {
1089 const CodeGenRegister &CGR = **it;
1090 // Compute the intersection of all sets containing this register.
1091 std::set<Record*> ContainingSet;
1093 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
1094 ie = RegisterSets.end(); it != ie; ++it) {
1095 if (!it->count(CGR.TheDef))
1098 if (ContainingSet.empty()) {
1099 ContainingSet = *it;
1103 std::set<Record*> Tmp;
1104 std::swap(Tmp, ContainingSet);
1105 std::insert_iterator< std::set<Record*> > II(ContainingSet,
1106 ContainingSet.begin());
1107 std::set_intersection(Tmp.begin(), Tmp.end(), it->begin(), it->end(), II);
1110 if (!ContainingSet.empty()) {
1111 RegisterSets.insert(ContainingSet);
1112 RegisterMap.insert(std::make_pair(CGR.TheDef, ContainingSet));
1116 // Construct the register classes.
1117 std::map<std::set<Record*>, ClassInfo*> RegisterSetClasses;
1119 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
1120 ie = RegisterSets.end(); it != ie; ++it, ++Index) {
1121 ClassInfo *CI = new ClassInfo();
1122 CI->Kind = ClassInfo::RegisterClass0 + Index;
1123 CI->ClassName = "Reg" + utostr(Index);
1124 CI->Name = "MCK_Reg" + utostr(Index);
1126 CI->PredicateMethod = ""; // unused
1127 CI->RenderMethod = "addRegOperands";
1128 CI->Registers = *it;
1129 // FIXME: diagnostic type.
1130 CI->DiagnosticType = "";
1131 Classes.push_back(CI);
1132 RegisterSetClasses.insert(std::make_pair(*it, CI));
1135 // Find the superclasses; we could compute only the subgroup lattice edges,
1136 // but there isn't really a point.
1137 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
1138 ie = RegisterSets.end(); it != ie; ++it) {
1139 ClassInfo *CI = RegisterSetClasses[*it];
1140 for (std::set< std::set<Record*> >::iterator it2 = RegisterSets.begin(),
1141 ie2 = RegisterSets.end(); it2 != ie2; ++it2)
1143 std::includes(it2->begin(), it2->end(), it->begin(), it->end()))
1144 CI->SuperClasses.push_back(RegisterSetClasses[*it2]);
1147 // Name the register classes which correspond to a user defined RegisterClass.
1148 for (ArrayRef<CodeGenRegisterClass*>::const_iterator
1149 it = RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it) {
1150 const CodeGenRegisterClass &RC = **it;
1151 // Def will be NULL for non-user defined register classes.
1152 Record *Def = RC.getDef();
1155 ClassInfo *CI = RegisterSetClasses[std::set<Record*>(RC.getOrder().begin(),
1156 RC.getOrder().end())];
1157 if (CI->ValueName.empty()) {
1158 CI->ClassName = RC.getName();
1159 CI->Name = "MCK_" + RC.getName();
1160 CI->ValueName = RC.getName();
1162 CI->ValueName = CI->ValueName + "," + RC.getName();
1164 RegisterClassClasses.insert(std::make_pair(Def, CI));
1167 // Populate the map for individual registers.
1168 for (std::map<Record*, std::set<Record*> >::iterator it = RegisterMap.begin(),
1169 ie = RegisterMap.end(); it != ie; ++it)
1170 RegisterClasses[it->first] = RegisterSetClasses[it->second];
1172 // Name the register classes which correspond to singleton registers.
1173 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
1174 ie = SingletonRegisters.end(); it != ie; ++it) {
1176 ClassInfo *CI = RegisterClasses[Rec];
1177 assert(CI && "Missing singleton register class info!");
1179 if (CI->ValueName.empty()) {
1180 CI->ClassName = Rec->getName();
1181 CI->Name = "MCK_" + Rec->getName();
1182 CI->ValueName = Rec->getName();
1184 CI->ValueName = CI->ValueName + "," + Rec->getName();
1188 void AsmMatcherInfo::buildOperandClasses() {
1189 std::vector<Record*> AsmOperands =
1190 Records.getAllDerivedDefinitions("AsmOperandClass");
1192 // Pre-populate AsmOperandClasses map.
1193 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
1194 ie = AsmOperands.end(); it != ie; ++it)
1195 AsmOperandClasses[*it] = new ClassInfo();
1198 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
1199 ie = AsmOperands.end(); it != ie; ++it, ++Index) {
1200 ClassInfo *CI = AsmOperandClasses[*it];
1201 CI->Kind = ClassInfo::UserClass0 + Index;
1203 ListInit *Supers = (*it)->getValueAsListInit("SuperClasses");
1204 for (unsigned i = 0, e = Supers->getSize(); i != e; ++i) {
1205 DefInit *DI = dyn_cast<DefInit>(Supers->getElement(i));
1207 PrintError((*it)->getLoc(), "Invalid super class reference!");
1211 ClassInfo *SC = AsmOperandClasses[DI->getDef()];
1213 PrintError((*it)->getLoc(), "Invalid super class reference!");
1215 CI->SuperClasses.push_back(SC);
1217 CI->ClassName = (*it)->getValueAsString("Name");
1218 CI->Name = "MCK_" + CI->ClassName;
1219 CI->ValueName = (*it)->getName();
1221 // Get or construct the predicate method name.
1222 Init *PMName = (*it)->getValueInit("PredicateMethod");
1223 if (StringInit *SI = dyn_cast<StringInit>(PMName)) {
1224 CI->PredicateMethod = SI->getValue();
1226 assert(isa<UnsetInit>(PMName) && "Unexpected PredicateMethod field!");
1227 CI->PredicateMethod = "is" + CI->ClassName;
1230 // Get or construct the render method name.
1231 Init *RMName = (*it)->getValueInit("RenderMethod");
1232 if (StringInit *SI = dyn_cast<StringInit>(RMName)) {
1233 CI->RenderMethod = SI->getValue();
1235 assert(isa<UnsetInit>(RMName) && "Unexpected RenderMethod field!");
1236 CI->RenderMethod = "add" + CI->ClassName + "Operands";
1239 // Get the parse method name or leave it as empty.
1240 Init *PRMName = (*it)->getValueInit("ParserMethod");
1241 if (StringInit *SI = dyn_cast<StringInit>(PRMName))
1242 CI->ParserMethod = SI->getValue();
1244 // Get the diagnostic type or leave it as empty.
1245 // Get the parse method name or leave it as empty.
1246 Init *DiagnosticType = (*it)->getValueInit("DiagnosticType");
1247 if (StringInit *SI = dyn_cast<StringInit>(DiagnosticType))
1248 CI->DiagnosticType = SI->getValue();
1250 AsmOperandClasses[*it] = CI;
1251 Classes.push_back(CI);
1255 AsmMatcherInfo::AsmMatcherInfo(Record *asmParser,
1256 CodeGenTarget &target,
1257 RecordKeeper &records)
1258 : Records(records), AsmParser(asmParser), Target(target) {
1261 /// buildOperandMatchInfo - Build the necessary information to handle user
1262 /// defined operand parsing methods.
1263 void AsmMatcherInfo::buildOperandMatchInfo() {
1265 /// Map containing a mask with all operands indices that can be found for
1266 /// that class inside a instruction.
1267 typedef std::map<ClassInfo*, unsigned, LessClassInfoPtr> OpClassMaskTy;
1268 OpClassMaskTy OpClassMask;
1270 for (std::vector<MatchableInfo*>::const_iterator it =
1271 Matchables.begin(), ie = Matchables.end();
1273 MatchableInfo &II = **it;
1274 OpClassMask.clear();
1276 // Keep track of all operands of this instructions which belong to the
1278 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) {
1279 MatchableInfo::AsmOperand &Op = II.AsmOperands[i];
1280 if (Op.Class->ParserMethod.empty())
1282 unsigned &OperandMask = OpClassMask[Op.Class];
1283 OperandMask |= (1 << i);
1286 // Generate operand match info for each mnemonic/operand class pair.
1287 for (OpClassMaskTy::iterator iit = OpClassMask.begin(),
1288 iie = OpClassMask.end(); iit != iie; ++iit) {
1289 unsigned OpMask = iit->second;
1290 ClassInfo *CI = iit->first;
1291 OperandMatchInfo.push_back(OperandMatchEntry::create(&II, CI, OpMask));
1296 void AsmMatcherInfo::buildInfo() {
1297 // Build information about all of the AssemblerPredicates.
1298 std::vector<Record*> AllPredicates =
1299 Records.getAllDerivedDefinitions("Predicate");
1300 for (unsigned i = 0, e = AllPredicates.size(); i != e; ++i) {
1301 Record *Pred = AllPredicates[i];
1302 // Ignore predicates that are not intended for the assembler.
1303 if (!Pred->getValueAsBit("AssemblerMatcherPredicate"))
1306 if (Pred->getName().empty())
1307 PrintFatalError(Pred->getLoc(), "Predicate has no name!");
1309 unsigned FeatureNo = SubtargetFeatures.size();
1310 SubtargetFeatures[Pred] = new SubtargetFeatureInfo(Pred, FeatureNo);
1311 assert(FeatureNo < 32 && "Too many subtarget features!");
1314 // Parse the instructions; we need to do this first so that we can gather the
1315 // singleton register classes.
1316 SmallPtrSet<Record*, 16> SingletonRegisters;
1317 unsigned VariantCount = Target.getAsmParserVariantCount();
1318 for (unsigned VC = 0; VC != VariantCount; ++VC) {
1319 Record *AsmVariant = Target.getAsmParserVariant(VC);
1320 std::string CommentDelimiter =
1321 AsmVariant->getValueAsString("CommentDelimiter");
1322 std::string RegisterPrefix = AsmVariant->getValueAsString("RegisterPrefix");
1323 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
1325 for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
1326 E = Target.inst_end(); I != E; ++I) {
1327 const CodeGenInstruction &CGI = **I;
1329 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1330 // filter the set of instructions we consider.
1331 if (!StringRef(CGI.TheDef->getName()).startswith(MatchPrefix))
1334 // Ignore "codegen only" instructions.
1335 if (CGI.TheDef->getValueAsBit("isCodeGenOnly"))
1338 OwningPtr<MatchableInfo> II(new MatchableInfo(CGI));
1340 II->initialize(*this, SingletonRegisters, AsmVariantNo, RegisterPrefix);
1342 // Ignore instructions which shouldn't be matched and diagnose invalid
1343 // instruction definitions with an error.
1344 if (!II->validate(CommentDelimiter, true))
1347 // Ignore "Int_*" and "*_Int" instructions, which are internal aliases.
1349 // FIXME: This is a total hack.
1350 if (StringRef(II->TheDef->getName()).startswith("Int_") ||
1351 StringRef(II->TheDef->getName()).endswith("_Int"))
1354 Matchables.push_back(II.take());
1357 // Parse all of the InstAlias definitions and stick them in the list of
1359 std::vector<Record*> AllInstAliases =
1360 Records.getAllDerivedDefinitions("InstAlias");
1361 for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) {
1362 CodeGenInstAlias *Alias = new CodeGenInstAlias(AllInstAliases[i], Target);
1364 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1365 // filter the set of instruction aliases we consider, based on the target
1367 if (!StringRef(Alias->ResultInst->TheDef->getName())
1368 .startswith( MatchPrefix))
1371 OwningPtr<MatchableInfo> II(new MatchableInfo(Alias));
1373 II->initialize(*this, SingletonRegisters, AsmVariantNo, RegisterPrefix);
1375 // Validate the alias definitions.
1376 II->validate(CommentDelimiter, false);
1378 Matchables.push_back(II.take());
1382 // Build info for the register classes.
1383 buildRegisterClasses(SingletonRegisters);
1385 // Build info for the user defined assembly operand classes.
1386 buildOperandClasses();
1388 // Build the information about matchables, now that we have fully formed
1390 std::vector<MatchableInfo*> NewMatchables;
1391 for (std::vector<MatchableInfo*>::iterator it = Matchables.begin(),
1392 ie = Matchables.end(); it != ie; ++it) {
1393 MatchableInfo *II = *it;
1395 // Parse the tokens after the mnemonic.
1396 // Note: buildInstructionOperandReference may insert new AsmOperands, so
1397 // don't precompute the loop bound.
1398 for (unsigned i = 0; i != II->AsmOperands.size(); ++i) {
1399 MatchableInfo::AsmOperand &Op = II->AsmOperands[i];
1400 StringRef Token = Op.Token;
1402 // Check for singleton registers.
1403 if (Record *RegRecord = II->AsmOperands[i].SingletonReg) {
1404 Op.Class = RegisterClasses[RegRecord];
1405 assert(Op.Class && Op.Class->Registers.size() == 1 &&
1406 "Unexpected class for singleton register");
1410 // Check for simple tokens.
1411 if (Token[0] != '$') {
1412 Op.Class = getTokenClass(Token);
1416 if (Token.size() > 1 && isdigit(Token[1])) {
1417 Op.Class = getTokenClass(Token);
1421 // Otherwise this is an operand reference.
1422 StringRef OperandName;
1423 if (Token[1] == '{')
1424 OperandName = Token.substr(2, Token.size() - 3);
1426 OperandName = Token.substr(1);
1428 if (II->DefRec.is<const CodeGenInstruction*>())
1429 buildInstructionOperandReference(II, OperandName, i);
1431 buildAliasOperandReference(II, OperandName, Op);
1434 if (II->DefRec.is<const CodeGenInstruction*>()) {
1435 II->buildInstructionResultOperands();
1436 // If the instruction has a two-operand alias, build up the
1437 // matchable here. We'll add them in bulk at the end to avoid
1438 // confusing this loop.
1439 std::string Constraint =
1440 II->TheDef->getValueAsString("TwoOperandAliasConstraint");
1441 if (Constraint != "") {
1442 // Start by making a copy of the original matchable.
1443 OwningPtr<MatchableInfo> AliasII(new MatchableInfo(*II));
1445 // Adjust it to be a two-operand alias.
1446 AliasII->formTwoOperandAlias(Constraint);
1448 // Add the alias to the matchables list.
1449 NewMatchables.push_back(AliasII.take());
1452 II->buildAliasResultOperands();
1454 if (!NewMatchables.empty())
1455 Matchables.insert(Matchables.end(), NewMatchables.begin(),
1456 NewMatchables.end());
1458 // Process token alias definitions and set up the associated superclass
1460 std::vector<Record*> AllTokenAliases =
1461 Records.getAllDerivedDefinitions("TokenAlias");
1462 for (unsigned i = 0, e = AllTokenAliases.size(); i != e; ++i) {
1463 Record *Rec = AllTokenAliases[i];
1464 ClassInfo *FromClass = getTokenClass(Rec->getValueAsString("FromToken"));
1465 ClassInfo *ToClass = getTokenClass(Rec->getValueAsString("ToToken"));
1466 if (FromClass == ToClass)
1467 PrintFatalError(Rec->getLoc(),
1468 "error: Destination value identical to source value.");
1469 FromClass->SuperClasses.push_back(ToClass);
1472 // Reorder classes so that classes precede super classes.
1473 std::sort(Classes.begin(), Classes.end(), less_ptr<ClassInfo>());
1476 /// buildInstructionOperandReference - The specified operand is a reference to a
1477 /// named operand such as $src. Resolve the Class and OperandInfo pointers.
1478 void AsmMatcherInfo::
1479 buildInstructionOperandReference(MatchableInfo *II,
1480 StringRef OperandName,
1481 unsigned AsmOpIdx) {
1482 const CodeGenInstruction &CGI = *II->DefRec.get<const CodeGenInstruction*>();
1483 const CGIOperandList &Operands = CGI.Operands;
1484 MatchableInfo::AsmOperand *Op = &II->AsmOperands[AsmOpIdx];
1486 // Map this token to an operand.
1488 if (!Operands.hasOperandNamed(OperandName, Idx))
1489 PrintFatalError(II->TheDef->getLoc(), "error: unable to find operand: '" +
1490 OperandName.str() + "'");
1492 // If the instruction operand has multiple suboperands, but the parser
1493 // match class for the asm operand is still the default "ImmAsmOperand",
1494 // then handle each suboperand separately.
1495 if (Op->SubOpIdx == -1 && Operands[Idx].MINumOperands > 1) {
1496 Record *Rec = Operands[Idx].Rec;
1497 assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
1498 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1499 if (MatchClass && MatchClass->getValueAsString("Name") == "Imm") {
1500 // Insert remaining suboperands after AsmOpIdx in II->AsmOperands.
1501 StringRef Token = Op->Token; // save this in case Op gets moved
1502 for (unsigned SI = 1, SE = Operands[Idx].MINumOperands; SI != SE; ++SI) {
1503 MatchableInfo::AsmOperand NewAsmOp(Token);
1504 NewAsmOp.SubOpIdx = SI;
1505 II->AsmOperands.insert(II->AsmOperands.begin()+AsmOpIdx+SI, NewAsmOp);
1507 // Replace Op with first suboperand.
1508 Op = &II->AsmOperands[AsmOpIdx]; // update the pointer in case it moved
1513 // Set up the operand class.
1514 Op->Class = getOperandClass(Operands[Idx], Op->SubOpIdx);
1516 // If the named operand is tied, canonicalize it to the untied operand.
1517 // For example, something like:
1518 // (outs GPR:$dst), (ins GPR:$src)
1519 // with an asmstring of
1521 // we want to canonicalize to:
1523 // so that we know how to provide the $dst operand when filling in the result.
1525 if (Operands[Idx].MINumOperands == 1)
1526 OITied = Operands[Idx].getTiedRegister();
1528 // The tied operand index is an MIOperand index, find the operand that
1530 std::pair<unsigned, unsigned> Idx = Operands.getSubOperandNumber(OITied);
1531 OperandName = Operands[Idx.first].Name;
1532 Op->SubOpIdx = Idx.second;
1535 Op->SrcOpName = OperandName;
1538 /// buildAliasOperandReference - When parsing an operand reference out of the
1539 /// matching string (e.g. "movsx $src, $dst"), determine what the class of the
1540 /// operand reference is by looking it up in the result pattern definition.
1541 void AsmMatcherInfo::buildAliasOperandReference(MatchableInfo *II,
1542 StringRef OperandName,
1543 MatchableInfo::AsmOperand &Op) {
1544 const CodeGenInstAlias &CGA = *II->DefRec.get<const CodeGenInstAlias*>();
1546 // Set up the operand class.
1547 for (unsigned i = 0, e = CGA.ResultOperands.size(); i != e; ++i)
1548 if (CGA.ResultOperands[i].isRecord() &&
1549 CGA.ResultOperands[i].getName() == OperandName) {
1550 // It's safe to go with the first one we find, because CodeGenInstAlias
1551 // validates that all operands with the same name have the same record.
1552 Op.SubOpIdx = CGA.ResultInstOperandIndex[i].second;
1553 // Use the match class from the Alias definition, not the
1554 // destination instruction, as we may have an immediate that's
1555 // being munged by the match class.
1556 Op.Class = getOperandClass(CGA.ResultOperands[i].getRecord(),
1558 Op.SrcOpName = OperandName;
1562 PrintFatalError(II->TheDef->getLoc(), "error: unable to find operand: '" +
1563 OperandName.str() + "'");
1566 void MatchableInfo::buildInstructionResultOperands() {
1567 const CodeGenInstruction *ResultInst = getResultInst();
1569 // Loop over all operands of the result instruction, determining how to
1571 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1572 const CGIOperandList::OperandInfo &OpInfo = ResultInst->Operands[i];
1574 // If this is a tied operand, just copy from the previously handled operand.
1576 if (OpInfo.MINumOperands == 1)
1577 TiedOp = OpInfo.getTiedRegister();
1579 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1583 // Find out what operand from the asmparser this MCInst operand comes from.
1584 int SrcOperand = findAsmOperandNamed(OpInfo.Name);
1585 if (OpInfo.Name.empty() || SrcOperand == -1) {
1586 // This may happen for operands that are tied to a suboperand of a
1587 // complex operand. Simply use a dummy value here; nobody should
1588 // use this operand slot.
1589 // FIXME: The long term goal is for the MCOperand list to not contain
1590 // tied operands at all.
1591 ResOperands.push_back(ResOperand::getImmOp(0));
1595 // Check if the one AsmOperand populates the entire operand.
1596 unsigned NumOperands = OpInfo.MINumOperands;
1597 if (AsmOperands[SrcOperand].SubOpIdx == -1) {
1598 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, NumOperands));
1602 // Add a separate ResOperand for each suboperand.
1603 for (unsigned AI = 0; AI < NumOperands; ++AI) {
1604 assert(AsmOperands[SrcOperand+AI].SubOpIdx == (int)AI &&
1605 AsmOperands[SrcOperand+AI].SrcOpName == OpInfo.Name &&
1606 "unexpected AsmOperands for suboperands");
1607 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand + AI, 1));
1612 void MatchableInfo::buildAliasResultOperands() {
1613 const CodeGenInstAlias &CGA = *DefRec.get<const CodeGenInstAlias*>();
1614 const CodeGenInstruction *ResultInst = getResultInst();
1616 // Loop over all operands of the result instruction, determining how to
1618 unsigned AliasOpNo = 0;
1619 unsigned LastOpNo = CGA.ResultInstOperandIndex.size();
1620 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1621 const CGIOperandList::OperandInfo *OpInfo = &ResultInst->Operands[i];
1623 // If this is a tied operand, just copy from the previously handled operand.
1625 if (OpInfo->MINumOperands == 1)
1626 TiedOp = OpInfo->getTiedRegister();
1628 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1632 // Handle all the suboperands for this operand.
1633 const std::string &OpName = OpInfo->Name;
1634 for ( ; AliasOpNo < LastOpNo &&
1635 CGA.ResultInstOperandIndex[AliasOpNo].first == i; ++AliasOpNo) {
1636 int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second;
1638 // Find out what operand from the asmparser that this MCInst operand
1640 switch (CGA.ResultOperands[AliasOpNo].Kind) {
1641 case CodeGenInstAlias::ResultOperand::K_Record: {
1642 StringRef Name = CGA.ResultOperands[AliasOpNo].getName();
1643 int SrcOperand = findAsmOperand(Name, SubIdx);
1644 if (SrcOperand == -1)
1645 PrintFatalError(TheDef->getLoc(), "Instruction '" +
1646 TheDef->getName() + "' has operand '" + OpName +
1647 "' that doesn't appear in asm string!");
1648 unsigned NumOperands = (SubIdx == -1 ? OpInfo->MINumOperands : 1);
1649 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand,
1653 case CodeGenInstAlias::ResultOperand::K_Imm: {
1654 int64_t ImmVal = CGA.ResultOperands[AliasOpNo].getImm();
1655 ResOperands.push_back(ResOperand::getImmOp(ImmVal));
1658 case CodeGenInstAlias::ResultOperand::K_Reg: {
1659 Record *Reg = CGA.ResultOperands[AliasOpNo].getRegister();
1660 ResOperands.push_back(ResOperand::getRegOp(Reg));
1668 static unsigned getConverterOperandID(const std::string &Name,
1669 SetVector<std::string> &Table,
1671 IsNew = Table.insert(Name);
1673 unsigned ID = IsNew ? Table.size() - 1 :
1674 std::find(Table.begin(), Table.end(), Name) - Table.begin();
1676 assert(ID < Table.size());
1682 static void emitConvertFuncs(CodeGenTarget &Target, StringRef ClassName,
1683 std::vector<MatchableInfo*> &Infos,
1685 SetVector<std::string> OperandConversionKinds;
1686 SetVector<std::string> InstructionConversionKinds;
1687 std::vector<std::vector<uint8_t> > ConversionTable;
1688 size_t MaxRowLength = 2; // minimum is custom converter plus terminator.
1690 // TargetOperandClass - This is the target's operand class, like X86Operand.
1691 std::string TargetOperandClass = Target.getName() + "Operand";
1693 // Write the convert function to a separate stream, so we can drop it after
1694 // the enum. We'll build up the conversion handlers for the individual
1695 // operand types opportunistically as we encounter them.
1696 std::string ConvertFnBody;
1697 raw_string_ostream CvtOS(ConvertFnBody);
1698 // Start the unified conversion function.
1699 CvtOS << "void " << Target.getName() << ClassName << "::\n"
1700 << "convertToMCInst(unsigned Kind, MCInst &Inst, "
1701 << "unsigned Opcode,\n"
1702 << " const SmallVectorImpl<MCParsedAsmOperand*"
1703 << "> &Operands) {\n"
1704 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
1705 << " const uint8_t *Converter = ConversionTable[Kind];\n"
1706 << " Inst.setOpcode(Opcode);\n"
1707 << " for (const uint8_t *p = Converter; *p; p+= 2) {\n"
1708 << " switch (*p) {\n"
1709 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
1710 << " case CVT_Reg:\n"
1711 << " static_cast<" << TargetOperandClass
1712 << "*>(Operands[*(p + 1)])->addRegOperands(Inst, 1);\n"
1714 << " case CVT_Tied:\n"
1715 << " Inst.addOperand(Inst.getOperand(*(p + 1)));\n"
1718 std::string OperandFnBody;
1719 raw_string_ostream OpOS(OperandFnBody);
1720 // Start the operand number lookup function.
1721 OpOS << "void " << Target.getName() << ClassName << "::\n"
1722 << "convertToMapAndConstraints(unsigned Kind,\n";
1724 OpOS << "const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {\n"
1725 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
1726 << " unsigned NumMCOperands = 0;\n"
1727 << " const uint8_t *Converter = ConversionTable[Kind];\n"
1728 << " for (const uint8_t *p = Converter; *p; p+= 2) {\n"
1729 << " switch (*p) {\n"
1730 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
1731 << " case CVT_Reg:\n"
1732 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1733 << " Operands[*(p + 1)]->setConstraint(\"r\");\n"
1734 << " ++NumMCOperands;\n"
1736 << " case CVT_Tied:\n"
1737 << " ++NumMCOperands;\n"
1740 // Pre-populate the operand conversion kinds with the standard always
1741 // available entries.
1742 OperandConversionKinds.insert("CVT_Done");
1743 OperandConversionKinds.insert("CVT_Reg");
1744 OperandConversionKinds.insert("CVT_Tied");
1745 enum { CVT_Done, CVT_Reg, CVT_Tied };
1747 for (std::vector<MatchableInfo*>::const_iterator it = Infos.begin(),
1748 ie = Infos.end(); it != ie; ++it) {
1749 MatchableInfo &II = **it;
1751 // Check if we have a custom match function.
1752 std::string AsmMatchConverter =
1753 II.getResultInst()->TheDef->getValueAsString("AsmMatchConverter");
1754 if (!AsmMatchConverter.empty()) {
1755 std::string Signature = "ConvertCustom_" + AsmMatchConverter;
1756 II.ConversionFnKind = Signature;
1758 // Check if we have already generated this signature.
1759 if (!InstructionConversionKinds.insert(Signature))
1762 // Remember this converter for the kind enum.
1763 unsigned KindID = OperandConversionKinds.size();
1764 OperandConversionKinds.insert("CVT_" +
1765 getEnumNameForToken(AsmMatchConverter));
1767 // Add the converter row for this instruction.
1768 ConversionTable.push_back(std::vector<uint8_t>());
1769 ConversionTable.back().push_back(KindID);
1770 ConversionTable.back().push_back(CVT_Done);
1772 // Add the handler to the conversion driver function.
1773 CvtOS << " case CVT_"
1774 << getEnumNameForToken(AsmMatchConverter) << ":\n"
1775 << " " << AsmMatchConverter << "(Inst, Operands);\n"
1778 // FIXME: Handle the operand number lookup for custom match functions.
1782 // Build the conversion function signature.
1783 std::string Signature = "Convert";
1785 std::vector<uint8_t> ConversionRow;
1787 // Compute the convert enum and the case body.
1788 MaxRowLength = std::max(MaxRowLength, II.ResOperands.size()*2 + 1 );
1790 for (unsigned i = 0, e = II.ResOperands.size(); i != e; ++i) {
1791 const MatchableInfo::ResOperand &OpInfo = II.ResOperands[i];
1793 // Generate code to populate each result operand.
1794 switch (OpInfo.Kind) {
1795 case MatchableInfo::ResOperand::RenderAsmOperand: {
1796 // This comes from something we parsed.
1797 MatchableInfo::AsmOperand &Op = II.AsmOperands[OpInfo.AsmOperandNum];
1799 // Registers are always converted the same, don't duplicate the
1800 // conversion function based on them.
1803 Class = Op.Class->isRegisterClass() ? "Reg" : Op.Class->ClassName;
1805 Signature += utostr(OpInfo.MINumOperands);
1806 Signature += "_" + itostr(OpInfo.AsmOperandNum);
1808 // Add the conversion kind, if necessary, and get the associated ID
1809 // the index of its entry in the vector).
1810 std::string Name = "CVT_" + (Op.Class->isRegisterClass() ? "Reg" :
1811 Op.Class->RenderMethod);
1812 Name = getEnumNameForToken(Name);
1814 bool IsNewConverter = false;
1815 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1818 // Add the operand entry to the instruction kind conversion row.
1819 ConversionRow.push_back(ID);
1820 ConversionRow.push_back(OpInfo.AsmOperandNum + 1);
1822 if (!IsNewConverter)
1825 // This is a new operand kind. Add a handler for it to the
1826 // converter driver.
1827 CvtOS << " case " << Name << ":\n"
1828 << " static_cast<" << TargetOperandClass
1829 << "*>(Operands[*(p + 1)])->"
1830 << Op.Class->RenderMethod << "(Inst, " << OpInfo.MINumOperands
1834 // Add a handler for the operand number lookup.
1835 OpOS << " case " << Name << ":\n"
1836 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n";
1838 if (Op.Class->isRegisterClass())
1839 OpOS << " Operands[*(p + 1)]->setConstraint(\"r\");\n";
1841 OpOS << " Operands[*(p + 1)]->setConstraint(\"m\");\n";
1842 OpOS << " NumMCOperands += " << OpInfo.MINumOperands << ";\n"
1846 case MatchableInfo::ResOperand::TiedOperand: {
1847 // If this operand is tied to a previous one, just copy the MCInst
1848 // operand from the earlier one.We can only tie single MCOperand values.
1849 assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand");
1850 unsigned TiedOp = OpInfo.TiedOperandNum;
1851 assert(i > TiedOp && "Tied operand precedes its target!");
1852 Signature += "__Tie" + utostr(TiedOp);
1853 ConversionRow.push_back(CVT_Tied);
1854 ConversionRow.push_back(TiedOp);
1857 case MatchableInfo::ResOperand::ImmOperand: {
1858 int64_t Val = OpInfo.ImmVal;
1859 std::string Ty = "imm_" + itostr(Val);
1860 Signature += "__" + Ty;
1862 std::string Name = "CVT_" + Ty;
1863 bool IsNewConverter = false;
1864 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1866 // Add the operand entry to the instruction kind conversion row.
1867 ConversionRow.push_back(ID);
1868 ConversionRow.push_back(0);
1870 if (!IsNewConverter)
1873 CvtOS << " case " << Name << ":\n"
1874 << " Inst.addOperand(MCOperand::CreateImm(" << Val << "));\n"
1877 OpOS << " case " << Name << ":\n"
1878 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1879 << " Operands[*(p + 1)]->setConstraint(\"\");\n"
1880 << " ++NumMCOperands;\n"
1884 case MatchableInfo::ResOperand::RegOperand: {
1885 std::string Reg, Name;
1886 if (OpInfo.Register == 0) {
1890 Reg = getQualifiedName(OpInfo.Register);
1891 Name = "reg" + OpInfo.Register->getName();
1893 Signature += "__" + Name;
1894 Name = "CVT_" + Name;
1895 bool IsNewConverter = false;
1896 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1898 // Add the operand entry to the instruction kind conversion row.
1899 ConversionRow.push_back(ID);
1900 ConversionRow.push_back(0);
1902 if (!IsNewConverter)
1904 CvtOS << " case " << Name << ":\n"
1905 << " Inst.addOperand(MCOperand::CreateReg(" << Reg << "));\n"
1908 OpOS << " case " << Name << ":\n"
1909 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1910 << " Operands[*(p + 1)]->setConstraint(\"m\");\n"
1911 << " ++NumMCOperands;\n"
1917 // If there were no operands, add to the signature to that effect
1918 if (Signature == "Convert")
1919 Signature += "_NoOperands";
1921 II.ConversionFnKind = Signature;
1923 // Save the signature. If we already have it, don't add a new row
1925 if (!InstructionConversionKinds.insert(Signature))
1928 // Add the row to the table.
1929 ConversionTable.push_back(ConversionRow);
1932 // Finish up the converter driver function.
1933 CvtOS << " }\n }\n}\n\n";
1935 // Finish up the operand number lookup function.
1936 OpOS << " }\n }\n}\n\n";
1938 OS << "namespace {\n";
1940 // Output the operand conversion kind enum.
1941 OS << "enum OperatorConversionKind {\n";
1942 for (unsigned i = 0, e = OperandConversionKinds.size(); i != e; ++i)
1943 OS << " " << OperandConversionKinds[i] << ",\n";
1944 OS << " CVT_NUM_CONVERTERS\n";
1947 // Output the instruction conversion kind enum.
1948 OS << "enum InstructionConversionKind {\n";
1949 for (SetVector<std::string>::const_iterator
1950 i = InstructionConversionKinds.begin(),
1951 e = InstructionConversionKinds.end(); i != e; ++i)
1952 OS << " " << *i << ",\n";
1953 OS << " CVT_NUM_SIGNATURES\n";
1957 OS << "} // end anonymous namespace\n\n";
1959 // Output the conversion table.
1960 OS << "static const uint8_t ConversionTable[CVT_NUM_SIGNATURES]["
1961 << MaxRowLength << "] = {\n";
1963 for (unsigned Row = 0, ERow = ConversionTable.size(); Row != ERow; ++Row) {
1964 assert(ConversionTable[Row].size() % 2 == 0 && "bad conversion row!");
1965 OS << " // " << InstructionConversionKinds[Row] << "\n";
1967 for (unsigned i = 0, e = ConversionTable[Row].size(); i != e; i += 2)
1968 OS << OperandConversionKinds[ConversionTable[Row][i]] << ", "
1969 << (unsigned)(ConversionTable[Row][i + 1]) << ", ";
1970 OS << "CVT_Done },\n";
1975 // Spit out the conversion driver function.
1978 // Spit out the operand number lookup function.
1982 /// emitMatchClassEnumeration - Emit the enumeration for match class kinds.
1983 static void emitMatchClassEnumeration(CodeGenTarget &Target,
1984 std::vector<ClassInfo*> &Infos,
1986 OS << "namespace {\n\n";
1988 OS << "/// MatchClassKind - The kinds of classes which participate in\n"
1989 << "/// instruction matching.\n";
1990 OS << "enum MatchClassKind {\n";
1991 OS << " InvalidMatchClass = 0,\n";
1992 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1993 ie = Infos.end(); it != ie; ++it) {
1994 ClassInfo &CI = **it;
1995 OS << " " << CI.Name << ", // ";
1996 if (CI.Kind == ClassInfo::Token) {
1997 OS << "'" << CI.ValueName << "'\n";
1998 } else if (CI.isRegisterClass()) {
1999 if (!CI.ValueName.empty())
2000 OS << "register class '" << CI.ValueName << "'\n";
2002 OS << "derived register class\n";
2004 OS << "user defined class '" << CI.ValueName << "'\n";
2007 OS << " NumMatchClassKinds\n";
2013 /// emitValidateOperandClass - Emit the function to validate an operand class.
2014 static void emitValidateOperandClass(AsmMatcherInfo &Info,
2016 OS << "static unsigned validateOperandClass(MCParsedAsmOperand *GOp, "
2017 << "MatchClassKind Kind) {\n";
2018 OS << " " << Info.Target.getName() << "Operand &Operand = *("
2019 << Info.Target.getName() << "Operand*)GOp;\n";
2021 // The InvalidMatchClass is not to match any operand.
2022 OS << " if (Kind == InvalidMatchClass)\n";
2023 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n\n";
2025 // Check for Token operands first.
2026 // FIXME: Use a more specific diagnostic type.
2027 OS << " if (Operand.isToken())\n";
2028 OS << " return isSubclass(matchTokenString(Operand.getToken()), Kind) ?\n"
2029 << " MCTargetAsmParser::Match_Success :\n"
2030 << " MCTargetAsmParser::Match_InvalidOperand;\n\n";
2032 // Check the user classes. We don't care what order since we're only
2033 // actually matching against one of them.
2034 for (std::vector<ClassInfo*>::iterator it = Info.Classes.begin(),
2035 ie = Info.Classes.end(); it != ie; ++it) {
2036 ClassInfo &CI = **it;
2038 if (!CI.isUserClass())
2041 OS << " // '" << CI.ClassName << "' class\n";
2042 OS << " if (Kind == " << CI.Name << ") {\n";
2043 OS << " if (Operand." << CI.PredicateMethod << "())\n";
2044 OS << " return MCTargetAsmParser::Match_Success;\n";
2045 if (!CI.DiagnosticType.empty())
2046 OS << " return " << Info.Target.getName() << "AsmParser::Match_"
2047 << CI.DiagnosticType << ";\n";
2051 // Check for register operands, including sub-classes.
2052 OS << " if (Operand.isReg()) {\n";
2053 OS << " MatchClassKind OpKind;\n";
2054 OS << " switch (Operand.getReg()) {\n";
2055 OS << " default: OpKind = InvalidMatchClass; break;\n";
2056 for (AsmMatcherInfo::RegisterClassesTy::iterator
2057 it = Info.RegisterClasses.begin(), ie = Info.RegisterClasses.end();
2059 OS << " case " << Info.Target.getName() << "::"
2060 << it->first->getName() << ": OpKind = " << it->second->Name
2063 OS << " return isSubclass(OpKind, Kind) ? "
2064 << "MCTargetAsmParser::Match_Success :\n "
2065 << " MCTargetAsmParser::Match_InvalidOperand;\n }\n\n";
2067 // Generic fallthrough match failure case for operands that don't have
2068 // specialized diagnostic types.
2069 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n";
2073 /// emitIsSubclass - Emit the subclass predicate function.
2074 static void emitIsSubclass(CodeGenTarget &Target,
2075 std::vector<ClassInfo*> &Infos,
2077 OS << "/// isSubclass - Compute whether \\p A is a subclass of \\p B.\n";
2078 OS << "static bool isSubclass(MatchClassKind A, MatchClassKind B) {\n";
2079 OS << " if (A == B)\n";
2080 OS << " return true;\n\n";
2083 raw_string_ostream SS(OStr);
2085 SS << " switch (A) {\n";
2086 SS << " default:\n";
2087 SS << " return false;\n";
2088 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
2089 ie = Infos.end(); it != ie; ++it) {
2090 ClassInfo &A = **it;
2092 std::vector<StringRef> SuperClasses;
2093 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
2094 ie = Infos.end(); it != ie; ++it) {
2095 ClassInfo &B = **it;
2097 if (&A != &B && A.isSubsetOf(B))
2098 SuperClasses.push_back(B.Name);
2101 if (SuperClasses.empty())
2105 SS << "\n case " << A.Name << ":\n";
2107 if (SuperClasses.size() == 1) {
2108 SS << " return B == " << SuperClasses.back().str() << ";\n";
2112 if (!SuperClasses.empty()) {
2113 SS << " switch (B) {\n";
2114 SS << " default: return false;\n";
2115 for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i)
2116 SS << " case " << SuperClasses[i].str() << ": return true;\n";
2119 // No case statement to emit
2120 SS << " return false;\n";
2125 // If there were case statements emitted into the string stream, write them
2126 // to the output stream, otherwise write the default.
2130 OS << " return false;\n";
2135 /// emitMatchTokenString - Emit the function to match a token string to the
2136 /// appropriate match class value.
2137 static void emitMatchTokenString(CodeGenTarget &Target,
2138 std::vector<ClassInfo*> &Infos,
2140 // Construct the match list.
2141 std::vector<StringMatcher::StringPair> Matches;
2142 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
2143 ie = Infos.end(); it != ie; ++it) {
2144 ClassInfo &CI = **it;
2146 if (CI.Kind == ClassInfo::Token)
2147 Matches.push_back(StringMatcher::StringPair(CI.ValueName,
2148 "return " + CI.Name + ";"));
2151 OS << "static MatchClassKind matchTokenString(StringRef Name) {\n";
2153 StringMatcher("Name", Matches, OS).Emit();
2155 OS << " return InvalidMatchClass;\n";
2159 /// emitMatchRegisterName - Emit the function to match a string to the target
2160 /// specific register enum.
2161 static void emitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
2163 // Construct the match list.
2164 std::vector<StringMatcher::StringPair> Matches;
2165 const std::vector<CodeGenRegister*> &Regs =
2166 Target.getRegBank().getRegisters();
2167 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
2168 const CodeGenRegister *Reg = Regs[i];
2169 if (Reg->TheDef->getValueAsString("AsmName").empty())
2172 Matches.push_back(StringMatcher::StringPair(
2173 Reg->TheDef->getValueAsString("AsmName"),
2174 "return " + utostr(Reg->EnumValue) + ";"));
2177 OS << "static unsigned MatchRegisterName(StringRef Name) {\n";
2179 StringMatcher("Name", Matches, OS).Emit();
2181 OS << " return 0;\n";
2185 /// emitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag
2187 static void emitSubtargetFeatureFlagEnumeration(AsmMatcherInfo &Info,
2189 OS << "// Flags for subtarget features that participate in "
2190 << "instruction matching.\n";
2191 OS << "enum SubtargetFeatureFlag {\n";
2192 for (std::map<Record*, SubtargetFeatureInfo*, LessRecordByID>::const_iterator
2193 it = Info.SubtargetFeatures.begin(),
2194 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
2195 SubtargetFeatureInfo &SFI = *it->second;
2196 OS << " " << SFI.getEnumName() << " = (1 << " << SFI.Index << "),\n";
2198 OS << " Feature_None = 0\n";
2202 /// emitOperandDiagnosticTypes - Emit the operand matching diagnostic types.
2203 static void emitOperandDiagnosticTypes(AsmMatcherInfo &Info, raw_ostream &OS) {
2204 // Get the set of diagnostic types from all of the operand classes.
2205 std::set<StringRef> Types;
2206 for (std::map<Record*, ClassInfo*>::const_iterator
2207 I = Info.AsmOperandClasses.begin(),
2208 E = Info.AsmOperandClasses.end(); I != E; ++I) {
2209 if (!I->second->DiagnosticType.empty())
2210 Types.insert(I->second->DiagnosticType);
2213 if (Types.empty()) return;
2215 // Now emit the enum entries.
2216 for (std::set<StringRef>::const_iterator I = Types.begin(), E = Types.end();
2218 OS << " Match_" << *I << ",\n";
2219 OS << " END_OPERAND_DIAGNOSTIC_TYPES\n";
2222 /// emitGetSubtargetFeatureName - Emit the helper function to get the
2223 /// user-level name for a subtarget feature.
2224 static void emitGetSubtargetFeatureName(AsmMatcherInfo &Info, raw_ostream &OS) {
2225 OS << "// User-level names for subtarget features that participate in\n"
2226 << "// instruction matching.\n"
2227 << "static const char *getSubtargetFeatureName(unsigned Val) {\n";
2228 if (!Info.SubtargetFeatures.empty()) {
2229 OS << " switch(Val) {\n";
2230 typedef std::map<Record*, SubtargetFeatureInfo*, LessRecordByID> RecFeatMap;
2231 for (RecFeatMap::const_iterator it = Info.SubtargetFeatures.begin(),
2232 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
2233 SubtargetFeatureInfo &SFI = *it->second;
2234 // FIXME: Totally just a placeholder name to get the algorithm working.
2235 OS << " case " << SFI.getEnumName() << ": return \""
2236 << SFI.TheDef->getValueAsString("PredicateName") << "\";\n";
2238 OS << " default: return \"(unknown)\";\n";
2241 // Nothing to emit, so skip the switch
2242 OS << " return \"(unknown)\";\n";
2247 /// emitComputeAvailableFeatures - Emit the function to compute the list of
2248 /// available features given a subtarget.
2249 static void emitComputeAvailableFeatures(AsmMatcherInfo &Info,
2251 std::string ClassName =
2252 Info.AsmParser->getValueAsString("AsmParserClassName");
2254 OS << "unsigned " << Info.Target.getName() << ClassName << "::\n"
2255 << "ComputeAvailableFeatures(uint64_t FB) const {\n";
2256 OS << " unsigned Features = 0;\n";
2257 for (std::map<Record*, SubtargetFeatureInfo*, LessRecordByID>::const_iterator
2258 it = Info.SubtargetFeatures.begin(),
2259 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
2260 SubtargetFeatureInfo &SFI = *it->second;
2263 std::string CondStorage =
2264 SFI.TheDef->getValueAsString("AssemblerCondString");
2265 StringRef Conds = CondStorage;
2266 std::pair<StringRef,StringRef> Comma = Conds.split(',');
2273 StringRef Cond = Comma.first;
2274 if (Cond[0] == '!') {
2276 Cond = Cond.substr(1);
2279 OS << "((FB & " << Info.Target.getName() << "::" << Cond << ")";
2286 if (Comma.second.empty())
2290 Comma = Comma.second.split(',');
2294 OS << " Features |= " << SFI.getEnumName() << ";\n";
2296 OS << " return Features;\n";
2300 static std::string GetAliasRequiredFeatures(Record *R,
2301 const AsmMatcherInfo &Info) {
2302 std::vector<Record*> ReqFeatures = R->getValueAsListOfDefs("Predicates");
2304 unsigned NumFeatures = 0;
2305 for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) {
2306 SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]);
2309 PrintFatalError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() +
2310 "' is not marked as an AssemblerPredicate!");
2315 Result += F->getEnumName();
2319 if (NumFeatures > 1)
2320 Result = '(' + Result + ')';
2324 static void emitMnemonicAliasVariant(raw_ostream &OS,const AsmMatcherInfo &Info,
2325 std::vector<Record*> &Aliases,
2326 unsigned Indent = 0,
2327 StringRef AsmParserVariantName = StringRef()){
2328 // Keep track of all the aliases from a mnemonic. Use an std::map so that the
2329 // iteration order of the map is stable.
2330 std::map<std::string, std::vector<Record*> > AliasesFromMnemonic;
2332 for (unsigned i = 0, e = Aliases.size(); i != e; ++i) {
2333 Record *R = Aliases[i];
2334 // FIXME: Allow AssemblerVariantName to be a comma separated list.
2335 std::string AsmVariantName = R->getValueAsString("AsmVariantName");
2336 if (AsmVariantName != AsmParserVariantName)
2338 AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R);
2340 if (AliasesFromMnemonic.empty())
2343 // Process each alias a "from" mnemonic at a time, building the code executed
2344 // by the string remapper.
2345 std::vector<StringMatcher::StringPair> Cases;
2346 for (std::map<std::string, std::vector<Record*> >::iterator
2347 I = AliasesFromMnemonic.begin(), E = AliasesFromMnemonic.end();
2349 const std::vector<Record*> &ToVec = I->second;
2351 // Loop through each alias and emit code that handles each case. If there
2352 // are two instructions without predicates, emit an error. If there is one,
2354 std::string MatchCode;
2355 int AliasWithNoPredicate = -1;
2357 for (unsigned i = 0, e = ToVec.size(); i != e; ++i) {
2358 Record *R = ToVec[i];
2359 std::string FeatureMask = GetAliasRequiredFeatures(R, Info);
2361 // If this unconditionally matches, remember it for later and diagnose
2363 if (FeatureMask.empty()) {
2364 if (AliasWithNoPredicate != -1) {
2365 // We can't have two aliases from the same mnemonic with no predicate.
2366 PrintError(ToVec[AliasWithNoPredicate]->getLoc(),
2367 "two MnemonicAliases with the same 'from' mnemonic!");
2368 PrintFatalError(R->getLoc(), "this is the other MnemonicAlias.");
2371 AliasWithNoPredicate = i;
2374 if (R->getValueAsString("ToMnemonic") == I->first)
2375 PrintFatalError(R->getLoc(), "MnemonicAlias to the same string");
2377 if (!MatchCode.empty())
2378 MatchCode += "else ";
2379 MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n";
2380 MatchCode += " Mnemonic = \"" +R->getValueAsString("ToMnemonic")+"\";\n";
2383 if (AliasWithNoPredicate != -1) {
2384 Record *R = ToVec[AliasWithNoPredicate];
2385 if (!MatchCode.empty())
2386 MatchCode += "else\n ";
2387 MatchCode += "Mnemonic = \"" + R->getValueAsString("ToMnemonic")+"\";\n";
2390 MatchCode += "return;";
2392 Cases.push_back(std::make_pair(I->first, MatchCode));
2394 StringMatcher("Mnemonic", Cases, OS).Emit(Indent);
2397 /// emitMnemonicAliases - If the target has any MnemonicAlias<> definitions,
2398 /// emit a function for them and return true, otherwise return false.
2399 static bool emitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info,
2400 CodeGenTarget &Target) {
2401 // Ignore aliases when match-prefix is set.
2402 if (!MatchPrefix.empty())
2405 std::vector<Record*> Aliases =
2406 Info.getRecords().getAllDerivedDefinitions("MnemonicAlias");
2407 if (Aliases.empty()) return false;
2409 OS << "static void applyMnemonicAliases(StringRef &Mnemonic, "
2410 "unsigned Features, unsigned VariantID) {\n";
2411 OS << " switch (VariantID) {\n";
2412 unsigned VariantCount = Target.getAsmParserVariantCount();
2413 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2414 Record *AsmVariant = Target.getAsmParserVariant(VC);
2415 int AsmParserVariantNo = AsmVariant->getValueAsInt("Variant");
2416 std::string AsmParserVariantName = AsmVariant->getValueAsString("Name");
2417 OS << " case " << AsmParserVariantNo << ":\n";
2418 emitMnemonicAliasVariant(OS, Info, Aliases, /*Indent=*/2,
2419 AsmParserVariantName);
2424 // Emit aliases that apply to all variants.
2425 emitMnemonicAliasVariant(OS, Info, Aliases);
2432 static const char *getMinimalTypeForRange(uint64_t Range) {
2433 assert(Range < 0xFFFFFFFFULL && "Enum too large");
2441 static void emitCustomOperandParsing(raw_ostream &OS, CodeGenTarget &Target,
2442 const AsmMatcherInfo &Info, StringRef ClassName,
2443 StringToOffsetTable &StringTable,
2444 unsigned MaxMnemonicIndex) {
2445 unsigned MaxMask = 0;
2446 for (std::vector<OperandMatchEntry>::const_iterator it =
2447 Info.OperandMatchInfo.begin(), ie = Info.OperandMatchInfo.end();
2449 MaxMask |= it->OperandMask;
2452 // Emit the static custom operand parsing table;
2453 OS << "namespace {\n";
2454 OS << " struct OperandMatchEntry {\n";
2455 OS << " " << getMinimalTypeForRange(1ULL << Info.SubtargetFeatures.size())
2456 << " RequiredFeatures;\n";
2457 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex)
2459 OS << " " << getMinimalTypeForRange(Info.Classes.size())
2461 OS << " " << getMinimalTypeForRange(MaxMask)
2462 << " OperandMask;\n\n";
2463 OS << " StringRef getMnemonic() const {\n";
2464 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2465 OS << " MnemonicTable[Mnemonic]);\n";
2469 OS << " // Predicate for searching for an opcode.\n";
2470 OS << " struct LessOpcodeOperand {\n";
2471 OS << " bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {\n";
2472 OS << " return LHS.getMnemonic() < RHS;\n";
2474 OS << " bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {\n";
2475 OS << " return LHS < RHS.getMnemonic();\n";
2477 OS << " bool operator()(const OperandMatchEntry &LHS,";
2478 OS << " const OperandMatchEntry &RHS) {\n";
2479 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2483 OS << "} // end anonymous namespace.\n\n";
2485 OS << "static const OperandMatchEntry OperandMatchTable["
2486 << Info.OperandMatchInfo.size() << "] = {\n";
2488 OS << " /* Operand List Mask, Mnemonic, Operand Class, Features */\n";
2489 for (std::vector<OperandMatchEntry>::const_iterator it =
2490 Info.OperandMatchInfo.begin(), ie = Info.OperandMatchInfo.end();
2492 const OperandMatchEntry &OMI = *it;
2493 const MatchableInfo &II = *OMI.MI;
2497 // Write the required features mask.
2498 if (!II.RequiredFeatures.empty()) {
2499 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
2501 OS << II.RequiredFeatures[i]->getEnumName();
2506 // Store a pascal-style length byte in the mnemonic.
2507 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2508 OS << ", " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2509 << " /* " << II.Mnemonic << " */, ";
2513 OS << ", " << OMI.OperandMask;
2515 bool printComma = false;
2516 for (int i = 0, e = 31; i !=e; ++i)
2517 if (OMI.OperandMask & (1 << i)) {
2529 // Emit the operand class switch to call the correct custom parser for
2530 // the found operand class.
2531 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
2532 << Target.getName() << ClassName << "::\n"
2533 << "tryCustomParseOperand(SmallVectorImpl<MCParsedAsmOperand*>"
2534 << " &Operands,\n unsigned MCK) {\n\n"
2535 << " switch(MCK) {\n";
2537 for (std::vector<ClassInfo*>::const_iterator it = Info.Classes.begin(),
2538 ie = Info.Classes.end(); it != ie; ++it) {
2539 ClassInfo *CI = *it;
2540 if (CI->ParserMethod.empty())
2542 OS << " case " << CI->Name << ":\n"
2543 << " return " << CI->ParserMethod << "(Operands);\n";
2546 OS << " default:\n";
2547 OS << " return MatchOperand_NoMatch;\n";
2549 OS << " return MatchOperand_NoMatch;\n";
2552 // Emit the static custom operand parser. This code is very similar with
2553 // the other matcher. Also use MatchResultTy here just in case we go for
2554 // a better error handling.
2555 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
2556 << Target.getName() << ClassName << "::\n"
2557 << "MatchOperandParserImpl(SmallVectorImpl<MCParsedAsmOperand*>"
2558 << " &Operands,\n StringRef Mnemonic) {\n";
2560 // Emit code to get the available features.
2561 OS << " // Get the current feature set.\n";
2562 OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n";
2564 OS << " // Get the next operand index.\n";
2565 OS << " unsigned NextOpNum = Operands.size()-1;\n";
2567 // Emit code to search the table.
2568 OS << " // Search the table.\n";
2569 OS << " std::pair<const OperandMatchEntry*, const OperandMatchEntry*>";
2570 OS << " MnemonicRange =\n";
2571 OS << " std::equal_range(OperandMatchTable, OperandMatchTable+"
2572 << Info.OperandMatchInfo.size() << ", Mnemonic,\n"
2573 << " LessOpcodeOperand());\n\n";
2575 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2576 OS << " return MatchOperand_NoMatch;\n\n";
2578 OS << " for (const OperandMatchEntry *it = MnemonicRange.first,\n"
2579 << " *ie = MnemonicRange.second; it != ie; ++it) {\n";
2581 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2582 OS << " assert(Mnemonic == it->getMnemonic());\n\n";
2584 // Emit check that the required features are available.
2585 OS << " // check if the available features match\n";
2586 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2587 << "!= it->RequiredFeatures) {\n";
2588 OS << " continue;\n";
2591 // Emit check to ensure the operand number matches.
2592 OS << " // check if the operand in question has a custom parser.\n";
2593 OS << " if (!(it->OperandMask & (1 << NextOpNum)))\n";
2594 OS << " continue;\n\n";
2596 // Emit call to the custom parser method
2597 OS << " // call custom parse method to handle the operand\n";
2598 OS << " OperandMatchResultTy Result = ";
2599 OS << "tryCustomParseOperand(Operands, it->Class);\n";
2600 OS << " if (Result != MatchOperand_NoMatch)\n";
2601 OS << " return Result;\n";
2604 OS << " // Okay, we had no match.\n";
2605 OS << " return MatchOperand_NoMatch;\n";
2609 void AsmMatcherEmitter::run(raw_ostream &OS) {
2610 CodeGenTarget Target(Records);
2611 Record *AsmParser = Target.getAsmParser();
2612 std::string ClassName = AsmParser->getValueAsString("AsmParserClassName");
2614 // Compute the information on the instructions to match.
2615 AsmMatcherInfo Info(AsmParser, Target, Records);
2618 // Sort the instruction table using the partial order on classes. We use
2619 // stable_sort to ensure that ambiguous instructions are still
2620 // deterministically ordered.
2621 std::stable_sort(Info.Matchables.begin(), Info.Matchables.end(),
2622 less_ptr<MatchableInfo>());
2624 DEBUG_WITH_TYPE("instruction_info", {
2625 for (std::vector<MatchableInfo*>::iterator
2626 it = Info.Matchables.begin(), ie = Info.Matchables.end();
2631 // Check for ambiguous matchables.
2632 DEBUG_WITH_TYPE("ambiguous_instrs", {
2633 unsigned NumAmbiguous = 0;
2634 for (unsigned i = 0, e = Info.Matchables.size(); i != e; ++i) {
2635 for (unsigned j = i + 1; j != e; ++j) {
2636 MatchableInfo &A = *Info.Matchables[i];
2637 MatchableInfo &B = *Info.Matchables[j];
2639 if (A.couldMatchAmbiguouslyWith(B)) {
2640 errs() << "warning: ambiguous matchables:\n";
2642 errs() << "\nis incomparable with:\n";
2650 errs() << "warning: " << NumAmbiguous
2651 << " ambiguous matchables!\n";
2654 // Compute the information on the custom operand parsing.
2655 Info.buildOperandMatchInfo();
2657 // Write the output.
2659 // Information for the class declaration.
2660 OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
2661 OS << "#undef GET_ASSEMBLER_HEADER\n";
2662 OS << " // This should be included into the middle of the declaration of\n";
2663 OS << " // your subclasses implementation of MCTargetAsmParser.\n";
2664 OS << " unsigned ComputeAvailableFeatures(uint64_t FeatureBits) const;\n";
2665 OS << " void convertToMCInst(unsigned Kind, MCInst &Inst, "
2666 << "unsigned Opcode,\n"
2667 << " const SmallVectorImpl<MCParsedAsmOperand*> "
2669 OS << " void convertToMapAndConstraints(unsigned Kind,\n ";
2670 OS << " const SmallVectorImpl<MCParsedAsmOperand*> &Operands);\n";
2671 OS << " bool mnemonicIsValid(StringRef Mnemonic, unsigned VariantID);\n";
2672 OS << " unsigned MatchInstructionImpl(\n";
2674 OS << "const SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n"
2675 << " MCInst &Inst,\n"
2676 << " unsigned &ErrorInfo,"
2677 << " bool matchingInlineAsm,\n"
2678 << " unsigned VariantID = 0);\n";
2680 if (Info.OperandMatchInfo.size()) {
2681 OS << "\n enum OperandMatchResultTy {\n";
2682 OS << " MatchOperand_Success, // operand matched successfully\n";
2683 OS << " MatchOperand_NoMatch, // operand did not match\n";
2684 OS << " MatchOperand_ParseFail // operand matched but had errors\n";
2686 OS << " OperandMatchResultTy MatchOperandParserImpl(\n";
2687 OS << " SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n";
2688 OS << " StringRef Mnemonic);\n";
2690 OS << " OperandMatchResultTy tryCustomParseOperand(\n";
2691 OS << " SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n";
2692 OS << " unsigned MCK);\n\n";
2695 OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n";
2697 // Emit the operand match diagnostic enum names.
2698 OS << "\n#ifdef GET_OPERAND_DIAGNOSTIC_TYPES\n";
2699 OS << "#undef GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
2700 emitOperandDiagnosticTypes(Info, OS);
2701 OS << "#endif // GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
2704 OS << "\n#ifdef GET_REGISTER_MATCHER\n";
2705 OS << "#undef GET_REGISTER_MATCHER\n\n";
2707 // Emit the subtarget feature enumeration.
2708 emitSubtargetFeatureFlagEnumeration(Info, OS);
2710 // Emit the function to match a register name to number.
2711 // This should be omitted for Mips target
2712 if (AsmParser->getValueAsBit("ShouldEmitMatchRegisterName"))
2713 emitMatchRegisterName(Target, AsmParser, OS);
2715 OS << "#endif // GET_REGISTER_MATCHER\n\n";
2717 OS << "\n#ifdef GET_SUBTARGET_FEATURE_NAME\n";
2718 OS << "#undef GET_SUBTARGET_FEATURE_NAME\n\n";
2720 // Generate the helper function to get the names for subtarget features.
2721 emitGetSubtargetFeatureName(Info, OS);
2723 OS << "#endif // GET_SUBTARGET_FEATURE_NAME\n\n";
2725 OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
2726 OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
2728 // Generate the function that remaps for mnemonic aliases.
2729 bool HasMnemonicAliases = emitMnemonicAliases(OS, Info, Target);
2731 // Generate the convertToMCInst function to convert operands into an MCInst.
2732 // Also, generate the convertToMapAndConstraints function for MS-style inline
2733 // assembly. The latter doesn't actually generate a MCInst.
2734 emitConvertFuncs(Target, ClassName, Info.Matchables, OS);
2736 // Emit the enumeration for classes which participate in matching.
2737 emitMatchClassEnumeration(Target, Info.Classes, OS);
2739 // Emit the routine to match token strings to their match class.
2740 emitMatchTokenString(Target, Info.Classes, OS);
2742 // Emit the subclass predicate routine.
2743 emitIsSubclass(Target, Info.Classes, OS);
2745 // Emit the routine to validate an operand against a match class.
2746 emitValidateOperandClass(Info, OS);
2748 // Emit the available features compute function.
2749 emitComputeAvailableFeatures(Info, OS);
2752 StringToOffsetTable StringTable;
2754 size_t MaxNumOperands = 0;
2755 unsigned MaxMnemonicIndex = 0;
2756 bool HasDeprecation = false;
2757 for (std::vector<MatchableInfo*>::const_iterator it =
2758 Info.Matchables.begin(), ie = Info.Matchables.end();
2760 MatchableInfo &II = **it;
2761 MaxNumOperands = std::max(MaxNumOperands, II.AsmOperands.size());
2762 HasDeprecation |= II.HasDeprecation;
2764 // Store a pascal-style length byte in the mnemonic.
2765 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2766 MaxMnemonicIndex = std::max(MaxMnemonicIndex,
2767 StringTable.GetOrAddStringOffset(LenMnemonic, false));
2770 OS << "static const char *const MnemonicTable =\n";
2771 StringTable.EmitString(OS);
2774 // Emit the static match table; unused classes get initalized to 0 which is
2775 // guaranteed to be InvalidMatchClass.
2777 // FIXME: We can reduce the size of this table very easily. First, we change
2778 // it so that store the kinds in separate bit-fields for each index, which
2779 // only needs to be the max width used for classes at that index (we also need
2780 // to reject based on this during classification). If we then make sure to
2781 // order the match kinds appropriately (putting mnemonics last), then we
2782 // should only end up using a few bits for each class, especially the ones
2783 // following the mnemonic.
2784 OS << "namespace {\n";
2785 OS << " struct MatchEntry {\n";
2786 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex)
2788 OS << " uint16_t Opcode;\n";
2789 OS << " " << getMinimalTypeForRange(Info.Matchables.size())
2791 OS << " " << getMinimalTypeForRange(1ULL << Info.SubtargetFeatures.size())
2792 << " RequiredFeatures;\n";
2793 OS << " " << getMinimalTypeForRange(Info.Classes.size())
2794 << " Classes[" << MaxNumOperands << "];\n";
2795 OS << " StringRef getMnemonic() const {\n";
2796 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2797 OS << " MnemonicTable[Mnemonic]);\n";
2801 OS << " // Predicate for searching for an opcode.\n";
2802 OS << " struct LessOpcode {\n";
2803 OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n";
2804 OS << " return LHS.getMnemonic() < RHS;\n";
2806 OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n";
2807 OS << " return LHS < RHS.getMnemonic();\n";
2809 OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n";
2810 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2814 OS << "} // end anonymous namespace.\n\n";
2816 unsigned VariantCount = Target.getAsmParserVariantCount();
2817 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2818 Record *AsmVariant = Target.getAsmParserVariant(VC);
2819 std::string CommentDelimiter =
2820 AsmVariant->getValueAsString("CommentDelimiter");
2821 std::string RegisterPrefix = AsmVariant->getValueAsString("RegisterPrefix");
2822 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2824 OS << "static const MatchEntry MatchTable" << VC << "[] = {\n";
2826 for (std::vector<MatchableInfo*>::const_iterator it =
2827 Info.Matchables.begin(), ie = Info.Matchables.end();
2829 MatchableInfo &II = **it;
2830 if (II.AsmVariantID != AsmVariantNo)
2833 // Store a pascal-style length byte in the mnemonic.
2834 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2835 OS << " { " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2836 << " /* " << II.Mnemonic << " */, "
2837 << Target.getName() << "::"
2838 << II.getResultInst()->TheDef->getName() << ", "
2839 << II.ConversionFnKind << ", ";
2841 // Write the required features mask.
2842 if (!II.RequiredFeatures.empty()) {
2843 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
2845 OS << II.RequiredFeatures[i]->getEnumName();
2851 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) {
2852 MatchableInfo::AsmOperand &Op = II.AsmOperands[i];
2855 OS << Op.Class->Name;
2863 // A method to determine if a mnemonic is in the list.
2864 OS << "bool " << Target.getName() << ClassName << "::\n"
2865 << "mnemonicIsValid(StringRef Mnemonic, unsigned VariantID) {\n";
2866 OS << " // Find the appropriate table for this asm variant.\n";
2867 OS << " const MatchEntry *Start, *End;\n";
2868 OS << " switch (VariantID) {\n";
2869 OS << " default: // unreachable\n";
2870 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2871 Record *AsmVariant = Target.getAsmParserVariant(VC);
2872 std::string CommentDelimiter =
2873 AsmVariant->getValueAsString("CommentDelimiter");
2874 std::string RegisterPrefix = AsmVariant->getValueAsString("RegisterPrefix");
2875 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2876 OS << " case " << AsmVariantNo << ": Start = MatchTable" << VC
2877 << "; End = array_endof(MatchTable" << VC << "); break;\n";
2880 OS << " // Search the table.\n";
2881 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
2882 OS << " std::equal_range(Start, End, Mnemonic, LessOpcode());\n";
2883 OS << " return MnemonicRange.first != MnemonicRange.second;\n";
2886 // Finally, build the match function.
2888 << Target.getName() << ClassName << "::\n"
2889 << "MatchInstructionImpl(const SmallVectorImpl<MCParsedAsmOperand*>"
2891 OS << " MCInst &Inst,\n"
2892 << "unsigned &ErrorInfo, bool matchingInlineAsm, unsigned VariantID) {\n";
2894 OS << " // Eliminate obvious mismatches.\n";
2895 OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n";
2896 OS << " ErrorInfo = " << (MaxNumOperands+1) << ";\n";
2897 OS << " return Match_InvalidOperand;\n";
2900 // Emit code to get the available features.
2901 OS << " // Get the current feature set.\n";
2902 OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n";
2904 OS << " // Get the instruction mnemonic, which is the first token.\n";
2905 OS << " StringRef Mnemonic = ((" << Target.getName()
2906 << "Operand*)Operands[0])->getToken();\n\n";
2908 if (HasMnemonicAliases) {
2909 OS << " // Process all MnemonicAliases to remap the mnemonic.\n";
2910 OS << " applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);\n\n";
2913 // Emit code to compute the class list for this operand vector.
2914 OS << " // Some state to try to produce better error messages.\n";
2915 OS << " bool HadMatchOtherThanFeatures = false;\n";
2916 OS << " bool HadMatchOtherThanPredicate = false;\n";
2917 OS << " unsigned RetCode = Match_InvalidOperand;\n";
2918 OS << " unsigned MissingFeatures = ~0U;\n";
2919 OS << " // Set ErrorInfo to the operand that mismatches if it is\n";
2920 OS << " // wrong for all instances of the instruction.\n";
2921 OS << " ErrorInfo = ~0U;\n";
2923 // Emit code to search the table.
2924 OS << " // Find the appropriate table for this asm variant.\n";
2925 OS << " const MatchEntry *Start, *End;\n";
2926 OS << " switch (VariantID) {\n";
2927 OS << " default: // unreachable\n";
2928 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2929 Record *AsmVariant = Target.getAsmParserVariant(VC);
2930 std::string CommentDelimiter =
2931 AsmVariant->getValueAsString("CommentDelimiter");
2932 std::string RegisterPrefix = AsmVariant->getValueAsString("RegisterPrefix");
2933 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2934 OS << " case " << AsmVariantNo << ": Start = MatchTable" << VC
2935 << "; End = array_endof(MatchTable" << VC << "); break;\n";
2938 OS << " // Search the table.\n";
2939 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
2940 OS << " std::equal_range(Start, End, Mnemonic, LessOpcode());\n\n";
2942 OS << " // Return a more specific error code if no mnemonics match.\n";
2943 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2944 OS << " return Match_MnemonicFail;\n\n";
2946 OS << " for (const MatchEntry *it = MnemonicRange.first, "
2947 << "*ie = MnemonicRange.second;\n";
2948 OS << " it != ie; ++it) {\n";
2950 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2951 OS << " assert(Mnemonic == it->getMnemonic());\n";
2953 // Emit check that the subclasses match.
2954 OS << " bool OperandsValid = true;\n";
2955 OS << " for (unsigned i = 0; i != " << MaxNumOperands << "; ++i) {\n";
2956 OS << " if (i + 1 >= Operands.size()) {\n";
2957 OS << " OperandsValid = (it->Classes[i] == " <<"InvalidMatchClass);\n";
2958 OS << " if (!OperandsValid) ErrorInfo = i + 1;\n";
2961 OS << " unsigned Diag = validateOperandClass(Operands[i+1],\n";
2963 OS << "(MatchClassKind)it->Classes[i]);\n";
2964 OS << " if (Diag == Match_Success)\n";
2965 OS << " continue;\n";
2966 OS << " // If the generic handler indicates an invalid operand\n";
2967 OS << " // failure, check for a special case.\n";
2968 OS << " if (Diag == Match_InvalidOperand) {\n";
2969 OS << " Diag = validateTargetOperandClass(Operands[i+1],\n";
2971 OS << "(MatchClassKind)it->Classes[i]);\n";
2972 OS << " if (Diag == Match_Success)\n";
2973 OS << " continue;\n";
2975 OS << " // If this operand is broken for all of the instances of this\n";
2976 OS << " // mnemonic, keep track of it so we can report loc info.\n";
2977 OS << " // If we already had a match that only failed due to a\n";
2978 OS << " // target predicate, that diagnostic is preferred.\n";
2979 OS << " if (!HadMatchOtherThanPredicate &&\n";
2980 OS << " (it == MnemonicRange.first || ErrorInfo <= i+1)) {\n";
2981 OS << " ErrorInfo = i+1;\n";
2982 OS << " // InvalidOperand is the default. Prefer specificity.\n";
2983 OS << " if (Diag != Match_InvalidOperand)\n";
2984 OS << " RetCode = Diag;\n";
2986 OS << " // Otherwise, just reject this instance of the mnemonic.\n";
2987 OS << " OperandsValid = false;\n";
2991 OS << " if (!OperandsValid) continue;\n";
2993 // Emit check that the required features are available.
2994 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2995 << "!= it->RequiredFeatures) {\n";
2996 OS << " HadMatchOtherThanFeatures = true;\n";
2997 OS << " unsigned NewMissingFeatures = it->RequiredFeatures & "
2998 "~AvailableFeatures;\n";
2999 OS << " if (CountPopulation_32(NewMissingFeatures) <=\n"
3000 " CountPopulation_32(MissingFeatures))\n";
3001 OS << " MissingFeatures = NewMissingFeatures;\n";
3002 OS << " continue;\n";
3005 OS << " if (matchingInlineAsm) {\n";
3006 OS << " Inst.setOpcode(it->Opcode);\n";
3007 OS << " convertToMapAndConstraints(it->ConvertFn, Operands);\n";
3008 OS << " return Match_Success;\n";
3010 OS << " // We have selected a definite instruction, convert the parsed\n"
3011 << " // operands into the appropriate MCInst.\n";
3012 OS << " convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n";
3015 // Verify the instruction with the target-specific match predicate function.
3016 OS << " // We have a potential match. Check the target predicate to\n"
3017 << " // handle any context sensitive constraints.\n"
3018 << " unsigned MatchResult;\n"
3019 << " if ((MatchResult = checkTargetMatchPredicate(Inst)) !="
3020 << " Match_Success) {\n"
3021 << " Inst.clear();\n"
3022 << " RetCode = MatchResult;\n"
3023 << " HadMatchOtherThanPredicate = true;\n"
3027 // Call the post-processing function, if used.
3028 std::string InsnCleanupFn =
3029 AsmParser->getValueAsString("AsmParserInstCleanup");
3030 if (!InsnCleanupFn.empty())
3031 OS << " " << InsnCleanupFn << "(Inst);\n";
3033 if (HasDeprecation) {
3034 OS << " std::string Info;\n";
3035 OS << " if (MII.get(Inst.getOpcode()).getDeprecatedInfo(Inst, STI, Info)) {\n";
3036 OS << " SMLoc Loc = ((" << Target.getName() << "Operand*)Operands[0])->getStartLoc();\n";
3037 OS << " Parser.Warning(Loc, Info, None);\n";
3041 OS << " return Match_Success;\n";
3044 OS << " // Okay, we had no match. Try to return a useful error code.\n";
3045 OS << " if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)\n";
3046 OS << " return RetCode;\n\n";
3047 OS << " // Missing feature matches return which features were missing\n";
3048 OS << " ErrorInfo = MissingFeatures;\n";
3049 OS << " return Match_MissingFeature;\n";
3052 if (Info.OperandMatchInfo.size())
3053 emitCustomOperandParsing(OS, Target, Info, ClassName, StringTable,
3056 OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";
3061 void EmitAsmMatcher(RecordKeeper &RK, raw_ostream &OS) {
3062 emitSourceFileHeader("Assembly Matcher Source Fragment", OS);
3063 AsmMatcherEmitter(RK).run(OS);
3066 } // End llvm namespace