1 //===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits a target specifier matcher for converting parsed
11 // assembly operands in the MCInst structures.
13 // The input to the target specific matcher is a list of literal tokens and
14 // operands. The target specific parser should generally eliminate any syntax
15 // which is not relevant for matching; for example, comma tokens should have
16 // already been consumed and eliminated by the parser. Most instructions will
17 // end up with a single literal token (the instruction name) and some number of
20 // Some example inputs, for X86:
21 // 'addl' (immediate ...) (register ...)
22 // 'add' (immediate ...) (memory ...)
25 // The assembly matcher is responsible for converting this input into a precise
26 // machine instruction (i.e., an instruction with a well defined encoding). This
27 // mapping has several properties which complicate matching:
29 // - It may be ambiguous; many architectures can legally encode particular
30 // variants of an instruction in different ways (for example, using a smaller
31 // encoding for small immediates). Such ambiguities should never be
32 // arbitrarily resolved by the assembler, the assembler is always responsible
33 // for choosing the "best" available instruction.
35 // - It may depend on the subtarget or the assembler context. Instructions
36 // which are invalid for the current mode, but otherwise unambiguous (e.g.,
37 // an SSE instruction in a file being assembled for i486) should be accepted
38 // and rejected by the assembler front end. However, if the proper encoding
39 // for an instruction is dependent on the assembler context then the matcher
40 // is responsible for selecting the correct machine instruction for the
43 // The core matching algorithm attempts to exploit the regularity in most
44 // instruction sets to quickly determine the set of possibly matching
45 // instructions, and the simplify the generated code. Additionally, this helps
46 // to ensure that the ambiguities are intentionally resolved by the user.
48 // The matching is divided into two distinct phases:
50 // 1. Classification: Each operand is mapped to the unique set which (a)
51 // contains it, and (b) is the largest such subset for which a single
52 // instruction could match all members.
54 // For register classes, we can generate these subgroups automatically. For
55 // arbitrary operands, we expect the user to define the classes and their
56 // relations to one another (for example, 8-bit signed immediates as a
57 // subset of 32-bit immediates).
59 // By partitioning the operands in this way, we guarantee that for any
60 // tuple of classes, any single instruction must match either all or none
61 // of the sets of operands which could classify to that tuple.
63 // In addition, the subset relation amongst classes induces a partial order
64 // on such tuples, which we use to resolve ambiguities.
66 // 2. The input can now be treated as a tuple of classes (static tokens are
67 // simple singleton sets). Each such tuple should generally map to a single
68 // instruction (we currently ignore cases where this isn't true, whee!!!),
69 // which we can emit a simple matcher for.
71 //===----------------------------------------------------------------------===//
73 #include "AsmMatcherEmitter.h"
74 #include "CodeGenTarget.h"
76 #include "StringMatcher.h"
77 #include "llvm/ADT/OwningPtr.h"
78 #include "llvm/ADT/PointerUnion.h"
79 #include "llvm/ADT/SmallPtrSet.h"
80 #include "llvm/ADT/SmallVector.h"
81 #include "llvm/ADT/STLExtras.h"
82 #include "llvm/ADT/StringExtras.h"
83 #include "llvm/Support/CommandLine.h"
84 #include "llvm/Support/Debug.h"
89 static cl::opt<std::string>
90 MatchPrefix("match-prefix", cl::init(""),
91 cl::desc("Only match instructions with the given prefix"));
96 struct SubtargetFeatureInfo;
98 /// ClassInfo - Helper class for storing the information about a particular
99 /// class of operands which can be matched.
102 /// Invalid kind, for use as a sentinel value.
105 /// The class for a particular token.
108 /// The (first) register class, subsequent register classes are
109 /// RegisterClass0+1, and so on.
112 /// The (first) user defined class, subsequent user defined classes are
113 /// UserClass0+1, and so on.
117 /// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
118 /// N) for the Nth user defined class.
121 /// SuperClasses - The super classes of this class. Note that for simplicities
122 /// sake user operands only record their immediate super class, while register
123 /// operands include all superclasses.
124 std::vector<ClassInfo*> SuperClasses;
126 /// Name - The full class name, suitable for use in an enum.
129 /// ClassName - The unadorned generic name for this class (e.g., Token).
130 std::string ClassName;
132 /// ValueName - The name of the value this class represents; for a token this
133 /// is the literal token string, for an operand it is the TableGen class (or
134 /// empty if this is a derived class).
135 std::string ValueName;
137 /// PredicateMethod - The name of the operand method to test whether the
138 /// operand matches this class; this is not valid for Token or register kinds.
139 std::string PredicateMethod;
141 /// RenderMethod - The name of the operand method to add this operand to an
142 /// MCInst; this is not valid for Token or register kinds.
143 std::string RenderMethod;
145 /// For register classes, the records for all the registers in this class.
146 std::set<Record*> Registers;
149 /// isRegisterClass() - Check if this is a register class.
150 bool isRegisterClass() const {
151 return Kind >= RegisterClass0 && Kind < UserClass0;
154 /// isUserClass() - Check if this is a user defined class.
155 bool isUserClass() const {
156 return Kind >= UserClass0;
159 /// isRelatedTo - Check whether this class is "related" to \arg RHS. Classes
160 /// are related if they are in the same class hierarchy.
161 bool isRelatedTo(const ClassInfo &RHS) const {
162 // Tokens are only related to tokens.
163 if (Kind == Token || RHS.Kind == Token)
164 return Kind == Token && RHS.Kind == Token;
166 // Registers classes are only related to registers classes, and only if
167 // their intersection is non-empty.
168 if (isRegisterClass() || RHS.isRegisterClass()) {
169 if (!isRegisterClass() || !RHS.isRegisterClass())
172 std::set<Record*> Tmp;
173 std::insert_iterator< std::set<Record*> > II(Tmp, Tmp.begin());
174 std::set_intersection(Registers.begin(), Registers.end(),
175 RHS.Registers.begin(), RHS.Registers.end(),
181 // Otherwise we have two users operands; they are related if they are in the
182 // same class hierarchy.
184 // FIXME: This is an oversimplification, they should only be related if they
185 // intersect, however we don't have that information.
186 assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");
187 const ClassInfo *Root = this;
188 while (!Root->SuperClasses.empty())
189 Root = Root->SuperClasses.front();
191 const ClassInfo *RHSRoot = &RHS;
192 while (!RHSRoot->SuperClasses.empty())
193 RHSRoot = RHSRoot->SuperClasses.front();
195 return Root == RHSRoot;
198 /// isSubsetOf - Test whether this class is a subset of \arg RHS;
199 bool isSubsetOf(const ClassInfo &RHS) const {
200 // This is a subset of RHS if it is the same class...
204 // ... or if any of its super classes are a subset of RHS.
205 for (std::vector<ClassInfo*>::const_iterator it = SuperClasses.begin(),
206 ie = SuperClasses.end(); it != ie; ++it)
207 if ((*it)->isSubsetOf(RHS))
213 /// operator< - Compare two classes.
214 bool operator<(const ClassInfo &RHS) const {
218 // Unrelated classes can be ordered by kind.
219 if (!isRelatedTo(RHS))
220 return Kind < RHS.Kind;
224 assert(0 && "Invalid kind!");
226 // Tokens are comparable by value.
228 // FIXME: Compare by enum value.
229 return ValueName < RHS.ValueName;
232 // This class preceeds the RHS if it is a proper subset of the RHS.
235 if (RHS.isSubsetOf(*this))
238 // Otherwise, order by name to ensure we have a total ordering.
239 return ValueName < RHS.ValueName;
244 /// MatchableInfo - Helper class for storing the necessary information for an
245 /// instruction or alias which is capable of being matched.
246 struct MatchableInfo {
248 /// Token - This is the token that the operand came from.
251 /// The unique class instance this operand should match.
254 /// The operand name this is, if anything.
257 explicit AsmOperand(StringRef T) : Token(T), Class(0) {}
260 /// ResOperand - This represents a single operand in the result instruction
261 /// generated by the match. In cases (like addressing modes) where a single
262 /// assembler operand expands to multiple MCOperands, this represents the
263 /// single assembler operand, not the MCOperand.
266 /// RenderAsmOperand - This represents an operand result that is
267 /// generated by calling the render method on the assembly operand. The
268 /// corresponding AsmOperand is specified by AsmOperandNum.
271 /// TiedOperand - This represents a result operand that is a duplicate of
272 /// a previous result operand.
275 /// ImmOperand - This represents an immediate value that is dumped into
279 /// RegOperand - This represents a fixed register that is dumped in.
284 /// This is the operand # in the AsmOperands list that this should be
286 unsigned AsmOperandNum;
288 /// TiedOperandNum - This is the (earlier) result operand that should be
290 unsigned TiedOperandNum;
292 /// ImmVal - This is the immediate value added to the instruction.
295 /// Register - This is the register record.
299 /// OpInfo - This is the information about the instruction operand that is
301 const CGIOperandList::OperandInfo *OpInfo;
303 static ResOperand getRenderedOp(unsigned AsmOpNum,
304 const CGIOperandList::OperandInfo *Op) {
306 X.Kind = RenderAsmOperand;
307 X.AsmOperandNum = AsmOpNum;
312 static ResOperand getTiedOp(unsigned TiedOperandNum,
313 const CGIOperandList::OperandInfo *Op) {
315 X.Kind = TiedOperand;
316 X.TiedOperandNum = TiedOperandNum;
321 static ResOperand getImmOp(int64_t Val,
322 const CGIOperandList::OperandInfo *Op) {
330 static ResOperand getRegOp(Record *Reg,
331 const CGIOperandList::OperandInfo *Op) {
341 /// TheDef - This is the definition of the instruction or InstAlias that this
342 /// matchable came from.
343 Record *const TheDef;
345 /// DefRec - This is the definition that it came from.
346 PointerUnion<const CodeGenInstruction*, const CodeGenInstAlias*> DefRec;
348 const CodeGenInstruction *getResultInst() const {
349 if (DefRec.is<const CodeGenInstruction*>())
350 return DefRec.get<const CodeGenInstruction*>();
351 return DefRec.get<const CodeGenInstAlias*>()->ResultInst;
354 /// ResOperands - This is the operand list that should be built for the result
356 std::vector<ResOperand> ResOperands;
358 /// AsmString - The assembly string for this instruction (with variants
359 /// removed), e.g. "movsx $src, $dst".
360 std::string AsmString;
362 /// Mnemonic - This is the first token of the matched instruction, its
366 /// AsmOperands - The textual operands that this instruction matches,
367 /// annotated with a class and where in the OperandList they were defined.
368 /// This directly corresponds to the tokenized AsmString after the mnemonic is
370 SmallVector<AsmOperand, 4> AsmOperands;
372 /// Predicates - The required subtarget features to match this instruction.
373 SmallVector<SubtargetFeatureInfo*, 4> RequiredFeatures;
375 /// ConversionFnKind - The enum value which is passed to the generated
376 /// ConvertToMCInst to convert parsed operands into an MCInst for this
378 std::string ConversionFnKind;
380 MatchableInfo(const CodeGenInstruction &CGI)
381 : TheDef(CGI.TheDef), DefRec(&CGI), AsmString(CGI.AsmString) {
384 MatchableInfo(const CodeGenInstAlias *Alias)
385 : TheDef(Alias->TheDef), DefRec(Alias), AsmString(Alias->AsmString) {
388 void Initialize(const AsmMatcherInfo &Info,
389 SmallPtrSet<Record*, 16> &SingletonRegisters);
391 /// Validate - Return true if this matchable is a valid thing to match against
392 /// and perform a bunch of validity checking.
393 bool Validate(StringRef CommentDelimiter, bool Hack) const;
395 /// getSingletonRegisterForAsmOperand - If the specified token is a singleton
396 /// register, return the Record for it, otherwise return null.
397 Record *getSingletonRegisterForAsmOperand(unsigned i,
398 const AsmMatcherInfo &Info) const;
400 int FindAsmOperandNamed(StringRef N) const {
401 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
402 if (N == AsmOperands[i].SrcOpName)
407 void BuildInstructionResultOperands();
408 void BuildAliasResultOperands();
410 /// operator< - Compare two matchables.
411 bool operator<(const MatchableInfo &RHS) const {
412 // The primary comparator is the instruction mnemonic.
413 if (Mnemonic != RHS.Mnemonic)
414 return Mnemonic < RHS.Mnemonic;
416 if (AsmOperands.size() != RHS.AsmOperands.size())
417 return AsmOperands.size() < RHS.AsmOperands.size();
419 // Compare lexicographically by operand. The matcher validates that other
420 // orderings wouldn't be ambiguous using \see CouldMatchAmiguouslyWith().
421 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
422 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
424 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
431 /// CouldMatchAmiguouslyWith - Check whether this matchable could
432 /// ambiguously match the same set of operands as \arg RHS (without being a
433 /// strictly superior match).
434 bool CouldMatchAmiguouslyWith(const MatchableInfo &RHS) {
435 // The primary comparator is the instruction mnemonic.
436 if (Mnemonic != RHS.Mnemonic)
439 // The number of operands is unambiguous.
440 if (AsmOperands.size() != RHS.AsmOperands.size())
443 // Otherwise, make sure the ordering of the two instructions is unambiguous
444 // by checking that either (a) a token or operand kind discriminates them,
445 // or (b) the ordering among equivalent kinds is consistent.
447 // Tokens and operand kinds are unambiguous (assuming a correct target
449 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
450 if (AsmOperands[i].Class->Kind != RHS.AsmOperands[i].Class->Kind ||
451 AsmOperands[i].Class->Kind == ClassInfo::Token)
452 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class ||
453 *RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
456 // Otherwise, this operand could commute if all operands are equivalent, or
457 // there is a pair of operands that compare less than and a pair that
458 // compare greater than.
459 bool HasLT = false, HasGT = false;
460 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
461 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
463 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
467 return !(HasLT ^ HasGT);
473 void TokenizeAsmString(const AsmMatcherInfo &Info);
476 /// SubtargetFeatureInfo - Helper class for storing information on a subtarget
477 /// feature which participates in instruction matching.
478 struct SubtargetFeatureInfo {
479 /// \brief The predicate record for this feature.
482 /// \brief An unique index assigned to represent this feature.
485 SubtargetFeatureInfo(Record *D, unsigned Idx) : TheDef(D), Index(Idx) {}
487 /// \brief The name of the enumerated constant identifying this feature.
488 std::string getEnumName() const {
489 return "Feature_" + TheDef->getName();
493 class AsmMatcherInfo {
495 /// The tablegen AsmParser record.
498 /// Target - The target information.
499 CodeGenTarget &Target;
501 /// The AsmParser "RegisterPrefix" value.
502 std::string RegisterPrefix;
504 /// The classes which are needed for matching.
505 std::vector<ClassInfo*> Classes;
507 /// The information on the matchables to match.
508 std::vector<MatchableInfo*> Matchables;
510 /// Map of Register records to their class information.
511 std::map<Record*, ClassInfo*> RegisterClasses;
513 /// Map of Predicate records to their subtarget information.
514 std::map<Record*, SubtargetFeatureInfo*> SubtargetFeatures;
517 /// Map of token to class information which has already been constructed.
518 std::map<std::string, ClassInfo*> TokenClasses;
520 /// Map of RegisterClass records to their class information.
521 std::map<Record*, ClassInfo*> RegisterClassClasses;
523 /// Map of AsmOperandClass records to their class information.
524 std::map<Record*, ClassInfo*> AsmOperandClasses;
527 /// getTokenClass - Lookup or create the class for the given token.
528 ClassInfo *getTokenClass(StringRef Token);
530 /// getOperandClass - Lookup or create the class for the given operand.
531 ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI);
533 /// BuildRegisterClasses - Build the ClassInfo* instances for register
535 void BuildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters);
537 /// BuildOperandClasses - Build the ClassInfo* instances for user defined
539 void BuildOperandClasses();
541 void BuildInstructionOperandReference(MatchableInfo *II,
543 MatchableInfo::AsmOperand &Op);
544 void BuildAliasOperandReference(MatchableInfo *II,
546 MatchableInfo::AsmOperand &Op);
549 AsmMatcherInfo(Record *AsmParser, CodeGenTarget &Target);
551 /// BuildInfo - Construct the various tables used during matching.
554 /// getSubtargetFeature - Lookup or create the subtarget feature info for the
556 SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const {
557 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
558 std::map<Record*, SubtargetFeatureInfo*>::const_iterator I =
559 SubtargetFeatures.find(Def);
560 return I == SubtargetFeatures.end() ? 0 : I->second;
566 void MatchableInfo::dump() {
567 errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n";
569 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
570 AsmOperand &Op = AsmOperands[i];
571 errs() << " op[" << i << "] = " << Op.Class->ClassName << " - ";
572 errs() << '\"' << Op.Token << "\"\n";
576 void MatchableInfo::Initialize(const AsmMatcherInfo &Info,
577 SmallPtrSet<Record*, 16> &SingletonRegisters) {
578 // TODO: Eventually support asmparser for Variant != 0.
579 AsmString = CodeGenInstruction::FlattenAsmStringVariants(AsmString, 0);
581 TokenizeAsmString(Info);
583 // Compute the require features.
584 std::vector<Record*> Predicates =TheDef->getValueAsListOfDefs("Predicates");
585 for (unsigned i = 0, e = Predicates.size(); i != e; ++i)
586 if (SubtargetFeatureInfo *Feature =
587 Info.getSubtargetFeature(Predicates[i]))
588 RequiredFeatures.push_back(Feature);
590 // Collect singleton registers, if used.
591 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
592 if (Record *Reg = getSingletonRegisterForAsmOperand(i, Info))
593 SingletonRegisters.insert(Reg);
597 /// TokenizeAsmString - Tokenize a simplified assembly string.
598 void MatchableInfo::TokenizeAsmString(const AsmMatcherInfo &Info) {
599 StringRef String = AsmString;
602 for (unsigned i = 0, e = String.size(); i != e; ++i) {
612 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
615 if (!isspace(String[i]) && String[i] != ',')
616 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
622 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
626 assert(i != String.size() && "Invalid quoted character");
627 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
632 // If this isn't "${", treat like a normal token.
633 if (i + 1 == String.size() || String[i + 1] != '{') {
635 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
643 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
647 StringRef::iterator End = std::find(String.begin() + i, String.end(),'}');
648 assert(End != String.end() && "Missing brace in operand reference!");
649 size_t EndPos = End - String.begin();
650 AsmOperands.push_back(AsmOperand(String.slice(i, EndPos+1)));
658 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
667 if (InTok && Prev != String.size())
668 AsmOperands.push_back(AsmOperand(String.substr(Prev)));
670 // The first token of the instruction is the mnemonic, which must be a
671 // simple string, not a $foo variable or a singleton register.
672 assert(!AsmOperands.empty() && "Instruction has no tokens?");
673 Mnemonic = AsmOperands[0].Token;
674 if (Mnemonic[0] == '$' || getSingletonRegisterForAsmOperand(0, Info))
675 throw TGError(TheDef->getLoc(),
676 "Invalid instruction mnemonic '" + Mnemonic.str() + "'!");
678 // Remove the first operand, it is tracked in the mnemonic field.
679 AsmOperands.erase(AsmOperands.begin());
684 bool MatchableInfo::Validate(StringRef CommentDelimiter, bool Hack) const {
685 // Reject matchables with no .s string.
686 if (AsmString.empty())
687 throw TGError(TheDef->getLoc(), "instruction with empty asm string");
689 // Reject any matchables with a newline in them, they should be marked
690 // isCodeGenOnly if they are pseudo instructions.
691 if (AsmString.find('\n') != std::string::npos)
692 throw TGError(TheDef->getLoc(),
693 "multiline instruction is not valid for the asmparser, "
694 "mark it isCodeGenOnly");
696 // Remove comments from the asm string. We know that the asmstring only
698 if (!CommentDelimiter.empty() &&
699 StringRef(AsmString).find(CommentDelimiter) != StringRef::npos)
700 throw TGError(TheDef->getLoc(),
701 "asmstring for instruction has comment character in it, "
702 "mark it isCodeGenOnly");
704 // Reject matchables with operand modifiers, these aren't something we can
705 /// handle, the target should be refactored to use operands instead of
708 // Also, check for instructions which reference the operand multiple times;
709 // this implies a constraint we would not honor.
710 std::set<std::string> OperandNames;
711 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
712 StringRef Tok = AsmOperands[i].Token;
713 if (Tok[0] == '$' && Tok.find(':') != StringRef::npos)
714 throw TGError(TheDef->getLoc(),
715 "matchable with operand modifier '" + Tok.str() +
716 "' not supported by asm matcher. Mark isCodeGenOnly!");
718 // Verify that any operand is only mentioned once.
719 // We reject aliases and ignore instructions for now.
720 if (Tok[0] == '$' && !OperandNames.insert(Tok).second) {
722 throw TGError(TheDef->getLoc(),
723 "ERROR: matchable with tied operand '" + Tok.str() +
724 "' can never be matched!");
725 // FIXME: Should reject these. The ARM backend hits this with $lane in a
726 // bunch of instructions. It is unclear what the right answer is.
728 errs() << "warning: '" << TheDef->getName() << "': "
729 << "ignoring instruction with tied operand '"
730 << Tok.str() << "'\n";
740 /// getSingletonRegisterForAsmOperand - If the specified token is a singleton
741 /// register, return the register name, otherwise return a null StringRef.
742 Record *MatchableInfo::
743 getSingletonRegisterForAsmOperand(unsigned i, const AsmMatcherInfo &Info) const{
744 StringRef Tok = AsmOperands[i].Token;
745 if (!Tok.startswith(Info.RegisterPrefix))
748 StringRef RegName = Tok.substr(Info.RegisterPrefix.size());
749 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName))
752 // If there is no register prefix (i.e. "%" in "%eax"), then this may
753 // be some random non-register token, just ignore it.
754 if (Info.RegisterPrefix.empty())
757 // Otherwise, we have something invalid prefixed with the register prefix,
759 std::string Err = "unable to find register for '" + RegName.str() +
760 "' (which matches register prefix)";
761 throw TGError(TheDef->getLoc(), Err);
765 static std::string getEnumNameForToken(StringRef Str) {
768 for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) {
770 case '*': Res += "_STAR_"; break;
771 case '%': Res += "_PCT_"; break;
772 case ':': Res += "_COLON_"; break;
777 Res += "_" + utostr((unsigned) *it) + "_";
784 ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) {
785 ClassInfo *&Entry = TokenClasses[Token];
788 Entry = new ClassInfo();
789 Entry->Kind = ClassInfo::Token;
790 Entry->ClassName = "Token";
791 Entry->Name = "MCK_" + getEnumNameForToken(Token);
792 Entry->ValueName = Token;
793 Entry->PredicateMethod = "<invalid>";
794 Entry->RenderMethod = "<invalid>";
795 Classes.push_back(Entry);
802 AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI) {
803 if (OI.Rec->isSubClassOf("RegisterClass")) {
804 if (ClassInfo *CI = RegisterClassClasses[OI.Rec])
806 throw TGError(OI.Rec->getLoc(), "register class has no class info!");
809 assert(OI.Rec->isSubClassOf("Operand") && "Unexpected operand!");
810 Record *MatchClass = OI.Rec->getValueAsDef("ParserMatchClass");
811 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
814 throw TGError(OI.Rec->getLoc(), "operand has no match class!");
817 void AsmMatcherInfo::
818 BuildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters) {
819 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
820 const std::vector<CodeGenRegisterClass> &RegClassList =
821 Target.getRegisterClasses();
823 // The register sets used for matching.
824 std::set< std::set<Record*> > RegisterSets;
826 // Gather the defined sets.
827 for (std::vector<CodeGenRegisterClass>::const_iterator it =
828 RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it)
829 RegisterSets.insert(std::set<Record*>(it->Elements.begin(),
830 it->Elements.end()));
832 // Add any required singleton sets.
833 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
834 ie = SingletonRegisters.end(); it != ie; ++it) {
836 RegisterSets.insert(std::set<Record*>(&Rec, &Rec + 1));
839 // Introduce derived sets where necessary (when a register does not determine
840 // a unique register set class), and build the mapping of registers to the set
841 // they should classify to.
842 std::map<Record*, std::set<Record*> > RegisterMap;
843 for (std::vector<CodeGenRegister>::const_iterator it = Registers.begin(),
844 ie = Registers.end(); it != ie; ++it) {
845 const CodeGenRegister &CGR = *it;
846 // Compute the intersection of all sets containing this register.
847 std::set<Record*> ContainingSet;
849 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
850 ie = RegisterSets.end(); it != ie; ++it) {
851 if (!it->count(CGR.TheDef))
854 if (ContainingSet.empty()) {
859 std::set<Record*> Tmp;
860 std::swap(Tmp, ContainingSet);
861 std::insert_iterator< std::set<Record*> > II(ContainingSet,
862 ContainingSet.begin());
863 std::set_intersection(Tmp.begin(), Tmp.end(), it->begin(), it->end(), II);
866 if (!ContainingSet.empty()) {
867 RegisterSets.insert(ContainingSet);
868 RegisterMap.insert(std::make_pair(CGR.TheDef, ContainingSet));
872 // Construct the register classes.
873 std::map<std::set<Record*>, ClassInfo*> RegisterSetClasses;
875 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
876 ie = RegisterSets.end(); it != ie; ++it, ++Index) {
877 ClassInfo *CI = new ClassInfo();
878 CI->Kind = ClassInfo::RegisterClass0 + Index;
879 CI->ClassName = "Reg" + utostr(Index);
880 CI->Name = "MCK_Reg" + utostr(Index);
882 CI->PredicateMethod = ""; // unused
883 CI->RenderMethod = "addRegOperands";
885 Classes.push_back(CI);
886 RegisterSetClasses.insert(std::make_pair(*it, CI));
889 // Find the superclasses; we could compute only the subgroup lattice edges,
890 // but there isn't really a point.
891 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
892 ie = RegisterSets.end(); it != ie; ++it) {
893 ClassInfo *CI = RegisterSetClasses[*it];
894 for (std::set< std::set<Record*> >::iterator it2 = RegisterSets.begin(),
895 ie2 = RegisterSets.end(); it2 != ie2; ++it2)
897 std::includes(it2->begin(), it2->end(), it->begin(), it->end()))
898 CI->SuperClasses.push_back(RegisterSetClasses[*it2]);
901 // Name the register classes which correspond to a user defined RegisterClass.
902 for (std::vector<CodeGenRegisterClass>::const_iterator
903 it = RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it) {
904 ClassInfo *CI = RegisterSetClasses[std::set<Record*>(it->Elements.begin(),
905 it->Elements.end())];
906 if (CI->ValueName.empty()) {
907 CI->ClassName = it->getName();
908 CI->Name = "MCK_" + it->getName();
909 CI->ValueName = it->getName();
911 CI->ValueName = CI->ValueName + "," + it->getName();
913 RegisterClassClasses.insert(std::make_pair(it->TheDef, CI));
916 // Populate the map for individual registers.
917 for (std::map<Record*, std::set<Record*> >::iterator it = RegisterMap.begin(),
918 ie = RegisterMap.end(); it != ie; ++it)
919 RegisterClasses[it->first] = RegisterSetClasses[it->second];
921 // Name the register classes which correspond to singleton registers.
922 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
923 ie = SingletonRegisters.end(); it != ie; ++it) {
925 ClassInfo *CI = RegisterClasses[Rec];
926 assert(CI && "Missing singleton register class info!");
928 if (CI->ValueName.empty()) {
929 CI->ClassName = Rec->getName();
930 CI->Name = "MCK_" + Rec->getName();
931 CI->ValueName = Rec->getName();
933 CI->ValueName = CI->ValueName + "," + Rec->getName();
937 void AsmMatcherInfo::BuildOperandClasses() {
938 std::vector<Record*> AsmOperands =
939 Records.getAllDerivedDefinitions("AsmOperandClass");
941 // Pre-populate AsmOperandClasses map.
942 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
943 ie = AsmOperands.end(); it != ie; ++it)
944 AsmOperandClasses[*it] = new ClassInfo();
947 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
948 ie = AsmOperands.end(); it != ie; ++it, ++Index) {
949 ClassInfo *CI = AsmOperandClasses[*it];
950 CI->Kind = ClassInfo::UserClass0 + Index;
952 ListInit *Supers = (*it)->getValueAsListInit("SuperClasses");
953 for (unsigned i = 0, e = Supers->getSize(); i != e; ++i) {
954 DefInit *DI = dynamic_cast<DefInit*>(Supers->getElement(i));
956 PrintError((*it)->getLoc(), "Invalid super class reference!");
960 ClassInfo *SC = AsmOperandClasses[DI->getDef()];
962 PrintError((*it)->getLoc(), "Invalid super class reference!");
964 CI->SuperClasses.push_back(SC);
966 CI->ClassName = (*it)->getValueAsString("Name");
967 CI->Name = "MCK_" + CI->ClassName;
968 CI->ValueName = (*it)->getName();
970 // Get or construct the predicate method name.
971 Init *PMName = (*it)->getValueInit("PredicateMethod");
972 if (StringInit *SI = dynamic_cast<StringInit*>(PMName)) {
973 CI->PredicateMethod = SI->getValue();
975 assert(dynamic_cast<UnsetInit*>(PMName) &&
976 "Unexpected PredicateMethod field!");
977 CI->PredicateMethod = "is" + CI->ClassName;
980 // Get or construct the render method name.
981 Init *RMName = (*it)->getValueInit("RenderMethod");
982 if (StringInit *SI = dynamic_cast<StringInit*>(RMName)) {
983 CI->RenderMethod = SI->getValue();
985 assert(dynamic_cast<UnsetInit*>(RMName) &&
986 "Unexpected RenderMethod field!");
987 CI->RenderMethod = "add" + CI->ClassName + "Operands";
990 AsmOperandClasses[*it] = CI;
991 Classes.push_back(CI);
995 AsmMatcherInfo::AsmMatcherInfo(Record *asmParser, CodeGenTarget &target)
996 : AsmParser(asmParser), Target(target),
997 RegisterPrefix(AsmParser->getValueAsString("RegisterPrefix")) {
1001 void AsmMatcherInfo::BuildInfo() {
1002 // Build information about all of the AssemblerPredicates.
1003 std::vector<Record*> AllPredicates =
1004 Records.getAllDerivedDefinitions("Predicate");
1005 for (unsigned i = 0, e = AllPredicates.size(); i != e; ++i) {
1006 Record *Pred = AllPredicates[i];
1007 // Ignore predicates that are not intended for the assembler.
1008 if (!Pred->getValueAsBit("AssemblerMatcherPredicate"))
1011 if (Pred->getName().empty())
1012 throw TGError(Pred->getLoc(), "Predicate has no name!");
1014 unsigned FeatureNo = SubtargetFeatures.size();
1015 SubtargetFeatures[Pred] = new SubtargetFeatureInfo(Pred, FeatureNo);
1016 assert(FeatureNo < 32 && "Too many subtarget features!");
1019 StringRef CommentDelimiter = AsmParser->getValueAsString("CommentDelimiter");
1021 // Parse the instructions; we need to do this first so that we can gather the
1022 // singleton register classes.
1023 SmallPtrSet<Record*, 16> SingletonRegisters;
1024 for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
1025 E = Target.inst_end(); I != E; ++I) {
1026 const CodeGenInstruction &CGI = **I;
1028 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1029 // filter the set of instructions we consider.
1030 if (!StringRef(CGI.TheDef->getName()).startswith(MatchPrefix))
1033 // Ignore "codegen only" instructions.
1034 if (CGI.TheDef->getValueAsBit("isCodeGenOnly"))
1037 // Validate the operand list to ensure we can handle this instruction.
1038 for (unsigned i = 0, e = CGI.Operands.size(); i != e; ++i) {
1039 const CGIOperandList::OperandInfo &OI = CGI.Operands[i];
1041 // Validate tied operands.
1042 if (OI.getTiedRegister() != -1) {
1043 // If we have a tied operand that consists of multiple MCOperands, reject
1044 // it. We reject aliases and ignore instructions for now.
1045 if (OI.MINumOperands != 1) {
1046 // FIXME: Should reject these. The ARM backend hits this with $lane
1047 // in a bunch of instructions. It is unclear what the right answer is.
1049 errs() << "warning: '" << CGI.TheDef->getName() << "': "
1050 << "ignoring instruction with multi-operand tied operand '"
1051 << OI.Name << "'\n";
1058 OwningPtr<MatchableInfo> II(new MatchableInfo(CGI));
1060 II->Initialize(*this, SingletonRegisters);
1062 // Ignore instructions which shouldn't be matched and diagnose invalid
1063 // instruction definitions with an error.
1064 if (!II->Validate(CommentDelimiter, true))
1067 // Ignore "Int_*" and "*_Int" instructions, which are internal aliases.
1069 // FIXME: This is a total hack.
1070 if (StringRef(II->TheDef->getName()).startswith("Int_") ||
1071 StringRef(II->TheDef->getName()).endswith("_Int"))
1074 Matchables.push_back(II.take());
1077 // Parse all of the InstAlias definitions and stick them in the list of
1079 std::vector<Record*> AllInstAliases =
1080 Records.getAllDerivedDefinitions("InstAlias");
1081 for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) {
1082 CodeGenInstAlias *Alias = new CodeGenInstAlias(AllInstAliases[i], Target);
1084 OwningPtr<MatchableInfo> II(new MatchableInfo(Alias));
1086 II->Initialize(*this, SingletonRegisters);
1088 // Validate the alias definitions.
1089 II->Validate(CommentDelimiter, false);
1091 Matchables.push_back(II.take());
1094 // Build info for the register classes.
1095 BuildRegisterClasses(SingletonRegisters);
1097 // Build info for the user defined assembly operand classes.
1098 BuildOperandClasses();
1100 // Build the information about matchables, now that we have fully formed
1102 for (std::vector<MatchableInfo*>::iterator it = Matchables.begin(),
1103 ie = Matchables.end(); it != ie; ++it) {
1104 MatchableInfo *II = *it;
1106 // Parse the tokens after the mnemonic.
1107 for (unsigned i = 0, e = II->AsmOperands.size(); i != e; ++i) {
1108 MatchableInfo::AsmOperand &Op = II->AsmOperands[i];
1109 StringRef Token = Op.Token;
1111 // Check for singleton registers.
1112 if (Record *RegRecord = II->getSingletonRegisterForAsmOperand(i, *this)) {
1113 Op.Class = RegisterClasses[RegRecord];
1114 assert(Op.Class && Op.Class->Registers.size() == 1 &&
1115 "Unexpected class for singleton register");
1119 // Check for simple tokens.
1120 if (Token[0] != '$') {
1121 Op.Class = getTokenClass(Token);
1125 // Otherwise this is an operand reference.
1126 StringRef OperandName;
1127 if (Token[1] == '{')
1128 OperandName = Token.substr(2, Token.size() - 3);
1130 OperandName = Token.substr(1);
1132 if (II->DefRec.is<const CodeGenInstruction*>())
1133 BuildInstructionOperandReference(II, OperandName, Op);
1135 BuildAliasOperandReference(II, OperandName, Op);
1138 if (II->DefRec.is<const CodeGenInstruction*>())
1139 II->BuildInstructionResultOperands();
1141 II->BuildAliasResultOperands();
1144 // Reorder classes so that classes preceed super classes.
1145 std::sort(Classes.begin(), Classes.end(), less_ptr<ClassInfo>());
1148 /// BuildInstructionOperandReference - The specified operand is a reference to a
1149 /// named operand such as $src. Resolve the Class and OperandInfo pointers.
1150 void AsmMatcherInfo::
1151 BuildInstructionOperandReference(MatchableInfo *II,
1152 StringRef OperandName,
1153 MatchableInfo::AsmOperand &Op) {
1154 const CodeGenInstruction &CGI = *II->DefRec.get<const CodeGenInstruction*>();
1155 const CGIOperandList &Operands = CGI.Operands;
1157 // Map this token to an operand.
1159 if (!Operands.hasOperandNamed(OperandName, Idx))
1160 throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" +
1161 OperandName.str() + "'");
1163 // Set up the operand class.
1164 Op.Class = getOperandClass(Operands[Idx]);
1166 // If the named operand is tied, canonicalize it to the untied operand.
1167 // For example, something like:
1168 // (outs GPR:$dst), (ins GPR:$src)
1169 // with an asmstring of
1171 // we want to canonicalize to:
1173 // so that we know how to provide the $dst operand when filling in the result.
1174 int OITied = Operands[Idx].getTiedRegister();
1176 // The tied operand index is an MIOperand index, find the operand that
1178 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
1179 if (Operands[i].MIOperandNo == unsigned(OITied)) {
1180 OperandName = Operands[i].Name;
1186 Op.SrcOpName = OperandName;
1189 /// BuildAliasOperandReference - When parsing an operand reference out of the
1190 /// matching string (e.g. "movsx $src, $dst"), determine what the class of the
1191 /// operand reference is by looking it up in the result pattern definition.
1192 void AsmMatcherInfo::BuildAliasOperandReference(MatchableInfo *II,
1193 StringRef OperandName,
1194 MatchableInfo::AsmOperand &Op) {
1195 const CodeGenInstAlias &CGA = *II->DefRec.get<const CodeGenInstAlias*>();
1197 // Set up the operand class.
1198 for (unsigned i = 0, e = CGA.ResultOperands.size(); i != e; ++i)
1199 if (CGA.ResultOperands[i].isRecord() &&
1200 CGA.ResultOperands[i].getName() == OperandName) {
1201 // It's safe to go with the first one we find, because CodeGenInstAlias
1202 // validates that all operands with the same name have the same record.
1203 unsigned ResultIdx =CGA.getResultInstOperandIndexForResultOperandIndex(i);
1204 Op.Class = getOperandClass(CGA.ResultInst->Operands[ResultIdx]);
1205 Op.SrcOpName = OperandName;
1209 throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" +
1210 OperandName.str() + "'");
1213 void MatchableInfo::BuildInstructionResultOperands() {
1214 const CodeGenInstruction *ResultInst = getResultInst();
1216 // Loop over all operands of the result instruction, determining how to
1218 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1219 const CGIOperandList::OperandInfo &OpInfo = ResultInst->Operands[i];
1221 // If this is a tied operand, just copy from the previously handled operand.
1222 int TiedOp = OpInfo.getTiedRegister();
1224 ResOperands.push_back(ResOperand::getTiedOp(TiedOp, &OpInfo));
1228 // Find out what operand from the asmparser that this MCInst operand comes
1230 int SrcOperand = FindAsmOperandNamed(OpInfo.Name);
1232 if (!OpInfo.Name.empty() && SrcOperand != -1) {
1233 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, &OpInfo));
1237 throw TGError(TheDef->getLoc(), "Instruction '" +
1238 TheDef->getName() + "' has operand '" + OpInfo.Name +
1239 "' that doesn't appear in asm string!");
1243 void MatchableInfo::BuildAliasResultOperands() {
1244 const CodeGenInstAlias &CGA = *DefRec.get<const CodeGenInstAlias*>();
1245 const CodeGenInstruction *ResultInst = getResultInst();
1247 // Loop over all operands of the result instruction, determining how to
1249 unsigned AliasOpNo = 0;
1250 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1251 const CGIOperandList::OperandInfo &OpInfo = ResultInst->Operands[i];
1253 // If this is a tied operand, just copy from the previously handled operand.
1254 int TiedOp = OpInfo.getTiedRegister();
1256 ResOperands.push_back(ResOperand::getTiedOp(TiedOp, &OpInfo));
1260 // Find out what operand from the asmparser that this MCInst operand comes
1262 switch (CGA.ResultOperands[AliasOpNo].Kind) {
1263 case CodeGenInstAlias::ResultOperand::K_Record: {
1264 StringRef Name = CGA.ResultOperands[AliasOpNo++].getName();
1265 int SrcOperand = FindAsmOperandNamed(Name);
1266 if (SrcOperand != -1) {
1267 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, &OpInfo));
1271 throw TGError(TheDef->getLoc(), "Instruction '" +
1272 TheDef->getName() + "' has operand '" + OpInfo.Name +
1273 "' that doesn't appear in asm string!");
1275 case CodeGenInstAlias::ResultOperand::K_Imm: {
1276 int64_t ImmVal = CGA.ResultOperands[AliasOpNo++].getImm();
1277 ResOperands.push_back(ResOperand::getImmOp(ImmVal, &OpInfo));
1281 case CodeGenInstAlias::ResultOperand::K_Reg: {
1282 Record *Reg = CGA.ResultOperands[AliasOpNo++].getRegister();
1283 ResOperands.push_back(ResOperand::getRegOp(Reg, &OpInfo));
1290 static void EmitConvertToMCInst(CodeGenTarget &Target,
1291 std::vector<MatchableInfo*> &Infos,
1293 // Write the convert function to a separate stream, so we can drop it after
1295 std::string ConvertFnBody;
1296 raw_string_ostream CvtOS(ConvertFnBody);
1298 // Function we have already generated.
1299 std::set<std::string> GeneratedFns;
1301 // Start the unified conversion function.
1302 CvtOS << "static void ConvertToMCInst(ConversionKind Kind, MCInst &Inst, "
1303 << "unsigned Opcode,\n"
1304 << " const SmallVectorImpl<MCParsedAsmOperand*"
1305 << "> &Operands) {\n";
1306 CvtOS << " Inst.setOpcode(Opcode);\n";
1307 CvtOS << " switch (Kind) {\n";
1308 CvtOS << " default:\n";
1310 // Start the enum, which we will generate inline.
1312 OS << "// Unified function for converting operands to MCInst instances.\n\n";
1313 OS << "enum ConversionKind {\n";
1315 // TargetOperandClass - This is the target's operand class, like X86Operand.
1316 std::string TargetOperandClass = Target.getName() + "Operand";
1318 for (std::vector<MatchableInfo*>::const_iterator it = Infos.begin(),
1319 ie = Infos.end(); it != ie; ++it) {
1320 MatchableInfo &II = **it;
1322 // Build the conversion function signature.
1323 std::string Signature = "Convert";
1324 std::string CaseBody;
1325 raw_string_ostream CaseOS(CaseBody);
1327 // Compute the convert enum and the case body.
1328 for (unsigned i = 0, e = II.ResOperands.size(); i != e; ++i) {
1329 const MatchableInfo::ResOperand &OpInfo = II.ResOperands[i];
1331 // Generate code to populate each result operand.
1332 switch (OpInfo.Kind) {
1333 case MatchableInfo::ResOperand::RenderAsmOperand: {
1334 // This comes from something we parsed.
1335 MatchableInfo::AsmOperand &Op = II.AsmOperands[OpInfo.AsmOperandNum];
1337 // Registers are always converted the same, don't duplicate the
1338 // conversion function based on them.
1340 if (Op.Class->isRegisterClass())
1343 Signature += Op.Class->ClassName;
1344 Signature += utostr(OpInfo.OpInfo->MINumOperands);
1345 Signature += "_" + itostr(OpInfo.AsmOperandNum);
1347 CaseOS << " ((" << TargetOperandClass << "*)Operands["
1348 << (OpInfo.AsmOperandNum+1) << "])->" << Op.Class->RenderMethod
1349 << "(Inst, " << OpInfo.OpInfo->MINumOperands << ");\n";
1353 case MatchableInfo::ResOperand::TiedOperand: {
1354 // If this operand is tied to a previous one, just copy the MCInst
1355 // operand from the earlier one.We can only tie single MCOperand values.
1356 //assert(OpInfo.OpInfo->MINumOperands == 1 && "Not a singular MCOperand");
1357 unsigned TiedOp = OpInfo.TiedOperandNum;
1358 assert(i > TiedOp && "Tied operand preceeds its target!");
1359 CaseOS << " Inst.addOperand(Inst.getOperand(" << TiedOp << "));\n";
1360 Signature += "__Tie" + utostr(TiedOp);
1363 case MatchableInfo::ResOperand::ImmOperand: {
1364 int64_t Val = OpInfo.ImmVal;
1365 CaseOS << " Inst.addOperand(MCOperand::CreateImm(" << Val << "));\n";
1366 Signature += "__imm" + itostr(Val);
1369 case MatchableInfo::ResOperand::RegOperand: {
1370 std::string N = getQualifiedName(OpInfo.Register);
1371 CaseOS << " Inst.addOperand(MCOperand::CreateReg(" << N << "));\n";
1372 Signature += "__reg" + OpInfo.Register->getName();
1377 II.ConversionFnKind = Signature;
1379 // Check if we have already generated this signature.
1380 if (!GeneratedFns.insert(Signature).second)
1383 // If not, emit it now. Add to the enum list.
1384 OS << " " << Signature << ",\n";
1386 CvtOS << " case " << Signature << ":\n";
1387 CvtOS << CaseOS.str();
1388 CvtOS << " return;\n";
1391 // Finish the convert function.
1396 // Finish the enum, and drop the convert function after it.
1398 OS << " NumConversionVariants\n";
1404 /// EmitMatchClassEnumeration - Emit the enumeration for match class kinds.
1405 static void EmitMatchClassEnumeration(CodeGenTarget &Target,
1406 std::vector<ClassInfo*> &Infos,
1408 OS << "namespace {\n\n";
1410 OS << "/// MatchClassKind - The kinds of classes which participate in\n"
1411 << "/// instruction matching.\n";
1412 OS << "enum MatchClassKind {\n";
1413 OS << " InvalidMatchClass = 0,\n";
1414 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1415 ie = Infos.end(); it != ie; ++it) {
1416 ClassInfo &CI = **it;
1417 OS << " " << CI.Name << ", // ";
1418 if (CI.Kind == ClassInfo::Token) {
1419 OS << "'" << CI.ValueName << "'\n";
1420 } else if (CI.isRegisterClass()) {
1421 if (!CI.ValueName.empty())
1422 OS << "register class '" << CI.ValueName << "'\n";
1424 OS << "derived register class\n";
1426 OS << "user defined class '" << CI.ValueName << "'\n";
1429 OS << " NumMatchClassKinds\n";
1435 /// EmitClassifyOperand - Emit the function to classify an operand.
1436 static void EmitClassifyOperand(AsmMatcherInfo &Info,
1438 OS << "static MatchClassKind ClassifyOperand(MCParsedAsmOperand *GOp) {\n"
1439 << " " << Info.Target.getName() << "Operand &Operand = *("
1440 << Info.Target.getName() << "Operand*)GOp;\n";
1443 OS << " if (Operand.isToken())\n";
1444 OS << " return MatchTokenString(Operand.getToken());\n\n";
1446 // Classify registers.
1448 // FIXME: Don't hardcode isReg, getReg.
1449 OS << " if (Operand.isReg()) {\n";
1450 OS << " switch (Operand.getReg()) {\n";
1451 OS << " default: return InvalidMatchClass;\n";
1452 for (std::map<Record*, ClassInfo*>::iterator
1453 it = Info.RegisterClasses.begin(), ie = Info.RegisterClasses.end();
1455 OS << " case " << Info.Target.getName() << "::"
1456 << it->first->getName() << ": return " << it->second->Name << ";\n";
1460 // Classify user defined operands.
1461 for (std::vector<ClassInfo*>::iterator it = Info.Classes.begin(),
1462 ie = Info.Classes.end(); it != ie; ++it) {
1463 ClassInfo &CI = **it;
1465 if (!CI.isUserClass())
1468 OS << " // '" << CI.ClassName << "' class";
1469 if (!CI.SuperClasses.empty()) {
1470 OS << ", subclass of ";
1471 for (unsigned i = 0, e = CI.SuperClasses.size(); i != e; ++i) {
1473 OS << "'" << CI.SuperClasses[i]->ClassName << "'";
1474 assert(CI < *CI.SuperClasses[i] && "Invalid class relation!");
1479 OS << " if (Operand." << CI.PredicateMethod << "()) {\n";
1481 // Validate subclass relationships.
1482 if (!CI.SuperClasses.empty()) {
1483 for (unsigned i = 0, e = CI.SuperClasses.size(); i != e; ++i)
1484 OS << " assert(Operand." << CI.SuperClasses[i]->PredicateMethod
1485 << "() && \"Invalid class relationship!\");\n";
1488 OS << " return " << CI.Name << ";\n";
1491 OS << " return InvalidMatchClass;\n";
1495 /// EmitIsSubclass - Emit the subclass predicate function.
1496 static void EmitIsSubclass(CodeGenTarget &Target,
1497 std::vector<ClassInfo*> &Infos,
1499 OS << "/// IsSubclass - Compute whether \\arg A is a subclass of \\arg B.\n";
1500 OS << "static bool IsSubclass(MatchClassKind A, MatchClassKind B) {\n";
1501 OS << " if (A == B)\n";
1502 OS << " return true;\n\n";
1504 OS << " switch (A) {\n";
1505 OS << " default:\n";
1506 OS << " return false;\n";
1507 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1508 ie = Infos.end(); it != ie; ++it) {
1509 ClassInfo &A = **it;
1511 if (A.Kind != ClassInfo::Token) {
1512 std::vector<StringRef> SuperClasses;
1513 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1514 ie = Infos.end(); it != ie; ++it) {
1515 ClassInfo &B = **it;
1517 if (&A != &B && A.isSubsetOf(B))
1518 SuperClasses.push_back(B.Name);
1521 if (SuperClasses.empty())
1524 OS << "\n case " << A.Name << ":\n";
1526 if (SuperClasses.size() == 1) {
1527 OS << " return B == " << SuperClasses.back() << ";\n";
1531 OS << " switch (B) {\n";
1532 OS << " default: return false;\n";
1533 for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i)
1534 OS << " case " << SuperClasses[i] << ": return true;\n";
1544 /// EmitMatchTokenString - Emit the function to match a token string to the
1545 /// appropriate match class value.
1546 static void EmitMatchTokenString(CodeGenTarget &Target,
1547 std::vector<ClassInfo*> &Infos,
1549 // Construct the match list.
1550 std::vector<StringMatcher::StringPair> Matches;
1551 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1552 ie = Infos.end(); it != ie; ++it) {
1553 ClassInfo &CI = **it;
1555 if (CI.Kind == ClassInfo::Token)
1556 Matches.push_back(StringMatcher::StringPair(CI.ValueName,
1557 "return " + CI.Name + ";"));
1560 OS << "static MatchClassKind MatchTokenString(StringRef Name) {\n";
1562 StringMatcher("Name", Matches, OS).Emit();
1564 OS << " return InvalidMatchClass;\n";
1568 /// EmitMatchRegisterName - Emit the function to match a string to the target
1569 /// specific register enum.
1570 static void EmitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
1572 // Construct the match list.
1573 std::vector<StringMatcher::StringPair> Matches;
1574 for (unsigned i = 0, e = Target.getRegisters().size(); i != e; ++i) {
1575 const CodeGenRegister &Reg = Target.getRegisters()[i];
1576 if (Reg.TheDef->getValueAsString("AsmName").empty())
1579 Matches.push_back(StringMatcher::StringPair(
1580 Reg.TheDef->getValueAsString("AsmName"),
1581 "return " + utostr(i + 1) + ";"));
1584 OS << "static unsigned MatchRegisterName(StringRef Name) {\n";
1586 StringMatcher("Name", Matches, OS).Emit();
1588 OS << " return 0;\n";
1592 /// EmitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag
1594 static void EmitSubtargetFeatureFlagEnumeration(AsmMatcherInfo &Info,
1596 OS << "// Flags for subtarget features that participate in "
1597 << "instruction matching.\n";
1598 OS << "enum SubtargetFeatureFlag {\n";
1599 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
1600 it = Info.SubtargetFeatures.begin(),
1601 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
1602 SubtargetFeatureInfo &SFI = *it->second;
1603 OS << " " << SFI.getEnumName() << " = (1 << " << SFI.Index << "),\n";
1605 OS << " Feature_None = 0\n";
1609 /// EmitComputeAvailableFeatures - Emit the function to compute the list of
1610 /// available features given a subtarget.
1611 static void EmitComputeAvailableFeatures(AsmMatcherInfo &Info,
1613 std::string ClassName =
1614 Info.AsmParser->getValueAsString("AsmParserClassName");
1616 OS << "unsigned " << Info.Target.getName() << ClassName << "::\n"
1617 << "ComputeAvailableFeatures(const " << Info.Target.getName()
1618 << "Subtarget *Subtarget) const {\n";
1619 OS << " unsigned Features = 0;\n";
1620 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
1621 it = Info.SubtargetFeatures.begin(),
1622 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
1623 SubtargetFeatureInfo &SFI = *it->second;
1624 OS << " if (" << SFI.TheDef->getValueAsString("CondString")
1626 OS << " Features |= " << SFI.getEnumName() << ";\n";
1628 OS << " return Features;\n";
1632 static std::string GetAliasRequiredFeatures(Record *R,
1633 const AsmMatcherInfo &Info) {
1634 std::vector<Record*> ReqFeatures = R->getValueAsListOfDefs("Predicates");
1636 unsigned NumFeatures = 0;
1637 for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) {
1638 SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]);
1641 throw TGError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() +
1642 "' is not marked as an AssemblerPredicate!");
1647 Result += F->getEnumName();
1651 if (NumFeatures > 1)
1652 Result = '(' + Result + ')';
1656 /// EmitMnemonicAliases - If the target has any MnemonicAlias<> definitions,
1657 /// emit a function for them and return true, otherwise return false.
1658 static bool EmitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info) {
1659 std::vector<Record*> Aliases =
1660 Records.getAllDerivedDefinitions("MnemonicAlias");
1661 if (Aliases.empty()) return false;
1663 OS << "static void ApplyMnemonicAliases(StringRef &Mnemonic, "
1664 "unsigned Features) {\n";
1666 // Keep track of all the aliases from a mnemonic. Use an std::map so that the
1667 // iteration order of the map is stable.
1668 std::map<std::string, std::vector<Record*> > AliasesFromMnemonic;
1670 for (unsigned i = 0, e = Aliases.size(); i != e; ++i) {
1671 Record *R = Aliases[i];
1672 AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R);
1675 // Process each alias a "from" mnemonic at a time, building the code executed
1676 // by the string remapper.
1677 std::vector<StringMatcher::StringPair> Cases;
1678 for (std::map<std::string, std::vector<Record*> >::iterator
1679 I = AliasesFromMnemonic.begin(), E = AliasesFromMnemonic.end();
1681 const std::vector<Record*> &ToVec = I->second;
1683 // Loop through each alias and emit code that handles each case. If there
1684 // are two instructions without predicates, emit an error. If there is one,
1686 std::string MatchCode;
1687 int AliasWithNoPredicate = -1;
1689 for (unsigned i = 0, e = ToVec.size(); i != e; ++i) {
1690 Record *R = ToVec[i];
1691 std::string FeatureMask = GetAliasRequiredFeatures(R, Info);
1693 // If this unconditionally matches, remember it for later and diagnose
1695 if (FeatureMask.empty()) {
1696 if (AliasWithNoPredicate != -1) {
1697 // We can't have two aliases from the same mnemonic with no predicate.
1698 PrintError(ToVec[AliasWithNoPredicate]->getLoc(),
1699 "two MnemonicAliases with the same 'from' mnemonic!");
1700 throw TGError(R->getLoc(), "this is the other MnemonicAlias.");
1703 AliasWithNoPredicate = i;
1707 if (!MatchCode.empty())
1708 MatchCode += "else ";
1709 MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n";
1710 MatchCode += " Mnemonic = \"" +R->getValueAsString("ToMnemonic")+"\";\n";
1713 if (AliasWithNoPredicate != -1) {
1714 Record *R = ToVec[AliasWithNoPredicate];
1715 if (!MatchCode.empty())
1716 MatchCode += "else\n ";
1717 MatchCode += "Mnemonic = \"" + R->getValueAsString("ToMnemonic")+"\";\n";
1720 MatchCode += "return;";
1722 Cases.push_back(std::make_pair(I->first, MatchCode));
1726 StringMatcher("Mnemonic", Cases, OS).Emit();
1732 void AsmMatcherEmitter::run(raw_ostream &OS) {
1733 CodeGenTarget Target;
1734 Record *AsmParser = Target.getAsmParser();
1735 std::string ClassName = AsmParser->getValueAsString("AsmParserClassName");
1737 // Compute the information on the instructions to match.
1738 AsmMatcherInfo Info(AsmParser, Target);
1741 // Sort the instruction table using the partial order on classes. We use
1742 // stable_sort to ensure that ambiguous instructions are still
1743 // deterministically ordered.
1744 std::stable_sort(Info.Matchables.begin(), Info.Matchables.end(),
1745 less_ptr<MatchableInfo>());
1747 DEBUG_WITH_TYPE("instruction_info", {
1748 for (std::vector<MatchableInfo*>::iterator
1749 it = Info.Matchables.begin(), ie = Info.Matchables.end();
1754 // Check for ambiguous matchables.
1755 DEBUG_WITH_TYPE("ambiguous_instrs", {
1756 unsigned NumAmbiguous = 0;
1757 for (unsigned i = 0, e = Info.Matchables.size(); i != e; ++i) {
1758 for (unsigned j = i + 1; j != e; ++j) {
1759 MatchableInfo &A = *Info.Matchables[i];
1760 MatchableInfo &B = *Info.Matchables[j];
1762 if (A.CouldMatchAmiguouslyWith(B)) {
1763 errs() << "warning: ambiguous matchables:\n";
1765 errs() << "\nis incomparable with:\n";
1773 errs() << "warning: " << NumAmbiguous
1774 << " ambiguous matchables!\n";
1777 // Write the output.
1779 EmitSourceFileHeader("Assembly Matcher Source Fragment", OS);
1781 // Information for the class declaration.
1782 OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
1783 OS << "#undef GET_ASSEMBLER_HEADER\n";
1784 OS << " // This should be included into the middle of the declaration of \n";
1785 OS << " // your subclasses implementation of TargetAsmParser.\n";
1786 OS << " unsigned ComputeAvailableFeatures(const " <<
1787 Target.getName() << "Subtarget *Subtarget) const;\n";
1788 OS << " enum MatchResultTy {\n";
1789 OS << " Match_Success, Match_MnemonicFail, Match_InvalidOperand,\n";
1790 OS << " Match_MissingFeature\n";
1792 OS << " MatchResultTy MatchInstructionImpl(const "
1793 << "SmallVectorImpl<MCParsedAsmOperand*>"
1794 << " &Operands, MCInst &Inst, unsigned &ErrorInfo);\n\n";
1795 OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n";
1800 OS << "\n#ifdef GET_REGISTER_MATCHER\n";
1801 OS << "#undef GET_REGISTER_MATCHER\n\n";
1803 // Emit the subtarget feature enumeration.
1804 EmitSubtargetFeatureFlagEnumeration(Info, OS);
1806 // Emit the function to match a register name to number.
1807 EmitMatchRegisterName(Target, AsmParser, OS);
1809 OS << "#endif // GET_REGISTER_MATCHER\n\n";
1812 OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
1813 OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
1815 // Generate the function that remaps for mnemonic aliases.
1816 bool HasMnemonicAliases = EmitMnemonicAliases(OS, Info);
1818 // Generate the unified function to convert operands into an MCInst.
1819 EmitConvertToMCInst(Target, Info.Matchables, OS);
1821 // Emit the enumeration for classes which participate in matching.
1822 EmitMatchClassEnumeration(Target, Info.Classes, OS);
1824 // Emit the routine to match token strings to their match class.
1825 EmitMatchTokenString(Target, Info.Classes, OS);
1827 // Emit the routine to classify an operand.
1828 EmitClassifyOperand(Info, OS);
1830 // Emit the subclass predicate routine.
1831 EmitIsSubclass(Target, Info.Classes, OS);
1833 // Emit the available features compute function.
1834 EmitComputeAvailableFeatures(Info, OS);
1837 size_t MaxNumOperands = 0;
1838 for (std::vector<MatchableInfo*>::const_iterator it =
1839 Info.Matchables.begin(), ie = Info.Matchables.end();
1841 MaxNumOperands = std::max(MaxNumOperands, (*it)->AsmOperands.size());
1844 // Emit the static match table; unused classes get initalized to 0 which is
1845 // guaranteed to be InvalidMatchClass.
1847 // FIXME: We can reduce the size of this table very easily. First, we change
1848 // it so that store the kinds in separate bit-fields for each index, which
1849 // only needs to be the max width used for classes at that index (we also need
1850 // to reject based on this during classification). If we then make sure to
1851 // order the match kinds appropriately (putting mnemonics last), then we
1852 // should only end up using a few bits for each class, especially the ones
1853 // following the mnemonic.
1854 OS << "namespace {\n";
1855 OS << " struct MatchEntry {\n";
1856 OS << " unsigned Opcode;\n";
1857 OS << " const char *Mnemonic;\n";
1858 OS << " ConversionKind ConvertFn;\n";
1859 OS << " MatchClassKind Classes[" << MaxNumOperands << "];\n";
1860 OS << " unsigned RequiredFeatures;\n";
1863 OS << "// Predicate for searching for an opcode.\n";
1864 OS << " struct LessOpcode {\n";
1865 OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n";
1866 OS << " return StringRef(LHS.Mnemonic) < RHS;\n";
1868 OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n";
1869 OS << " return LHS < StringRef(RHS.Mnemonic);\n";
1871 OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n";
1872 OS << " return StringRef(LHS.Mnemonic) < StringRef(RHS.Mnemonic);\n";
1876 OS << "} // end anonymous namespace.\n\n";
1878 OS << "static const MatchEntry MatchTable["
1879 << Info.Matchables.size() << "] = {\n";
1881 for (std::vector<MatchableInfo*>::const_iterator it =
1882 Info.Matchables.begin(), ie = Info.Matchables.end();
1884 MatchableInfo &II = **it;
1887 OS << " { " << Target.getName() << "::"
1888 << II.getResultInst()->TheDef->getName() << ", \"" << II.Mnemonic << "\""
1889 << ", " << II.ConversionFnKind << ", { ";
1890 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) {
1891 MatchableInfo::AsmOperand &Op = II.AsmOperands[i];
1894 OS << Op.Class->Name;
1898 // Write the required features mask.
1899 if (!II.RequiredFeatures.empty()) {
1900 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
1902 OS << II.RequiredFeatures[i]->getEnumName();
1912 // Finally, build the match function.
1913 OS << Target.getName() << ClassName << "::MatchResultTy "
1914 << Target.getName() << ClassName << "::\n"
1915 << "MatchInstructionImpl(const SmallVectorImpl<MCParsedAsmOperand*>"
1917 OS << " MCInst &Inst, unsigned &ErrorInfo) {\n";
1919 // Emit code to get the available features.
1920 OS << " // Get the current feature set.\n";
1921 OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n";
1923 OS << " // Get the instruction mnemonic, which is the first token.\n";
1924 OS << " StringRef Mnemonic = ((" << Target.getName()
1925 << "Operand*)Operands[0])->getToken();\n\n";
1927 if (HasMnemonicAliases) {
1928 OS << " // Process all MnemonicAliases to remap the mnemonic.\n";
1929 OS << " ApplyMnemonicAliases(Mnemonic, AvailableFeatures);\n\n";
1932 // Emit code to compute the class list for this operand vector.
1933 OS << " // Eliminate obvious mismatches.\n";
1934 OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n";
1935 OS << " ErrorInfo = " << (MaxNumOperands+1) << ";\n";
1936 OS << " return Match_InvalidOperand;\n";
1939 OS << " // Compute the class list for this operand vector.\n";
1940 OS << " MatchClassKind Classes[" << MaxNumOperands << "];\n";
1941 OS << " for (unsigned i = 1, e = Operands.size(); i != e; ++i) {\n";
1942 OS << " Classes[i-1] = ClassifyOperand(Operands[i]);\n\n";
1944 OS << " // Check for invalid operands before matching.\n";
1945 OS << " if (Classes[i-1] == InvalidMatchClass) {\n";
1946 OS << " ErrorInfo = i;\n";
1947 OS << " return Match_InvalidOperand;\n";
1951 OS << " // Mark unused classes.\n";
1952 OS << " for (unsigned i = Operands.size()-1, e = " << MaxNumOperands << "; "
1953 << "i != e; ++i)\n";
1954 OS << " Classes[i] = InvalidMatchClass;\n\n";
1956 OS << " // Some state to try to produce better error messages.\n";
1957 OS << " bool HadMatchOtherThanFeatures = false;\n\n";
1958 OS << " // Set ErrorInfo to the operand that mismatches if it is \n";
1959 OS << " // wrong for all instances of the instruction.\n";
1960 OS << " ErrorInfo = ~0U;\n";
1962 // Emit code to search the table.
1963 OS << " // Search the table.\n";
1964 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
1965 OS << " std::equal_range(MatchTable, MatchTable+"
1966 << Info.Matchables.size() << ", Mnemonic, LessOpcode());\n\n";
1968 OS << " // Return a more specific error code if no mnemonics match.\n";
1969 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
1970 OS << " return Match_MnemonicFail;\n\n";
1972 OS << " for (const MatchEntry *it = MnemonicRange.first, "
1973 << "*ie = MnemonicRange.second;\n";
1974 OS << " it != ie; ++it) {\n";
1976 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
1977 OS << " assert(Mnemonic == it->Mnemonic);\n";
1979 // Emit check that the subclasses match.
1980 OS << " bool OperandsValid = true;\n";
1981 OS << " for (unsigned i = 0; i != " << MaxNumOperands << "; ++i) {\n";
1982 OS << " if (IsSubclass(Classes[i], it->Classes[i]))\n";
1983 OS << " continue;\n";
1984 OS << " // If this operand is broken for all of the instances of this\n";
1985 OS << " // mnemonic, keep track of it so we can report loc info.\n";
1986 OS << " if (it == MnemonicRange.first || ErrorInfo == i+1)\n";
1987 OS << " ErrorInfo = i+1;\n";
1989 OS << " ErrorInfo = ~0U;";
1990 OS << " // Otherwise, just reject this instance of the mnemonic.\n";
1991 OS << " OperandsValid = false;\n";
1995 OS << " if (!OperandsValid) continue;\n";
1997 // Emit check that the required features are available.
1998 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
1999 << "!= it->RequiredFeatures) {\n";
2000 OS << " HadMatchOtherThanFeatures = true;\n";
2001 OS << " continue;\n";
2005 OS << " ConvertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n";
2007 // Call the post-processing function, if used.
2008 std::string InsnCleanupFn =
2009 AsmParser->getValueAsString("AsmParserInstCleanup");
2010 if (!InsnCleanupFn.empty())
2011 OS << " " << InsnCleanupFn << "(Inst);\n";
2013 OS << " return Match_Success;\n";
2016 OS << " // Okay, we had no match. Try to return a useful error code.\n";
2017 OS << " if (HadMatchOtherThanFeatures) return Match_MissingFeature;\n";
2018 OS << " return Match_InvalidOperand;\n";
2021 OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";