1 //===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits a target specifier matcher for converting parsed
11 // assembly operands in the MCInst structures.
13 // The input to the target specific matcher is a list of literal tokens and
14 // operands. The target specific parser should generally eliminate any syntax
15 // which is not relevant for matching; for example, comma tokens should have
16 // already been consumed and eliminated by the parser. Most instructions will
17 // end up with a single literal token (the instruction name) and some number of
20 // Some example inputs, for X86:
21 // 'addl' (immediate ...) (register ...)
22 // 'add' (immediate ...) (memory ...)
25 // The assembly matcher is responsible for converting this input into a precise
26 // machine instruction (i.e., an instruction with a well defined encoding). This
27 // mapping has several properties which complicate matching:
29 // - It may be ambiguous; many architectures can legally encode particular
30 // variants of an instruction in different ways (for example, using a smaller
31 // encoding for small immediates). Such ambiguities should never be
32 // arbitrarily resolved by the assembler, the assembler is always responsible
33 // for choosing the "best" available instruction.
35 // - It may depend on the subtarget or the assembler context. Instructions
36 // which are invalid for the current mode, but otherwise unambiguous (e.g.,
37 // an SSE instruction in a file being assembled for i486) should be accepted
38 // and rejected by the assembler front end. However, if the proper encoding
39 // for an instruction is dependent on the assembler context then the matcher
40 // is responsible for selecting the correct machine instruction for the
43 // The core matching algorithm attempts to exploit the regularity in most
44 // instruction sets to quickly determine the set of possibly matching
45 // instructions, and the simplify the generated code. Additionally, this helps
46 // to ensure that the ambiguities are intentionally resolved by the user.
48 // The matching is divided into two distinct phases:
50 // 1. Classification: Each operand is mapped to the unique set which (a)
51 // contains it, and (b) is the largest such subset for which a single
52 // instruction could match all members.
54 // For register classes, we can generate these subgroups automatically. For
55 // arbitrary operands, we expect the user to define the classes and their
56 // relations to one another (for example, 8-bit signed immediates as a
57 // subset of 32-bit immediates).
59 // By partitioning the operands in this way, we guarantee that for any
60 // tuple of classes, any single instruction must match either all or none
61 // of the sets of operands which could classify to that tuple.
63 // In addition, the subset relation amongst classes induces a partial order
64 // on such tuples, which we use to resolve ambiguities.
66 // 2. The input can now be treated as a tuple of classes (static tokens are
67 // simple singleton sets). Each such tuple should generally map to a single
68 // instruction (we currently ignore cases where this isn't true, whee!!!),
69 // which we can emit a simple matcher for.
71 //===----------------------------------------------------------------------===//
73 #include "AsmMatcherEmitter.h"
74 #include "CodeGenTarget.h"
76 #include "StringMatcher.h"
77 #include "llvm/ADT/OwningPtr.h"
78 #include "llvm/ADT/PointerUnion.h"
79 #include "llvm/ADT/SmallPtrSet.h"
80 #include "llvm/ADT/SmallVector.h"
81 #include "llvm/ADT/STLExtras.h"
82 #include "llvm/ADT/StringExtras.h"
83 #include "llvm/Support/CommandLine.h"
84 #include "llvm/Support/Debug.h"
89 static cl::opt<std::string>
90 MatchPrefix("match-prefix", cl::init(""),
91 cl::desc("Only match instructions with the given prefix"));
96 struct SubtargetFeatureInfo;
98 /// ClassInfo - Helper class for storing the information about a particular
99 /// class of operands which can be matched.
102 /// Invalid kind, for use as a sentinel value.
105 /// The class for a particular token.
108 /// The (first) register class, subsequent register classes are
109 /// RegisterClass0+1, and so on.
112 /// The (first) user defined class, subsequent user defined classes are
113 /// UserClass0+1, and so on.
117 /// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
118 /// N) for the Nth user defined class.
121 /// SuperClasses - The super classes of this class. Note that for simplicities
122 /// sake user operands only record their immediate super class, while register
123 /// operands include all superclasses.
124 std::vector<ClassInfo*> SuperClasses;
126 /// Name - The full class name, suitable for use in an enum.
129 /// ClassName - The unadorned generic name for this class (e.g., Token).
130 std::string ClassName;
132 /// ValueName - The name of the value this class represents; for a token this
133 /// is the literal token string, for an operand it is the TableGen class (or
134 /// empty if this is a derived class).
135 std::string ValueName;
137 /// PredicateMethod - The name of the operand method to test whether the
138 /// operand matches this class; this is not valid for Token or register kinds.
139 std::string PredicateMethod;
141 /// RenderMethod - The name of the operand method to add this operand to an
142 /// MCInst; this is not valid for Token or register kinds.
143 std::string RenderMethod;
145 /// For register classes, the records for all the registers in this class.
146 std::set<Record*> Registers;
149 /// isRegisterClass() - Check if this is a register class.
150 bool isRegisterClass() const {
151 return Kind >= RegisterClass0 && Kind < UserClass0;
154 /// isUserClass() - Check if this is a user defined class.
155 bool isUserClass() const {
156 return Kind >= UserClass0;
159 /// isRelatedTo - Check whether this class is "related" to \arg RHS. Classes
160 /// are related if they are in the same class hierarchy.
161 bool isRelatedTo(const ClassInfo &RHS) const {
162 // Tokens are only related to tokens.
163 if (Kind == Token || RHS.Kind == Token)
164 return Kind == Token && RHS.Kind == Token;
166 // Registers classes are only related to registers classes, and only if
167 // their intersection is non-empty.
168 if (isRegisterClass() || RHS.isRegisterClass()) {
169 if (!isRegisterClass() || !RHS.isRegisterClass())
172 std::set<Record*> Tmp;
173 std::insert_iterator< std::set<Record*> > II(Tmp, Tmp.begin());
174 std::set_intersection(Registers.begin(), Registers.end(),
175 RHS.Registers.begin(), RHS.Registers.end(),
181 // Otherwise we have two users operands; they are related if they are in the
182 // same class hierarchy.
184 // FIXME: This is an oversimplification, they should only be related if they
185 // intersect, however we don't have that information.
186 assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");
187 const ClassInfo *Root = this;
188 while (!Root->SuperClasses.empty())
189 Root = Root->SuperClasses.front();
191 const ClassInfo *RHSRoot = &RHS;
192 while (!RHSRoot->SuperClasses.empty())
193 RHSRoot = RHSRoot->SuperClasses.front();
195 return Root == RHSRoot;
198 /// isSubsetOf - Test whether this class is a subset of \arg RHS;
199 bool isSubsetOf(const ClassInfo &RHS) const {
200 // This is a subset of RHS if it is the same class...
204 // ... or if any of its super classes are a subset of RHS.
205 for (std::vector<ClassInfo*>::const_iterator it = SuperClasses.begin(),
206 ie = SuperClasses.end(); it != ie; ++it)
207 if ((*it)->isSubsetOf(RHS))
213 /// operator< - Compare two classes.
214 bool operator<(const ClassInfo &RHS) const {
218 // Unrelated classes can be ordered by kind.
219 if (!isRelatedTo(RHS))
220 return Kind < RHS.Kind;
224 assert(0 && "Invalid kind!");
226 // Tokens are comparable by value.
228 // FIXME: Compare by enum value.
229 return ValueName < RHS.ValueName;
232 // This class preceeds the RHS if it is a proper subset of the RHS.
235 if (RHS.isSubsetOf(*this))
238 // Otherwise, order by name to ensure we have a total ordering.
239 return ValueName < RHS.ValueName;
244 /// MatchableInfo - Helper class for storing the necessary information for an
245 /// instruction or alias which is capable of being matched.
246 struct MatchableInfo {
248 /// Token - This is the token that the operand came from.
251 /// The unique class instance this operand should match.
254 /// The operand name this is, if anything.
257 explicit AsmOperand(StringRef T) : Token(T), Class(0) {}
260 /// ResOperand - This represents a single operand in the result instruction
261 /// generated by the match. In cases (like addressing modes) where a single
262 /// assembler operand expands to multiple MCOperands, this represents the
263 /// single assembler operand, not the MCOperand.
266 /// RenderAsmOperand - This represents an operand result that is
267 /// generated by calling the render method on the assembly operand. The
268 /// corresponding AsmOperand is specified by AsmOperandNum.
271 /// TiedOperand - This represents a result operand that is a duplicate of
272 /// a previous result operand.
275 /// ImmOperand - This represents an immediate value that is dumped into
279 /// RegOperand - This represents a fixed register that is dumped in.
284 /// This is the operand # in the AsmOperands list that this should be
286 unsigned AsmOperandNum;
288 /// TiedOperandNum - This is the (earlier) result operand that should be
290 unsigned TiedOperandNum;
292 /// ImmVal - This is the immediate value added to the instruction.
295 /// Register - This is the register record.
299 /// OpInfo - This is the information about the instruction operand that is
301 const CGIOperandList::OperandInfo *OpInfo;
303 static ResOperand getRenderedOp(unsigned AsmOpNum,
304 const CGIOperandList::OperandInfo *Op) {
306 X.Kind = RenderAsmOperand;
307 X.AsmOperandNum = AsmOpNum;
312 static ResOperand getTiedOp(unsigned TiedOperandNum,
313 const CGIOperandList::OperandInfo *Op) {
315 X.Kind = TiedOperand;
316 X.TiedOperandNum = TiedOperandNum;
321 static ResOperand getImmOp(int64_t Val,
322 const CGIOperandList::OperandInfo *Op) {
330 static ResOperand getRegOp(Record *Reg,
331 const CGIOperandList::OperandInfo *Op) {
341 /// TheDef - This is the definition of the instruction or InstAlias that this
342 /// matchable came from.
343 Record *const TheDef;
345 /// DefRec - This is the definition that it came from.
346 PointerUnion<const CodeGenInstruction*, const CodeGenInstAlias*> DefRec;
348 const CodeGenInstruction *getResultInst() const {
349 if (DefRec.is<const CodeGenInstruction*>())
350 return DefRec.get<const CodeGenInstruction*>();
351 return DefRec.get<const CodeGenInstAlias*>()->ResultInst;
354 /// ResOperands - This is the operand list that should be built for the result
356 std::vector<ResOperand> ResOperands;
358 /// AsmString - The assembly string for this instruction (with variants
359 /// removed), e.g. "movsx $src, $dst".
360 std::string AsmString;
362 /// Mnemonic - This is the first token of the matched instruction, its
366 /// AsmOperands - The textual operands that this instruction matches,
367 /// annotated with a class and where in the OperandList they were defined.
368 /// This directly corresponds to the tokenized AsmString after the mnemonic is
370 SmallVector<AsmOperand, 4> AsmOperands;
372 /// Predicates - The required subtarget features to match this instruction.
373 SmallVector<SubtargetFeatureInfo*, 4> RequiredFeatures;
375 /// ConversionFnKind - The enum value which is passed to the generated
376 /// ConvertToMCInst to convert parsed operands into an MCInst for this
378 std::string ConversionFnKind;
380 MatchableInfo(const CodeGenInstruction &CGI)
381 : TheDef(CGI.TheDef), DefRec(&CGI), AsmString(CGI.AsmString) {
384 MatchableInfo(const CodeGenInstAlias *Alias)
385 : TheDef(Alias->TheDef), DefRec(Alias), AsmString(Alias->AsmString) {
388 void Initialize(const AsmMatcherInfo &Info,
389 SmallPtrSet<Record*, 16> &SingletonRegisters);
391 /// Validate - Return true if this matchable is a valid thing to match against
392 /// and perform a bunch of validity checking.
393 bool Validate(StringRef CommentDelimiter, bool Hack) const;
395 /// getSingletonRegisterForAsmOperand - If the specified token is a singleton
396 /// register, return the Record for it, otherwise return null.
397 Record *getSingletonRegisterForAsmOperand(unsigned i,
398 const AsmMatcherInfo &Info) const;
400 int FindAsmOperandNamed(StringRef N) const {
401 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
402 if (N == AsmOperands[i].SrcOpName)
407 void BuildInstructionResultOperands();
408 void BuildAliasResultOperands();
410 /// operator< - Compare two matchables.
411 bool operator<(const MatchableInfo &RHS) const {
412 // The primary comparator is the instruction mnemonic.
413 if (Mnemonic != RHS.Mnemonic)
414 return Mnemonic < RHS.Mnemonic;
416 if (AsmOperands.size() != RHS.AsmOperands.size())
417 return AsmOperands.size() < RHS.AsmOperands.size();
419 // Compare lexicographically by operand. The matcher validates that other
420 // orderings wouldn't be ambiguous using \see CouldMatchAmiguouslyWith().
421 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
422 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
424 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
431 /// CouldMatchAmiguouslyWith - Check whether this matchable could
432 /// ambiguously match the same set of operands as \arg RHS (without being a
433 /// strictly superior match).
434 bool CouldMatchAmiguouslyWith(const MatchableInfo &RHS) {
435 // The primary comparator is the instruction mnemonic.
436 if (Mnemonic != RHS.Mnemonic)
439 // The number of operands is unambiguous.
440 if (AsmOperands.size() != RHS.AsmOperands.size())
443 // Otherwise, make sure the ordering of the two instructions is unambiguous
444 // by checking that either (a) a token or operand kind discriminates them,
445 // or (b) the ordering among equivalent kinds is consistent.
447 // Tokens and operand kinds are unambiguous (assuming a correct target
449 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
450 if (AsmOperands[i].Class->Kind != RHS.AsmOperands[i].Class->Kind ||
451 AsmOperands[i].Class->Kind == ClassInfo::Token)
452 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class ||
453 *RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
456 // Otherwise, this operand could commute if all operands are equivalent, or
457 // there is a pair of operands that compare less than and a pair that
458 // compare greater than.
459 bool HasLT = false, HasGT = false;
460 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
461 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
463 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
467 return !(HasLT ^ HasGT);
473 void TokenizeAsmString(const AsmMatcherInfo &Info);
476 /// SubtargetFeatureInfo - Helper class for storing information on a subtarget
477 /// feature which participates in instruction matching.
478 struct SubtargetFeatureInfo {
479 /// \brief The predicate record for this feature.
482 /// \brief An unique index assigned to represent this feature.
485 SubtargetFeatureInfo(Record *D, unsigned Idx) : TheDef(D), Index(Idx) {}
487 /// \brief The name of the enumerated constant identifying this feature.
488 std::string getEnumName() const {
489 return "Feature_" + TheDef->getName();
493 class AsmMatcherInfo {
495 /// The tablegen AsmParser record.
498 /// Target - The target information.
499 CodeGenTarget &Target;
501 /// The AsmParser "RegisterPrefix" value.
502 std::string RegisterPrefix;
504 /// The classes which are needed for matching.
505 std::vector<ClassInfo*> Classes;
507 /// The information on the matchables to match.
508 std::vector<MatchableInfo*> Matchables;
510 /// Map of Register records to their class information.
511 std::map<Record*, ClassInfo*> RegisterClasses;
513 /// Map of Predicate records to their subtarget information.
514 std::map<Record*, SubtargetFeatureInfo*> SubtargetFeatures;
517 /// Map of token to class information which has already been constructed.
518 std::map<std::string, ClassInfo*> TokenClasses;
520 /// Map of RegisterClass records to their class information.
521 std::map<Record*, ClassInfo*> RegisterClassClasses;
523 /// Map of AsmOperandClass records to their class information.
524 std::map<Record*, ClassInfo*> AsmOperandClasses;
527 /// getTokenClass - Lookup or create the class for the given token.
528 ClassInfo *getTokenClass(StringRef Token);
530 /// getOperandClass - Lookup or create the class for the given operand.
531 ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI);
533 /// BuildRegisterClasses - Build the ClassInfo* instances for register
535 void BuildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters);
537 /// BuildOperandClasses - Build the ClassInfo* instances for user defined
539 void BuildOperandClasses();
541 void BuildInstructionOperandReference(MatchableInfo *II,
543 MatchableInfo::AsmOperand &Op);
544 void BuildAliasOperandReference(MatchableInfo *II,
546 MatchableInfo::AsmOperand &Op);
549 AsmMatcherInfo(Record *AsmParser, CodeGenTarget &Target);
551 /// BuildInfo - Construct the various tables used during matching.
554 /// getSubtargetFeature - Lookup or create the subtarget feature info for the
556 SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const {
557 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
558 std::map<Record*, SubtargetFeatureInfo*>::const_iterator I =
559 SubtargetFeatures.find(Def);
560 return I == SubtargetFeatures.end() ? 0 : I->second;
566 void MatchableInfo::dump() {
567 errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n";
569 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
570 AsmOperand &Op = AsmOperands[i];
571 errs() << " op[" << i << "] = " << Op.Class->ClassName << " - ";
572 errs() << '\"' << Op.Token << "\"\n";
576 void MatchableInfo::Initialize(const AsmMatcherInfo &Info,
577 SmallPtrSet<Record*, 16> &SingletonRegisters) {
578 // TODO: Eventually support asmparser for Variant != 0.
579 AsmString = CodeGenInstruction::FlattenAsmStringVariants(AsmString, 0);
581 TokenizeAsmString(Info);
583 // Compute the require features.
584 std::vector<Record*> Predicates =TheDef->getValueAsListOfDefs("Predicates");
585 for (unsigned i = 0, e = Predicates.size(); i != e; ++i)
586 if (SubtargetFeatureInfo *Feature =
587 Info.getSubtargetFeature(Predicates[i]))
588 RequiredFeatures.push_back(Feature);
590 // Collect singleton registers, if used.
591 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
592 if (Record *Reg = getSingletonRegisterForAsmOperand(i, Info))
593 SingletonRegisters.insert(Reg);
597 /// TokenizeAsmString - Tokenize a simplified assembly string.
598 void MatchableInfo::TokenizeAsmString(const AsmMatcherInfo &Info) {
599 StringRef String = AsmString;
602 for (unsigned i = 0, e = String.size(); i != e; ++i) {
612 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
615 if (!isspace(String[i]) && String[i] != ',')
616 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
622 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
626 assert(i != String.size() && "Invalid quoted character");
627 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
633 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
637 // If this isn't "${", treat like a normal token.
638 if (i + 1 == String.size() || String[i + 1] != '{') {
643 StringRef::iterator End = std::find(String.begin() + i, String.end(),'}');
644 assert(End != String.end() && "Missing brace in operand reference!");
645 size_t EndPos = End - String.begin();
646 AsmOperands.push_back(AsmOperand(String.slice(i, EndPos+1)));
654 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
663 if (InTok && Prev != String.size())
664 AsmOperands.push_back(AsmOperand(String.substr(Prev)));
666 // The first token of the instruction is the mnemonic, which must be a
667 // simple string, not a $foo variable or a singleton register.
668 assert(!AsmOperands.empty() && "Instruction has no tokens?");
669 Mnemonic = AsmOperands[0].Token;
670 if (Mnemonic[0] == '$' || getSingletonRegisterForAsmOperand(0, Info))
671 throw TGError(TheDef->getLoc(),
672 "Invalid instruction mnemonic '" + Mnemonic.str() + "'!");
674 // Remove the first operand, it is tracked in the mnemonic field.
675 AsmOperands.erase(AsmOperands.begin());
680 bool MatchableInfo::Validate(StringRef CommentDelimiter, bool Hack) const {
681 // Reject matchables with no .s string.
682 if (AsmString.empty())
683 throw TGError(TheDef->getLoc(), "instruction with empty asm string");
685 // Reject any matchables with a newline in them, they should be marked
686 // isCodeGenOnly if they are pseudo instructions.
687 if (AsmString.find('\n') != std::string::npos)
688 throw TGError(TheDef->getLoc(),
689 "multiline instruction is not valid for the asmparser, "
690 "mark it isCodeGenOnly");
692 // Remove comments from the asm string. We know that the asmstring only
694 if (!CommentDelimiter.empty() &&
695 StringRef(AsmString).find(CommentDelimiter) != StringRef::npos)
696 throw TGError(TheDef->getLoc(),
697 "asmstring for instruction has comment character in it, "
698 "mark it isCodeGenOnly");
700 // Reject matchables with operand modifiers, these aren't something we can
701 /// handle, the target should be refactored to use operands instead of
704 // Also, check for instructions which reference the operand multiple times;
705 // this implies a constraint we would not honor.
706 std::set<std::string> OperandNames;
707 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
708 StringRef Tok = AsmOperands[i].Token;
709 if (Tok[0] == '$' && Tok.find(':') != StringRef::npos)
710 throw TGError(TheDef->getLoc(),
711 "matchable with operand modifier '" + Tok.str() +
712 "' not supported by asm matcher. Mark isCodeGenOnly!");
714 // Verify that any operand is only mentioned once.
715 // We reject aliases and ignore instructions for now.
716 if (Tok[0] == '$' && !OperandNames.insert(Tok).second) {
718 throw TGError(TheDef->getLoc(),
719 "ERROR: matchable with tied operand '" + Tok.str() +
720 "' can never be matched!");
721 // FIXME: Should reject these. The ARM backend hits this with $lane in a
722 // bunch of instructions. It is unclear what the right answer is.
724 errs() << "warning: '" << TheDef->getName() << "': "
725 << "ignoring instruction with tied operand '"
726 << Tok.str() << "'\n";
736 /// getSingletonRegisterForAsmOperand - If the specified token is a singleton
737 /// register, return the register name, otherwise return a null StringRef.
738 Record *MatchableInfo::
739 getSingletonRegisterForAsmOperand(unsigned i, const AsmMatcherInfo &Info) const{
740 StringRef Tok = AsmOperands[i].Token;
741 if (!Tok.startswith(Info.RegisterPrefix))
744 StringRef RegName = Tok.substr(Info.RegisterPrefix.size());
745 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName))
748 // If there is no register prefix (i.e. "%" in "%eax"), then this may
749 // be some random non-register token, just ignore it.
750 if (Info.RegisterPrefix.empty())
753 // Otherwise, we have something invalid prefixed with the register prefix,
755 std::string Err = "unable to find register for '" + RegName.str() +
756 "' (which matches register prefix)";
757 throw TGError(TheDef->getLoc(), Err);
761 static std::string getEnumNameForToken(StringRef Str) {
764 for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) {
766 case '*': Res += "_STAR_"; break;
767 case '%': Res += "_PCT_"; break;
768 case ':': Res += "_COLON_"; break;
769 case '!': Res += "_EXCLAIM_"; break;
774 Res += "_" + utostr((unsigned) *it) + "_";
781 ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) {
782 ClassInfo *&Entry = TokenClasses[Token];
785 Entry = new ClassInfo();
786 Entry->Kind = ClassInfo::Token;
787 Entry->ClassName = "Token";
788 Entry->Name = "MCK_" + getEnumNameForToken(Token);
789 Entry->ValueName = Token;
790 Entry->PredicateMethod = "<invalid>";
791 Entry->RenderMethod = "<invalid>";
792 Classes.push_back(Entry);
799 AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI) {
800 if (OI.Rec->isSubClassOf("RegisterClass")) {
801 if (ClassInfo *CI = RegisterClassClasses[OI.Rec])
803 throw TGError(OI.Rec->getLoc(), "register class has no class info!");
806 assert(OI.Rec->isSubClassOf("Operand") && "Unexpected operand!");
807 Record *MatchClass = OI.Rec->getValueAsDef("ParserMatchClass");
808 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
811 throw TGError(OI.Rec->getLoc(), "operand has no match class!");
814 void AsmMatcherInfo::
815 BuildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters) {
816 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
817 const std::vector<CodeGenRegisterClass> &RegClassList =
818 Target.getRegisterClasses();
820 // The register sets used for matching.
821 std::set< std::set<Record*> > RegisterSets;
823 // Gather the defined sets.
824 for (std::vector<CodeGenRegisterClass>::const_iterator it =
825 RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it)
826 RegisterSets.insert(std::set<Record*>(it->Elements.begin(),
827 it->Elements.end()));
829 // Add any required singleton sets.
830 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
831 ie = SingletonRegisters.end(); it != ie; ++it) {
833 RegisterSets.insert(std::set<Record*>(&Rec, &Rec + 1));
836 // Introduce derived sets where necessary (when a register does not determine
837 // a unique register set class), and build the mapping of registers to the set
838 // they should classify to.
839 std::map<Record*, std::set<Record*> > RegisterMap;
840 for (std::vector<CodeGenRegister>::const_iterator it = Registers.begin(),
841 ie = Registers.end(); it != ie; ++it) {
842 const CodeGenRegister &CGR = *it;
843 // Compute the intersection of all sets containing this register.
844 std::set<Record*> ContainingSet;
846 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
847 ie = RegisterSets.end(); it != ie; ++it) {
848 if (!it->count(CGR.TheDef))
851 if (ContainingSet.empty()) {
856 std::set<Record*> Tmp;
857 std::swap(Tmp, ContainingSet);
858 std::insert_iterator< std::set<Record*> > II(ContainingSet,
859 ContainingSet.begin());
860 std::set_intersection(Tmp.begin(), Tmp.end(), it->begin(), it->end(), II);
863 if (!ContainingSet.empty()) {
864 RegisterSets.insert(ContainingSet);
865 RegisterMap.insert(std::make_pair(CGR.TheDef, ContainingSet));
869 // Construct the register classes.
870 std::map<std::set<Record*>, ClassInfo*> RegisterSetClasses;
872 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
873 ie = RegisterSets.end(); it != ie; ++it, ++Index) {
874 ClassInfo *CI = new ClassInfo();
875 CI->Kind = ClassInfo::RegisterClass0 + Index;
876 CI->ClassName = "Reg" + utostr(Index);
877 CI->Name = "MCK_Reg" + utostr(Index);
879 CI->PredicateMethod = ""; // unused
880 CI->RenderMethod = "addRegOperands";
882 Classes.push_back(CI);
883 RegisterSetClasses.insert(std::make_pair(*it, CI));
886 // Find the superclasses; we could compute only the subgroup lattice edges,
887 // but there isn't really a point.
888 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
889 ie = RegisterSets.end(); it != ie; ++it) {
890 ClassInfo *CI = RegisterSetClasses[*it];
891 for (std::set< std::set<Record*> >::iterator it2 = RegisterSets.begin(),
892 ie2 = RegisterSets.end(); it2 != ie2; ++it2)
894 std::includes(it2->begin(), it2->end(), it->begin(), it->end()))
895 CI->SuperClasses.push_back(RegisterSetClasses[*it2]);
898 // Name the register classes which correspond to a user defined RegisterClass.
899 for (std::vector<CodeGenRegisterClass>::const_iterator
900 it = RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it) {
901 ClassInfo *CI = RegisterSetClasses[std::set<Record*>(it->Elements.begin(),
902 it->Elements.end())];
903 if (CI->ValueName.empty()) {
904 CI->ClassName = it->getName();
905 CI->Name = "MCK_" + it->getName();
906 CI->ValueName = it->getName();
908 CI->ValueName = CI->ValueName + "," + it->getName();
910 RegisterClassClasses.insert(std::make_pair(it->TheDef, CI));
913 // Populate the map for individual registers.
914 for (std::map<Record*, std::set<Record*> >::iterator it = RegisterMap.begin(),
915 ie = RegisterMap.end(); it != ie; ++it)
916 RegisterClasses[it->first] = RegisterSetClasses[it->second];
918 // Name the register classes which correspond to singleton registers.
919 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
920 ie = SingletonRegisters.end(); it != ie; ++it) {
922 ClassInfo *CI = RegisterClasses[Rec];
923 assert(CI && "Missing singleton register class info!");
925 if (CI->ValueName.empty()) {
926 CI->ClassName = Rec->getName();
927 CI->Name = "MCK_" + Rec->getName();
928 CI->ValueName = Rec->getName();
930 CI->ValueName = CI->ValueName + "," + Rec->getName();
934 void AsmMatcherInfo::BuildOperandClasses() {
935 std::vector<Record*> AsmOperands =
936 Records.getAllDerivedDefinitions("AsmOperandClass");
938 // Pre-populate AsmOperandClasses map.
939 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
940 ie = AsmOperands.end(); it != ie; ++it)
941 AsmOperandClasses[*it] = new ClassInfo();
944 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
945 ie = AsmOperands.end(); it != ie; ++it, ++Index) {
946 ClassInfo *CI = AsmOperandClasses[*it];
947 CI->Kind = ClassInfo::UserClass0 + Index;
949 ListInit *Supers = (*it)->getValueAsListInit("SuperClasses");
950 for (unsigned i = 0, e = Supers->getSize(); i != e; ++i) {
951 DefInit *DI = dynamic_cast<DefInit*>(Supers->getElement(i));
953 PrintError((*it)->getLoc(), "Invalid super class reference!");
957 ClassInfo *SC = AsmOperandClasses[DI->getDef()];
959 PrintError((*it)->getLoc(), "Invalid super class reference!");
961 CI->SuperClasses.push_back(SC);
963 CI->ClassName = (*it)->getValueAsString("Name");
964 CI->Name = "MCK_" + CI->ClassName;
965 CI->ValueName = (*it)->getName();
967 // Get or construct the predicate method name.
968 Init *PMName = (*it)->getValueInit("PredicateMethod");
969 if (StringInit *SI = dynamic_cast<StringInit*>(PMName)) {
970 CI->PredicateMethod = SI->getValue();
972 assert(dynamic_cast<UnsetInit*>(PMName) &&
973 "Unexpected PredicateMethod field!");
974 CI->PredicateMethod = "is" + CI->ClassName;
977 // Get or construct the render method name.
978 Init *RMName = (*it)->getValueInit("RenderMethod");
979 if (StringInit *SI = dynamic_cast<StringInit*>(RMName)) {
980 CI->RenderMethod = SI->getValue();
982 assert(dynamic_cast<UnsetInit*>(RMName) &&
983 "Unexpected RenderMethod field!");
984 CI->RenderMethod = "add" + CI->ClassName + "Operands";
987 AsmOperandClasses[*it] = CI;
988 Classes.push_back(CI);
992 AsmMatcherInfo::AsmMatcherInfo(Record *asmParser, CodeGenTarget &target)
993 : AsmParser(asmParser), Target(target),
994 RegisterPrefix(AsmParser->getValueAsString("RegisterPrefix")) {
998 void AsmMatcherInfo::BuildInfo() {
999 // Build information about all of the AssemblerPredicates.
1000 std::vector<Record*> AllPredicates =
1001 Records.getAllDerivedDefinitions("Predicate");
1002 for (unsigned i = 0, e = AllPredicates.size(); i != e; ++i) {
1003 Record *Pred = AllPredicates[i];
1004 // Ignore predicates that are not intended for the assembler.
1005 if (!Pred->getValueAsBit("AssemblerMatcherPredicate"))
1008 if (Pred->getName().empty())
1009 throw TGError(Pred->getLoc(), "Predicate has no name!");
1011 unsigned FeatureNo = SubtargetFeatures.size();
1012 SubtargetFeatures[Pred] = new SubtargetFeatureInfo(Pred, FeatureNo);
1013 assert(FeatureNo < 32 && "Too many subtarget features!");
1016 StringRef CommentDelimiter = AsmParser->getValueAsString("CommentDelimiter");
1018 // Parse the instructions; we need to do this first so that we can gather the
1019 // singleton register classes.
1020 SmallPtrSet<Record*, 16> SingletonRegisters;
1021 for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
1022 E = Target.inst_end(); I != E; ++I) {
1023 const CodeGenInstruction &CGI = **I;
1025 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1026 // filter the set of instructions we consider.
1027 if (!StringRef(CGI.TheDef->getName()).startswith(MatchPrefix))
1030 // Ignore "codegen only" instructions.
1031 if (CGI.TheDef->getValueAsBit("isCodeGenOnly"))
1034 // Validate the operand list to ensure we can handle this instruction.
1035 for (unsigned i = 0, e = CGI.Operands.size(); i != e; ++i) {
1036 const CGIOperandList::OperandInfo &OI = CGI.Operands[i];
1038 // Validate tied operands.
1039 if (OI.getTiedRegister() != -1) {
1040 // If we have a tied operand that consists of multiple MCOperands, reject
1041 // it. We reject aliases and ignore instructions for now.
1042 if (OI.MINumOperands != 1) {
1043 // FIXME: Should reject these. The ARM backend hits this with $lane
1044 // in a bunch of instructions. It is unclear what the right answer is.
1046 errs() << "warning: '" << CGI.TheDef->getName() << "': "
1047 << "ignoring instruction with multi-operand tied operand '"
1048 << OI.Name << "'\n";
1055 OwningPtr<MatchableInfo> II(new MatchableInfo(CGI));
1057 II->Initialize(*this, SingletonRegisters);
1059 // Ignore instructions which shouldn't be matched and diagnose invalid
1060 // instruction definitions with an error.
1061 if (!II->Validate(CommentDelimiter, true))
1064 // Ignore "Int_*" and "*_Int" instructions, which are internal aliases.
1066 // FIXME: This is a total hack.
1067 if (StringRef(II->TheDef->getName()).startswith("Int_") ||
1068 StringRef(II->TheDef->getName()).endswith("_Int"))
1071 Matchables.push_back(II.take());
1074 // Parse all of the InstAlias definitions and stick them in the list of
1076 std::vector<Record*> AllInstAliases =
1077 Records.getAllDerivedDefinitions("InstAlias");
1078 for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) {
1079 CodeGenInstAlias *Alias = new CodeGenInstAlias(AllInstAliases[i], Target);
1081 OwningPtr<MatchableInfo> II(new MatchableInfo(Alias));
1083 II->Initialize(*this, SingletonRegisters);
1085 // Validate the alias definitions.
1086 II->Validate(CommentDelimiter, false);
1088 Matchables.push_back(II.take());
1091 // Build info for the register classes.
1092 BuildRegisterClasses(SingletonRegisters);
1094 // Build info for the user defined assembly operand classes.
1095 BuildOperandClasses();
1097 // Build the information about matchables, now that we have fully formed
1099 for (std::vector<MatchableInfo*>::iterator it = Matchables.begin(),
1100 ie = Matchables.end(); it != ie; ++it) {
1101 MatchableInfo *II = *it;
1103 // Parse the tokens after the mnemonic.
1104 for (unsigned i = 0, e = II->AsmOperands.size(); i != e; ++i) {
1105 MatchableInfo::AsmOperand &Op = II->AsmOperands[i];
1106 StringRef Token = Op.Token;
1108 // Check for singleton registers.
1109 if (Record *RegRecord = II->getSingletonRegisterForAsmOperand(i, *this)) {
1110 Op.Class = RegisterClasses[RegRecord];
1111 assert(Op.Class && Op.Class->Registers.size() == 1 &&
1112 "Unexpected class for singleton register");
1116 // Check for simple tokens.
1117 if (Token[0] != '$') {
1118 Op.Class = getTokenClass(Token);
1122 if (Token.size() > 1 && isdigit(Token[1])) {
1123 Op.Class = getTokenClass(Token);
1127 // Otherwise this is an operand reference.
1128 StringRef OperandName;
1129 if (Token[1] == '{')
1130 OperandName = Token.substr(2, Token.size() - 3);
1132 OperandName = Token.substr(1);
1134 if (II->DefRec.is<const CodeGenInstruction*>())
1135 BuildInstructionOperandReference(II, OperandName, Op);
1137 BuildAliasOperandReference(II, OperandName, Op);
1140 if (II->DefRec.is<const CodeGenInstruction*>())
1141 II->BuildInstructionResultOperands();
1143 II->BuildAliasResultOperands();
1146 // Reorder classes so that classes preceed super classes.
1147 std::sort(Classes.begin(), Classes.end(), less_ptr<ClassInfo>());
1150 /// BuildInstructionOperandReference - The specified operand is a reference to a
1151 /// named operand such as $src. Resolve the Class and OperandInfo pointers.
1152 void AsmMatcherInfo::
1153 BuildInstructionOperandReference(MatchableInfo *II,
1154 StringRef OperandName,
1155 MatchableInfo::AsmOperand &Op) {
1156 const CodeGenInstruction &CGI = *II->DefRec.get<const CodeGenInstruction*>();
1157 const CGIOperandList &Operands = CGI.Operands;
1159 // Map this token to an operand.
1161 if (!Operands.hasOperandNamed(OperandName, Idx))
1162 throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" +
1163 OperandName.str() + "'");
1165 // Set up the operand class.
1166 Op.Class = getOperandClass(Operands[Idx]);
1168 // If the named operand is tied, canonicalize it to the untied operand.
1169 // For example, something like:
1170 // (outs GPR:$dst), (ins GPR:$src)
1171 // with an asmstring of
1173 // we want to canonicalize to:
1175 // so that we know how to provide the $dst operand when filling in the result.
1176 int OITied = Operands[Idx].getTiedRegister();
1178 // The tied operand index is an MIOperand index, find the operand that
1180 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
1181 if (Operands[i].MIOperandNo == unsigned(OITied)) {
1182 OperandName = Operands[i].Name;
1188 Op.SrcOpName = OperandName;
1191 /// BuildAliasOperandReference - When parsing an operand reference out of the
1192 /// matching string (e.g. "movsx $src, $dst"), determine what the class of the
1193 /// operand reference is by looking it up in the result pattern definition.
1194 void AsmMatcherInfo::BuildAliasOperandReference(MatchableInfo *II,
1195 StringRef OperandName,
1196 MatchableInfo::AsmOperand &Op) {
1197 const CodeGenInstAlias &CGA = *II->DefRec.get<const CodeGenInstAlias*>();
1199 // Set up the operand class.
1200 for (unsigned i = 0, e = CGA.ResultOperands.size(); i != e; ++i)
1201 if (CGA.ResultOperands[i].isRecord() &&
1202 CGA.ResultOperands[i].getName() == OperandName) {
1203 // It's safe to go with the first one we find, because CodeGenInstAlias
1204 // validates that all operands with the same name have the same record.
1205 unsigned ResultIdx =CGA.getResultInstOperandIndexForResultOperandIndex(i);
1206 Op.Class = getOperandClass(CGA.ResultInst->Operands[ResultIdx]);
1207 Op.SrcOpName = OperandName;
1211 throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" +
1212 OperandName.str() + "'");
1215 void MatchableInfo::BuildInstructionResultOperands() {
1216 const CodeGenInstruction *ResultInst = getResultInst();
1218 // Loop over all operands of the result instruction, determining how to
1220 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1221 const CGIOperandList::OperandInfo &OpInfo = ResultInst->Operands[i];
1223 // If this is a tied operand, just copy from the previously handled operand.
1224 int TiedOp = OpInfo.getTiedRegister();
1226 ResOperands.push_back(ResOperand::getTiedOp(TiedOp, &OpInfo));
1230 // Find out what operand from the asmparser that this MCInst operand comes
1232 int SrcOperand = FindAsmOperandNamed(OpInfo.Name);
1234 if (!OpInfo.Name.empty() && SrcOperand != -1) {
1235 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, &OpInfo));
1239 throw TGError(TheDef->getLoc(), "Instruction '" +
1240 TheDef->getName() + "' has operand '" + OpInfo.Name +
1241 "' that doesn't appear in asm string!");
1245 void MatchableInfo::BuildAliasResultOperands() {
1246 const CodeGenInstAlias &CGA = *DefRec.get<const CodeGenInstAlias*>();
1247 const CodeGenInstruction *ResultInst = getResultInst();
1249 // Loop over all operands of the result instruction, determining how to
1251 unsigned AliasOpNo = 0;
1252 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1253 const CGIOperandList::OperandInfo &OpInfo = ResultInst->Operands[i];
1255 // If this is a tied operand, just copy from the previously handled operand.
1256 int TiedOp = OpInfo.getTiedRegister();
1258 ResOperands.push_back(ResOperand::getTiedOp(TiedOp, &OpInfo));
1262 // Find out what operand from the asmparser that this MCInst operand comes
1264 switch (CGA.ResultOperands[AliasOpNo].Kind) {
1265 case CodeGenInstAlias::ResultOperand::K_Record: {
1266 StringRef Name = CGA.ResultOperands[AliasOpNo++].getName();
1267 int SrcOperand = FindAsmOperandNamed(Name);
1268 if (SrcOperand != -1) {
1269 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, &OpInfo));
1273 throw TGError(TheDef->getLoc(), "Instruction '" +
1274 TheDef->getName() + "' has operand '" + OpInfo.Name +
1275 "' that doesn't appear in asm string!");
1277 case CodeGenInstAlias::ResultOperand::K_Imm: {
1278 int64_t ImmVal = CGA.ResultOperands[AliasOpNo++].getImm();
1279 ResOperands.push_back(ResOperand::getImmOp(ImmVal, &OpInfo));
1283 case CodeGenInstAlias::ResultOperand::K_Reg: {
1284 Record *Reg = CGA.ResultOperands[AliasOpNo++].getRegister();
1285 ResOperands.push_back(ResOperand::getRegOp(Reg, &OpInfo));
1292 static void EmitConvertToMCInst(CodeGenTarget &Target,
1293 std::vector<MatchableInfo*> &Infos,
1295 // Write the convert function to a separate stream, so we can drop it after
1297 std::string ConvertFnBody;
1298 raw_string_ostream CvtOS(ConvertFnBody);
1300 // Function we have already generated.
1301 std::set<std::string> GeneratedFns;
1303 // Start the unified conversion function.
1304 CvtOS << "static void ConvertToMCInst(ConversionKind Kind, MCInst &Inst, "
1305 << "unsigned Opcode,\n"
1306 << " const SmallVectorImpl<MCParsedAsmOperand*"
1307 << "> &Operands) {\n";
1308 CvtOS << " Inst.setOpcode(Opcode);\n";
1309 CvtOS << " switch (Kind) {\n";
1310 CvtOS << " default:\n";
1312 // Start the enum, which we will generate inline.
1314 OS << "// Unified function for converting operands to MCInst instances.\n\n";
1315 OS << "enum ConversionKind {\n";
1317 // TargetOperandClass - This is the target's operand class, like X86Operand.
1318 std::string TargetOperandClass = Target.getName() + "Operand";
1320 for (std::vector<MatchableInfo*>::const_iterator it = Infos.begin(),
1321 ie = Infos.end(); it != ie; ++it) {
1322 MatchableInfo &II = **it;
1324 // Build the conversion function signature.
1325 std::string Signature = "Convert";
1326 std::string CaseBody;
1327 raw_string_ostream CaseOS(CaseBody);
1329 // Compute the convert enum and the case body.
1330 for (unsigned i = 0, e = II.ResOperands.size(); i != e; ++i) {
1331 const MatchableInfo::ResOperand &OpInfo = II.ResOperands[i];
1333 // Generate code to populate each result operand.
1334 switch (OpInfo.Kind) {
1335 case MatchableInfo::ResOperand::RenderAsmOperand: {
1336 // This comes from something we parsed.
1337 MatchableInfo::AsmOperand &Op = II.AsmOperands[OpInfo.AsmOperandNum];
1339 // Registers are always converted the same, don't duplicate the
1340 // conversion function based on them.
1342 if (Op.Class->isRegisterClass())
1345 Signature += Op.Class->ClassName;
1346 Signature += utostr(OpInfo.OpInfo->MINumOperands);
1347 Signature += "_" + itostr(OpInfo.AsmOperandNum);
1349 CaseOS << " ((" << TargetOperandClass << "*)Operands["
1350 << (OpInfo.AsmOperandNum+1) << "])->" << Op.Class->RenderMethod
1351 << "(Inst, " << OpInfo.OpInfo->MINumOperands << ");\n";
1355 case MatchableInfo::ResOperand::TiedOperand: {
1356 // If this operand is tied to a previous one, just copy the MCInst
1357 // operand from the earlier one.We can only tie single MCOperand values.
1358 //assert(OpInfo.OpInfo->MINumOperands == 1 && "Not a singular MCOperand");
1359 unsigned TiedOp = OpInfo.TiedOperandNum;
1360 assert(i > TiedOp && "Tied operand preceeds its target!");
1361 CaseOS << " Inst.addOperand(Inst.getOperand(" << TiedOp << "));\n";
1362 Signature += "__Tie" + utostr(TiedOp);
1365 case MatchableInfo::ResOperand::ImmOperand: {
1366 int64_t Val = OpInfo.ImmVal;
1367 CaseOS << " Inst.addOperand(MCOperand::CreateImm(" << Val << "));\n";
1368 Signature += "__imm" + itostr(Val);
1371 case MatchableInfo::ResOperand::RegOperand: {
1372 std::string N = getQualifiedName(OpInfo.Register);
1373 CaseOS << " Inst.addOperand(MCOperand::CreateReg(" << N << "));\n";
1374 Signature += "__reg" + OpInfo.Register->getName();
1379 II.ConversionFnKind = Signature;
1381 // Check if we have already generated this signature.
1382 if (!GeneratedFns.insert(Signature).second)
1385 // If not, emit it now. Add to the enum list.
1386 OS << " " << Signature << ",\n";
1388 CvtOS << " case " << Signature << ":\n";
1389 CvtOS << CaseOS.str();
1390 CvtOS << " return;\n";
1393 // Finish the convert function.
1398 // Finish the enum, and drop the convert function after it.
1400 OS << " NumConversionVariants\n";
1406 /// EmitMatchClassEnumeration - Emit the enumeration for match class kinds.
1407 static void EmitMatchClassEnumeration(CodeGenTarget &Target,
1408 std::vector<ClassInfo*> &Infos,
1410 OS << "namespace {\n\n";
1412 OS << "/// MatchClassKind - The kinds of classes which participate in\n"
1413 << "/// instruction matching.\n";
1414 OS << "enum MatchClassKind {\n";
1415 OS << " InvalidMatchClass = 0,\n";
1416 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1417 ie = Infos.end(); it != ie; ++it) {
1418 ClassInfo &CI = **it;
1419 OS << " " << CI.Name << ", // ";
1420 if (CI.Kind == ClassInfo::Token) {
1421 OS << "'" << CI.ValueName << "'\n";
1422 } else if (CI.isRegisterClass()) {
1423 if (!CI.ValueName.empty())
1424 OS << "register class '" << CI.ValueName << "'\n";
1426 OS << "derived register class\n";
1428 OS << "user defined class '" << CI.ValueName << "'\n";
1431 OS << " NumMatchClassKinds\n";
1437 /// EmitClassifyOperand - Emit the function to classify an operand.
1438 static void EmitClassifyOperand(AsmMatcherInfo &Info,
1440 OS << "static MatchClassKind ClassifyOperand(MCParsedAsmOperand *GOp) {\n"
1441 << " " << Info.Target.getName() << "Operand &Operand = *("
1442 << Info.Target.getName() << "Operand*)GOp;\n";
1445 OS << " if (Operand.isToken())\n";
1446 OS << " return MatchTokenString(Operand.getToken());\n\n";
1448 // Classify registers.
1450 // FIXME: Don't hardcode isReg, getReg.
1451 OS << " if (Operand.isReg()) {\n";
1452 OS << " switch (Operand.getReg()) {\n";
1453 OS << " default: return InvalidMatchClass;\n";
1454 for (std::map<Record*, ClassInfo*>::iterator
1455 it = Info.RegisterClasses.begin(), ie = Info.RegisterClasses.end();
1457 OS << " case " << Info.Target.getName() << "::"
1458 << it->first->getName() << ": return " << it->second->Name << ";\n";
1462 // Classify user defined operands.
1463 for (std::vector<ClassInfo*>::iterator it = Info.Classes.begin(),
1464 ie = Info.Classes.end(); it != ie; ++it) {
1465 ClassInfo &CI = **it;
1467 if (!CI.isUserClass())
1470 OS << " // '" << CI.ClassName << "' class";
1471 if (!CI.SuperClasses.empty()) {
1472 OS << ", subclass of ";
1473 for (unsigned i = 0, e = CI.SuperClasses.size(); i != e; ++i) {
1475 OS << "'" << CI.SuperClasses[i]->ClassName << "'";
1476 assert(CI < *CI.SuperClasses[i] && "Invalid class relation!");
1481 OS << " if (Operand." << CI.PredicateMethod << "()) {\n";
1483 // Validate subclass relationships.
1484 if (!CI.SuperClasses.empty()) {
1485 for (unsigned i = 0, e = CI.SuperClasses.size(); i != e; ++i)
1486 OS << " assert(Operand." << CI.SuperClasses[i]->PredicateMethod
1487 << "() && \"Invalid class relationship!\");\n";
1490 OS << " return " << CI.Name << ";\n";
1493 OS << " return InvalidMatchClass;\n";
1497 /// EmitIsSubclass - Emit the subclass predicate function.
1498 static void EmitIsSubclass(CodeGenTarget &Target,
1499 std::vector<ClassInfo*> &Infos,
1501 OS << "/// IsSubclass - Compute whether \\arg A is a subclass of \\arg B.\n";
1502 OS << "static bool IsSubclass(MatchClassKind A, MatchClassKind B) {\n";
1503 OS << " if (A == B)\n";
1504 OS << " return true;\n\n";
1506 OS << " switch (A) {\n";
1507 OS << " default:\n";
1508 OS << " return false;\n";
1509 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1510 ie = Infos.end(); it != ie; ++it) {
1511 ClassInfo &A = **it;
1513 if (A.Kind != ClassInfo::Token) {
1514 std::vector<StringRef> SuperClasses;
1515 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1516 ie = Infos.end(); it != ie; ++it) {
1517 ClassInfo &B = **it;
1519 if (&A != &B && A.isSubsetOf(B))
1520 SuperClasses.push_back(B.Name);
1523 if (SuperClasses.empty())
1526 OS << "\n case " << A.Name << ":\n";
1528 if (SuperClasses.size() == 1) {
1529 OS << " return B == " << SuperClasses.back() << ";\n";
1533 OS << " switch (B) {\n";
1534 OS << " default: return false;\n";
1535 for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i)
1536 OS << " case " << SuperClasses[i] << ": return true;\n";
1546 /// EmitMatchTokenString - Emit the function to match a token string to the
1547 /// appropriate match class value.
1548 static void EmitMatchTokenString(CodeGenTarget &Target,
1549 std::vector<ClassInfo*> &Infos,
1551 // Construct the match list.
1552 std::vector<StringMatcher::StringPair> Matches;
1553 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1554 ie = Infos.end(); it != ie; ++it) {
1555 ClassInfo &CI = **it;
1557 if (CI.Kind == ClassInfo::Token)
1558 Matches.push_back(StringMatcher::StringPair(CI.ValueName,
1559 "return " + CI.Name + ";"));
1562 OS << "static MatchClassKind MatchTokenString(StringRef Name) {\n";
1564 StringMatcher("Name", Matches, OS).Emit();
1566 OS << " return InvalidMatchClass;\n";
1570 /// EmitMatchRegisterName - Emit the function to match a string to the target
1571 /// specific register enum.
1572 static void EmitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
1574 // Construct the match list.
1575 std::vector<StringMatcher::StringPair> Matches;
1576 for (unsigned i = 0, e = Target.getRegisters().size(); i != e; ++i) {
1577 const CodeGenRegister &Reg = Target.getRegisters()[i];
1578 if (Reg.TheDef->getValueAsString("AsmName").empty())
1581 Matches.push_back(StringMatcher::StringPair(
1582 Reg.TheDef->getValueAsString("AsmName"),
1583 "return " + utostr(i + 1) + ";"));
1586 OS << "static unsigned MatchRegisterName(StringRef Name) {\n";
1588 StringMatcher("Name", Matches, OS).Emit();
1590 OS << " return 0;\n";
1594 /// EmitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag
1596 static void EmitSubtargetFeatureFlagEnumeration(AsmMatcherInfo &Info,
1598 OS << "// Flags for subtarget features that participate in "
1599 << "instruction matching.\n";
1600 OS << "enum SubtargetFeatureFlag {\n";
1601 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
1602 it = Info.SubtargetFeatures.begin(),
1603 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
1604 SubtargetFeatureInfo &SFI = *it->second;
1605 OS << " " << SFI.getEnumName() << " = (1 << " << SFI.Index << "),\n";
1607 OS << " Feature_None = 0\n";
1611 /// EmitComputeAvailableFeatures - Emit the function to compute the list of
1612 /// available features given a subtarget.
1613 static void EmitComputeAvailableFeatures(AsmMatcherInfo &Info,
1615 std::string ClassName =
1616 Info.AsmParser->getValueAsString("AsmParserClassName");
1618 OS << "unsigned " << Info.Target.getName() << ClassName << "::\n"
1619 << "ComputeAvailableFeatures(const " << Info.Target.getName()
1620 << "Subtarget *Subtarget) const {\n";
1621 OS << " unsigned Features = 0;\n";
1622 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
1623 it = Info.SubtargetFeatures.begin(),
1624 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
1625 SubtargetFeatureInfo &SFI = *it->second;
1626 OS << " if (" << SFI.TheDef->getValueAsString("CondString")
1628 OS << " Features |= " << SFI.getEnumName() << ";\n";
1630 OS << " return Features;\n";
1634 static std::string GetAliasRequiredFeatures(Record *R,
1635 const AsmMatcherInfo &Info) {
1636 std::vector<Record*> ReqFeatures = R->getValueAsListOfDefs("Predicates");
1638 unsigned NumFeatures = 0;
1639 for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) {
1640 SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]);
1643 throw TGError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() +
1644 "' is not marked as an AssemblerPredicate!");
1649 Result += F->getEnumName();
1653 if (NumFeatures > 1)
1654 Result = '(' + Result + ')';
1658 /// EmitMnemonicAliases - If the target has any MnemonicAlias<> definitions,
1659 /// emit a function for them and return true, otherwise return false.
1660 static bool EmitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info) {
1661 std::vector<Record*> Aliases =
1662 Records.getAllDerivedDefinitions("MnemonicAlias");
1663 if (Aliases.empty()) return false;
1665 OS << "static void ApplyMnemonicAliases(StringRef &Mnemonic, "
1666 "unsigned Features) {\n";
1668 // Keep track of all the aliases from a mnemonic. Use an std::map so that the
1669 // iteration order of the map is stable.
1670 std::map<std::string, std::vector<Record*> > AliasesFromMnemonic;
1672 for (unsigned i = 0, e = Aliases.size(); i != e; ++i) {
1673 Record *R = Aliases[i];
1674 AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R);
1677 // Process each alias a "from" mnemonic at a time, building the code executed
1678 // by the string remapper.
1679 std::vector<StringMatcher::StringPair> Cases;
1680 for (std::map<std::string, std::vector<Record*> >::iterator
1681 I = AliasesFromMnemonic.begin(), E = AliasesFromMnemonic.end();
1683 const std::vector<Record*> &ToVec = I->second;
1685 // Loop through each alias and emit code that handles each case. If there
1686 // are two instructions without predicates, emit an error. If there is one,
1688 std::string MatchCode;
1689 int AliasWithNoPredicate = -1;
1691 for (unsigned i = 0, e = ToVec.size(); i != e; ++i) {
1692 Record *R = ToVec[i];
1693 std::string FeatureMask = GetAliasRequiredFeatures(R, Info);
1695 // If this unconditionally matches, remember it for later and diagnose
1697 if (FeatureMask.empty()) {
1698 if (AliasWithNoPredicate != -1) {
1699 // We can't have two aliases from the same mnemonic with no predicate.
1700 PrintError(ToVec[AliasWithNoPredicate]->getLoc(),
1701 "two MnemonicAliases with the same 'from' mnemonic!");
1702 throw TGError(R->getLoc(), "this is the other MnemonicAlias.");
1705 AliasWithNoPredicate = i;
1709 if (!MatchCode.empty())
1710 MatchCode += "else ";
1711 MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n";
1712 MatchCode += " Mnemonic = \"" +R->getValueAsString("ToMnemonic")+"\";\n";
1715 if (AliasWithNoPredicate != -1) {
1716 Record *R = ToVec[AliasWithNoPredicate];
1717 if (!MatchCode.empty())
1718 MatchCode += "else\n ";
1719 MatchCode += "Mnemonic = \"" + R->getValueAsString("ToMnemonic")+"\";\n";
1722 MatchCode += "return;";
1724 Cases.push_back(std::make_pair(I->first, MatchCode));
1728 StringMatcher("Mnemonic", Cases, OS).Emit();
1734 void AsmMatcherEmitter::run(raw_ostream &OS) {
1735 CodeGenTarget Target;
1736 Record *AsmParser = Target.getAsmParser();
1737 std::string ClassName = AsmParser->getValueAsString("AsmParserClassName");
1739 // Compute the information on the instructions to match.
1740 AsmMatcherInfo Info(AsmParser, Target);
1743 // Sort the instruction table using the partial order on classes. We use
1744 // stable_sort to ensure that ambiguous instructions are still
1745 // deterministically ordered.
1746 std::stable_sort(Info.Matchables.begin(), Info.Matchables.end(),
1747 less_ptr<MatchableInfo>());
1749 DEBUG_WITH_TYPE("instruction_info", {
1750 for (std::vector<MatchableInfo*>::iterator
1751 it = Info.Matchables.begin(), ie = Info.Matchables.end();
1756 // Check for ambiguous matchables.
1757 DEBUG_WITH_TYPE("ambiguous_instrs", {
1758 unsigned NumAmbiguous = 0;
1759 for (unsigned i = 0, e = Info.Matchables.size(); i != e; ++i) {
1760 for (unsigned j = i + 1; j != e; ++j) {
1761 MatchableInfo &A = *Info.Matchables[i];
1762 MatchableInfo &B = *Info.Matchables[j];
1764 if (A.CouldMatchAmiguouslyWith(B)) {
1765 errs() << "warning: ambiguous matchables:\n";
1767 errs() << "\nis incomparable with:\n";
1775 errs() << "warning: " << NumAmbiguous
1776 << " ambiguous matchables!\n";
1779 // Write the output.
1781 EmitSourceFileHeader("Assembly Matcher Source Fragment", OS);
1783 // Information for the class declaration.
1784 OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
1785 OS << "#undef GET_ASSEMBLER_HEADER\n";
1786 OS << " // This should be included into the middle of the declaration of \n";
1787 OS << " // your subclasses implementation of TargetAsmParser.\n";
1788 OS << " unsigned ComputeAvailableFeatures(const " <<
1789 Target.getName() << "Subtarget *Subtarget) const;\n";
1790 OS << " enum MatchResultTy {\n";
1791 OS << " Match_Success, Match_MnemonicFail, Match_InvalidOperand,\n";
1792 OS << " Match_MissingFeature\n";
1794 OS << " MatchResultTy MatchInstructionImpl(const "
1795 << "SmallVectorImpl<MCParsedAsmOperand*>"
1796 << " &Operands, MCInst &Inst, unsigned &ErrorInfo);\n\n";
1797 OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n";
1802 OS << "\n#ifdef GET_REGISTER_MATCHER\n";
1803 OS << "#undef GET_REGISTER_MATCHER\n\n";
1805 // Emit the subtarget feature enumeration.
1806 EmitSubtargetFeatureFlagEnumeration(Info, OS);
1808 // Emit the function to match a register name to number.
1809 EmitMatchRegisterName(Target, AsmParser, OS);
1811 OS << "#endif // GET_REGISTER_MATCHER\n\n";
1814 OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
1815 OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
1817 // Generate the function that remaps for mnemonic aliases.
1818 bool HasMnemonicAliases = EmitMnemonicAliases(OS, Info);
1820 // Generate the unified function to convert operands into an MCInst.
1821 EmitConvertToMCInst(Target, Info.Matchables, OS);
1823 // Emit the enumeration for classes which participate in matching.
1824 EmitMatchClassEnumeration(Target, Info.Classes, OS);
1826 // Emit the routine to match token strings to their match class.
1827 EmitMatchTokenString(Target, Info.Classes, OS);
1829 // Emit the routine to classify an operand.
1830 EmitClassifyOperand(Info, OS);
1832 // Emit the subclass predicate routine.
1833 EmitIsSubclass(Target, Info.Classes, OS);
1835 // Emit the available features compute function.
1836 EmitComputeAvailableFeatures(Info, OS);
1839 size_t MaxNumOperands = 0;
1840 for (std::vector<MatchableInfo*>::const_iterator it =
1841 Info.Matchables.begin(), ie = Info.Matchables.end();
1843 MaxNumOperands = std::max(MaxNumOperands, (*it)->AsmOperands.size());
1846 // Emit the static match table; unused classes get initalized to 0 which is
1847 // guaranteed to be InvalidMatchClass.
1849 // FIXME: We can reduce the size of this table very easily. First, we change
1850 // it so that store the kinds in separate bit-fields for each index, which
1851 // only needs to be the max width used for classes at that index (we also need
1852 // to reject based on this during classification). If we then make sure to
1853 // order the match kinds appropriately (putting mnemonics last), then we
1854 // should only end up using a few bits for each class, especially the ones
1855 // following the mnemonic.
1856 OS << "namespace {\n";
1857 OS << " struct MatchEntry {\n";
1858 OS << " unsigned Opcode;\n";
1859 OS << " const char *Mnemonic;\n";
1860 OS << " ConversionKind ConvertFn;\n";
1861 OS << " MatchClassKind Classes[" << MaxNumOperands << "];\n";
1862 OS << " unsigned RequiredFeatures;\n";
1865 OS << "// Predicate for searching for an opcode.\n";
1866 OS << " struct LessOpcode {\n";
1867 OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n";
1868 OS << " return StringRef(LHS.Mnemonic) < RHS;\n";
1870 OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n";
1871 OS << " return LHS < StringRef(RHS.Mnemonic);\n";
1873 OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n";
1874 OS << " return StringRef(LHS.Mnemonic) < StringRef(RHS.Mnemonic);\n";
1878 OS << "} // end anonymous namespace.\n\n";
1880 OS << "static const MatchEntry MatchTable["
1881 << Info.Matchables.size() << "] = {\n";
1883 for (std::vector<MatchableInfo*>::const_iterator it =
1884 Info.Matchables.begin(), ie = Info.Matchables.end();
1886 MatchableInfo &II = **it;
1889 OS << " { " << Target.getName() << "::"
1890 << II.getResultInst()->TheDef->getName() << ", \"" << II.Mnemonic << "\""
1891 << ", " << II.ConversionFnKind << ", { ";
1892 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) {
1893 MatchableInfo::AsmOperand &Op = II.AsmOperands[i];
1896 OS << Op.Class->Name;
1900 // Write the required features mask.
1901 if (!II.RequiredFeatures.empty()) {
1902 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
1904 OS << II.RequiredFeatures[i]->getEnumName();
1914 // Finally, build the match function.
1915 OS << Target.getName() << ClassName << "::MatchResultTy "
1916 << Target.getName() << ClassName << "::\n"
1917 << "MatchInstructionImpl(const SmallVectorImpl<MCParsedAsmOperand*>"
1919 OS << " MCInst &Inst, unsigned &ErrorInfo) {\n";
1921 // Emit code to get the available features.
1922 OS << " // Get the current feature set.\n";
1923 OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n";
1925 OS << " // Get the instruction mnemonic, which is the first token.\n";
1926 OS << " StringRef Mnemonic = ((" << Target.getName()
1927 << "Operand*)Operands[0])->getToken();\n\n";
1929 if (HasMnemonicAliases) {
1930 OS << " // Process all MnemonicAliases to remap the mnemonic.\n";
1931 OS << " ApplyMnemonicAliases(Mnemonic, AvailableFeatures);\n\n";
1934 // Emit code to compute the class list for this operand vector.
1935 OS << " // Eliminate obvious mismatches.\n";
1936 OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n";
1937 OS << " ErrorInfo = " << (MaxNumOperands+1) << ";\n";
1938 OS << " return Match_InvalidOperand;\n";
1941 OS << " // Compute the class list for this operand vector.\n";
1942 OS << " MatchClassKind Classes[" << MaxNumOperands << "];\n";
1943 OS << " for (unsigned i = 1, e = Operands.size(); i != e; ++i) {\n";
1944 OS << " Classes[i-1] = ClassifyOperand(Operands[i]);\n\n";
1946 OS << " // Check for invalid operands before matching.\n";
1947 OS << " if (Classes[i-1] == InvalidMatchClass) {\n";
1948 OS << " ErrorInfo = i;\n";
1949 OS << " return Match_InvalidOperand;\n";
1953 OS << " // Mark unused classes.\n";
1954 OS << " for (unsigned i = Operands.size()-1, e = " << MaxNumOperands << "; "
1955 << "i != e; ++i)\n";
1956 OS << " Classes[i] = InvalidMatchClass;\n\n";
1958 OS << " // Some state to try to produce better error messages.\n";
1959 OS << " bool HadMatchOtherThanFeatures = false;\n\n";
1960 OS << " // Set ErrorInfo to the operand that mismatches if it is \n";
1961 OS << " // wrong for all instances of the instruction.\n";
1962 OS << " ErrorInfo = ~0U;\n";
1964 // Emit code to search the table.
1965 OS << " // Search the table.\n";
1966 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
1967 OS << " std::equal_range(MatchTable, MatchTable+"
1968 << Info.Matchables.size() << ", Mnemonic, LessOpcode());\n\n";
1970 OS << " // Return a more specific error code if no mnemonics match.\n";
1971 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
1972 OS << " return Match_MnemonicFail;\n\n";
1974 OS << " for (const MatchEntry *it = MnemonicRange.first, "
1975 << "*ie = MnemonicRange.second;\n";
1976 OS << " it != ie; ++it) {\n";
1978 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
1979 OS << " assert(Mnemonic == it->Mnemonic);\n";
1981 // Emit check that the subclasses match.
1982 OS << " bool OperandsValid = true;\n";
1983 OS << " for (unsigned i = 0; i != " << MaxNumOperands << "; ++i) {\n";
1984 OS << " if (IsSubclass(Classes[i], it->Classes[i]))\n";
1985 OS << " continue;\n";
1986 OS << " // If this operand is broken for all of the instances of this\n";
1987 OS << " // mnemonic, keep track of it so we can report loc info.\n";
1988 OS << " if (it == MnemonicRange.first || ErrorInfo == i+1)\n";
1989 OS << " ErrorInfo = i+1;\n";
1991 OS << " ErrorInfo = ~0U;";
1992 OS << " // Otherwise, just reject this instance of the mnemonic.\n";
1993 OS << " OperandsValid = false;\n";
1997 OS << " if (!OperandsValid) continue;\n";
1999 // Emit check that the required features are available.
2000 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2001 << "!= it->RequiredFeatures) {\n";
2002 OS << " HadMatchOtherThanFeatures = true;\n";
2003 OS << " continue;\n";
2007 OS << " ConvertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n";
2009 // Call the post-processing function, if used.
2010 std::string InsnCleanupFn =
2011 AsmParser->getValueAsString("AsmParserInstCleanup");
2012 if (!InsnCleanupFn.empty())
2013 OS << " " << InsnCleanupFn << "(Inst);\n";
2015 OS << " return Match_Success;\n";
2018 OS << " // Okay, we had no match. Try to return a useful error code.\n";
2019 OS << " if (HadMatchOtherThanFeatures) return Match_MissingFeature;\n";
2020 OS << " return Match_InvalidOperand;\n";
2023 OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";