1 //===- AsmWriterEmitter.cpp - Generate an assembly writer -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is emits an assembly printer for the current target.
11 // Note that this is currently fairly skeletal, but will grow over time.
13 //===----------------------------------------------------------------------===//
15 #include "AsmWriterEmitter.h"
16 #include "AsmWriterInst.h"
17 #include "CodeGenTarget.h"
18 #include "StringToOffsetTable.h"
19 #include "llvm/ADT/Twine.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/MathExtras.h"
22 #include "llvm/TableGen/Error.h"
23 #include "llvm/TableGen/Record.h"
27 static void PrintCases(std::vector<std::pair<std::string,
28 AsmWriterOperand> > &OpsToPrint, raw_ostream &O) {
29 O << " case " << OpsToPrint.back().first << ": ";
30 AsmWriterOperand TheOp = OpsToPrint.back().second;
31 OpsToPrint.pop_back();
33 // Check to see if any other operands are identical in this list, and if so,
34 // emit a case label for them.
35 for (unsigned i = OpsToPrint.size(); i != 0; --i)
36 if (OpsToPrint[i-1].second == TheOp) {
37 O << "\n case " << OpsToPrint[i-1].first << ": ";
38 OpsToPrint.erase(OpsToPrint.begin()+i-1);
41 // Finally, emit the code.
47 /// EmitInstructions - Emit the last instruction in the vector and any other
48 /// instructions that are suitably similar to it.
49 static void EmitInstructions(std::vector<AsmWriterInst> &Insts,
51 AsmWriterInst FirstInst = Insts.back();
54 std::vector<AsmWriterInst> SimilarInsts;
55 unsigned DifferingOperand = ~0;
56 for (unsigned i = Insts.size(); i != 0; --i) {
57 unsigned DiffOp = Insts[i-1].MatchesAllButOneOp(FirstInst);
59 if (DifferingOperand == ~0U) // First match!
60 DifferingOperand = DiffOp;
62 // If this differs in the same operand as the rest of the instructions in
63 // this class, move it to the SimilarInsts list.
64 if (DifferingOperand == DiffOp || DiffOp == ~0U) {
65 SimilarInsts.push_back(Insts[i-1]);
66 Insts.erase(Insts.begin()+i-1);
71 O << " case " << FirstInst.CGI->Namespace << "::"
72 << FirstInst.CGI->TheDef->getName() << ":\n";
73 for (unsigned i = 0, e = SimilarInsts.size(); i != e; ++i)
74 O << " case " << SimilarInsts[i].CGI->Namespace << "::"
75 << SimilarInsts[i].CGI->TheDef->getName() << ":\n";
76 for (unsigned i = 0, e = FirstInst.Operands.size(); i != e; ++i) {
77 if (i != DifferingOperand) {
78 // If the operand is the same for all instructions, just print it.
79 O << " " << FirstInst.Operands[i].getCode();
81 // If this is the operand that varies between all of the instructions,
82 // emit a switch for just this operand now.
83 O << " switch (MI->getOpcode()) {\n";
84 std::vector<std::pair<std::string, AsmWriterOperand> > OpsToPrint;
85 OpsToPrint.push_back(std::make_pair(FirstInst.CGI->Namespace + "::" +
86 FirstInst.CGI->TheDef->getName(),
87 FirstInst.Operands[i]));
89 for (unsigned si = 0, e = SimilarInsts.size(); si != e; ++si) {
90 AsmWriterInst &AWI = SimilarInsts[si];
91 OpsToPrint.push_back(std::make_pair(AWI.CGI->Namespace+"::"+
92 AWI.CGI->TheDef->getName(),
95 std::reverse(OpsToPrint.begin(), OpsToPrint.end());
96 while (!OpsToPrint.empty())
97 PrintCases(OpsToPrint, O);
105 void AsmWriterEmitter::
106 FindUniqueOperandCommands(std::vector<std::string> &UniqueOperandCommands,
107 std::vector<unsigned> &InstIdxs,
108 std::vector<unsigned> &InstOpsUsed) const {
109 InstIdxs.assign(NumberedInstructions.size(), ~0U);
111 // This vector parallels UniqueOperandCommands, keeping track of which
112 // instructions each case are used for. It is a comma separated string of
114 std::vector<std::string> InstrsForCase;
115 InstrsForCase.resize(UniqueOperandCommands.size());
116 InstOpsUsed.assign(UniqueOperandCommands.size(), 0);
118 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
119 const AsmWriterInst *Inst = getAsmWriterInstByID(i);
120 if (Inst == 0) continue; // PHI, INLINEASM, PROLOG_LABEL, etc.
123 if (Inst->Operands.empty())
124 continue; // Instruction already done.
126 Command = " " + Inst->Operands[0].getCode() + "\n";
128 // Check to see if we already have 'Command' in UniqueOperandCommands.
130 bool FoundIt = false;
131 for (unsigned idx = 0, e = UniqueOperandCommands.size(); idx != e; ++idx)
132 if (UniqueOperandCommands[idx] == Command) {
134 InstrsForCase[idx] += ", ";
135 InstrsForCase[idx] += Inst->CGI->TheDef->getName();
140 InstIdxs[i] = UniqueOperandCommands.size();
141 UniqueOperandCommands.push_back(Command);
142 InstrsForCase.push_back(Inst->CGI->TheDef->getName());
144 // This command matches one operand so far.
145 InstOpsUsed.push_back(1);
149 // For each entry of UniqueOperandCommands, there is a set of instructions
150 // that uses it. If the next command of all instructions in the set are
151 // identical, fold it into the command.
152 for (unsigned CommandIdx = 0, e = UniqueOperandCommands.size();
153 CommandIdx != e; ++CommandIdx) {
155 for (unsigned Op = 1; ; ++Op) {
156 // Scan for the first instruction in the set.
157 std::vector<unsigned>::iterator NIT =
158 std::find(InstIdxs.begin(), InstIdxs.end(), CommandIdx);
159 if (NIT == InstIdxs.end()) break; // No commonality.
161 // If this instruction has no more operands, we isn't anything to merge
162 // into this command.
163 const AsmWriterInst *FirstInst =
164 getAsmWriterInstByID(NIT-InstIdxs.begin());
165 if (!FirstInst || FirstInst->Operands.size() == Op)
168 // Otherwise, scan to see if all of the other instructions in this command
169 // set share the operand.
171 // Keep track of the maximum, number of operands or any
172 // instruction we see in the group.
173 size_t MaxSize = FirstInst->Operands.size();
175 for (NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx);
176 NIT != InstIdxs.end();
177 NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx)) {
178 // Okay, found another instruction in this command set. If the operand
179 // matches, we're ok, otherwise bail out.
180 const AsmWriterInst *OtherInst =
181 getAsmWriterInstByID(NIT-InstIdxs.begin());
184 OtherInst->Operands.size() > FirstInst->Operands.size())
185 MaxSize = std::max(MaxSize, OtherInst->Operands.size());
187 if (!OtherInst || OtherInst->Operands.size() == Op ||
188 OtherInst->Operands[Op] != FirstInst->Operands[Op]) {
195 // Okay, everything in this command set has the same next operand. Add it
196 // to UniqueOperandCommands and remember that it was consumed.
197 std::string Command = " " + FirstInst->Operands[Op].getCode() + "\n";
199 UniqueOperandCommands[CommandIdx] += Command;
200 InstOpsUsed[CommandIdx]++;
204 // Prepend some of the instructions each case is used for onto the case val.
205 for (unsigned i = 0, e = InstrsForCase.size(); i != e; ++i) {
206 std::string Instrs = InstrsForCase[i];
207 if (Instrs.size() > 70) {
208 Instrs.erase(Instrs.begin()+70, Instrs.end());
213 UniqueOperandCommands[i] = " // " + Instrs + "\n" +
214 UniqueOperandCommands[i];
219 static void UnescapeString(std::string &Str) {
220 for (unsigned i = 0; i != Str.size(); ++i) {
221 if (Str[i] == '\\' && i != Str.size()-1) {
223 default: continue; // Don't execute the code after the switch.
224 case 'a': Str[i] = '\a'; break;
225 case 'b': Str[i] = '\b'; break;
226 case 'e': Str[i] = 27; break;
227 case 'f': Str[i] = '\f'; break;
228 case 'n': Str[i] = '\n'; break;
229 case 'r': Str[i] = '\r'; break;
230 case 't': Str[i] = '\t'; break;
231 case 'v': Str[i] = '\v'; break;
232 case '"': Str[i] = '\"'; break;
233 case '\'': Str[i] = '\''; break;
234 case '\\': Str[i] = '\\'; break;
236 // Nuke the second character.
237 Str.erase(Str.begin()+i+1);
242 /// EmitPrintInstruction - Generate the code for the "printInstruction" method
244 void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) {
245 CodeGenTarget Target(Records);
246 Record *AsmWriter = Target.getAsmWriter();
247 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
248 bool isMC = AsmWriter->getValueAsBit("isMCAsmWriter");
249 const char *MachineInstrClassName = isMC ? "MCInst" : "MachineInstr";
252 "/// printInstruction - This method is automatically generated by tablegen\n"
253 "/// from the instruction set description.\n"
254 "void " << Target.getName() << ClassName
255 << "::printInstruction(const " << MachineInstrClassName
256 << " *MI, raw_ostream &O) {\n";
258 std::vector<AsmWriterInst> Instructions;
260 for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
261 E = Target.inst_end(); I != E; ++I)
262 if (!(*I)->AsmString.empty() &&
263 (*I)->TheDef->getName() != "PHI")
264 Instructions.push_back(
266 AsmWriter->getValueAsInt("Variant"),
267 AsmWriter->getValueAsInt("FirstOperandColumn"),
268 AsmWriter->getValueAsInt("OperandSpacing")));
270 // Get the instruction numbering.
271 NumberedInstructions = Target.getInstructionsByEnumValue();
273 // Compute the CodeGenInstruction -> AsmWriterInst mapping. Note that not
274 // all machine instructions are necessarily being printed, so there may be
275 // target instructions not in this map.
276 for (unsigned i = 0, e = Instructions.size(); i != e; ++i)
277 CGIAWIMap.insert(std::make_pair(Instructions[i].CGI, &Instructions[i]));
279 // Build an aggregate string, and build a table of offsets into it.
280 StringToOffsetTable StringTable;
282 /// OpcodeInfo - This encodes the index of the string to use for the first
283 /// chunk of the output as well as indices used for operand printing.
284 std::vector<unsigned> OpcodeInfo;
286 unsigned MaxStringIdx = 0;
287 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
288 AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions[i]];
291 // Something not handled by the asmwriter printer.
293 } else if (AWI->Operands[0].OperandType !=
294 AsmWriterOperand::isLiteralTextOperand ||
295 AWI->Operands[0].Str.empty()) {
296 // Something handled by the asmwriter printer, but with no leading string.
297 Idx = StringTable.GetOrAddStringOffset("");
299 std::string Str = AWI->Operands[0].Str;
301 Idx = StringTable.GetOrAddStringOffset(Str);
302 MaxStringIdx = std::max(MaxStringIdx, Idx);
304 // Nuke the string from the operand list. It is now handled!
305 AWI->Operands.erase(AWI->Operands.begin());
308 // Bias offset by one since we want 0 as a sentinel.
309 assert((Idx+1) <= 0xffff && "String offset too large to fit in table");
310 OpcodeInfo.push_back(Idx+1);
313 // Figure out how many bits we used for the string index.
314 unsigned AsmStrBits = Log2_32_Ceil(MaxStringIdx+2);
316 // To reduce code size, we compactify common instructions into a few bits
317 // in the opcode-indexed table.
318 unsigned BitsLeft = 32-AsmStrBits;
320 std::vector<std::vector<std::string> > TableDrivenOperandPrinters;
323 std::vector<std::string> UniqueOperandCommands;
324 std::vector<unsigned> InstIdxs;
325 std::vector<unsigned> NumInstOpsHandled;
326 FindUniqueOperandCommands(UniqueOperandCommands, InstIdxs,
329 // If we ran out of operands to print, we're done.
330 if (UniqueOperandCommands.empty()) break;
332 // Compute the number of bits we need to represent these cases, this is
333 // ceil(log2(numentries)).
334 unsigned NumBits = Log2_32_Ceil(UniqueOperandCommands.size());
336 // If we don't have enough bits for this operand, don't include it.
337 if (NumBits > BitsLeft) {
338 DEBUG(errs() << "Not enough bits to densely encode " << NumBits
343 // Otherwise, we can include this in the initial lookup table. Add it in.
345 for (unsigned i = 0, e = InstIdxs.size(); i != e; ++i)
346 if (InstIdxs[i] != ~0U)
347 OpcodeInfo[i] |= InstIdxs[i] << (BitsLeft+AsmStrBits);
349 // Remove the info about this operand.
350 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
351 if (AsmWriterInst *Inst = getAsmWriterInstByID(i))
352 if (!Inst->Operands.empty()) {
353 unsigned NumOps = NumInstOpsHandled[InstIdxs[i]];
354 assert(NumOps <= Inst->Operands.size() &&
355 "Can't remove this many ops!");
356 Inst->Operands.erase(Inst->Operands.begin(),
357 Inst->Operands.begin()+NumOps);
361 // Remember the handlers for this set of operands.
362 TableDrivenOperandPrinters.push_back(UniqueOperandCommands);
367 O<<" static const unsigned OpInfo[] = {\n";
368 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
369 O << " " << OpcodeInfo[i] << "U,\t// "
370 << NumberedInstructions[i]->TheDef->getName() << "\n";
372 // Add a dummy entry so the array init doesn't end with a comma.
376 // Emit the string itself.
377 O << " const char *const AsmStrs = \n";
378 StringTable.EmitString(O);
381 O << " O << \"\\t\";\n\n";
383 O << " // Emit the opcode for the instruction.\n"
384 << " unsigned Bits = OpInfo[MI->getOpcode()];\n"
385 << " assert(Bits != 0 && \"Cannot print this instruction.\");\n"
386 << " O << AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << ")-1;\n\n";
388 // Output the table driven operand information.
389 BitsLeft = 32-AsmStrBits;
390 for (unsigned i = 0, e = TableDrivenOperandPrinters.size(); i != e; ++i) {
391 std::vector<std::string> &Commands = TableDrivenOperandPrinters[i];
393 // Compute the number of bits we need to represent these cases, this is
394 // ceil(log2(numentries)).
395 unsigned NumBits = Log2_32_Ceil(Commands.size());
396 assert(NumBits <= BitsLeft && "consistency error");
398 // Emit code to extract this field from Bits.
401 O << "\n // Fragment " << i << " encoded into " << NumBits
402 << " bits for " << Commands.size() << " unique commands.\n";
404 if (Commands.size() == 2) {
405 // Emit two possibilitys with if/else.
406 O << " if ((Bits >> " << (BitsLeft+AsmStrBits) << ") & "
407 << ((1 << NumBits)-1) << ") {\n"
412 } else if (Commands.size() == 1) {
413 // Emit a single possibility.
414 O << Commands[0] << "\n\n";
416 O << " switch ((Bits >> " << (BitsLeft+AsmStrBits) << ") & "
417 << ((1 << NumBits)-1) << ") {\n"
418 << " default: // unreachable.\n";
420 // Print out all the cases.
421 for (unsigned i = 0, e = Commands.size(); i != e; ++i) {
422 O << " case " << i << ":\n";
430 // Okay, delete instructions with no operand info left.
431 for (unsigned i = 0, e = Instructions.size(); i != e; ++i) {
432 // Entire instruction has been emitted?
433 AsmWriterInst &Inst = Instructions[i];
434 if (Inst.Operands.empty()) {
435 Instructions.erase(Instructions.begin()+i);
441 // Because this is a vector, we want to emit from the end. Reverse all of the
442 // elements in the vector.
443 std::reverse(Instructions.begin(), Instructions.end());
446 // Now that we've emitted all of the operand info that fit into 32 bits, emit
447 // information for those instructions that are left. This is a less dense
448 // encoding, but we expect the main 32-bit table to handle the majority of
450 if (!Instructions.empty()) {
451 // Find the opcode # of inline asm.
452 O << " switch (MI->getOpcode()) {\n";
453 while (!Instructions.empty())
454 EmitInstructions(Instructions, O);
464 emitRegisterNameString(raw_ostream &O, StringRef AltName,
465 const std::vector<CodeGenRegister*> &Registers) {
466 StringToOffsetTable StringTable;
467 O << " static const unsigned RegAsmOffset" << AltName << "[] = {\n ";
468 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
469 const CodeGenRegister &Reg = *Registers[i];
472 // "NoRegAltName" is special. We don't need to do a lookup for that,
473 // as it's just a reference to the default register name.
474 if (AltName == "" || AltName == "NoRegAltName") {
475 AsmName = Reg.TheDef->getValueAsString("AsmName");
477 AsmName = Reg.getName();
479 // Make sure the register has an alternate name for this index.
480 std::vector<Record*> AltNameList =
481 Reg.TheDef->getValueAsListOfDefs("RegAltNameIndices");
483 for (e = AltNameList.size();
484 Idx < e && (AltNameList[Idx]->getName() != AltName);
487 // If the register has an alternate name for this index, use it.
488 // Otherwise, leave it empty as an error flag.
490 std::vector<std::string> AltNames =
491 Reg.TheDef->getValueAsListOfStrings("AltNames");
492 if (AltNames.size() <= Idx)
493 throw TGError(Reg.TheDef->getLoc(),
494 (Twine("Register definition missing alt name for '") +
495 AltName + "'.").str());
496 AsmName = AltNames[Idx];
500 unsigned Idx = StringTable.GetOrAddStringOffset(AsmName);
501 assert(Idx <= 0xffff && "String offset too large to fit in table");
503 if (((i + 1) % 14) == 0)
513 O << " const char *AsmStrs" << AltName << " =\n";
514 StringTable.EmitString(O);
518 void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) {
519 CodeGenTarget Target(Records);
520 Record *AsmWriter = Target.getAsmWriter();
521 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
522 const std::vector<CodeGenRegister*> &Registers =
523 Target.getRegBank().getRegisters();
524 std::vector<Record*> AltNameIndices = Target.getRegAltNameIndices();
525 bool hasAltNames = AltNameIndices.size() > 1;
528 "\n\n/// getRegisterName - This method is automatically generated by tblgen\n"
529 "/// from the register set description. This returns the assembler name\n"
530 "/// for the specified register.\n"
531 "const char *" << Target.getName() << ClassName << "::";
533 O << "\ngetRegisterName(unsigned RegNo, unsigned AltIdx) {\n";
535 O << "getRegisterName(unsigned RegNo) {\n";
536 O << " assert(RegNo && RegNo < " << (Registers.size()+1)
537 << " && \"Invalid register number!\");\n"
541 for (unsigned i = 0, e = AltNameIndices.size(); i < e; ++i)
542 emitRegisterNameString(O, AltNameIndices[i]->getName(), Registers);
544 emitRegisterNameString(O, "", Registers);
547 O << " const unsigned *RegAsmOffset;\n"
548 << " const char *AsmStrs;\n"
549 << " switch(AltIdx) {\n"
550 << " default: llvm_unreachable(\"Invalid register alt name index!\");\n";
551 for (unsigned i = 0, e = AltNameIndices.size(); i < e; ++i) {
552 StringRef Namespace = AltNameIndices[1]->getValueAsString("Namespace");
553 StringRef AltName(AltNameIndices[i]->getName());
554 O << " case " << Namespace << "::" << AltName
556 << " AsmStrs = AsmStrs" << AltName << ";\n"
557 << " RegAsmOffset = RegAsmOffset" << AltName << ";\n"
563 O << " assert (*(AsmStrs+RegAsmOffset[RegNo-1]) &&\n"
564 << " \"Invalid alt name index for register!\");\n"
565 << " return AsmStrs+RegAsmOffset[RegNo-1];\n"
569 void AsmWriterEmitter::EmitGetInstructionName(raw_ostream &O) {
570 CodeGenTarget Target(Records);
571 Record *AsmWriter = Target.getAsmWriter();
572 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
574 const std::vector<const CodeGenInstruction*> &NumberedInstructions =
575 Target.getInstructionsByEnumValue();
577 StringToOffsetTable StringTable;
579 "\n\n#ifdef GET_INSTRUCTION_NAME\n"
580 "#undef GET_INSTRUCTION_NAME\n\n"
581 "/// getInstructionName: This method is automatically generated by tblgen\n"
582 "/// from the instruction set description. This returns the enum name of the\n"
583 "/// specified instruction.\n"
584 "const char *" << Target.getName() << ClassName
585 << "::getInstructionName(unsigned Opcode) {\n"
586 << " assert(Opcode < " << NumberedInstructions.size()
587 << " && \"Invalid instruction number!\");\n"
589 << " static const unsigned InstAsmOffset[] = {";
590 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
591 const CodeGenInstruction &Inst = *NumberedInstructions[i];
593 std::string AsmName = Inst.TheDef->getName();
597 unsigned Idx = StringTable.GetOrAddStringOffset(AsmName);
598 assert(Idx <= 0xffff && "String offset too large to fit in table");
605 O << " const char *Strs =\n";
606 StringTable.EmitString(O);
609 O << " return Strs+InstAsmOffset[Opcode];\n"
614 // IAPrinter - Holds information about an InstAlias. Two InstAliases match if
615 // they both have the same conditionals. In which case, we cannot print out the
616 // alias for that pattern.
618 std::vector<std::string> Conds;
619 std::map<StringRef, unsigned> OpMap;
621 std::string AsmString;
622 std::vector<Record*> ReqFeatures;
624 IAPrinter(std::string R, std::string AS)
625 : Result(R), AsmString(AS) {}
627 void addCond(const std::string &C) { Conds.push_back(C); }
629 void addOperand(StringRef Op, unsigned Idx) { OpMap[Op] = Idx; }
630 unsigned getOpIndex(StringRef Op) { return OpMap[Op]; }
631 bool isOpMapped(StringRef Op) { return OpMap.find(Op) != OpMap.end(); }
633 void print(raw_ostream &O) {
634 if (Conds.empty() && ReqFeatures.empty()) {
635 O.indent(6) << "return true;\n";
641 for (std::vector<std::string>::iterator
642 I = Conds.begin(), E = Conds.end(); I != E; ++I) {
643 if (I != Conds.begin()) {
652 O.indent(6) << "// " << Result << "\n";
653 O.indent(6) << "AsmString = \"" << AsmString << "\";\n";
655 for (std::map<StringRef, unsigned>::iterator
656 I = OpMap.begin(), E = OpMap.end(); I != E; ++I)
657 O.indent(6) << "OpMap.push_back(std::make_pair(\"" << I->first << "\", "
658 << I->second << "));\n";
660 O.indent(6) << "break;\n";
664 bool operator==(const IAPrinter &RHS) {
665 if (Conds.size() != RHS.Conds.size())
669 for (std::vector<std::string>::iterator
670 I = Conds.begin(), E = Conds.end(); I != E; ++I)
671 if (*I != RHS.Conds[Idx++])
677 bool operator()(const IAPrinter &RHS) {
678 if (Conds.size() < RHS.Conds.size())
682 for (std::vector<std::string>::iterator
683 I = Conds.begin(), E = Conds.end(); I != E; ++I)
684 if (*I != RHS.Conds[Idx++])
685 return *I < RHS.Conds[Idx++];
691 } // end anonymous namespace
693 static void EmitGetMapOperandNumber(raw_ostream &O) {
694 O << "static unsigned getMapOperandNumber("
695 << "const SmallVectorImpl<std::pair<StringRef, unsigned> > &OpMap,\n";
696 O << " StringRef Name) {\n";
697 O << " for (SmallVectorImpl<std::pair<StringRef, unsigned> >::"
698 << "const_iterator\n";
699 O << " I = OpMap.begin(), E = OpMap.end(); I != E; ++I)\n";
700 O << " if (I->first == Name)\n";
701 O << " return I->second;\n";
702 O << " assert(false && \"Operand not in map!\");\n";
707 void AsmWriterEmitter::EmitRegIsInRegClass(raw_ostream &O) {
708 CodeGenTarget Target(Records);
710 // Enumerate the register classes.
711 ArrayRef<CodeGenRegisterClass*> RegisterClasses =
712 Target.getRegBank().getRegClasses();
714 O << "namespace { // Register classes\n";
715 O << " enum RegClass {\n";
717 // Emit the register enum value for each RegisterClass.
718 for (unsigned I = 0, E = RegisterClasses.size(); I != E; ++I) {
719 if (I != 0) O << ",\n";
720 O << " RC_" << RegisterClasses[I]->getName();
724 O << "} // end anonymous namespace\n\n";
726 // Emit a function that returns 'true' if a regsiter is part of a particular
727 // register class. I.e., RAX is part of GR64 on X86.
728 O << "static bool regIsInRegisterClass"
729 << "(unsigned RegClass, unsigned Reg) {\n";
731 // Emit the switch that checks if a register belongs to a particular register
733 O << " switch (RegClass) {\n";
734 O << " default: break;\n";
736 for (unsigned I = 0, E = RegisterClasses.size(); I != E; ++I) {
737 const CodeGenRegisterClass &RC = *RegisterClasses[I];
739 // Give the register class a legal C name if it's anonymous.
740 std::string Name = RC.getName();
741 O << " case RC_" << Name << ":\n";
743 // Emit the register list now.
744 unsigned IE = RC.getOrder().size();
746 O << " if (Reg == " << getQualifiedName(RC.getOrder()[0]) << ")\n";
747 O << " return true;\n";
749 O << " switch (Reg) {\n";
750 O << " default: break;\n";
752 for (unsigned II = 0; II != IE; ++II) {
753 Record *Reg = RC.getOrder()[II];
754 O << " case " << getQualifiedName(Reg) << ":\n";
757 O << " return true;\n";
765 O << " return false;\n";
769 static unsigned CountNumOperands(StringRef AsmString) {
771 std::pair<StringRef, StringRef> ASM = AsmString.split(' ');
773 while (!ASM.second.empty()) {
775 ASM = ASM.second.split(' ');
781 static unsigned CountResultNumOperands(StringRef AsmString) {
783 std::pair<StringRef, StringRef> ASM = AsmString.split('\t');
785 if (!ASM.second.empty()) {
786 size_t I = ASM.second.find('{');
787 StringRef Str = ASM.second;
788 if (I != StringRef::npos)
789 Str = ASM.second.substr(I, ASM.second.find('|', I));
791 ASM = Str.split(' ');
795 ASM = ASM.second.split(' ');
796 } while (!ASM.second.empty());
802 void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
803 CodeGenTarget Target(Records);
804 Record *AsmWriter = Target.getAsmWriter();
806 if (!AsmWriter->getValueAsBit("isMCAsmWriter"))
809 O << "\n#ifdef PRINT_ALIAS_INSTR\n";
810 O << "#undef PRINT_ALIAS_INSTR\n\n";
812 EmitRegIsInRegClass(O);
814 // Emit the method that prints the alias instruction.
815 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
817 std::vector<Record*> AllInstAliases =
818 Records.getAllDerivedDefinitions("InstAlias");
820 // Create a map from the qualified name to a list of potential matches.
821 std::map<std::string, std::vector<CodeGenInstAlias*> > AliasMap;
822 for (std::vector<Record*>::iterator
823 I = AllInstAliases.begin(), E = AllInstAliases.end(); I != E; ++I) {
824 CodeGenInstAlias *Alias = new CodeGenInstAlias(*I, Target);
825 const Record *R = *I;
826 if (!R->getValueAsBit("EmitAlias"))
827 continue; // We were told not to emit the alias, but to emit the aliasee.
828 const DagInit *DI = R->getValueAsDag("ResultInst");
829 const DefInit *Op = dynamic_cast<const DefInit*>(DI->getOperator());
830 AliasMap[getQualifiedName(Op->getDef())].push_back(Alias);
833 // A map of which conditions need to be met for each instruction operand
834 // before it can be matched to the mnemonic.
835 std::map<std::string, std::vector<IAPrinter*> > IAPrinterMap;
837 for (std::map<std::string, std::vector<CodeGenInstAlias*> >::iterator
838 I = AliasMap.begin(), E = AliasMap.end(); I != E; ++I) {
839 std::vector<CodeGenInstAlias*> &Aliases = I->second;
841 for (std::vector<CodeGenInstAlias*>::iterator
842 II = Aliases.begin(), IE = Aliases.end(); II != IE; ++II) {
843 const CodeGenInstAlias *CGA = *II;
844 unsigned LastOpNo = CGA->ResultInstOperandIndex.size();
845 unsigned NumResultOps =
846 CountResultNumOperands(CGA->ResultInst->AsmString);
848 // Don't emit the alias if it has more operands than what it's aliasing.
849 if (NumResultOps < CountNumOperands(CGA->AsmString))
852 IAPrinter *IAP = new IAPrinter(CGA->Result->getAsString(),
856 Cond = std::string("MI->getNumOperands() == ") + llvm::utostr(LastOpNo);
859 std::map<StringRef, unsigned> OpMap;
860 bool CantHandle = false;
862 for (unsigned i = 0, e = LastOpNo; i != e; ++i) {
863 const CodeGenInstAlias::ResultOperand &RO = CGA->ResultOperands[i];
866 case CodeGenInstAlias::ResultOperand::K_Record: {
867 const Record *Rec = RO.getRecord();
868 StringRef ROName = RO.getName();
871 if (Rec->isSubClassOf("RegisterOperand"))
872 Rec = Rec->getValueAsDef("RegClass");
873 if (Rec->isSubClassOf("RegisterClass")) {
874 Cond = std::string("MI->getOperand(")+llvm::utostr(i)+").isReg()";
877 if (!IAP->isOpMapped(ROName)) {
878 IAP->addOperand(ROName, i);
879 Cond = std::string("regIsInRegisterClass(RC_") +
880 CGA->ResultOperands[i].getRecord()->getName() +
881 ", MI->getOperand(" + llvm::utostr(i) + ").getReg())";
884 Cond = std::string("MI->getOperand(") +
885 llvm::utostr(i) + ").getReg() == MI->getOperand(" +
886 llvm::utostr(IAP->getOpIndex(ROName)) + ").getReg()";
890 assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
891 // FIXME: We may need to handle these situations.
900 case CodeGenInstAlias::ResultOperand::K_Imm:
901 Cond = std::string("MI->getOperand(") +
902 llvm::utostr(i) + ").getImm() == " +
903 llvm::utostr(CGA->ResultOperands[i].getImm());
906 case CodeGenInstAlias::ResultOperand::K_Reg:
907 // If this is zero_reg, something's playing tricks we're not
908 // equipped to handle.
909 if (!CGA->ResultOperands[i].getRegister()) {
914 Cond = std::string("MI->getOperand(") +
915 llvm::utostr(i) + ").getReg() == " + Target.getName() +
916 "::" + CGA->ResultOperands[i].getRegister()->getName();
924 if (CantHandle) continue;
925 IAPrinterMap[I->first].push_back(IAP);
930 raw_string_ostream HeaderO(Header);
932 HeaderO << "bool " << Target.getName() << ClassName
933 << "::printAliasInstr(const MCInst"
934 << " *MI, raw_ostream &OS) {\n";
937 raw_string_ostream CasesO(Cases);
939 for (std::map<std::string, std::vector<IAPrinter*> >::iterator
940 I = IAPrinterMap.begin(), E = IAPrinterMap.end(); I != E; ++I) {
941 std::vector<IAPrinter*> &IAPs = I->second;
942 std::vector<IAPrinter*> UniqueIAPs;
944 for (std::vector<IAPrinter*>::iterator
945 II = IAPs.begin(), IE = IAPs.end(); II != IE; ++II) {
946 IAPrinter *LHS = *II;
948 for (std::vector<IAPrinter*>::iterator
949 III = IAPs.begin(), IIE = IAPs.end(); III != IIE; ++III) {
950 IAPrinter *RHS = *III;
951 if (LHS != RHS && *LHS == *RHS) {
957 if (!IsDup) UniqueIAPs.push_back(LHS);
960 if (UniqueIAPs.empty()) continue;
962 CasesO.indent(2) << "case " << I->first << ":\n";
964 for (std::vector<IAPrinter*>::iterator
965 II = UniqueIAPs.begin(), IE = UniqueIAPs.end(); II != IE; ++II) {
966 IAPrinter *IAP = *II;
972 CasesO.indent(4) << "return false;\n";
975 if (CasesO.str().empty()) {
977 O << " return false;\n";
979 O << "#endif // PRINT_ALIAS_INSTR\n";
983 EmitGetMapOperandNumber(O);
986 O.indent(2) << "StringRef AsmString;\n";
987 O.indent(2) << "SmallVector<std::pair<StringRef, unsigned>, 4> OpMap;\n";
988 O.indent(2) << "switch (MI->getOpcode()) {\n";
989 O.indent(2) << "default: return false;\n";
991 O.indent(2) << "}\n\n";
993 // Code that prints the alias, replacing the operands with the ones from the
995 O << " std::pair<StringRef, StringRef> ASM = AsmString.split(' ');\n";
996 O << " OS << '\\t' << ASM.first;\n";
998 O << " if (!ASM.second.empty()) {\n";
999 O << " OS << '\\t';\n";
1000 O << " for (StringRef::iterator\n";
1001 O << " I = ASM.second.begin(), E = ASM.second.end(); I != E; ) {\n";
1002 O << " if (*I == '$') {\n";
1003 O << " StringRef::iterator Start = ++I;\n";
1004 O << " while (I != E &&\n";
1005 O << " ((*I >= 'a' && *I <= 'z') ||\n";
1006 O << " (*I >= 'A' && *I <= 'Z') ||\n";
1007 O << " (*I >= '0' && *I <= '9') ||\n";
1008 O << " *I == '_'))\n";
1010 O << " StringRef Name(Start, I - Start);\n";
1011 O << " printOperand(MI, getMapOperandNumber(OpMap, Name), OS);\n";
1013 O << " OS << *I++;\n";
1018 O << " return true;\n";
1021 O << "#endif // PRINT_ALIAS_INSTR\n";
1024 void AsmWriterEmitter::run(raw_ostream &O) {
1025 EmitSourceFileHeader("Assembly Writer Source Fragment", O);
1027 EmitPrintInstruction(O);
1028 EmitGetRegisterName(O);
1029 EmitGetInstructionName(O);
1030 EmitPrintAliasInstruction(O);