1 //===- AsmWriterEmitter.cpp - Generate an assembly writer -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is emits an assembly printer for the current target.
11 // Note that this is currently fairly skeletal, but will grow over time.
13 //===----------------------------------------------------------------------===//
15 #include "AsmWriterEmitter.h"
16 #include "CodeGenTarget.h"
18 #include "llvm/ADT/StringExtras.h"
19 #include "llvm/Support/Debug.h"
20 #include "llvm/Support/MathExtras.h"
24 static bool isIdentChar(char C) {
25 return (C >= 'a' && C <= 'z') ||
26 (C >= 'A' && C <= 'Z') ||
27 (C >= '0' && C <= '9') ||
32 struct AsmWriterOperand {
33 enum { isLiteralTextOperand, isMachineInstrOperand } OperandType;
35 /// Str - For isLiteralTextOperand, this IS the literal text. For
36 /// isMachineInstrOperand, this is the PrinterMethodName for the operand.
39 /// MiOpNo - For isMachineInstrOperand, this is the operand number of the
40 /// machine instruction.
43 /// MiModifier - For isMachineInstrOperand, this is the modifier string for
44 /// an operand, specified with syntax like ${opname:modifier}.
45 std::string MiModifier;
47 AsmWriterOperand(const std::string &LitStr)
48 : OperandType(isLiteralTextOperand), Str(LitStr) {}
50 AsmWriterOperand(const std::string &Printer, unsigned OpNo,
51 const std::string &Modifier)
52 : OperandType(isMachineInstrOperand), Str(Printer), MIOpNo(OpNo),
53 MiModifier(Modifier) {}
55 bool operator!=(const AsmWriterOperand &Other) const {
56 if (OperandType != Other.OperandType || Str != Other.Str) return true;
57 if (OperandType == isMachineInstrOperand)
58 return MIOpNo != Other.MIOpNo || MiModifier != Other.MiModifier;
61 bool operator==(const AsmWriterOperand &Other) const {
62 return !operator!=(Other);
65 /// getCode - Return the code that prints this operand.
66 std::string getCode() const;
73 std::vector<AsmWriterOperand> Operands;
74 const CodeGenInstruction *CGI;
76 AsmWriterInst(const CodeGenInstruction &CGI, unsigned Variant);
78 /// MatchesAllButOneOp - If this instruction is exactly identical to the
79 /// specified instruction except for one differing operand, return the
80 /// differing operand number. Otherwise return ~0.
81 unsigned MatchesAllButOneOp(const AsmWriterInst &Other) const;
84 void AddLiteralString(const std::string &Str) {
85 // If the last operand was already a literal text string, append this to
86 // it, otherwise add a new operand.
87 if (!Operands.empty() &&
88 Operands.back().OperandType == AsmWriterOperand::isLiteralTextOperand)
89 Operands.back().Str.append(Str);
91 Operands.push_back(AsmWriterOperand(Str));
97 std::string AsmWriterOperand::getCode() const {
98 if (OperandType == isLiteralTextOperand)
99 return "O << \"" + Str + "\"; ";
101 std::string Result = Str + "(MI";
103 Result += ", " + utostr(MIOpNo);
104 if (!MiModifier.empty())
105 Result += ", \"" + MiModifier + '"';
106 return Result + "); ";
110 /// ParseAsmString - Parse the specified Instruction's AsmString into this
113 AsmWriterInst::AsmWriterInst(const CodeGenInstruction &CGI, unsigned Variant) {
115 unsigned CurVariant = ~0U; // ~0 if we are outside a {.|.|.} region, other #.
117 // NOTE: Any extensions to this code need to be mirrored in the
118 // AsmPrinter::printInlineAsm code that executes as compile time (assuming
119 // that inline asm strings should also get the new feature)!
120 const std::string &AsmString = CGI.AsmString;
121 std::string::size_type LastEmitted = 0;
122 while (LastEmitted != AsmString.size()) {
123 std::string::size_type DollarPos =
124 AsmString.find_first_of("${|}", LastEmitted);
125 if (DollarPos == std::string::npos) DollarPos = AsmString.size();
127 // Emit a constant string fragment.
128 if (DollarPos != LastEmitted) {
129 // TODO: this should eventually handle escaping.
130 if (CurVariant == Variant || CurVariant == ~0U)
131 AddLiteralString(std::string(AsmString.begin()+LastEmitted,
132 AsmString.begin()+DollarPos));
133 LastEmitted = DollarPos;
134 } else if (AsmString[DollarPos] == '{') {
135 if (CurVariant != ~0U)
136 throw "Nested variants found for instruction '" +
137 CGI.TheDef->getName() + "'!";
138 LastEmitted = DollarPos+1;
139 CurVariant = 0; // We are now inside of the variant!
140 } else if (AsmString[DollarPos] == '|') {
141 if (CurVariant == ~0U)
142 throw "'|' character found outside of a variant in instruction '"
143 + CGI.TheDef->getName() + "'!";
146 } else if (AsmString[DollarPos] == '}') {
147 if (CurVariant == ~0U)
148 throw "'}' character found outside of a variant in instruction '"
149 + CGI.TheDef->getName() + "'!";
152 } else if (DollarPos+1 != AsmString.size() &&
153 AsmString[DollarPos+1] == '$') {
154 if (CurVariant == Variant || CurVariant == ~0U)
155 AddLiteralString("$"); // "$$" -> $
156 LastEmitted = DollarPos+2;
158 // Get the name of the variable.
159 std::string::size_type VarEnd = DollarPos+1;
161 // handle ${foo}bar as $foo by detecting whether the character following
162 // the dollar sign is a curly brace. If so, advance VarEnd and DollarPos
163 // so the variable name does not contain the leading curly brace.
164 bool hasCurlyBraces = false;
165 if (VarEnd < AsmString.size() && '{' == AsmString[VarEnd]) {
166 hasCurlyBraces = true;
171 while (VarEnd < AsmString.size() && isIdentChar(AsmString[VarEnd]))
173 std::string VarName(AsmString.begin()+DollarPos+1,
174 AsmString.begin()+VarEnd);
176 // Modifier - Support ${foo:modifier} syntax, where "modifier" is passed
177 // into printOperand. Also support ${:feature}, which is passed into
179 std::string Modifier;
181 // In order to avoid starting the next string at the terminating curly
182 // brace, advance the end position past it if we found an opening curly
184 if (hasCurlyBraces) {
185 if (VarEnd >= AsmString.size())
186 throw "Reached end of string before terminating curly brace in '"
187 + CGI.TheDef->getName() + "'";
189 // Look for a modifier string.
190 if (AsmString[VarEnd] == ':') {
192 if (VarEnd >= AsmString.size())
193 throw "Reached end of string before terminating curly brace in '"
194 + CGI.TheDef->getName() + "'";
196 unsigned ModifierStart = VarEnd;
197 while (VarEnd < AsmString.size() && isIdentChar(AsmString[VarEnd]))
199 Modifier = std::string(AsmString.begin()+ModifierStart,
200 AsmString.begin()+VarEnd);
201 if (Modifier.empty())
202 throw "Bad operand modifier name in '"+ CGI.TheDef->getName() + "'";
205 if (AsmString[VarEnd] != '}')
206 throw "Variable name beginning with '{' did not end with '}' in '"
207 + CGI.TheDef->getName() + "'";
210 if (VarName.empty() && Modifier.empty())
211 throw "Stray '$' in '" + CGI.TheDef->getName() +
212 "' asm string, maybe you want $$?";
214 if (VarName.empty()) {
215 // Just a modifier, pass this into PrintSpecial.
216 Operands.push_back(AsmWriterOperand("PrintSpecial", ~0U, Modifier));
218 // Otherwise, normal operand.
219 unsigned OpNo = CGI.getOperandNamed(VarName);
220 CodeGenInstruction::OperandInfo OpInfo = CGI.OperandList[OpNo];
222 if (CurVariant == Variant || CurVariant == ~0U) {
223 unsigned MIOp = OpInfo.MIOperandNo;
224 Operands.push_back(AsmWriterOperand(OpInfo.PrinterMethodName, MIOp,
228 LastEmitted = VarEnd;
232 AddLiteralString("\\n");
235 /// MatchesAllButOneOp - If this instruction is exactly identical to the
236 /// specified instruction except for one differing operand, return the differing
237 /// operand number. If more than one operand mismatches, return ~1, otherwise
238 /// if the instructions are identical return ~0.
239 unsigned AsmWriterInst::MatchesAllButOneOp(const AsmWriterInst &Other)const{
240 if (Operands.size() != Other.Operands.size()) return ~1;
242 unsigned MismatchOperand = ~0U;
243 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
244 if (Operands[i] != Other.Operands[i])
245 if (MismatchOperand != ~0U) // Already have one mismatch?
250 return MismatchOperand;
253 static void PrintCases(std::vector<std::pair<std::string,
254 AsmWriterOperand> > &OpsToPrint, std::ostream &O) {
255 O << " case " << OpsToPrint.back().first << ": ";
256 AsmWriterOperand TheOp = OpsToPrint.back().second;
257 OpsToPrint.pop_back();
259 // Check to see if any other operands are identical in this list, and if so,
260 // emit a case label for them.
261 for (unsigned i = OpsToPrint.size(); i != 0; --i)
262 if (OpsToPrint[i-1].second == TheOp) {
263 O << "\n case " << OpsToPrint[i-1].first << ": ";
264 OpsToPrint.erase(OpsToPrint.begin()+i-1);
267 // Finally, emit the code.
268 O << TheOp.getCode();
273 /// EmitInstructions - Emit the last instruction in the vector and any other
274 /// instructions that are suitably similar to it.
275 static void EmitInstructions(std::vector<AsmWriterInst> &Insts,
277 AsmWriterInst FirstInst = Insts.back();
280 std::vector<AsmWriterInst> SimilarInsts;
281 unsigned DifferingOperand = ~0;
282 for (unsigned i = Insts.size(); i != 0; --i) {
283 unsigned DiffOp = Insts[i-1].MatchesAllButOneOp(FirstInst);
285 if (DifferingOperand == ~0U) // First match!
286 DifferingOperand = DiffOp;
288 // If this differs in the same operand as the rest of the instructions in
289 // this class, move it to the SimilarInsts list.
290 if (DifferingOperand == DiffOp || DiffOp == ~0U) {
291 SimilarInsts.push_back(Insts[i-1]);
292 Insts.erase(Insts.begin()+i-1);
297 O << " case " << FirstInst.CGI->Namespace << "::"
298 << FirstInst.CGI->TheDef->getName() << ":\n";
299 for (unsigned i = 0, e = SimilarInsts.size(); i != e; ++i)
300 O << " case " << SimilarInsts[i].CGI->Namespace << "::"
301 << SimilarInsts[i].CGI->TheDef->getName() << ":\n";
302 for (unsigned i = 0, e = FirstInst.Operands.size(); i != e; ++i) {
303 if (i != DifferingOperand) {
304 // If the operand is the same for all instructions, just print it.
305 O << " " << FirstInst.Operands[i].getCode();
307 // If this is the operand that varies between all of the instructions,
308 // emit a switch for just this operand now.
309 O << " switch (MI->getOpcode()) {\n";
310 std::vector<std::pair<std::string, AsmWriterOperand> > OpsToPrint;
311 OpsToPrint.push_back(std::make_pair(FirstInst.CGI->Namespace + "::" +
312 FirstInst.CGI->TheDef->getName(),
313 FirstInst.Operands[i]));
315 for (unsigned si = 0, e = SimilarInsts.size(); si != e; ++si) {
316 AsmWriterInst &AWI = SimilarInsts[si];
317 OpsToPrint.push_back(std::make_pair(AWI.CGI->Namespace+"::"+
318 AWI.CGI->TheDef->getName(),
321 std::reverse(OpsToPrint.begin(), OpsToPrint.end());
322 while (!OpsToPrint.empty())
323 PrintCases(OpsToPrint, O);
332 void AsmWriterEmitter::
333 FindUniqueOperandCommands(std::vector<std::string> &UniqueOperandCommands,
334 std::vector<unsigned> &InstIdxs,
335 std::vector<unsigned> &InstOpsUsed) const {
336 InstIdxs.assign(NumberedInstructions.size(), ~0U);
338 // This vector parallels UniqueOperandCommands, keeping track of which
339 // instructions each case are used for. It is a comma separated string of
341 std::vector<std::string> InstrsForCase;
342 InstrsForCase.resize(UniqueOperandCommands.size());
343 InstOpsUsed.assign(UniqueOperandCommands.size(), 0);
345 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
346 const AsmWriterInst *Inst = getAsmWriterInstByID(i);
347 if (Inst == 0) continue; // PHI, INLINEASM, LABEL, etc.
350 if (Inst->Operands.empty())
351 continue; // Instruction already done.
353 Command = " " + Inst->Operands[0].getCode() + "\n";
355 // If this is the last operand, emit a return.
356 if (Inst->Operands.size() == 1)
357 Command += " return true;\n";
359 // Check to see if we already have 'Command' in UniqueOperandCommands.
361 bool FoundIt = false;
362 for (unsigned idx = 0, e = UniqueOperandCommands.size(); idx != e; ++idx)
363 if (UniqueOperandCommands[idx] == Command) {
365 InstrsForCase[idx] += ", ";
366 InstrsForCase[idx] += Inst->CGI->TheDef->getName();
371 InstIdxs[i] = UniqueOperandCommands.size();
372 UniqueOperandCommands.push_back(Command);
373 InstrsForCase.push_back(Inst->CGI->TheDef->getName());
375 // This command matches one operand so far.
376 InstOpsUsed.push_back(1);
380 // For each entry of UniqueOperandCommands, there is a set of instructions
381 // that uses it. If the next command of all instructions in the set are
382 // identical, fold it into the command.
383 for (unsigned CommandIdx = 0, e = UniqueOperandCommands.size();
384 CommandIdx != e; ++CommandIdx) {
386 for (unsigned Op = 1; ; ++Op) {
387 // Scan for the first instruction in the set.
388 std::vector<unsigned>::iterator NIT =
389 std::find(InstIdxs.begin(), InstIdxs.end(), CommandIdx);
390 if (NIT == InstIdxs.end()) break; // No commonality.
392 // If this instruction has no more operands, we isn't anything to merge
393 // into this command.
394 const AsmWriterInst *FirstInst =
395 getAsmWriterInstByID(NIT-InstIdxs.begin());
396 if (!FirstInst || FirstInst->Operands.size() == Op)
399 // Otherwise, scan to see if all of the other instructions in this command
400 // set share the operand.
403 for (NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx);
404 NIT != InstIdxs.end();
405 NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx)) {
406 // Okay, found another instruction in this command set. If the operand
407 // matches, we're ok, otherwise bail out.
408 const AsmWriterInst *OtherInst =
409 getAsmWriterInstByID(NIT-InstIdxs.begin());
410 if (!OtherInst || OtherInst->Operands.size() == Op ||
411 OtherInst->Operands[Op] != FirstInst->Operands[Op]) {
418 // Okay, everything in this command set has the same next operand. Add it
419 // to UniqueOperandCommands and remember that it was consumed.
420 std::string Command = " " + FirstInst->Operands[Op].getCode() + "\n";
422 // If this is the last operand, emit a return after the code.
423 if (FirstInst->Operands.size() == Op+1)
424 Command += " return true;\n";
426 UniqueOperandCommands[CommandIdx] += Command;
427 InstOpsUsed[CommandIdx]++;
431 // Prepend some of the instructions each case is used for onto the case val.
432 for (unsigned i = 0, e = InstrsForCase.size(); i != e; ++i) {
433 std::string Instrs = InstrsForCase[i];
434 if (Instrs.size() > 70) {
435 Instrs.erase(Instrs.begin()+70, Instrs.end());
440 UniqueOperandCommands[i] = " // " + Instrs + "\n" +
441 UniqueOperandCommands[i];
447 void AsmWriterEmitter::run(std::ostream &O) {
448 EmitSourceFileHeader("Assembly Writer Source Fragment", O);
450 CodeGenTarget Target;
451 Record *AsmWriter = Target.getAsmWriter();
452 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
453 unsigned Variant = AsmWriter->getValueAsInt("Variant");
456 "/// printInstruction - This method is automatically generated by tablegen\n"
457 "/// from the instruction set description. This method returns true if the\n"
458 "/// machine instruction was sufficiently described to print it, otherwise\n"
459 "/// it returns false.\n"
460 "bool " << Target.getName() << ClassName
461 << "::printInstruction(const MachineInstr *MI) {\n";
463 std::vector<AsmWriterInst> Instructions;
465 for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
466 E = Target.inst_end(); I != E; ++I)
467 if (!I->second.AsmString.empty())
468 Instructions.push_back(AsmWriterInst(I->second, Variant));
470 // Get the instruction numbering.
471 Target.getInstructionsByEnumValue(NumberedInstructions);
473 // Compute the CodeGenInstruction -> AsmWriterInst mapping. Note that not
474 // all machine instructions are necessarily being printed, so there may be
475 // target instructions not in this map.
476 for (unsigned i = 0, e = Instructions.size(); i != e; ++i)
477 CGIAWIMap.insert(std::make_pair(Instructions[i].CGI, &Instructions[i]));
479 // Build an aggregate string, and build a table of offsets into it.
480 std::map<std::string, unsigned> StringOffset;
481 std::string AggregateString;
482 AggregateString.push_back(0); // "\0"
483 AggregateString.push_back(0); // "\0"
485 /// OpcodeInfo - This encodes the index of the string to use for the first
486 /// chunk of the output as well as indices used for operand printing.
487 std::vector<unsigned> OpcodeInfo;
489 unsigned MaxStringIdx = 0;
490 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
491 AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions[i]];
494 // Something not handled by the asmwriter printer.
496 } else if (AWI->Operands[0].OperandType !=
497 AsmWriterOperand::isLiteralTextOperand ||
498 AWI->Operands[0].Str.empty()) {
499 // Something handled by the asmwriter printer, but with no leading string.
502 unsigned &Entry = StringOffset[AWI->Operands[0].Str];
504 // Add the string to the aggregate if this is the first time found.
505 MaxStringIdx = Entry = AggregateString.size();
506 std::string Str = AWI->Operands[0].Str;
508 AggregateString += Str;
509 AggregateString += '\0';
513 // Nuke the string from the operand list. It is now handled!
514 AWI->Operands.erase(AWI->Operands.begin());
516 OpcodeInfo.push_back(Idx);
519 // Figure out how many bits we used for the string index.
520 unsigned AsmStrBits = Log2_32_Ceil(MaxStringIdx);
522 // To reduce code size, we compactify common instructions into a few bits
523 // in the opcode-indexed table.
524 unsigned BitsLeft = 32-AsmStrBits;
526 std::vector<std::vector<std::string> > TableDrivenOperandPrinters;
530 std::vector<std::string> UniqueOperandCommands;
532 // For the first operand check, add a default value for instructions with
533 // just opcode strings to use.
535 UniqueOperandCommands.push_back(" return true;\n");
539 std::vector<unsigned> InstIdxs;
540 std::vector<unsigned> NumInstOpsHandled;
541 FindUniqueOperandCommands(UniqueOperandCommands, InstIdxs,
544 // If we ran out of operands to print, we're done.
545 if (UniqueOperandCommands.empty()) break;
547 // Compute the number of bits we need to represent these cases, this is
548 // ceil(log2(numentries)).
549 unsigned NumBits = Log2_32_Ceil(UniqueOperandCommands.size());
551 // If we don't have enough bits for this operand, don't include it.
552 if (NumBits > BitsLeft) {
553 DOUT << "Not enough bits to densely encode " << NumBits
558 // Otherwise, we can include this in the initial lookup table. Add it in.
560 for (unsigned i = 0, e = InstIdxs.size(); i != e; ++i)
561 if (InstIdxs[i] != ~0U)
562 OpcodeInfo[i] |= InstIdxs[i] << (BitsLeft+AsmStrBits);
564 // Remove the info about this operand.
565 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
566 if (AsmWriterInst *Inst = getAsmWriterInstByID(i))
567 if (!Inst->Operands.empty()) {
568 unsigned NumOps = NumInstOpsHandled[InstIdxs[i]];
569 assert(NumOps <= Inst->Operands.size() &&
570 "Can't remove this many ops!");
571 Inst->Operands.erase(Inst->Operands.begin(),
572 Inst->Operands.begin()+NumOps);
576 // Remember the handlers for this set of operands.
577 TableDrivenOperandPrinters.push_back(UniqueOperandCommands);
582 O<<" static const unsigned OpInfo[] = {\n";
583 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
584 O << " " << OpcodeInfo[i] << "U,\t// "
585 << NumberedInstructions[i]->TheDef->getName() << "\n";
587 // Add a dummy entry so the array init doesn't end with a comma.
591 // Emit the string itself.
592 O << " const char *AsmStrs = \n \"";
593 unsigned CharsPrinted = 0;
594 EscapeString(AggregateString);
595 for (unsigned i = 0, e = AggregateString.size(); i != e; ++i) {
596 if (CharsPrinted > 70) {
600 O << AggregateString[i];
603 // Print escape sequences all together.
604 if (AggregateString[i] == '\\') {
605 assert(i+1 < AggregateString.size() && "Incomplete escape sequence!");
606 if (isdigit(AggregateString[i+1])) {
607 assert(isdigit(AggregateString[i+2]) && isdigit(AggregateString[i+3]) &&
608 "Expected 3 digit octal escape!");
609 O << AggregateString[++i];
610 O << AggregateString[++i];
611 O << AggregateString[++i];
614 O << AggregateString[++i];
621 O << " if (MI->getOpcode() == TargetInstrInfo::INLINEASM) {\n"
622 << " printInlineAsm(MI);\n"
624 << " } else if (MI->getOpcode() == TargetInstrInfo::LABEL) {\n"
625 << " printLabel(MI);\n"
629 O << " // Emit the opcode for the instruction.\n"
630 << " unsigned Bits = OpInfo[MI->getOpcode()];\n"
631 << " if (Bits == 0) return false;\n"
632 << " O << AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << ");\n\n";
634 // Output the table driven operand information.
635 BitsLeft = 32-AsmStrBits;
636 for (unsigned i = 0, e = TableDrivenOperandPrinters.size(); i != e; ++i) {
637 std::vector<std::string> &Commands = TableDrivenOperandPrinters[i];
639 // Compute the number of bits we need to represent these cases, this is
640 // ceil(log2(numentries)).
641 unsigned NumBits = Log2_32_Ceil(Commands.size());
642 assert(NumBits <= BitsLeft && "consistency error");
644 // Emit code to extract this field from Bits.
647 O << "\n // Fragment " << i << " encoded into " << NumBits
648 << " bits for " << Commands.size() << " unique commands.\n";
650 if (Commands.size() == 2) {
651 // Emit two possibilitys with if/else.
652 O << " if ((Bits >> " << (BitsLeft+AsmStrBits) << ") & "
653 << ((1 << NumBits)-1) << ") {\n"
659 O << " switch ((Bits >> " << (BitsLeft+AsmStrBits) << ") & "
660 << ((1 << NumBits)-1) << ") {\n"
661 << " default: // unreachable.\n";
663 // Print out all the cases.
664 for (unsigned i = 0, e = Commands.size(); i != e; ++i) {
665 O << " case " << i << ":\n";
673 // Okay, delete instructions with no operand info left.
674 for (unsigned i = 0, e = Instructions.size(); i != e; ++i) {
675 // Entire instruction has been emitted?
676 AsmWriterInst &Inst = Instructions[i];
677 if (Inst.Operands.empty()) {
678 Instructions.erase(Instructions.begin()+i);
684 // Because this is a vector, we want to emit from the end. Reverse all of the
685 // elements in the vector.
686 std::reverse(Instructions.begin(), Instructions.end());
688 if (!Instructions.empty()) {
689 // Find the opcode # of inline asm.
690 O << " switch (MI->getOpcode()) {\n";
691 while (!Instructions.empty())
692 EmitInstructions(Instructions, O);
695 O << " return true;\n";