1 //===- AsmWriterEmitter.cpp - Generate an assembly writer -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is emits an assembly printer for the current target.
11 // Note that this is currently fairly skeletal, but will grow over time.
13 //===----------------------------------------------------------------------===//
15 #include "AsmWriterEmitter.h"
16 #include "CodeGenTarget.h"
18 #include "llvm/ADT/StringExtras.h"
19 #include "llvm/Support/Debug.h"
20 #include "llvm/Support/MathExtras.h"
24 static bool isIdentChar(char C) {
25 return (C >= 'a' && C <= 'z') ||
26 (C >= 'A' && C <= 'Z') ||
27 (C >= '0' && C <= '9') ||
31 // This should be an anon namespace, this works around a GCC warning.
33 struct AsmWriterOperand {
34 enum { isLiteralTextOperand, isMachineInstrOperand } OperandType;
36 /// Str - For isLiteralTextOperand, this IS the literal text. For
37 /// isMachineInstrOperand, this is the PrinterMethodName for the operand.
40 /// MiOpNo - For isMachineInstrOperand, this is the operand number of the
41 /// machine instruction.
44 /// MiModifier - For isMachineInstrOperand, this is the modifier string for
45 /// an operand, specified with syntax like ${opname:modifier}.
46 std::string MiModifier;
48 AsmWriterOperand(const std::string &LitStr)
49 : OperandType(isLiteralTextOperand), Str(LitStr) {}
51 AsmWriterOperand(const std::string &Printer, unsigned OpNo,
52 const std::string &Modifier)
53 : OperandType(isMachineInstrOperand), Str(Printer), MIOpNo(OpNo),
54 MiModifier(Modifier) {}
56 bool operator!=(const AsmWriterOperand &Other) const {
57 if (OperandType != Other.OperandType || Str != Other.Str) return true;
58 if (OperandType == isMachineInstrOperand)
59 return MIOpNo != Other.MIOpNo || MiModifier != Other.MiModifier;
62 bool operator==(const AsmWriterOperand &Other) const {
63 return !operator!=(Other);
66 /// getCode - Return the code that prints this operand.
67 std::string getCode() const;
74 std::vector<AsmWriterOperand> Operands;
75 const CodeGenInstruction *CGI;
77 AsmWriterInst(const CodeGenInstruction &CGI, unsigned Variant);
79 /// MatchesAllButOneOp - If this instruction is exactly identical to the
80 /// specified instruction except for one differing operand, return the
81 /// differing operand number. Otherwise return ~0.
82 unsigned MatchesAllButOneOp(const AsmWriterInst &Other) const;
85 void AddLiteralString(const std::string &Str) {
86 // If the last operand was already a literal text string, append this to
87 // it, otherwise add a new operand.
88 if (!Operands.empty() &&
89 Operands.back().OperandType == AsmWriterOperand::isLiteralTextOperand)
90 Operands.back().Str.append(Str);
92 Operands.push_back(AsmWriterOperand(Str));
98 std::string AsmWriterOperand::getCode() const {
99 if (OperandType == isLiteralTextOperand)
100 return "O << \"" + Str + "\"; ";
102 std::string Result = Str + "(MI";
104 Result += ", " + utostr(MIOpNo);
105 if (!MiModifier.empty())
106 Result += ", \"" + MiModifier + '"';
107 return Result + "); ";
111 /// ParseAsmString - Parse the specified Instruction's AsmString into this
114 AsmWriterInst::AsmWriterInst(const CodeGenInstruction &CGI, unsigned Variant) {
116 unsigned CurVariant = ~0U; // ~0 if we are outside a {.|.|.} region, other #.
118 // NOTE: Any extensions to this code need to be mirrored in the
119 // AsmPrinter::printInlineAsm code that executes as compile time (assuming
120 // that inline asm strings should also get the new feature)!
121 const std::string &AsmString = CGI.AsmString;
122 std::string::size_type LastEmitted = 0;
123 while (LastEmitted != AsmString.size()) {
124 std::string::size_type DollarPos =
125 AsmString.find_first_of("${|}", LastEmitted);
126 if (DollarPos == std::string::npos) DollarPos = AsmString.size();
128 // Emit a constant string fragment.
129 if (DollarPos != LastEmitted) {
130 // TODO: this should eventually handle escaping.
131 if (CurVariant == Variant || CurVariant == ~0U)
132 AddLiteralString(std::string(AsmString.begin()+LastEmitted,
133 AsmString.begin()+DollarPos));
134 LastEmitted = DollarPos;
135 } else if (AsmString[DollarPos] == '{') {
136 if (CurVariant != ~0U)
137 throw "Nested variants found for instruction '" +
138 CGI.TheDef->getName() + "'!";
139 LastEmitted = DollarPos+1;
140 CurVariant = 0; // We are now inside of the variant!
141 } else if (AsmString[DollarPos] == '|') {
142 if (CurVariant == ~0U)
143 throw "'|' character found outside of a variant in instruction '"
144 + CGI.TheDef->getName() + "'!";
147 } else if (AsmString[DollarPos] == '}') {
148 if (CurVariant == ~0U)
149 throw "'}' character found outside of a variant in instruction '"
150 + CGI.TheDef->getName() + "'!";
153 } else if (DollarPos+1 != AsmString.size() &&
154 AsmString[DollarPos+1] == '$') {
155 if (CurVariant == Variant || CurVariant == ~0U)
156 AddLiteralString("$"); // "$$" -> $
157 LastEmitted = DollarPos+2;
159 // Get the name of the variable.
160 std::string::size_type VarEnd = DollarPos+1;
162 // handle ${foo}bar as $foo by detecting whether the character following
163 // the dollar sign is a curly brace. If so, advance VarEnd and DollarPos
164 // so the variable name does not contain the leading curly brace.
165 bool hasCurlyBraces = false;
166 if (VarEnd < AsmString.size() && '{' == AsmString[VarEnd]) {
167 hasCurlyBraces = true;
172 while (VarEnd < AsmString.size() && isIdentChar(AsmString[VarEnd]))
174 std::string VarName(AsmString.begin()+DollarPos+1,
175 AsmString.begin()+VarEnd);
177 // Modifier - Support ${foo:modifier} syntax, where "modifier" is passed
178 // into printOperand. Also support ${:feature}, which is passed into
180 std::string Modifier;
182 // In order to avoid starting the next string at the terminating curly
183 // brace, advance the end position past it if we found an opening curly
185 if (hasCurlyBraces) {
186 if (VarEnd >= AsmString.size())
187 throw "Reached end of string before terminating curly brace in '"
188 + CGI.TheDef->getName() + "'";
190 // Look for a modifier string.
191 if (AsmString[VarEnd] == ':') {
193 if (VarEnd >= AsmString.size())
194 throw "Reached end of string before terminating curly brace in '"
195 + CGI.TheDef->getName() + "'";
197 unsigned ModifierStart = VarEnd;
198 while (VarEnd < AsmString.size() && isIdentChar(AsmString[VarEnd]))
200 Modifier = std::string(AsmString.begin()+ModifierStart,
201 AsmString.begin()+VarEnd);
202 if (Modifier.empty())
203 throw "Bad operand modifier name in '"+ CGI.TheDef->getName() + "'";
206 if (AsmString[VarEnd] != '}')
207 throw "Variable name beginning with '{' did not end with '}' in '"
208 + CGI.TheDef->getName() + "'";
211 if (VarName.empty() && Modifier.empty())
212 throw "Stray '$' in '" + CGI.TheDef->getName() +
213 "' asm string, maybe you want $$?";
215 if (VarName.empty()) {
216 // Just a modifier, pass this into PrintSpecial.
217 Operands.push_back(AsmWriterOperand("PrintSpecial", ~0U, Modifier));
219 // Otherwise, normal operand.
220 unsigned OpNo = CGI.getOperandNamed(VarName);
221 CodeGenInstruction::OperandInfo OpInfo = CGI.OperandList[OpNo];
223 if (CurVariant == Variant || CurVariant == ~0U) {
224 unsigned MIOp = OpInfo.MIOperandNo;
225 Operands.push_back(AsmWriterOperand(OpInfo.PrinterMethodName, MIOp,
229 LastEmitted = VarEnd;
233 AddLiteralString("\\n");
236 /// MatchesAllButOneOp - If this instruction is exactly identical to the
237 /// specified instruction except for one differing operand, return the differing
238 /// operand number. If more than one operand mismatches, return ~1, otherwise
239 /// if the instructions are identical return ~0.
240 unsigned AsmWriterInst::MatchesAllButOneOp(const AsmWriterInst &Other)const{
241 if (Operands.size() != Other.Operands.size()) return ~1;
243 unsigned MismatchOperand = ~0U;
244 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
245 if (Operands[i] != Other.Operands[i]) {
246 if (MismatchOperand != ~0U) // Already have one mismatch?
252 return MismatchOperand;
255 static void PrintCases(std::vector<std::pair<std::string,
256 AsmWriterOperand> > &OpsToPrint, std::ostream &O) {
257 O << " case " << OpsToPrint.back().first << ": ";
258 AsmWriterOperand TheOp = OpsToPrint.back().second;
259 OpsToPrint.pop_back();
261 // Check to see if any other operands are identical in this list, and if so,
262 // emit a case label for them.
263 for (unsigned i = OpsToPrint.size(); i != 0; --i)
264 if (OpsToPrint[i-1].second == TheOp) {
265 O << "\n case " << OpsToPrint[i-1].first << ": ";
266 OpsToPrint.erase(OpsToPrint.begin()+i-1);
269 // Finally, emit the code.
270 O << TheOp.getCode();
275 /// EmitInstructions - Emit the last instruction in the vector and any other
276 /// instructions that are suitably similar to it.
277 static void EmitInstructions(std::vector<AsmWriterInst> &Insts,
279 AsmWriterInst FirstInst = Insts.back();
282 std::vector<AsmWriterInst> SimilarInsts;
283 unsigned DifferingOperand = ~0;
284 for (unsigned i = Insts.size(); i != 0; --i) {
285 unsigned DiffOp = Insts[i-1].MatchesAllButOneOp(FirstInst);
287 if (DifferingOperand == ~0U) // First match!
288 DifferingOperand = DiffOp;
290 // If this differs in the same operand as the rest of the instructions in
291 // this class, move it to the SimilarInsts list.
292 if (DifferingOperand == DiffOp || DiffOp == ~0U) {
293 SimilarInsts.push_back(Insts[i-1]);
294 Insts.erase(Insts.begin()+i-1);
299 O << " case " << FirstInst.CGI->Namespace << "::"
300 << FirstInst.CGI->TheDef->getName() << ":\n";
301 for (unsigned i = 0, e = SimilarInsts.size(); i != e; ++i)
302 O << " case " << SimilarInsts[i].CGI->Namespace << "::"
303 << SimilarInsts[i].CGI->TheDef->getName() << ":\n";
304 for (unsigned i = 0, e = FirstInst.Operands.size(); i != e; ++i) {
305 if (i != DifferingOperand) {
306 // If the operand is the same for all instructions, just print it.
307 O << " " << FirstInst.Operands[i].getCode();
309 // If this is the operand that varies between all of the instructions,
310 // emit a switch for just this operand now.
311 O << " switch (MI->getOpcode()) {\n";
312 std::vector<std::pair<std::string, AsmWriterOperand> > OpsToPrint;
313 OpsToPrint.push_back(std::make_pair(FirstInst.CGI->Namespace + "::" +
314 FirstInst.CGI->TheDef->getName(),
315 FirstInst.Operands[i]));
317 for (unsigned si = 0, e = SimilarInsts.size(); si != e; ++si) {
318 AsmWriterInst &AWI = SimilarInsts[si];
319 OpsToPrint.push_back(std::make_pair(AWI.CGI->Namespace+"::"+
320 AWI.CGI->TheDef->getName(),
323 std::reverse(OpsToPrint.begin(), OpsToPrint.end());
324 while (!OpsToPrint.empty())
325 PrintCases(OpsToPrint, O);
334 void AsmWriterEmitter::
335 FindUniqueOperandCommands(std::vector<std::string> &UniqueOperandCommands,
336 std::vector<unsigned> &InstIdxs,
337 std::vector<unsigned> &InstOpsUsed) const {
338 InstIdxs.assign(NumberedInstructions.size(), ~0U);
340 // This vector parallels UniqueOperandCommands, keeping track of which
341 // instructions each case are used for. It is a comma separated string of
343 std::vector<std::string> InstrsForCase;
344 InstrsForCase.resize(UniqueOperandCommands.size());
345 InstOpsUsed.assign(UniqueOperandCommands.size(), 0);
347 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
348 const AsmWriterInst *Inst = getAsmWriterInstByID(i);
349 if (Inst == 0) continue; // PHI, INLINEASM, LABEL, etc.
352 if (Inst->Operands.empty())
353 continue; // Instruction already done.
355 Command = " " + Inst->Operands[0].getCode() + "\n";
357 // If this is the last operand, emit a return.
358 if (Inst->Operands.size() == 1)
359 Command += " return true;\n";
361 // Check to see if we already have 'Command' in UniqueOperandCommands.
363 bool FoundIt = false;
364 for (unsigned idx = 0, e = UniqueOperandCommands.size(); idx != e; ++idx)
365 if (UniqueOperandCommands[idx] == Command) {
367 InstrsForCase[idx] += ", ";
368 InstrsForCase[idx] += Inst->CGI->TheDef->getName();
373 InstIdxs[i] = UniqueOperandCommands.size();
374 UniqueOperandCommands.push_back(Command);
375 InstrsForCase.push_back(Inst->CGI->TheDef->getName());
377 // This command matches one operand so far.
378 InstOpsUsed.push_back(1);
382 // For each entry of UniqueOperandCommands, there is a set of instructions
383 // that uses it. If the next command of all instructions in the set are
384 // identical, fold it into the command.
385 for (unsigned CommandIdx = 0, e = UniqueOperandCommands.size();
386 CommandIdx != e; ++CommandIdx) {
388 for (unsigned Op = 1; ; ++Op) {
389 // Scan for the first instruction in the set.
390 std::vector<unsigned>::iterator NIT =
391 std::find(InstIdxs.begin(), InstIdxs.end(), CommandIdx);
392 if (NIT == InstIdxs.end()) break; // No commonality.
394 // If this instruction has no more operands, we isn't anything to merge
395 // into this command.
396 const AsmWriterInst *FirstInst =
397 getAsmWriterInstByID(NIT-InstIdxs.begin());
398 if (!FirstInst || FirstInst->Operands.size() == Op)
401 // Otherwise, scan to see if all of the other instructions in this command
402 // set share the operand.
405 for (NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx);
406 NIT != InstIdxs.end();
407 NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx)) {
408 // Okay, found another instruction in this command set. If the operand
409 // matches, we're ok, otherwise bail out.
410 const AsmWriterInst *OtherInst =
411 getAsmWriterInstByID(NIT-InstIdxs.begin());
412 if (!OtherInst || OtherInst->Operands.size() == Op ||
413 OtherInst->Operands[Op] != FirstInst->Operands[Op]) {
420 // Okay, everything in this command set has the same next operand. Add it
421 // to UniqueOperandCommands and remember that it was consumed.
422 std::string Command = " " + FirstInst->Operands[Op].getCode() + "\n";
424 // If this is the last operand, emit a return after the code.
425 if (FirstInst->Operands.size() == Op+1)
426 Command += " return true;\n";
428 UniqueOperandCommands[CommandIdx] += Command;
429 InstOpsUsed[CommandIdx]++;
433 // Prepend some of the instructions each case is used for onto the case val.
434 for (unsigned i = 0, e = InstrsForCase.size(); i != e; ++i) {
435 std::string Instrs = InstrsForCase[i];
436 if (Instrs.size() > 70) {
437 Instrs.erase(Instrs.begin()+70, Instrs.end());
442 UniqueOperandCommands[i] = " // " + Instrs + "\n" +
443 UniqueOperandCommands[i];
449 void AsmWriterEmitter::run(std::ostream &O) {
450 EmitSourceFileHeader("Assembly Writer Source Fragment", O);
452 CodeGenTarget Target;
453 Record *AsmWriter = Target.getAsmWriter();
454 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
455 unsigned Variant = AsmWriter->getValueAsInt("Variant");
458 "/// printInstruction - This method is automatically generated by tablegen\n"
459 "/// from the instruction set description. This method returns true if the\n"
460 "/// machine instruction was sufficiently described to print it, otherwise\n"
461 "/// it returns false.\n"
462 "bool " << Target.getName() << ClassName
463 << "::printInstruction(const MachineInstr *MI) {\n";
465 std::vector<AsmWriterInst> Instructions;
467 for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
468 E = Target.inst_end(); I != E; ++I)
469 if (!I->second.AsmString.empty())
470 Instructions.push_back(AsmWriterInst(I->second, Variant));
472 // Get the instruction numbering.
473 Target.getInstructionsByEnumValue(NumberedInstructions);
475 // Compute the CodeGenInstruction -> AsmWriterInst mapping. Note that not
476 // all machine instructions are necessarily being printed, so there may be
477 // target instructions not in this map.
478 for (unsigned i = 0, e = Instructions.size(); i != e; ++i)
479 CGIAWIMap.insert(std::make_pair(Instructions[i].CGI, &Instructions[i]));
481 // Build an aggregate string, and build a table of offsets into it.
482 std::map<std::string, unsigned> StringOffset;
483 std::string AggregateString;
484 AggregateString.push_back(0); // "\0"
485 AggregateString.push_back(0); // "\0"
487 /// OpcodeInfo - This encodes the index of the string to use for the first
488 /// chunk of the output as well as indices used for operand printing.
489 std::vector<unsigned> OpcodeInfo;
491 unsigned MaxStringIdx = 0;
492 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
493 AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions[i]];
496 // Something not handled by the asmwriter printer.
498 } else if (AWI->Operands[0].OperandType !=
499 AsmWriterOperand::isLiteralTextOperand ||
500 AWI->Operands[0].Str.empty()) {
501 // Something handled by the asmwriter printer, but with no leading string.
504 unsigned &Entry = StringOffset[AWI->Operands[0].Str];
506 // Add the string to the aggregate if this is the first time found.
507 MaxStringIdx = Entry = AggregateString.size();
508 std::string Str = AWI->Operands[0].Str;
510 AggregateString += Str;
511 AggregateString += '\0';
515 // Nuke the string from the operand list. It is now handled!
516 AWI->Operands.erase(AWI->Operands.begin());
518 OpcodeInfo.push_back(Idx);
521 // Figure out how many bits we used for the string index.
522 unsigned AsmStrBits = Log2_32_Ceil(MaxStringIdx);
524 // To reduce code size, we compactify common instructions into a few bits
525 // in the opcode-indexed table.
526 unsigned BitsLeft = 32-AsmStrBits;
528 std::vector<std::vector<std::string> > TableDrivenOperandPrinters;
532 std::vector<std::string> UniqueOperandCommands;
534 // For the first operand check, add a default value for instructions with
535 // just opcode strings to use.
537 UniqueOperandCommands.push_back(" return true;\n");
541 std::vector<unsigned> InstIdxs;
542 std::vector<unsigned> NumInstOpsHandled;
543 FindUniqueOperandCommands(UniqueOperandCommands, InstIdxs,
546 // If we ran out of operands to print, we're done.
547 if (UniqueOperandCommands.empty()) break;
549 // Compute the number of bits we need to represent these cases, this is
550 // ceil(log2(numentries)).
551 unsigned NumBits = Log2_32_Ceil(UniqueOperandCommands.size());
553 // If we don't have enough bits for this operand, don't include it.
554 if (NumBits > BitsLeft) {
555 DOUT << "Not enough bits to densely encode " << NumBits
560 // Otherwise, we can include this in the initial lookup table. Add it in.
562 for (unsigned i = 0, e = InstIdxs.size(); i != e; ++i)
563 if (InstIdxs[i] != ~0U)
564 OpcodeInfo[i] |= InstIdxs[i] << (BitsLeft+AsmStrBits);
566 // Remove the info about this operand.
567 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
568 if (AsmWriterInst *Inst = getAsmWriterInstByID(i))
569 if (!Inst->Operands.empty()) {
570 unsigned NumOps = NumInstOpsHandled[InstIdxs[i]];
571 assert(NumOps <= Inst->Operands.size() &&
572 "Can't remove this many ops!");
573 Inst->Operands.erase(Inst->Operands.begin(),
574 Inst->Operands.begin()+NumOps);
578 // Remember the handlers for this set of operands.
579 TableDrivenOperandPrinters.push_back(UniqueOperandCommands);
584 O<<" static const unsigned OpInfo[] = {\n";
585 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
586 O << " " << OpcodeInfo[i] << "U,\t// "
587 << NumberedInstructions[i]->TheDef->getName() << "\n";
589 // Add a dummy entry so the array init doesn't end with a comma.
593 // Emit the string itself.
594 O << " const char *AsmStrs = \n \"";
595 unsigned CharsPrinted = 0;
596 EscapeString(AggregateString);
597 for (unsigned i = 0, e = AggregateString.size(); i != e; ++i) {
598 if (CharsPrinted > 70) {
602 O << AggregateString[i];
605 // Print escape sequences all together.
606 if (AggregateString[i] == '\\') {
607 assert(i+1 < AggregateString.size() && "Incomplete escape sequence!");
608 if (isdigit(AggregateString[i+1])) {
609 assert(isdigit(AggregateString[i+2]) && isdigit(AggregateString[i+3]) &&
610 "Expected 3 digit octal escape!");
611 O << AggregateString[++i];
612 O << AggregateString[++i];
613 O << AggregateString[++i];
616 O << AggregateString[++i];
623 O << " if (MI->getOpcode() == TargetInstrInfo::INLINEASM) {\n"
624 << " O << \"\\t\";\n"
625 << " printInlineAsm(MI);\n"
627 << " } else if (MI->getOpcode() == TargetInstrInfo::LABEL) {\n"
628 << " printLabel(MI);\n"
630 << " } else if (MI->getOpcode() == TargetInstrInfo::DECLARE) {\n"
631 << " printDeclare(MI);\n"
635 O << " O << \"\\t\";\n\n";
637 O << " // Emit the opcode for the instruction.\n"
638 << " unsigned Bits = OpInfo[MI->getOpcode()];\n"
639 << " if (Bits == 0) return false;\n"
640 << " O << AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << ");\n\n";
642 // Output the table driven operand information.
643 BitsLeft = 32-AsmStrBits;
644 for (unsigned i = 0, e = TableDrivenOperandPrinters.size(); i != e; ++i) {
645 std::vector<std::string> &Commands = TableDrivenOperandPrinters[i];
647 // Compute the number of bits we need to represent these cases, this is
648 // ceil(log2(numentries)).
649 unsigned NumBits = Log2_32_Ceil(Commands.size());
650 assert(NumBits <= BitsLeft && "consistency error");
652 // Emit code to extract this field from Bits.
655 O << "\n // Fragment " << i << " encoded into " << NumBits
656 << " bits for " << Commands.size() << " unique commands.\n";
658 if (Commands.size() == 2) {
659 // Emit two possibilitys with if/else.
660 O << " if ((Bits >> " << (BitsLeft+AsmStrBits) << ") & "
661 << ((1 << NumBits)-1) << ") {\n"
667 O << " switch ((Bits >> " << (BitsLeft+AsmStrBits) << ") & "
668 << ((1 << NumBits)-1) << ") {\n"
669 << " default: // unreachable.\n";
671 // Print out all the cases.
672 for (unsigned i = 0, e = Commands.size(); i != e; ++i) {
673 O << " case " << i << ":\n";
681 // Okay, delete instructions with no operand info left.
682 for (unsigned i = 0, e = Instructions.size(); i != e; ++i) {
683 // Entire instruction has been emitted?
684 AsmWriterInst &Inst = Instructions[i];
685 if (Inst.Operands.empty()) {
686 Instructions.erase(Instructions.begin()+i);
692 // Because this is a vector, we want to emit from the end. Reverse all of the
693 // elements in the vector.
694 std::reverse(Instructions.begin(), Instructions.end());
696 if (!Instructions.empty()) {
697 // Find the opcode # of inline asm.
698 O << " switch (MI->getOpcode()) {\n";
699 while (!Instructions.empty())
700 EmitInstructions(Instructions, O);
703 O << " return true;\n";