1 //===- AsmWriterEmitter.cpp - Generate an assembly writer -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is emits an assembly printer for the current target.
11 // Note that this is currently fairly skeletal, but will grow over time.
13 //===----------------------------------------------------------------------===//
15 #include "AsmWriterInst.h"
16 #include "CodeGenTarget.h"
17 #include "SequenceToOffsetTable.h"
18 #include "llvm/ADT/StringExtras.h"
19 #include "llvm/ADT/Twine.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/MathExtras.h"
22 #include "llvm/TableGen/Error.h"
23 #include "llvm/TableGen/Record.h"
24 #include "llvm/TableGen/TableGenBackend.h"
32 class AsmWriterEmitter {
33 RecordKeeper &Records;
34 std::map<const CodeGenInstruction*, AsmWriterInst*> CGIAWIMap;
35 std::vector<const CodeGenInstruction*> NumberedInstructions;
37 AsmWriterEmitter(RecordKeeper &R) : Records(R) {}
39 void run(raw_ostream &o);
42 void EmitPrintInstruction(raw_ostream &o);
43 void EmitGetRegisterName(raw_ostream &o);
44 void EmitPrintAliasInstruction(raw_ostream &O);
46 AsmWriterInst *getAsmWriterInstByID(unsigned ID) const {
47 assert(ID < NumberedInstructions.size());
48 std::map<const CodeGenInstruction*, AsmWriterInst*>::const_iterator I =
49 CGIAWIMap.find(NumberedInstructions[ID]);
50 assert(I != CGIAWIMap.end() && "Didn't find inst!");
53 void FindUniqueOperandCommands(std::vector<std::string> &UOC,
54 std::vector<unsigned> &InstIdxs,
55 std::vector<unsigned> &InstOpsUsed) const;
57 } // end anonymous namespace
59 static void PrintCases(std::vector<std::pair<std::string,
60 AsmWriterOperand> > &OpsToPrint, raw_ostream &O) {
61 O << " case " << OpsToPrint.back().first << ": ";
62 AsmWriterOperand TheOp = OpsToPrint.back().second;
63 OpsToPrint.pop_back();
65 // Check to see if any other operands are identical in this list, and if so,
66 // emit a case label for them.
67 for (unsigned i = OpsToPrint.size(); i != 0; --i)
68 if (OpsToPrint[i-1].second == TheOp) {
69 O << "\n case " << OpsToPrint[i-1].first << ": ";
70 OpsToPrint.erase(OpsToPrint.begin()+i-1);
73 // Finally, emit the code.
79 /// EmitInstructions - Emit the last instruction in the vector and any other
80 /// instructions that are suitably similar to it.
81 static void EmitInstructions(std::vector<AsmWriterInst> &Insts,
83 AsmWriterInst FirstInst = Insts.back();
86 std::vector<AsmWriterInst> SimilarInsts;
87 unsigned DifferingOperand = ~0;
88 for (unsigned i = Insts.size(); i != 0; --i) {
89 unsigned DiffOp = Insts[i-1].MatchesAllButOneOp(FirstInst);
91 if (DifferingOperand == ~0U) // First match!
92 DifferingOperand = DiffOp;
94 // If this differs in the same operand as the rest of the instructions in
95 // this class, move it to the SimilarInsts list.
96 if (DifferingOperand == DiffOp || DiffOp == ~0U) {
97 SimilarInsts.push_back(Insts[i-1]);
98 Insts.erase(Insts.begin()+i-1);
103 O << " case " << FirstInst.CGI->Namespace << "::"
104 << FirstInst.CGI->TheDef->getName() << ":\n";
105 for (unsigned i = 0, e = SimilarInsts.size(); i != e; ++i)
106 O << " case " << SimilarInsts[i].CGI->Namespace << "::"
107 << SimilarInsts[i].CGI->TheDef->getName() << ":\n";
108 for (unsigned i = 0, e = FirstInst.Operands.size(); i != e; ++i) {
109 if (i != DifferingOperand) {
110 // If the operand is the same for all instructions, just print it.
111 O << " " << FirstInst.Operands[i].getCode();
113 // If this is the operand that varies between all of the instructions,
114 // emit a switch for just this operand now.
115 O << " switch (MI->getOpcode()) {\n";
116 std::vector<std::pair<std::string, AsmWriterOperand> > OpsToPrint;
117 OpsToPrint.push_back(std::make_pair(FirstInst.CGI->Namespace + "::" +
118 FirstInst.CGI->TheDef->getName(),
119 FirstInst.Operands[i]));
121 for (unsigned si = 0, e = SimilarInsts.size(); si != e; ++si) {
122 AsmWriterInst &AWI = SimilarInsts[si];
123 OpsToPrint.push_back(std::make_pair(AWI.CGI->Namespace+"::"+
124 AWI.CGI->TheDef->getName(),
127 std::reverse(OpsToPrint.begin(), OpsToPrint.end());
128 while (!OpsToPrint.empty())
129 PrintCases(OpsToPrint, O);
137 void AsmWriterEmitter::
138 FindUniqueOperandCommands(std::vector<std::string> &UniqueOperandCommands,
139 std::vector<unsigned> &InstIdxs,
140 std::vector<unsigned> &InstOpsUsed) const {
141 InstIdxs.assign(NumberedInstructions.size(), ~0U);
143 // This vector parallels UniqueOperandCommands, keeping track of which
144 // instructions each case are used for. It is a comma separated string of
146 std::vector<std::string> InstrsForCase;
147 InstrsForCase.resize(UniqueOperandCommands.size());
148 InstOpsUsed.assign(UniqueOperandCommands.size(), 0);
150 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
151 const AsmWriterInst *Inst = getAsmWriterInstByID(i);
152 if (Inst == 0) continue; // PHI, INLINEASM, PROLOG_LABEL, etc.
155 if (Inst->Operands.empty())
156 continue; // Instruction already done.
158 Command = " " + Inst->Operands[0].getCode() + "\n";
160 // Check to see if we already have 'Command' in UniqueOperandCommands.
162 bool FoundIt = false;
163 for (unsigned idx = 0, e = UniqueOperandCommands.size(); idx != e; ++idx)
164 if (UniqueOperandCommands[idx] == Command) {
166 InstrsForCase[idx] += ", ";
167 InstrsForCase[idx] += Inst->CGI->TheDef->getName();
172 InstIdxs[i] = UniqueOperandCommands.size();
173 UniqueOperandCommands.push_back(Command);
174 InstrsForCase.push_back(Inst->CGI->TheDef->getName());
176 // This command matches one operand so far.
177 InstOpsUsed.push_back(1);
181 // For each entry of UniqueOperandCommands, there is a set of instructions
182 // that uses it. If the next command of all instructions in the set are
183 // identical, fold it into the command.
184 for (unsigned CommandIdx = 0, e = UniqueOperandCommands.size();
185 CommandIdx != e; ++CommandIdx) {
187 for (unsigned Op = 1; ; ++Op) {
188 // Scan for the first instruction in the set.
189 std::vector<unsigned>::iterator NIT =
190 std::find(InstIdxs.begin(), InstIdxs.end(), CommandIdx);
191 if (NIT == InstIdxs.end()) break; // No commonality.
193 // If this instruction has no more operands, we isn't anything to merge
194 // into this command.
195 const AsmWriterInst *FirstInst =
196 getAsmWriterInstByID(NIT-InstIdxs.begin());
197 if (!FirstInst || FirstInst->Operands.size() == Op)
200 // Otherwise, scan to see if all of the other instructions in this command
201 // set share the operand.
203 // Keep track of the maximum, number of operands or any
204 // instruction we see in the group.
205 size_t MaxSize = FirstInst->Operands.size();
207 for (NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx);
208 NIT != InstIdxs.end();
209 NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx)) {
210 // Okay, found another instruction in this command set. If the operand
211 // matches, we're ok, otherwise bail out.
212 const AsmWriterInst *OtherInst =
213 getAsmWriterInstByID(NIT-InstIdxs.begin());
216 OtherInst->Operands.size() > FirstInst->Operands.size())
217 MaxSize = std::max(MaxSize, OtherInst->Operands.size());
219 if (!OtherInst || OtherInst->Operands.size() == Op ||
220 OtherInst->Operands[Op] != FirstInst->Operands[Op]) {
227 // Okay, everything in this command set has the same next operand. Add it
228 // to UniqueOperandCommands and remember that it was consumed.
229 std::string Command = " " + FirstInst->Operands[Op].getCode() + "\n";
231 UniqueOperandCommands[CommandIdx] += Command;
232 InstOpsUsed[CommandIdx]++;
236 // Prepend some of the instructions each case is used for onto the case val.
237 for (unsigned i = 0, e = InstrsForCase.size(); i != e; ++i) {
238 std::string Instrs = InstrsForCase[i];
239 if (Instrs.size() > 70) {
240 Instrs.erase(Instrs.begin()+70, Instrs.end());
245 UniqueOperandCommands[i] = " // " + Instrs + "\n" +
246 UniqueOperandCommands[i];
251 static void UnescapeString(std::string &Str) {
252 for (unsigned i = 0; i != Str.size(); ++i) {
253 if (Str[i] == '\\' && i != Str.size()-1) {
255 default: continue; // Don't execute the code after the switch.
256 case 'a': Str[i] = '\a'; break;
257 case 'b': Str[i] = '\b'; break;
258 case 'e': Str[i] = 27; break;
259 case 'f': Str[i] = '\f'; break;
260 case 'n': Str[i] = '\n'; break;
261 case 'r': Str[i] = '\r'; break;
262 case 't': Str[i] = '\t'; break;
263 case 'v': Str[i] = '\v'; break;
264 case '"': Str[i] = '\"'; break;
265 case '\'': Str[i] = '\''; break;
266 case '\\': Str[i] = '\\'; break;
268 // Nuke the second character.
269 Str.erase(Str.begin()+i+1);
274 /// EmitPrintInstruction - Generate the code for the "printInstruction" method
276 void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) {
277 CodeGenTarget Target(Records);
278 Record *AsmWriter = Target.getAsmWriter();
279 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
280 bool isMC = AsmWriter->getValueAsBit("isMCAsmWriter");
281 const char *MachineInstrClassName = isMC ? "MCInst" : "MachineInstr";
284 "/// printInstruction - This method is automatically generated by tablegen\n"
285 "/// from the instruction set description.\n"
286 "void " << Target.getName() << ClassName
287 << "::printInstruction(const " << MachineInstrClassName
288 << " *MI, raw_ostream &O) {\n";
290 std::vector<AsmWriterInst> Instructions;
292 for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
293 E = Target.inst_end(); I != E; ++I)
294 if (!(*I)->AsmString.empty() &&
295 (*I)->TheDef->getName() != "PHI")
296 Instructions.push_back(
298 AsmWriter->getValueAsInt("Variant"),
299 AsmWriter->getValueAsInt("FirstOperandColumn"),
300 AsmWriter->getValueAsInt("OperandSpacing")));
302 // Get the instruction numbering.
303 NumberedInstructions = Target.getInstructionsByEnumValue();
305 // Compute the CodeGenInstruction -> AsmWriterInst mapping. Note that not
306 // all machine instructions are necessarily being printed, so there may be
307 // target instructions not in this map.
308 for (unsigned i = 0, e = Instructions.size(); i != e; ++i)
309 CGIAWIMap.insert(std::make_pair(Instructions[i].CGI, &Instructions[i]));
311 // Build an aggregate string, and build a table of offsets into it.
312 SequenceToOffsetTable<std::string> StringTable;
314 /// OpcodeInfo - This encodes the index of the string to use for the first
315 /// chunk of the output as well as indices used for operand printing.
316 /// To reduce the number of unhandled cases, we expand the size from 32-bit
317 /// to 32+16 = 48-bit.
318 std::vector<uint64_t> OpcodeInfo;
320 // Add all strings to the string table upfront so it can generate an optimized
322 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
323 AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions[i]];
325 AWI->Operands[0].OperandType ==
326 AsmWriterOperand::isLiteralTextOperand &&
327 !AWI->Operands[0].Str.empty()) {
328 std::string Str = AWI->Operands[0].Str;
330 StringTable.add(Str);
334 StringTable.layout();
336 unsigned MaxStringIdx = 0;
337 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
338 AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions[i]];
341 // Something not handled by the asmwriter printer.
343 } else if (AWI->Operands[0].OperandType !=
344 AsmWriterOperand::isLiteralTextOperand ||
345 AWI->Operands[0].Str.empty()) {
346 // Something handled by the asmwriter printer, but with no leading string.
347 Idx = StringTable.get("");
349 std::string Str = AWI->Operands[0].Str;
351 Idx = StringTable.get(Str);
352 MaxStringIdx = std::max(MaxStringIdx, Idx);
354 // Nuke the string from the operand list. It is now handled!
355 AWI->Operands.erase(AWI->Operands.begin());
358 // Bias offset by one since we want 0 as a sentinel.
359 OpcodeInfo.push_back(Idx+1);
362 // Figure out how many bits we used for the string index.
363 unsigned AsmStrBits = Log2_32_Ceil(MaxStringIdx+2);
365 // To reduce code size, we compactify common instructions into a few bits
366 // in the opcode-indexed table.
367 unsigned BitsLeft = 64-AsmStrBits;
369 std::vector<std::vector<std::string> > TableDrivenOperandPrinters;
372 std::vector<std::string> UniqueOperandCommands;
373 std::vector<unsigned> InstIdxs;
374 std::vector<unsigned> NumInstOpsHandled;
375 FindUniqueOperandCommands(UniqueOperandCommands, InstIdxs,
378 // If we ran out of operands to print, we're done.
379 if (UniqueOperandCommands.empty()) break;
381 // Compute the number of bits we need to represent these cases, this is
382 // ceil(log2(numentries)).
383 unsigned NumBits = Log2_32_Ceil(UniqueOperandCommands.size());
385 // If we don't have enough bits for this operand, don't include it.
386 if (NumBits > BitsLeft) {
387 DEBUG(errs() << "Not enough bits to densely encode " << NumBits
392 // Otherwise, we can include this in the initial lookup table. Add it in.
393 for (unsigned i = 0, e = InstIdxs.size(); i != e; ++i)
394 if (InstIdxs[i] != ~0U) {
395 OpcodeInfo[i] |= (uint64_t)InstIdxs[i] << (64-BitsLeft);
399 // Remove the info about this operand.
400 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
401 if (AsmWriterInst *Inst = getAsmWriterInstByID(i))
402 if (!Inst->Operands.empty()) {
403 unsigned NumOps = NumInstOpsHandled[InstIdxs[i]];
404 assert(NumOps <= Inst->Operands.size() &&
405 "Can't remove this many ops!");
406 Inst->Operands.erase(Inst->Operands.begin(),
407 Inst->Operands.begin()+NumOps);
411 // Remember the handlers for this set of operands.
412 TableDrivenOperandPrinters.push_back(UniqueOperandCommands);
416 // We always emit at least one 32-bit table. A second table is emitted if
417 // more bits are needed.
418 O<<" static const uint32_t OpInfo[] = {\n";
419 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
420 O << " " << (OpcodeInfo[i] & 0xffffffff) << "U,\t// "
421 << NumberedInstructions[i]->TheDef->getName() << "\n";
423 // Add a dummy entry so the array init doesn't end with a comma.
428 // Add a second OpInfo table only when it is necessary.
429 // Adjust the type of the second table based on the number of bits needed.
430 O << " static const uint"
431 << ((BitsLeft < 16) ? "32" : (BitsLeft < 24) ? "16" : "8")
432 << "_t OpInfo2[] = {\n";
433 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
434 O << " " << (OpcodeInfo[i] >> 32) << "U,\t// "
435 << NumberedInstructions[i]->TheDef->getName() << "\n";
437 // Add a dummy entry so the array init doesn't end with a comma.
442 // Emit the string itself.
443 O << " const char AsmStrs[] = {\n";
444 StringTable.emit(O, printChar);
447 O << " O << \"\\t\";\n\n";
449 O << " // Emit the opcode for the instruction.\n";
451 // If we have two tables then we need to perform two lookups and combine
452 // the results into a single 64-bit value.
453 O << " uint64_t Bits1 = OpInfo[MI->getOpcode()];\n"
454 << " uint64_t Bits2 = OpInfo2[MI->getOpcode()];\n"
455 << " uint64_t Bits = (Bits2 << 32) | Bits1;\n";
457 // If only one table is used we just need to perform a single lookup.
458 O << " uint32_t Bits = OpInfo[MI->getOpcode()];\n";
460 O << " assert(Bits != 0 && \"Cannot print this instruction.\");\n"
461 << " O << AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << ")-1;\n\n";
463 // Output the table driven operand information.
464 BitsLeft = 64-AsmStrBits;
465 for (unsigned i = 0, e = TableDrivenOperandPrinters.size(); i != e; ++i) {
466 std::vector<std::string> &Commands = TableDrivenOperandPrinters[i];
468 // Compute the number of bits we need to represent these cases, this is
469 // ceil(log2(numentries)).
470 unsigned NumBits = Log2_32_Ceil(Commands.size());
471 assert(NumBits <= BitsLeft && "consistency error");
473 // Emit code to extract this field from Bits.
474 O << "\n // Fragment " << i << " encoded into " << NumBits
475 << " bits for " << Commands.size() << " unique commands.\n";
477 if (Commands.size() == 2) {
478 // Emit two possibilitys with if/else.
479 O << " if ((Bits >> "
480 << (64-BitsLeft) << ") & "
481 << ((1 << NumBits)-1) << ") {\n"
486 } else if (Commands.size() == 1) {
487 // Emit a single possibility.
488 O << Commands[0] << "\n\n";
490 O << " switch ((Bits >> "
491 << (64-BitsLeft) << ") & "
492 << ((1 << NumBits)-1) << ") {\n"
493 << " default: // unreachable.\n";
495 // Print out all the cases.
496 for (unsigned i = 0, e = Commands.size(); i != e; ++i) {
497 O << " case " << i << ":\n";
506 // Okay, delete instructions with no operand info left.
507 for (unsigned i = 0, e = Instructions.size(); i != e; ++i) {
508 // Entire instruction has been emitted?
509 AsmWriterInst &Inst = Instructions[i];
510 if (Inst.Operands.empty()) {
511 Instructions.erase(Instructions.begin()+i);
517 // Because this is a vector, we want to emit from the end. Reverse all of the
518 // elements in the vector.
519 std::reverse(Instructions.begin(), Instructions.end());
522 // Now that we've emitted all of the operand info that fit into 32 bits, emit
523 // information for those instructions that are left. This is a less dense
524 // encoding, but we expect the main 32-bit table to handle the majority of
526 if (!Instructions.empty()) {
527 // Find the opcode # of inline asm.
528 O << " switch (MI->getOpcode()) {\n";
529 while (!Instructions.empty())
530 EmitInstructions(Instructions, O);
540 emitRegisterNameString(raw_ostream &O, StringRef AltName,
541 const std::vector<CodeGenRegister*> &Registers) {
542 SequenceToOffsetTable<std::string> StringTable;
543 SmallVector<std::string, 4> AsmNames(Registers.size());
544 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
545 const CodeGenRegister &Reg = *Registers[i];
546 std::string &AsmName = AsmNames[i];
548 // "NoRegAltName" is special. We don't need to do a lookup for that,
549 // as it's just a reference to the default register name.
550 if (AltName == "" || AltName == "NoRegAltName") {
551 AsmName = Reg.TheDef->getValueAsString("AsmName");
553 AsmName = Reg.getName();
555 // Make sure the register has an alternate name for this index.
556 std::vector<Record*> AltNameList =
557 Reg.TheDef->getValueAsListOfDefs("RegAltNameIndices");
559 for (e = AltNameList.size();
560 Idx < e && (AltNameList[Idx]->getName() != AltName);
563 // If the register has an alternate name for this index, use it.
564 // Otherwise, leave it empty as an error flag.
566 std::vector<std::string> AltNames =
567 Reg.TheDef->getValueAsListOfStrings("AltNames");
568 if (AltNames.size() <= Idx)
569 PrintFatalError(Reg.TheDef->getLoc(),
570 (Twine("Register definition missing alt name for '") +
571 AltName + "'.").str());
572 AsmName = AltNames[Idx];
575 StringTable.add(AsmName);
578 StringTable.layout();
579 O << " static const char AsmStrs" << AltName << "[] = {\n";
580 StringTable.emit(O, printChar);
583 O << " static const uint32_t RegAsmOffset" << AltName << "[] = {";
584 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
587 O << StringTable.get(AsmNames[i]) << ", ";
593 void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) {
594 CodeGenTarget Target(Records);
595 Record *AsmWriter = Target.getAsmWriter();
596 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
597 const std::vector<CodeGenRegister*> &Registers =
598 Target.getRegBank().getRegisters();
599 std::vector<Record*> AltNameIndices = Target.getRegAltNameIndices();
600 bool hasAltNames = AltNameIndices.size() > 1;
603 "\n\n/// getRegisterName - This method is automatically generated by tblgen\n"
604 "/// from the register set description. This returns the assembler name\n"
605 "/// for the specified register.\n"
606 "const char *" << Target.getName() << ClassName << "::";
608 O << "\ngetRegisterName(unsigned RegNo, unsigned AltIdx) {\n";
610 O << "getRegisterName(unsigned RegNo) {\n";
611 O << " assert(RegNo && RegNo < " << (Registers.size()+1)
612 << " && \"Invalid register number!\");\n"
616 for (unsigned i = 0, e = AltNameIndices.size(); i < e; ++i)
617 emitRegisterNameString(O, AltNameIndices[i]->getName(), Registers);
619 emitRegisterNameString(O, "", Registers);
622 O << " const uint32_t *RegAsmOffset;\n"
623 << " const char *AsmStrs;\n"
624 << " switch(AltIdx) {\n"
625 << " default: llvm_unreachable(\"Invalid register alt name index!\");\n";
626 for (unsigned i = 0, e = AltNameIndices.size(); i < e; ++i) {
627 StringRef Namespace = AltNameIndices[1]->getValueAsString("Namespace");
628 StringRef AltName(AltNameIndices[i]->getName());
629 O << " case " << Namespace << "::" << AltName
631 << " AsmStrs = AsmStrs" << AltName << ";\n"
632 << " RegAsmOffset = RegAsmOffset" << AltName << ";\n"
638 O << " assert (*(AsmStrs+RegAsmOffset[RegNo-1]) &&\n"
639 << " \"Invalid alt name index for register!\");\n"
640 << " return AsmStrs+RegAsmOffset[RegNo-1];\n"
645 // IAPrinter - Holds information about an InstAlias. Two InstAliases match if
646 // they both have the same conditionals. In which case, we cannot print out the
647 // alias for that pattern.
649 std::vector<std::string> Conds;
650 std::map<StringRef, unsigned> OpMap;
652 std::string AsmString;
653 SmallVector<Record*, 4> ReqFeatures;
655 IAPrinter(std::string R, std::string AS)
656 : Result(R), AsmString(AS) {}
658 void addCond(const std::string &C) { Conds.push_back(C); }
660 void addOperand(StringRef Op, unsigned Idx) { OpMap[Op] = Idx; }
661 unsigned getOpIndex(StringRef Op) { return OpMap[Op]; }
662 bool isOpMapped(StringRef Op) { return OpMap.find(Op) != OpMap.end(); }
664 void print(raw_ostream &O) {
665 if (Conds.empty() && ReqFeatures.empty()) {
666 O.indent(6) << "return true;\n";
672 for (std::vector<std::string>::iterator
673 I = Conds.begin(), E = Conds.end(); I != E; ++I) {
674 if (I != Conds.begin()) {
683 O.indent(6) << "// " << Result << "\n";
684 O.indent(6) << "AsmString = \"" << AsmString << "\";\n";
686 for (std::map<StringRef, unsigned>::iterator
687 I = OpMap.begin(), E = OpMap.end(); I != E; ++I)
688 O.indent(6) << "OpMap.push_back(std::make_pair(\"" << I->first << "\", "
689 << I->second << "));\n";
691 O.indent(6) << "break;\n";
695 bool operator==(const IAPrinter &RHS) {
696 if (Conds.size() != RHS.Conds.size())
700 for (std::vector<std::string>::iterator
701 I = Conds.begin(), E = Conds.end(); I != E; ++I)
702 if (*I != RHS.Conds[Idx++])
708 bool operator()(const IAPrinter &RHS) {
709 if (Conds.size() < RHS.Conds.size())
713 for (std::vector<std::string>::iterator
714 I = Conds.begin(), E = Conds.end(); I != E; ++I)
715 if (*I != RHS.Conds[Idx++])
716 return *I < RHS.Conds[Idx++];
722 } // end anonymous namespace
724 static void EmitGetMapOperandNumber(raw_ostream &O) {
725 O << "static unsigned getMapOperandNumber("
726 << "const SmallVectorImpl<std::pair<StringRef, unsigned> > &OpMap,\n";
727 O << " StringRef Name) {\n";
728 O << " for (SmallVectorImpl<std::pair<StringRef, unsigned> >::"
729 << "const_iterator\n";
730 O << " I = OpMap.begin(), E = OpMap.end(); I != E; ++I)\n";
731 O << " if (I->first == Name)\n";
732 O << " return I->second;\n";
733 O << " llvm_unreachable(\"Operand not in map!\");\n";
737 static unsigned CountNumOperands(StringRef AsmString) {
739 std::pair<StringRef, StringRef> ASM = AsmString.split(' ');
741 while (!ASM.second.empty()) {
743 ASM = ASM.second.split(' ');
749 static unsigned CountResultNumOperands(StringRef AsmString) {
751 std::pair<StringRef, StringRef> ASM = AsmString.split('\t');
753 if (!ASM.second.empty()) {
754 size_t I = ASM.second.find('{');
755 StringRef Str = ASM.second;
756 if (I != StringRef::npos)
757 Str = ASM.second.substr(I, ASM.second.find('|', I));
759 ASM = Str.split(' ');
763 ASM = ASM.second.split(' ');
764 } while (!ASM.second.empty());
770 void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
771 CodeGenTarget Target(Records);
772 Record *AsmWriter = Target.getAsmWriter();
774 if (!AsmWriter->getValueAsBit("isMCAsmWriter"))
777 O << "\n#ifdef PRINT_ALIAS_INSTR\n";
778 O << "#undef PRINT_ALIAS_INSTR\n\n";
780 // Emit the method that prints the alias instruction.
781 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
783 std::vector<Record*> AllInstAliases =
784 Records.getAllDerivedDefinitions("InstAlias");
786 // Create a map from the qualified name to a list of potential matches.
787 std::map<std::string, std::vector<CodeGenInstAlias*> > AliasMap;
788 for (std::vector<Record*>::iterator
789 I = AllInstAliases.begin(), E = AllInstAliases.end(); I != E; ++I) {
790 CodeGenInstAlias *Alias = new CodeGenInstAlias(*I, Target);
791 const Record *R = *I;
792 if (!R->getValueAsBit("EmitAlias"))
793 continue; // We were told not to emit the alias, but to emit the aliasee.
794 const DagInit *DI = R->getValueAsDag("ResultInst");
795 const DefInit *Op = cast<DefInit>(DI->getOperator());
796 AliasMap[getQualifiedName(Op->getDef())].push_back(Alias);
799 // A map of which conditions need to be met for each instruction operand
800 // before it can be matched to the mnemonic.
801 std::map<std::string, std::vector<IAPrinter*> > IAPrinterMap;
803 for (std::map<std::string, std::vector<CodeGenInstAlias*> >::iterator
804 I = AliasMap.begin(), E = AliasMap.end(); I != E; ++I) {
805 std::vector<CodeGenInstAlias*> &Aliases = I->second;
807 for (std::vector<CodeGenInstAlias*>::iterator
808 II = Aliases.begin(), IE = Aliases.end(); II != IE; ++II) {
809 const CodeGenInstAlias *CGA = *II;
810 unsigned LastOpNo = CGA->ResultInstOperandIndex.size();
811 unsigned NumResultOps =
812 CountResultNumOperands(CGA->ResultInst->AsmString);
814 // Don't emit the alias if it has more operands than what it's aliasing.
815 if (NumResultOps < CountNumOperands(CGA->AsmString))
818 IAPrinter *IAP = new IAPrinter(CGA->Result->getAsString(),
822 Cond = std::string("MI->getNumOperands() == ") + llvm::utostr(LastOpNo);
825 std::map<StringRef, unsigned> OpMap;
826 bool CantHandle = false;
828 for (unsigned i = 0, e = LastOpNo; i != e; ++i) {
829 const CodeGenInstAlias::ResultOperand &RO = CGA->ResultOperands[i];
832 case CodeGenInstAlias::ResultOperand::K_Record: {
833 const Record *Rec = RO.getRecord();
834 StringRef ROName = RO.getName();
837 if (Rec->isSubClassOf("RegisterOperand"))
838 Rec = Rec->getValueAsDef("RegClass");
839 if (Rec->isSubClassOf("RegisterClass")) {
840 Cond = std::string("MI->getOperand(")+llvm::utostr(i)+").isReg()";
843 if (!IAP->isOpMapped(ROName)) {
844 IAP->addOperand(ROName, i);
845 Cond = std::string("MRI.getRegClass(") + Target.getName() + "::" +
846 CGA->ResultOperands[i].getRecord()->getName() + "RegClassID)"
847 ".contains(MI->getOperand(" + llvm::utostr(i) + ").getReg())";
850 Cond = std::string("MI->getOperand(") +
851 llvm::utostr(i) + ").getReg() == MI->getOperand(" +
852 llvm::utostr(IAP->getOpIndex(ROName)) + ").getReg()";
856 assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
857 // FIXME: We may need to handle these situations.
866 case CodeGenInstAlias::ResultOperand::K_Imm: {
867 std::string Op = "MI->getOperand(" + llvm::utostr(i) + ")";
869 // Just because the alias has an immediate result, doesn't mean the
870 // MCInst will. An MCExpr could be present, for example.
871 IAP->addCond(Op + ".isImm()");
873 Cond = Op + ".getImm() == "
874 + llvm::utostr(CGA->ResultOperands[i].getImm());
878 case CodeGenInstAlias::ResultOperand::K_Reg:
879 // If this is zero_reg, something's playing tricks we're not
880 // equipped to handle.
881 if (!CGA->ResultOperands[i].getRegister()) {
886 Cond = std::string("MI->getOperand(") +
887 llvm::utostr(i) + ").getReg() == " + Target.getName() +
888 "::" + CGA->ResultOperands[i].getRegister()->getName();
896 if (CantHandle) continue;
897 IAPrinterMap[I->first].push_back(IAP);
902 raw_string_ostream HeaderO(Header);
904 HeaderO << "bool " << Target.getName() << ClassName
905 << "::printAliasInstr(const MCInst"
906 << " *MI, raw_ostream &OS) {\n";
909 raw_string_ostream CasesO(Cases);
911 for (std::map<std::string, std::vector<IAPrinter*> >::iterator
912 I = IAPrinterMap.begin(), E = IAPrinterMap.end(); I != E; ++I) {
913 std::vector<IAPrinter*> &IAPs = I->second;
914 std::vector<IAPrinter*> UniqueIAPs;
916 for (std::vector<IAPrinter*>::iterator
917 II = IAPs.begin(), IE = IAPs.end(); II != IE; ++II) {
918 IAPrinter *LHS = *II;
920 for (std::vector<IAPrinter*>::iterator
921 III = IAPs.begin(), IIE = IAPs.end(); III != IIE; ++III) {
922 IAPrinter *RHS = *III;
923 if (LHS != RHS && *LHS == *RHS) {
929 if (!IsDup) UniqueIAPs.push_back(LHS);
932 if (UniqueIAPs.empty()) continue;
934 CasesO.indent(2) << "case " << I->first << ":\n";
936 for (std::vector<IAPrinter*>::iterator
937 II = UniqueIAPs.begin(), IE = UniqueIAPs.end(); II != IE; ++II) {
938 IAPrinter *IAP = *II;
944 CasesO.indent(4) << "return false;\n";
947 if (CasesO.str().empty()) {
949 O << " return false;\n";
951 O << "#endif // PRINT_ALIAS_INSTR\n";
955 EmitGetMapOperandNumber(O);
958 O.indent(2) << "StringRef AsmString;\n";
959 O.indent(2) << "SmallVector<std::pair<StringRef, unsigned>, 4> OpMap;\n";
960 O.indent(2) << "switch (MI->getOpcode()) {\n";
961 O.indent(2) << "default: return false;\n";
963 O.indent(2) << "}\n\n";
965 // Code that prints the alias, replacing the operands with the ones from the
967 O << " std::pair<StringRef, StringRef> ASM = AsmString.split(' ');\n";
968 O << " OS << '\\t' << ASM.first;\n";
970 O << " if (!ASM.second.empty()) {\n";
971 O << " OS << '\\t';\n";
972 O << " for (StringRef::iterator\n";
973 O << " I = ASM.second.begin(), E = ASM.second.end(); I != E; ) {\n";
974 O << " if (*I == '$') {\n";
975 O << " StringRef::iterator Start = ++I;\n";
976 O << " while (I != E &&\n";
977 O << " ((*I >= 'a' && *I <= 'z') ||\n";
978 O << " (*I >= 'A' && *I <= 'Z') ||\n";
979 O << " (*I >= '0' && *I <= '9') ||\n";
980 O << " *I == '_'))\n";
982 O << " StringRef Name(Start, I - Start);\n";
983 O << " printOperand(MI, getMapOperandNumber(OpMap, Name), OS);\n";
985 O << " OS << *I++;\n";
990 O << " return true;\n";
993 O << "#endif // PRINT_ALIAS_INSTR\n";
996 void AsmWriterEmitter::run(raw_ostream &O) {
997 EmitPrintInstruction(O);
998 EmitGetRegisterName(O);
999 EmitPrintAliasInstruction(O);
1005 void EmitAsmWriter(RecordKeeper &RK, raw_ostream &OS) {
1006 emitSourceFileHeader("Assembly Writer Source Fragment", OS);
1007 AsmWriterEmitter(RK).run(OS);
1010 } // End llvm namespace