1 //===- AsmWriterEmitter.cpp - Generate an assembly writer -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is emits an assembly printer for the current target.
11 // Note that this is currently fairly skeletal, but will grow over time.
13 //===----------------------------------------------------------------------===//
15 #include "AsmWriterEmitter.h"
16 #include "CodeGenTarget.h"
18 #include "llvm/ADT/StringExtras.h"
19 #include "llvm/Support/Debug.h"
20 #include "llvm/Support/MathExtras.h"
25 static bool isIdentChar(char C) {
26 return (C >= 'a' && C <= 'z') ||
27 (C >= 'A' && C <= 'Z') ||
28 (C >= '0' && C <= '9') ||
32 // This should be an anon namespace, this works around a GCC warning.
34 struct AsmWriterOperand {
35 enum { isLiteralTextOperand, isMachineInstrOperand } OperandType;
37 /// Str - For isLiteralTextOperand, this IS the literal text. For
38 /// isMachineInstrOperand, this is the PrinterMethodName for the operand.
41 /// MiOpNo - For isMachineInstrOperand, this is the operand number of the
42 /// machine instruction.
45 /// MiModifier - For isMachineInstrOperand, this is the modifier string for
46 /// an operand, specified with syntax like ${opname:modifier}.
47 std::string MiModifier;
49 // To make VS STL happy
50 AsmWriterOperand():OperandType(isLiteralTextOperand) {}
52 explicit AsmWriterOperand(const std::string &LitStr)
53 : OperandType(isLiteralTextOperand), Str(LitStr) {}
55 AsmWriterOperand(const std::string &Printer, unsigned OpNo,
56 const std::string &Modifier)
57 : OperandType(isMachineInstrOperand), Str(Printer), MIOpNo(OpNo),
58 MiModifier(Modifier) {}
60 bool operator!=(const AsmWriterOperand &Other) const {
61 if (OperandType != Other.OperandType || Str != Other.Str) return true;
62 if (OperandType == isMachineInstrOperand)
63 return MIOpNo != Other.MIOpNo || MiModifier != Other.MiModifier;
66 bool operator==(const AsmWriterOperand &Other) const {
67 return !operator!=(Other);
70 /// getCode - Return the code that prints this operand.
71 std::string getCode() const;
78 std::vector<AsmWriterOperand> Operands;
79 const CodeGenInstruction *CGI;
81 AsmWriterInst(const CodeGenInstruction &CGI, unsigned Variant);
83 /// MatchesAllButOneOp - If this instruction is exactly identical to the
84 /// specified instruction except for one differing operand, return the
85 /// differing operand number. Otherwise return ~0.
86 unsigned MatchesAllButOneOp(const AsmWriterInst &Other) const;
89 void AddLiteralString(const std::string &Str) {
90 // If the last operand was already a literal text string, append this to
91 // it, otherwise add a new operand.
92 if (!Operands.empty() &&
93 Operands.back().OperandType == AsmWriterOperand::isLiteralTextOperand)
94 Operands.back().Str.append(Str);
96 Operands.push_back(AsmWriterOperand(Str));
102 std::string AsmWriterOperand::getCode() const {
103 if (OperandType == isLiteralTextOperand)
104 return "O << \"" + Str + "\"; ";
106 std::string Result = Str + "(MI";
108 Result += ", " + utostr(MIOpNo);
109 if (!MiModifier.empty())
110 Result += ", \"" + MiModifier + '"';
111 return Result + "); ";
115 /// ParseAsmString - Parse the specified Instruction's AsmString into this
118 AsmWriterInst::AsmWriterInst(const CodeGenInstruction &CGI, unsigned Variant) {
120 unsigned CurVariant = ~0U; // ~0 if we are outside a {.|.|.} region, other #.
122 // NOTE: Any extensions to this code need to be mirrored in the
123 // AsmPrinter::printInlineAsm code that executes as compile time (assuming
124 // that inline asm strings should also get the new feature)!
125 const std::string &AsmString = CGI.AsmString;
126 std::string::size_type LastEmitted = 0;
127 while (LastEmitted != AsmString.size()) {
128 std::string::size_type DollarPos =
129 AsmString.find_first_of("${|}\\", LastEmitted);
130 if (DollarPos == std::string::npos) DollarPos = AsmString.size();
132 // Emit a constant string fragment.
133 if (DollarPos != LastEmitted) {
134 if (CurVariant == Variant || CurVariant == ~0U) {
135 for (; LastEmitted != DollarPos; ++LastEmitted)
136 switch (AsmString[LastEmitted]) {
137 case '\n': AddLiteralString("\\n"); break;
138 case '\t': AddLiteralString("\\t"); break;
139 case '"': AddLiteralString("\\\""); break;
140 case '\\': AddLiteralString("\\\\"); break;
142 AddLiteralString(std::string(1, AsmString[LastEmitted]));
146 LastEmitted = DollarPos;
148 } else if (AsmString[DollarPos] == '\\') {
149 if (DollarPos+1 != AsmString.size() &&
150 (CurVariant == Variant || CurVariant == ~0U)) {
151 if (AsmString[DollarPos+1] == 'n') {
152 AddLiteralString("\\n");
153 } else if (AsmString[DollarPos+1] == 't') {
154 AddLiteralString("\\t");
155 } else if (std::string("${|}\\").find(AsmString[DollarPos+1])
156 != std::string::npos) {
157 AddLiteralString(std::string(1, AsmString[DollarPos+1]));
159 throw "Non-supported escaped character found in instruction '" +
160 CGI.TheDef->getName() + "'!";
162 LastEmitted = DollarPos+2;
165 } else if (AsmString[DollarPos] == '{') {
166 if (CurVariant != ~0U)
167 throw "Nested variants found for instruction '" +
168 CGI.TheDef->getName() + "'!";
169 LastEmitted = DollarPos+1;
170 CurVariant = 0; // We are now inside of the variant!
171 } else if (AsmString[DollarPos] == '|') {
172 if (CurVariant == ~0U)
173 throw "'|' character found outside of a variant in instruction '"
174 + CGI.TheDef->getName() + "'!";
177 } else if (AsmString[DollarPos] == '}') {
178 if (CurVariant == ~0U)
179 throw "'}' character found outside of a variant in instruction '"
180 + CGI.TheDef->getName() + "'!";
183 } else if (DollarPos+1 != AsmString.size() &&
184 AsmString[DollarPos+1] == '$') {
185 if (CurVariant == Variant || CurVariant == ~0U)
186 AddLiteralString("$"); // "$$" -> $
187 LastEmitted = DollarPos+2;
189 // Get the name of the variable.
190 std::string::size_type VarEnd = DollarPos+1;
192 // handle ${foo}bar as $foo by detecting whether the character following
193 // the dollar sign is a curly brace. If so, advance VarEnd and DollarPos
194 // so the variable name does not contain the leading curly brace.
195 bool hasCurlyBraces = false;
196 if (VarEnd < AsmString.size() && '{' == AsmString[VarEnd]) {
197 hasCurlyBraces = true;
202 while (VarEnd < AsmString.size() && isIdentChar(AsmString[VarEnd]))
204 std::string VarName(AsmString.begin()+DollarPos+1,
205 AsmString.begin()+VarEnd);
207 // Modifier - Support ${foo:modifier} syntax, where "modifier" is passed
208 // into printOperand. Also support ${:feature}, which is passed into
210 std::string Modifier;
212 // In order to avoid starting the next string at the terminating curly
213 // brace, advance the end position past it if we found an opening curly
215 if (hasCurlyBraces) {
216 if (VarEnd >= AsmString.size())
217 throw "Reached end of string before terminating curly brace in '"
218 + CGI.TheDef->getName() + "'";
220 // Look for a modifier string.
221 if (AsmString[VarEnd] == ':') {
223 if (VarEnd >= AsmString.size())
224 throw "Reached end of string before terminating curly brace in '"
225 + CGI.TheDef->getName() + "'";
227 unsigned ModifierStart = VarEnd;
228 while (VarEnd < AsmString.size() && isIdentChar(AsmString[VarEnd]))
230 Modifier = std::string(AsmString.begin()+ModifierStart,
231 AsmString.begin()+VarEnd);
232 if (Modifier.empty())
233 throw "Bad operand modifier name in '"+ CGI.TheDef->getName() + "'";
236 if (AsmString[VarEnd] != '}')
237 throw "Variable name beginning with '{' did not end with '}' in '"
238 + CGI.TheDef->getName() + "'";
241 if (VarName.empty() && Modifier.empty())
242 throw "Stray '$' in '" + CGI.TheDef->getName() +
243 "' asm string, maybe you want $$?";
245 if (VarName.empty()) {
246 // Just a modifier, pass this into PrintSpecial.
247 Operands.push_back(AsmWriterOperand("PrintSpecial", ~0U, Modifier));
249 // Otherwise, normal operand.
250 unsigned OpNo = CGI.getOperandNamed(VarName);
251 CodeGenInstruction::OperandInfo OpInfo = CGI.OperandList[OpNo];
253 if (CurVariant == Variant || CurVariant == ~0U) {
254 unsigned MIOp = OpInfo.MIOperandNo;
255 Operands.push_back(AsmWriterOperand(OpInfo.PrinterMethodName, MIOp,
259 LastEmitted = VarEnd;
264 /// MatchesAllButOneOp - If this instruction is exactly identical to the
265 /// specified instruction except for one differing operand, return the differing
266 /// operand number. If more than one operand mismatches, return ~1, otherwise
267 /// if the instructions are identical return ~0.
268 unsigned AsmWriterInst::MatchesAllButOneOp(const AsmWriterInst &Other)const{
269 if (Operands.size() != Other.Operands.size()) return ~1;
271 unsigned MismatchOperand = ~0U;
272 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
273 if (Operands[i] != Other.Operands[i]) {
274 if (MismatchOperand != ~0U) // Already have one mismatch?
280 return MismatchOperand;
283 static void PrintCases(std::vector<std::pair<std::string,
284 AsmWriterOperand> > &OpsToPrint, raw_ostream &O) {
285 O << " case " << OpsToPrint.back().first << ": ";
286 AsmWriterOperand TheOp = OpsToPrint.back().second;
287 OpsToPrint.pop_back();
289 // Check to see if any other operands are identical in this list, and if so,
290 // emit a case label for them.
291 for (unsigned i = OpsToPrint.size(); i != 0; --i)
292 if (OpsToPrint[i-1].second == TheOp) {
293 O << "\n case " << OpsToPrint[i-1].first << ": ";
294 OpsToPrint.erase(OpsToPrint.begin()+i-1);
297 // Finally, emit the code.
298 O << TheOp.getCode();
303 /// EmitInstructions - Emit the last instruction in the vector and any other
304 /// instructions that are suitably similar to it.
305 static void EmitInstructions(std::vector<AsmWriterInst> &Insts,
307 AsmWriterInst FirstInst = Insts.back();
310 std::vector<AsmWriterInst> SimilarInsts;
311 unsigned DifferingOperand = ~0;
312 for (unsigned i = Insts.size(); i != 0; --i) {
313 unsigned DiffOp = Insts[i-1].MatchesAllButOneOp(FirstInst);
315 if (DifferingOperand == ~0U) // First match!
316 DifferingOperand = DiffOp;
318 // If this differs in the same operand as the rest of the instructions in
319 // this class, move it to the SimilarInsts list.
320 if (DifferingOperand == DiffOp || DiffOp == ~0U) {
321 SimilarInsts.push_back(Insts[i-1]);
322 Insts.erase(Insts.begin()+i-1);
327 O << " case " << FirstInst.CGI->Namespace << "::"
328 << FirstInst.CGI->TheDef->getName() << ":\n";
329 for (unsigned i = 0, e = SimilarInsts.size(); i != e; ++i)
330 O << " case " << SimilarInsts[i].CGI->Namespace << "::"
331 << SimilarInsts[i].CGI->TheDef->getName() << ":\n";
332 for (unsigned i = 0, e = FirstInst.Operands.size(); i != e; ++i) {
333 if (i != DifferingOperand) {
334 // If the operand is the same for all instructions, just print it.
335 O << " " << FirstInst.Operands[i].getCode();
337 // If this is the operand that varies between all of the instructions,
338 // emit a switch for just this operand now.
339 O << " switch (MI->getOpcode()) {\n";
340 std::vector<std::pair<std::string, AsmWriterOperand> > OpsToPrint;
341 OpsToPrint.push_back(std::make_pair(FirstInst.CGI->Namespace + "::" +
342 FirstInst.CGI->TheDef->getName(),
343 FirstInst.Operands[i]));
345 for (unsigned si = 0, e = SimilarInsts.size(); si != e; ++si) {
346 AsmWriterInst &AWI = SimilarInsts[si];
347 OpsToPrint.push_back(std::make_pair(AWI.CGI->Namespace+"::"+
348 AWI.CGI->TheDef->getName(),
351 std::reverse(OpsToPrint.begin(), OpsToPrint.end());
352 while (!OpsToPrint.empty())
353 PrintCases(OpsToPrint, O);
361 void AsmWriterEmitter::
362 FindUniqueOperandCommands(std::vector<std::string> &UniqueOperandCommands,
363 std::vector<unsigned> &InstIdxs,
364 std::vector<unsigned> &InstOpsUsed) const {
365 InstIdxs.assign(NumberedInstructions.size(), ~0U);
367 // This vector parallels UniqueOperandCommands, keeping track of which
368 // instructions each case are used for. It is a comma separated string of
370 std::vector<std::string> InstrsForCase;
371 InstrsForCase.resize(UniqueOperandCommands.size());
372 InstOpsUsed.assign(UniqueOperandCommands.size(), 0);
374 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
375 const AsmWriterInst *Inst = getAsmWriterInstByID(i);
376 if (Inst == 0) continue; // PHI, INLINEASM, DBG_LABEL, etc.
379 if (Inst->Operands.empty())
380 continue; // Instruction already done.
382 Command = " " + Inst->Operands[0].getCode() + "\n";
384 // If this is the last operand, emit a return.
385 if (Inst->Operands.size() == 1) {
386 Command += " postInstructionAction(*MI);\n";
387 // Print the final newline
388 Command += " O << \"\\n\";\n";
389 Command += " return true;\n";
392 // Check to see if we already have 'Command' in UniqueOperandCommands.
394 bool FoundIt = false;
395 for (unsigned idx = 0, e = UniqueOperandCommands.size(); idx != e; ++idx)
396 if (UniqueOperandCommands[idx] == Command) {
398 InstrsForCase[idx] += ", ";
399 InstrsForCase[idx] += Inst->CGI->TheDef->getName();
404 InstIdxs[i] = UniqueOperandCommands.size();
405 UniqueOperandCommands.push_back(Command);
406 InstrsForCase.push_back(Inst->CGI->TheDef->getName());
408 // This command matches one operand so far.
409 InstOpsUsed.push_back(1);
413 // For each entry of UniqueOperandCommands, there is a set of instructions
414 // that uses it. If the next command of all instructions in the set are
415 // identical, fold it into the command.
416 for (unsigned CommandIdx = 0, e = UniqueOperandCommands.size();
417 CommandIdx != e; ++CommandIdx) {
419 for (unsigned Op = 1; ; ++Op) {
420 // Scan for the first instruction in the set.
421 std::vector<unsigned>::iterator NIT =
422 std::find(InstIdxs.begin(), InstIdxs.end(), CommandIdx);
423 if (NIT == InstIdxs.end()) break; // No commonality.
425 // If this instruction has no more operands, we isn't anything to merge
426 // into this command.
427 const AsmWriterInst *FirstInst =
428 getAsmWriterInstByID(NIT-InstIdxs.begin());
429 if (!FirstInst || FirstInst->Operands.size() == Op)
432 // Otherwise, scan to see if all of the other instructions in this command
433 // set share the operand.
436 for (NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx);
437 NIT != InstIdxs.end();
438 NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx)) {
439 // Okay, found another instruction in this command set. If the operand
440 // matches, we're ok, otherwise bail out.
441 const AsmWriterInst *OtherInst =
442 getAsmWriterInstByID(NIT-InstIdxs.begin());
443 if (!OtherInst || OtherInst->Operands.size() == Op ||
444 OtherInst->Operands[Op] != FirstInst->Operands[Op]) {
451 // Okay, everything in this command set has the same next operand. Add it
452 // to UniqueOperandCommands and remember that it was consumed.
453 std::string Command = " " + FirstInst->Operands[Op].getCode() + "\n";
455 // If this is the last operand, emit a return after the code.
456 if (FirstInst->Operands.size() == Op+1) {
457 Command += " postInstructionAction(*MI);\n";
458 // Print the final newline
459 Command += " O << \"\\n\";\n";
460 Command += " return true;\n";
463 UniqueOperandCommands[CommandIdx] += Command;
464 InstOpsUsed[CommandIdx]++;
468 // Prepend some of the instructions each case is used for onto the case val.
469 for (unsigned i = 0, e = InstrsForCase.size(); i != e; ++i) {
470 std::string Instrs = InstrsForCase[i];
471 if (Instrs.size() > 70) {
472 Instrs.erase(Instrs.begin()+70, Instrs.end());
477 UniqueOperandCommands[i] = " // " + Instrs + "\n" +
478 UniqueOperandCommands[i];
484 void AsmWriterEmitter::run(raw_ostream &O) {
485 EmitSourceFileHeader("Assembly Writer Source Fragment", O);
487 CodeGenTarget Target;
488 Record *AsmWriter = Target.getAsmWriter();
489 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
490 unsigned Variant = AsmWriter->getValueAsInt("Variant");
493 "/// printInstruction - This method is automatically generated by tablegen\n"
494 "/// from the instruction set description. This method returns true if the\n"
495 "/// machine instruction was sufficiently described to print it, otherwise\n"
496 "/// it returns false.\n"
497 "bool " << Target.getName() << ClassName
498 << "::printInstruction(const MachineInstr *MI) {\n";
500 std::vector<AsmWriterInst> Instructions;
502 for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
503 E = Target.inst_end(); I != E; ++I)
504 if (!I->second.AsmString.empty())
505 Instructions.push_back(AsmWriterInst(I->second, Variant));
507 // Get the instruction numbering.
508 Target.getInstructionsByEnumValue(NumberedInstructions);
510 // Compute the CodeGenInstruction -> AsmWriterInst mapping. Note that not
511 // all machine instructions are necessarily being printed, so there may be
512 // target instructions not in this map.
513 for (unsigned i = 0, e = Instructions.size(); i != e; ++i)
514 CGIAWIMap.insert(std::make_pair(Instructions[i].CGI, &Instructions[i]));
516 // Build an aggregate string, and build a table of offsets into it.
517 std::map<std::string, unsigned> StringOffset;
518 std::string AggregateString;
519 AggregateString.push_back(0); // "\0"
520 AggregateString.push_back(0); // "\0"
522 /// OpcodeInfo - This encodes the index of the string to use for the first
523 /// chunk of the output as well as indices used for operand printing.
524 std::vector<unsigned> OpcodeInfo;
526 unsigned MaxStringIdx = 0;
527 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
528 AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions[i]];
531 // Something not handled by the asmwriter printer.
533 } else if (AWI->Operands[0].OperandType !=
534 AsmWriterOperand::isLiteralTextOperand ||
535 AWI->Operands[0].Str.empty()) {
536 // Something handled by the asmwriter printer, but with no leading string.
539 unsigned &Entry = StringOffset[AWI->Operands[0].Str];
541 // Add the string to the aggregate if this is the first time found.
542 MaxStringIdx = Entry = AggregateString.size();
543 std::string Str = AWI->Operands[0].Str;
545 AggregateString += Str;
546 AggregateString += '\0';
550 // Nuke the string from the operand list. It is now handled!
551 AWI->Operands.erase(AWI->Operands.begin());
553 OpcodeInfo.push_back(Idx);
556 // Figure out how many bits we used for the string index.
557 unsigned AsmStrBits = Log2_32_Ceil(MaxStringIdx+1);
559 // To reduce code size, we compactify common instructions into a few bits
560 // in the opcode-indexed table.
561 unsigned BitsLeft = 32-AsmStrBits;
563 std::vector<std::vector<std::string> > TableDrivenOperandPrinters;
567 std::vector<std::string> UniqueOperandCommands;
569 // For the first operand check, add a default value for instructions with
570 // just opcode strings to use.
572 // Do the post instruction processing and print the final newline
573 UniqueOperandCommands.push_back(" postInstructionAction(*MI);\n O << \"\\n\";\n return true;\n");
577 std::vector<unsigned> InstIdxs;
578 std::vector<unsigned> NumInstOpsHandled;
579 FindUniqueOperandCommands(UniqueOperandCommands, InstIdxs,
582 // If we ran out of operands to print, we're done.
583 if (UniqueOperandCommands.empty()) break;
585 // Compute the number of bits we need to represent these cases, this is
586 // ceil(log2(numentries)).
587 unsigned NumBits = Log2_32_Ceil(UniqueOperandCommands.size());
589 // If we don't have enough bits for this operand, don't include it.
590 if (NumBits > BitsLeft) {
591 DOUT << "Not enough bits to densely encode " << NumBits
596 // Otherwise, we can include this in the initial lookup table. Add it in.
598 for (unsigned i = 0, e = InstIdxs.size(); i != e; ++i)
599 if (InstIdxs[i] != ~0U)
600 OpcodeInfo[i] |= InstIdxs[i] << (BitsLeft+AsmStrBits);
602 // Remove the info about this operand.
603 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
604 if (AsmWriterInst *Inst = getAsmWriterInstByID(i))
605 if (!Inst->Operands.empty()) {
606 unsigned NumOps = NumInstOpsHandled[InstIdxs[i]];
607 assert(NumOps <= Inst->Operands.size() &&
608 "Can't remove this many ops!");
609 Inst->Operands.erase(Inst->Operands.begin(),
610 Inst->Operands.begin()+NumOps);
614 // Remember the handlers for this set of operands.
615 TableDrivenOperandPrinters.push_back(UniqueOperandCommands);
620 O<<" static const unsigned OpInfo[] = {\n";
621 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
622 O << " " << OpcodeInfo[i] << "U,\t// "
623 << NumberedInstructions[i]->TheDef->getName() << "\n";
625 // Add a dummy entry so the array init doesn't end with a comma.
629 // Emit the string itself.
630 O << " const char *AsmStrs = \n \"";
631 unsigned CharsPrinted = 0;
632 EscapeString(AggregateString);
633 for (unsigned i = 0, e = AggregateString.size(); i != e; ++i) {
634 if (CharsPrinted > 70) {
638 O << AggregateString[i];
641 // Print escape sequences all together.
642 if (AggregateString[i] == '\\') {
643 assert(i+1 < AggregateString.size() && "Incomplete escape sequence!");
644 if (isdigit(AggregateString[i+1])) {
645 assert(isdigit(AggregateString[i+2]) && isdigit(AggregateString[i+3]) &&
646 "Expected 3 digit octal escape!");
647 O << AggregateString[++i];
648 O << AggregateString[++i];
649 O << AggregateString[++i];
652 O << AggregateString[++i];
659 O << " processDebugLoc(MI->getDebugLoc());\n\n";
661 O << "\n#ifndef NO_ASM_WRITER_BOILERPLATE\n";
663 O << " if (MI->getOpcode() == TargetInstrInfo::INLINEASM) {\n"
664 << " O << \"\\t\";\n"
665 << " printInlineAsm(MI);\n"
667 << " } else if (MI->isLabel()) {\n"
668 << " printLabel(MI);\n"
670 << " } else if (MI->getOpcode() == TargetInstrInfo::DECLARE) {\n"
671 << " printDeclare(MI);\n"
673 << " } else if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {\n"
674 << " printImplicitDef(MI);\n"
680 O << " O << \"\\t\";\n\n";
682 O << " // Emit the opcode for the instruction.\n"
683 << " unsigned Bits = OpInfo[MI->getOpcode()];\n"
684 << " if (Bits == 0) return false;\n"
685 << " O << AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << ");\n\n";
687 // Output the table driven operand information.
688 BitsLeft = 32-AsmStrBits;
689 for (unsigned i = 0, e = TableDrivenOperandPrinters.size(); i != e; ++i) {
690 std::vector<std::string> &Commands = TableDrivenOperandPrinters[i];
692 // Compute the number of bits we need to represent these cases, this is
693 // ceil(log2(numentries)).
694 unsigned NumBits = Log2_32_Ceil(Commands.size());
695 assert(NumBits <= BitsLeft && "consistency error");
697 // Emit code to extract this field from Bits.
700 O << "\n // Fragment " << i << " encoded into " << NumBits
701 << " bits for " << Commands.size() << " unique commands.\n";
703 if (Commands.size() == 2) {
704 // Emit two possibilitys with if/else.
705 O << " if ((Bits >> " << (BitsLeft+AsmStrBits) << ") & "
706 << ((1 << NumBits)-1) << ") {\n"
712 O << " switch ((Bits >> " << (BitsLeft+AsmStrBits) << ") & "
713 << ((1 << NumBits)-1) << ") {\n"
714 << " default: // unreachable.\n";
716 // Print out all the cases.
717 for (unsigned i = 0, e = Commands.size(); i != e; ++i) {
718 O << " case " << i << ":\n";
726 // Okay, delete instructions with no operand info left.
727 for (unsigned i = 0, e = Instructions.size(); i != e; ++i) {
728 // Entire instruction has been emitted?
729 AsmWriterInst &Inst = Instructions[i];
730 if (Inst.Operands.empty()) {
731 Instructions.erase(Instructions.begin()+i);
737 // Because this is a vector, we want to emit from the end. Reverse all of the
738 // elements in the vector.
739 std::reverse(Instructions.begin(), Instructions.end());
741 if (!Instructions.empty()) {
742 // Find the opcode # of inline asm.
743 O << " switch (MI->getOpcode()) {\n";
744 while (!Instructions.empty())
745 EmitInstructions(Instructions, O);
748 O << " postInstructionAction(*MI);\n";
749 // Print the final newline
750 O << " O << \"\\n\";\n";
751 O << " return true;\n";