1 //===- AsmWriterEmitter.cpp - Generate an assembly writer -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is emits an assembly printer for the current target.
11 // Note that this is currently fairly skeletal, but will grow over time.
13 //===----------------------------------------------------------------------===//
15 #include "AsmWriterEmitter.h"
16 #include "AsmWriterInst.h"
17 #include "CodeGenTarget.h"
19 #include "StringToOffsetTable.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/MathExtras.h"
25 static void PrintCases(std::vector<std::pair<std::string,
26 AsmWriterOperand> > &OpsToPrint, raw_ostream &O) {
27 O << " case " << OpsToPrint.back().first << ": ";
28 AsmWriterOperand TheOp = OpsToPrint.back().second;
29 OpsToPrint.pop_back();
31 // Check to see if any other operands are identical in this list, and if so,
32 // emit a case label for them.
33 for (unsigned i = OpsToPrint.size(); i != 0; --i)
34 if (OpsToPrint[i-1].second == TheOp) {
35 O << "\n case " << OpsToPrint[i-1].first << ": ";
36 OpsToPrint.erase(OpsToPrint.begin()+i-1);
39 // Finally, emit the code.
45 /// EmitInstructions - Emit the last instruction in the vector and any other
46 /// instructions that are suitably similar to it.
47 static void EmitInstructions(std::vector<AsmWriterInst> &Insts,
49 AsmWriterInst FirstInst = Insts.back();
52 std::vector<AsmWriterInst> SimilarInsts;
53 unsigned DifferingOperand = ~0;
54 for (unsigned i = Insts.size(); i != 0; --i) {
55 unsigned DiffOp = Insts[i-1].MatchesAllButOneOp(FirstInst);
57 if (DifferingOperand == ~0U) // First match!
58 DifferingOperand = DiffOp;
60 // If this differs in the same operand as the rest of the instructions in
61 // this class, move it to the SimilarInsts list.
62 if (DifferingOperand == DiffOp || DiffOp == ~0U) {
63 SimilarInsts.push_back(Insts[i-1]);
64 Insts.erase(Insts.begin()+i-1);
69 O << " case " << FirstInst.CGI->Namespace << "::"
70 << FirstInst.CGI->TheDef->getName() << ":\n";
71 for (unsigned i = 0, e = SimilarInsts.size(); i != e; ++i)
72 O << " case " << SimilarInsts[i].CGI->Namespace << "::"
73 << SimilarInsts[i].CGI->TheDef->getName() << ":\n";
74 for (unsigned i = 0, e = FirstInst.Operands.size(); i != e; ++i) {
75 if (i != DifferingOperand) {
76 // If the operand is the same for all instructions, just print it.
77 O << " " << FirstInst.Operands[i].getCode();
79 // If this is the operand that varies between all of the instructions,
80 // emit a switch for just this operand now.
81 O << " switch (MI->getOpcode()) {\n";
82 std::vector<std::pair<std::string, AsmWriterOperand> > OpsToPrint;
83 OpsToPrint.push_back(std::make_pair(FirstInst.CGI->Namespace + "::" +
84 FirstInst.CGI->TheDef->getName(),
85 FirstInst.Operands[i]));
87 for (unsigned si = 0, e = SimilarInsts.size(); si != e; ++si) {
88 AsmWriterInst &AWI = SimilarInsts[si];
89 OpsToPrint.push_back(std::make_pair(AWI.CGI->Namespace+"::"+
90 AWI.CGI->TheDef->getName(),
93 std::reverse(OpsToPrint.begin(), OpsToPrint.end());
94 while (!OpsToPrint.empty())
95 PrintCases(OpsToPrint, O);
103 void AsmWriterEmitter::
104 FindUniqueOperandCommands(std::vector<std::string> &UniqueOperandCommands,
105 std::vector<unsigned> &InstIdxs,
106 std::vector<unsigned> &InstOpsUsed) const {
107 InstIdxs.assign(NumberedInstructions.size(), ~0U);
109 // This vector parallels UniqueOperandCommands, keeping track of which
110 // instructions each case are used for. It is a comma separated string of
112 std::vector<std::string> InstrsForCase;
113 InstrsForCase.resize(UniqueOperandCommands.size());
114 InstOpsUsed.assign(UniqueOperandCommands.size(), 0);
116 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
117 const AsmWriterInst *Inst = getAsmWriterInstByID(i);
118 if (Inst == 0) continue; // PHI, INLINEASM, DBG_LABEL, etc.
121 if (Inst->Operands.empty())
122 continue; // Instruction already done.
124 Command = " " + Inst->Operands[0].getCode() + "\n";
126 // Check to see if we already have 'Command' in UniqueOperandCommands.
128 bool FoundIt = false;
129 for (unsigned idx = 0, e = UniqueOperandCommands.size(); idx != e; ++idx)
130 if (UniqueOperandCommands[idx] == Command) {
132 InstrsForCase[idx] += ", ";
133 InstrsForCase[idx] += Inst->CGI->TheDef->getName();
138 InstIdxs[i] = UniqueOperandCommands.size();
139 UniqueOperandCommands.push_back(Command);
140 InstrsForCase.push_back(Inst->CGI->TheDef->getName());
142 // This command matches one operand so far.
143 InstOpsUsed.push_back(1);
147 // For each entry of UniqueOperandCommands, there is a set of instructions
148 // that uses it. If the next command of all instructions in the set are
149 // identical, fold it into the command.
150 for (unsigned CommandIdx = 0, e = UniqueOperandCommands.size();
151 CommandIdx != e; ++CommandIdx) {
153 for (unsigned Op = 1; ; ++Op) {
154 // Scan for the first instruction in the set.
155 std::vector<unsigned>::iterator NIT =
156 std::find(InstIdxs.begin(), InstIdxs.end(), CommandIdx);
157 if (NIT == InstIdxs.end()) break; // No commonality.
159 // If this instruction has no more operands, we isn't anything to merge
160 // into this command.
161 const AsmWriterInst *FirstInst =
162 getAsmWriterInstByID(NIT-InstIdxs.begin());
163 if (!FirstInst || FirstInst->Operands.size() == Op)
166 // Otherwise, scan to see if all of the other instructions in this command
167 // set share the operand.
169 // Keep track of the maximum, number of operands or any
170 // instruction we see in the group.
171 size_t MaxSize = FirstInst->Operands.size();
173 for (NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx);
174 NIT != InstIdxs.end();
175 NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx)) {
176 // Okay, found another instruction in this command set. If the operand
177 // matches, we're ok, otherwise bail out.
178 const AsmWriterInst *OtherInst =
179 getAsmWriterInstByID(NIT-InstIdxs.begin());
182 OtherInst->Operands.size() > FirstInst->Operands.size())
183 MaxSize = std::max(MaxSize, OtherInst->Operands.size());
185 if (!OtherInst || OtherInst->Operands.size() == Op ||
186 OtherInst->Operands[Op] != FirstInst->Operands[Op]) {
193 // Okay, everything in this command set has the same next operand. Add it
194 // to UniqueOperandCommands and remember that it was consumed.
195 std::string Command = " " + FirstInst->Operands[Op].getCode() + "\n";
197 UniqueOperandCommands[CommandIdx] += Command;
198 InstOpsUsed[CommandIdx]++;
202 // Prepend some of the instructions each case is used for onto the case val.
203 for (unsigned i = 0, e = InstrsForCase.size(); i != e; ++i) {
204 std::string Instrs = InstrsForCase[i];
205 if (Instrs.size() > 70) {
206 Instrs.erase(Instrs.begin()+70, Instrs.end());
211 UniqueOperandCommands[i] = " // " + Instrs + "\n" +
212 UniqueOperandCommands[i];
217 static void UnescapeString(std::string &Str) {
218 for (unsigned i = 0; i != Str.size(); ++i) {
219 if (Str[i] == '\\' && i != Str.size()-1) {
221 default: continue; // Don't execute the code after the switch.
222 case 'a': Str[i] = '\a'; break;
223 case 'b': Str[i] = '\b'; break;
224 case 'e': Str[i] = 27; break;
225 case 'f': Str[i] = '\f'; break;
226 case 'n': Str[i] = '\n'; break;
227 case 'r': Str[i] = '\r'; break;
228 case 't': Str[i] = '\t'; break;
229 case 'v': Str[i] = '\v'; break;
230 case '"': Str[i] = '\"'; break;
231 case '\'': Str[i] = '\''; break;
232 case '\\': Str[i] = '\\'; break;
234 // Nuke the second character.
235 Str.erase(Str.begin()+i+1);
240 /// EmitPrintInstruction - Generate the code for the "printInstruction" method
242 void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) {
243 CodeGenTarget Target;
244 Record *AsmWriter = Target.getAsmWriter();
245 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
248 "/// printInstruction - This method is automatically generated by tablegen\n"
249 "/// from the instruction set description.\n"
250 "void " << Target.getName() << ClassName
251 << "::printInstruction(const MachineInstr *MI) {\n";
253 std::vector<AsmWriterInst> Instructions;
255 for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
256 E = Target.inst_end(); I != E; ++I)
257 if (!(*I)->AsmString.empty() &&
258 (*I)->TheDef->getName() != "PHI")
259 Instructions.push_back(
261 AsmWriter->getValueAsInt("Variant"),
262 AsmWriter->getValueAsInt("FirstOperandColumn"),
263 AsmWriter->getValueAsInt("OperandSpacing")));
265 // Get the instruction numbering.
266 NumberedInstructions = Target.getInstructionsByEnumValue();
268 // Compute the CodeGenInstruction -> AsmWriterInst mapping. Note that not
269 // all machine instructions are necessarily being printed, so there may be
270 // target instructions not in this map.
271 for (unsigned i = 0, e = Instructions.size(); i != e; ++i)
272 CGIAWIMap.insert(std::make_pair(Instructions[i].CGI, &Instructions[i]));
274 // Build an aggregate string, and build a table of offsets into it.
275 StringToOffsetTable StringTable;
277 /// OpcodeInfo - This encodes the index of the string to use for the first
278 /// chunk of the output as well as indices used for operand printing.
279 std::vector<unsigned> OpcodeInfo;
281 unsigned MaxStringIdx = 0;
282 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
283 AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions[i]];
286 // Something not handled by the asmwriter printer.
288 } else if (AWI->Operands[0].OperandType !=
289 AsmWriterOperand::isLiteralTextOperand ||
290 AWI->Operands[0].Str.empty()) {
291 // Something handled by the asmwriter printer, but with no leading string.
292 Idx = StringTable.GetOrAddStringOffset("");
294 std::string Str = AWI->Operands[0].Str;
296 Idx = StringTable.GetOrAddStringOffset(Str);
297 MaxStringIdx = std::max(MaxStringIdx, Idx);
299 // Nuke the string from the operand list. It is now handled!
300 AWI->Operands.erase(AWI->Operands.begin());
303 // Bias offset by one since we want 0 as a sentinel.
304 OpcodeInfo.push_back(Idx+1);
307 // Figure out how many bits we used for the string index.
308 unsigned AsmStrBits = Log2_32_Ceil(MaxStringIdx+2);
310 // To reduce code size, we compactify common instructions into a few bits
311 // in the opcode-indexed table.
312 unsigned BitsLeft = 32-AsmStrBits;
314 std::vector<std::vector<std::string> > TableDrivenOperandPrinters;
317 std::vector<std::string> UniqueOperandCommands;
318 std::vector<unsigned> InstIdxs;
319 std::vector<unsigned> NumInstOpsHandled;
320 FindUniqueOperandCommands(UniqueOperandCommands, InstIdxs,
323 // If we ran out of operands to print, we're done.
324 if (UniqueOperandCommands.empty()) break;
326 // Compute the number of bits we need to represent these cases, this is
327 // ceil(log2(numentries)).
328 unsigned NumBits = Log2_32_Ceil(UniqueOperandCommands.size());
330 // If we don't have enough bits for this operand, don't include it.
331 if (NumBits > BitsLeft) {
332 DEBUG(errs() << "Not enough bits to densely encode " << NumBits
337 // Otherwise, we can include this in the initial lookup table. Add it in.
339 for (unsigned i = 0, e = InstIdxs.size(); i != e; ++i)
340 if (InstIdxs[i] != ~0U)
341 OpcodeInfo[i] |= InstIdxs[i] << (BitsLeft+AsmStrBits);
343 // Remove the info about this operand.
344 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
345 if (AsmWriterInst *Inst = getAsmWriterInstByID(i))
346 if (!Inst->Operands.empty()) {
347 unsigned NumOps = NumInstOpsHandled[InstIdxs[i]];
348 assert(NumOps <= Inst->Operands.size() &&
349 "Can't remove this many ops!");
350 Inst->Operands.erase(Inst->Operands.begin(),
351 Inst->Operands.begin()+NumOps);
355 // Remember the handlers for this set of operands.
356 TableDrivenOperandPrinters.push_back(UniqueOperandCommands);
361 O<<" static const unsigned OpInfo[] = {\n";
362 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
363 O << " " << OpcodeInfo[i] << "U,\t// "
364 << NumberedInstructions[i]->TheDef->getName() << "\n";
366 // Add a dummy entry so the array init doesn't end with a comma.
370 // Emit the string itself.
371 O << " const char *AsmStrs = \n";
372 StringTable.EmitString(O);
375 O << " O << \"\\t\";\n\n";
377 O << " // Emit the opcode for the instruction.\n"
378 << " unsigned Bits = OpInfo[MI->getOpcode()];\n"
379 << " assert(Bits != 0 && \"Cannot print this instruction.\");\n"
380 << " O << AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << ")-1;\n\n";
382 // Output the table driven operand information.
383 BitsLeft = 32-AsmStrBits;
384 for (unsigned i = 0, e = TableDrivenOperandPrinters.size(); i != e; ++i) {
385 std::vector<std::string> &Commands = TableDrivenOperandPrinters[i];
387 // Compute the number of bits we need to represent these cases, this is
388 // ceil(log2(numentries)).
389 unsigned NumBits = Log2_32_Ceil(Commands.size());
390 assert(NumBits <= BitsLeft && "consistency error");
392 // Emit code to extract this field from Bits.
395 O << "\n // Fragment " << i << " encoded into " << NumBits
396 << " bits for " << Commands.size() << " unique commands.\n";
398 if (Commands.size() == 2) {
399 // Emit two possibilitys with if/else.
400 O << " if ((Bits >> " << (BitsLeft+AsmStrBits) << ") & "
401 << ((1 << NumBits)-1) << ") {\n"
407 O << " switch ((Bits >> " << (BitsLeft+AsmStrBits) << ") & "
408 << ((1 << NumBits)-1) << ") {\n"
409 << " default: // unreachable.\n";
411 // Print out all the cases.
412 for (unsigned i = 0, e = Commands.size(); i != e; ++i) {
413 O << " case " << i << ":\n";
421 // Okay, delete instructions with no operand info left.
422 for (unsigned i = 0, e = Instructions.size(); i != e; ++i) {
423 // Entire instruction has been emitted?
424 AsmWriterInst &Inst = Instructions[i];
425 if (Inst.Operands.empty()) {
426 Instructions.erase(Instructions.begin()+i);
432 // Because this is a vector, we want to emit from the end. Reverse all of the
433 // elements in the vector.
434 std::reverse(Instructions.begin(), Instructions.end());
437 // Now that we've emitted all of the operand info that fit into 32 bits, emit
438 // information for those instructions that are left. This is a less dense
439 // encoding, but we expect the main 32-bit table to handle the majority of
441 if (!Instructions.empty()) {
442 // Find the opcode # of inline asm.
443 O << " switch (MI->getOpcode()) {\n";
444 while (!Instructions.empty())
445 EmitInstructions(Instructions, O);
455 void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) {
456 CodeGenTarget Target;
457 Record *AsmWriter = Target.getAsmWriter();
458 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
459 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
461 StringToOffsetTable StringTable;
463 "\n\n/// getRegisterName - This method is automatically generated by tblgen\n"
464 "/// from the register set description. This returns the assembler name\n"
465 "/// for the specified register.\n"
466 "const char *" << Target.getName() << ClassName
467 << "::getRegisterName(unsigned RegNo) {\n"
468 << " assert(RegNo && RegNo < " << (Registers.size()+1)
469 << " && \"Invalid register number!\");\n"
471 << " static const unsigned RegAsmOffset[] = {";
472 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
473 const CodeGenRegister &Reg = Registers[i];
475 std::string AsmName = Reg.TheDef->getValueAsString("AsmName");
477 AsmName = Reg.getName();
483 O << StringTable.GetOrAddStringOffset(AsmName) << ", ";
489 O << " const char *AsmStrs =\n";
490 StringTable.EmitString(O);
493 O << " return AsmStrs+RegAsmOffset[RegNo-1];\n"
497 void AsmWriterEmitter::EmitGetInstructionName(raw_ostream &O) {
498 CodeGenTarget Target;
499 Record *AsmWriter = Target.getAsmWriter();
500 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
502 const std::vector<const CodeGenInstruction*> &NumberedInstructions =
503 Target.getInstructionsByEnumValue();
505 StringToOffsetTable StringTable;
507 "\n\n#ifdef GET_INSTRUCTION_NAME\n"
508 "#undef GET_INSTRUCTION_NAME\n\n"
509 "/// getInstructionName: This method is automatically generated by tblgen\n"
510 "/// from the instruction set description. This returns the enum name of the\n"
511 "/// specified instruction.\n"
512 "const char *" << Target.getName() << ClassName
513 << "::getInstructionName(unsigned Opcode) {\n"
514 << " assert(Opcode < " << NumberedInstructions.size()
515 << " && \"Invalid instruction number!\");\n"
517 << " static const unsigned InstAsmOffset[] = {";
518 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
519 const CodeGenInstruction &Inst = *NumberedInstructions[i];
521 std::string AsmName = Inst.TheDef->getName();
525 O << StringTable.GetOrAddStringOffset(AsmName) << ", ";
531 O << " const char *Strs =\n";
532 StringTable.EmitString(O);
535 O << " return Strs+InstAsmOffset[Opcode];\n"
541 void AsmWriterEmitter::run(raw_ostream &O) {
542 EmitSourceFileHeader("Assembly Writer Source Fragment", O);
544 EmitPrintInstruction(O);
545 EmitGetRegisterName(O);
546 EmitGetInstructionName(O);