1 //===- AsmWriterEmitter.cpp - Generate an assembly writer -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is emits an assembly printer for the current target.
11 // Note that this is currently fairly skeletal, but will grow over time.
13 //===----------------------------------------------------------------------===//
15 #include "AsmWriterEmitter.h"
16 #include "CodeGenTarget.h"
18 #include "llvm/ADT/StringExtras.h"
19 #include "llvm/Support/Debug.h"
20 #include "llvm/Support/MathExtras.h"
24 static bool isIdentChar(char C) {
25 return (C >= 'a' && C <= 'z') ||
26 (C >= 'A' && C <= 'Z') ||
27 (C >= '0' && C <= '9') ||
31 // This should be an anon namespace, this works around a GCC warning.
33 struct AsmWriterOperand {
34 enum { isLiteralTextOperand, isMachineInstrOperand } OperandType;
36 /// Str - For isLiteralTextOperand, this IS the literal text. For
37 /// isMachineInstrOperand, this is the PrinterMethodName for the operand.
40 /// MiOpNo - For isMachineInstrOperand, this is the operand number of the
41 /// machine instruction.
44 /// MiModifier - For isMachineInstrOperand, this is the modifier string for
45 /// an operand, specified with syntax like ${opname:modifier}.
46 std::string MiModifier;
48 // To make VS STL happy
49 AsmWriterOperand():OperandType(isLiteralTextOperand) {}
51 AsmWriterOperand(const std::string &LitStr)
52 : OperandType(isLiteralTextOperand), Str(LitStr) {}
54 AsmWriterOperand(const std::string &Printer, unsigned OpNo,
55 const std::string &Modifier)
56 : OperandType(isMachineInstrOperand), Str(Printer), MIOpNo(OpNo),
57 MiModifier(Modifier) {}
59 bool operator!=(const AsmWriterOperand &Other) const {
60 if (OperandType != Other.OperandType || Str != Other.Str) return true;
61 if (OperandType == isMachineInstrOperand)
62 return MIOpNo != Other.MIOpNo || MiModifier != Other.MiModifier;
65 bool operator==(const AsmWriterOperand &Other) const {
66 return !operator!=(Other);
69 /// getCode - Return the code that prints this operand.
70 std::string getCode() const;
77 std::vector<AsmWriterOperand> Operands;
78 const CodeGenInstruction *CGI;
80 AsmWriterInst(const CodeGenInstruction &CGI, unsigned Variant);
82 /// MatchesAllButOneOp - If this instruction is exactly identical to the
83 /// specified instruction except for one differing operand, return the
84 /// differing operand number. Otherwise return ~0.
85 unsigned MatchesAllButOneOp(const AsmWriterInst &Other) const;
88 void AddLiteralString(const std::string &Str) {
89 // If the last operand was already a literal text string, append this to
90 // it, otherwise add a new operand.
91 if (!Operands.empty() &&
92 Operands.back().OperandType == AsmWriterOperand::isLiteralTextOperand)
93 Operands.back().Str.append(Str);
95 Operands.push_back(AsmWriterOperand(Str));
101 std::string AsmWriterOperand::getCode() const {
102 if (OperandType == isLiteralTextOperand)
103 return "O << \"" + Str + "\"; ";
105 std::string Result = Str + "(MI";
107 Result += ", " + utostr(MIOpNo);
108 if (!MiModifier.empty())
109 Result += ", \"" + MiModifier + '"';
110 return Result + "); ";
114 /// ParseAsmString - Parse the specified Instruction's AsmString into this
117 AsmWriterInst::AsmWriterInst(const CodeGenInstruction &CGI, unsigned Variant) {
119 unsigned CurVariant = ~0U; // ~0 if we are outside a {.|.|.} region, other #.
121 // NOTE: Any extensions to this code need to be mirrored in the
122 // AsmPrinter::printInlineAsm code that executes as compile time (assuming
123 // that inline asm strings should also get the new feature)!
124 const std::string &AsmString = CGI.AsmString;
125 std::string::size_type LastEmitted = 0;
126 while (LastEmitted != AsmString.size()) {
127 std::string::size_type DollarPos =
128 AsmString.find_first_of("${|}\\", LastEmitted);
129 if (DollarPos == std::string::npos) DollarPos = AsmString.size();
131 // Emit a constant string fragment.
132 if (DollarPos != LastEmitted) {
133 // TODO: this should eventually handle escaping.
134 if (CurVariant == Variant || CurVariant == ~0U)
135 AddLiteralString(std::string(AsmString.begin()+LastEmitted,
136 AsmString.begin()+DollarPos));
137 LastEmitted = DollarPos;
138 } else if (AsmString[DollarPos] == '\\') {
139 if (DollarPos+1 != AsmString.size() &&
140 (CurVariant == Variant || CurVariant == ~0U)) {
141 if (AsmString[DollarPos+1] == 'n') {
142 AddLiteralString("\\n");
143 } else if (AsmString[DollarPos+1] == 't') {
144 AddLiteralString("\\t");
145 } else if (std::string("${|}\\").find(AsmString[DollarPos+1])
146 != std::string::npos) {
147 AddLiteralString(std::string(1, AsmString[DollarPos+1]));
149 throw "Non-supported escaped character found in instruction '" +
150 CGI.TheDef->getName() + "'!";
152 LastEmitted = DollarPos+2;
155 } else if (AsmString[DollarPos] == '{') {
156 if (CurVariant != ~0U)
157 throw "Nested variants found for instruction '" +
158 CGI.TheDef->getName() + "'!";
159 LastEmitted = DollarPos+1;
160 CurVariant = 0; // We are now inside of the variant!
161 } else if (AsmString[DollarPos] == '|') {
162 if (CurVariant == ~0U)
163 throw "'|' character found outside of a variant in instruction '"
164 + CGI.TheDef->getName() + "'!";
167 } else if (AsmString[DollarPos] == '}') {
168 if (CurVariant == ~0U)
169 throw "'}' character found outside of a variant in instruction '"
170 + CGI.TheDef->getName() + "'!";
173 } else if (DollarPos+1 != AsmString.size() &&
174 AsmString[DollarPos+1] == '$') {
175 if (CurVariant == Variant || CurVariant == ~0U)
176 AddLiteralString("$"); // "$$" -> $
177 LastEmitted = DollarPos+2;
179 // Get the name of the variable.
180 std::string::size_type VarEnd = DollarPos+1;
182 // handle ${foo}bar as $foo by detecting whether the character following
183 // the dollar sign is a curly brace. If so, advance VarEnd and DollarPos
184 // so the variable name does not contain the leading curly brace.
185 bool hasCurlyBraces = false;
186 if (VarEnd < AsmString.size() && '{' == AsmString[VarEnd]) {
187 hasCurlyBraces = true;
192 while (VarEnd < AsmString.size() && isIdentChar(AsmString[VarEnd]))
194 std::string VarName(AsmString.begin()+DollarPos+1,
195 AsmString.begin()+VarEnd);
197 // Modifier - Support ${foo:modifier} syntax, where "modifier" is passed
198 // into printOperand. Also support ${:feature}, which is passed into
200 std::string Modifier;
202 // In order to avoid starting the next string at the terminating curly
203 // brace, advance the end position past it if we found an opening curly
205 if (hasCurlyBraces) {
206 if (VarEnd >= AsmString.size())
207 throw "Reached end of string before terminating curly brace in '"
208 + CGI.TheDef->getName() + "'";
210 // Look for a modifier string.
211 if (AsmString[VarEnd] == ':') {
213 if (VarEnd >= AsmString.size())
214 throw "Reached end of string before terminating curly brace in '"
215 + CGI.TheDef->getName() + "'";
217 unsigned ModifierStart = VarEnd;
218 while (VarEnd < AsmString.size() && isIdentChar(AsmString[VarEnd]))
220 Modifier = std::string(AsmString.begin()+ModifierStart,
221 AsmString.begin()+VarEnd);
222 if (Modifier.empty())
223 throw "Bad operand modifier name in '"+ CGI.TheDef->getName() + "'";
226 if (AsmString[VarEnd] != '}')
227 throw "Variable name beginning with '{' did not end with '}' in '"
228 + CGI.TheDef->getName() + "'";
231 if (VarName.empty() && Modifier.empty())
232 throw "Stray '$' in '" + CGI.TheDef->getName() +
233 "' asm string, maybe you want $$?";
235 if (VarName.empty()) {
236 // Just a modifier, pass this into PrintSpecial.
237 Operands.push_back(AsmWriterOperand("PrintSpecial", ~0U, Modifier));
239 // Otherwise, normal operand.
240 unsigned OpNo = CGI.getOperandNamed(VarName);
241 CodeGenInstruction::OperandInfo OpInfo = CGI.OperandList[OpNo];
243 if (CurVariant == Variant || CurVariant == ~0U) {
244 unsigned MIOp = OpInfo.MIOperandNo;
245 Operands.push_back(AsmWriterOperand(OpInfo.PrinterMethodName, MIOp,
249 LastEmitted = VarEnd;
253 AddLiteralString("\\n");
256 /// MatchesAllButOneOp - If this instruction is exactly identical to the
257 /// specified instruction except for one differing operand, return the differing
258 /// operand number. If more than one operand mismatches, return ~1, otherwise
259 /// if the instructions are identical return ~0.
260 unsigned AsmWriterInst::MatchesAllButOneOp(const AsmWriterInst &Other)const{
261 if (Operands.size() != Other.Operands.size()) return ~1;
263 unsigned MismatchOperand = ~0U;
264 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
265 if (Operands[i] != Other.Operands[i]) {
266 if (MismatchOperand != ~0U) // Already have one mismatch?
272 return MismatchOperand;
275 static void PrintCases(std::vector<std::pair<std::string,
276 AsmWriterOperand> > &OpsToPrint, std::ostream &O) {
277 O << " case " << OpsToPrint.back().first << ": ";
278 AsmWriterOperand TheOp = OpsToPrint.back().second;
279 OpsToPrint.pop_back();
281 // Check to see if any other operands are identical in this list, and if so,
282 // emit a case label for them.
283 for (unsigned i = OpsToPrint.size(); i != 0; --i)
284 if (OpsToPrint[i-1].second == TheOp) {
285 O << "\n case " << OpsToPrint[i-1].first << ": ";
286 OpsToPrint.erase(OpsToPrint.begin()+i-1);
289 // Finally, emit the code.
290 O << TheOp.getCode();
295 /// EmitInstructions - Emit the last instruction in the vector and any other
296 /// instructions that are suitably similar to it.
297 static void EmitInstructions(std::vector<AsmWriterInst> &Insts,
299 AsmWriterInst FirstInst = Insts.back();
302 std::vector<AsmWriterInst> SimilarInsts;
303 unsigned DifferingOperand = ~0;
304 for (unsigned i = Insts.size(); i != 0; --i) {
305 unsigned DiffOp = Insts[i-1].MatchesAllButOneOp(FirstInst);
307 if (DifferingOperand == ~0U) // First match!
308 DifferingOperand = DiffOp;
310 // If this differs in the same operand as the rest of the instructions in
311 // this class, move it to the SimilarInsts list.
312 if (DifferingOperand == DiffOp || DiffOp == ~0U) {
313 SimilarInsts.push_back(Insts[i-1]);
314 Insts.erase(Insts.begin()+i-1);
319 O << " case " << FirstInst.CGI->Namespace << "::"
320 << FirstInst.CGI->TheDef->getName() << ":\n";
321 for (unsigned i = 0, e = SimilarInsts.size(); i != e; ++i)
322 O << " case " << SimilarInsts[i].CGI->Namespace << "::"
323 << SimilarInsts[i].CGI->TheDef->getName() << ":\n";
324 for (unsigned i = 0, e = FirstInst.Operands.size(); i != e; ++i) {
325 if (i != DifferingOperand) {
326 // If the operand is the same for all instructions, just print it.
327 O << " " << FirstInst.Operands[i].getCode();
329 // If this is the operand that varies between all of the instructions,
330 // emit a switch for just this operand now.
331 O << " switch (MI->getOpcode()) {\n";
332 std::vector<std::pair<std::string, AsmWriterOperand> > OpsToPrint;
333 OpsToPrint.push_back(std::make_pair(FirstInst.CGI->Namespace + "::" +
334 FirstInst.CGI->TheDef->getName(),
335 FirstInst.Operands[i]));
337 for (unsigned si = 0, e = SimilarInsts.size(); si != e; ++si) {
338 AsmWriterInst &AWI = SimilarInsts[si];
339 OpsToPrint.push_back(std::make_pair(AWI.CGI->Namespace+"::"+
340 AWI.CGI->TheDef->getName(),
343 std::reverse(OpsToPrint.begin(), OpsToPrint.end());
344 while (!OpsToPrint.empty())
345 PrintCases(OpsToPrint, O);
354 void AsmWriterEmitter::
355 FindUniqueOperandCommands(std::vector<std::string> &UniqueOperandCommands,
356 std::vector<unsigned> &InstIdxs,
357 std::vector<unsigned> &InstOpsUsed) const {
358 InstIdxs.assign(NumberedInstructions.size(), ~0U);
360 // This vector parallels UniqueOperandCommands, keeping track of which
361 // instructions each case are used for. It is a comma separated string of
363 std::vector<std::string> InstrsForCase;
364 InstrsForCase.resize(UniqueOperandCommands.size());
365 InstOpsUsed.assign(UniqueOperandCommands.size(), 0);
367 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
368 const AsmWriterInst *Inst = getAsmWriterInstByID(i);
369 if (Inst == 0) continue; // PHI, INLINEASM, DBG_LABEL, etc.
372 if (Inst->Operands.empty())
373 continue; // Instruction already done.
375 Command = " " + Inst->Operands[0].getCode() + "\n";
377 // If this is the last operand, emit a return.
378 if (Inst->Operands.size() == 1)
379 Command += " return true;\n";
381 // Check to see if we already have 'Command' in UniqueOperandCommands.
383 bool FoundIt = false;
384 for (unsigned idx = 0, e = UniqueOperandCommands.size(); idx != e; ++idx)
385 if (UniqueOperandCommands[idx] == Command) {
387 InstrsForCase[idx] += ", ";
388 InstrsForCase[idx] += Inst->CGI->TheDef->getName();
393 InstIdxs[i] = UniqueOperandCommands.size();
394 UniqueOperandCommands.push_back(Command);
395 InstrsForCase.push_back(Inst->CGI->TheDef->getName());
397 // This command matches one operand so far.
398 InstOpsUsed.push_back(1);
402 // For each entry of UniqueOperandCommands, there is a set of instructions
403 // that uses it. If the next command of all instructions in the set are
404 // identical, fold it into the command.
405 for (unsigned CommandIdx = 0, e = UniqueOperandCommands.size();
406 CommandIdx != e; ++CommandIdx) {
408 for (unsigned Op = 1; ; ++Op) {
409 // Scan for the first instruction in the set.
410 std::vector<unsigned>::iterator NIT =
411 std::find(InstIdxs.begin(), InstIdxs.end(), CommandIdx);
412 if (NIT == InstIdxs.end()) break; // No commonality.
414 // If this instruction has no more operands, we isn't anything to merge
415 // into this command.
416 const AsmWriterInst *FirstInst =
417 getAsmWriterInstByID(NIT-InstIdxs.begin());
418 if (!FirstInst || FirstInst->Operands.size() == Op)
421 // Otherwise, scan to see if all of the other instructions in this command
422 // set share the operand.
425 for (NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx);
426 NIT != InstIdxs.end();
427 NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx)) {
428 // Okay, found another instruction in this command set. If the operand
429 // matches, we're ok, otherwise bail out.
430 const AsmWriterInst *OtherInst =
431 getAsmWriterInstByID(NIT-InstIdxs.begin());
432 if (!OtherInst || OtherInst->Operands.size() == Op ||
433 OtherInst->Operands[Op] != FirstInst->Operands[Op]) {
440 // Okay, everything in this command set has the same next operand. Add it
441 // to UniqueOperandCommands and remember that it was consumed.
442 std::string Command = " " + FirstInst->Operands[Op].getCode() + "\n";
444 // If this is the last operand, emit a return after the code.
445 if (FirstInst->Operands.size() == Op+1)
446 Command += " return true;\n";
448 UniqueOperandCommands[CommandIdx] += Command;
449 InstOpsUsed[CommandIdx]++;
453 // Prepend some of the instructions each case is used for onto the case val.
454 for (unsigned i = 0, e = InstrsForCase.size(); i != e; ++i) {
455 std::string Instrs = InstrsForCase[i];
456 if (Instrs.size() > 70) {
457 Instrs.erase(Instrs.begin()+70, Instrs.end());
462 UniqueOperandCommands[i] = " // " + Instrs + "\n" +
463 UniqueOperandCommands[i];
469 void AsmWriterEmitter::run(std::ostream &O) {
470 EmitSourceFileHeader("Assembly Writer Source Fragment", O);
472 CodeGenTarget Target;
473 Record *AsmWriter = Target.getAsmWriter();
474 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
475 unsigned Variant = AsmWriter->getValueAsInt("Variant");
478 "/// printInstruction - This method is automatically generated by tablegen\n"
479 "/// from the instruction set description. This method returns true if the\n"
480 "/// machine instruction was sufficiently described to print it, otherwise\n"
481 "/// it returns false.\n"
482 "bool " << Target.getName() << ClassName
483 << "::printInstruction(const MachineInstr *MI) {\n";
485 std::vector<AsmWriterInst> Instructions;
487 for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
488 E = Target.inst_end(); I != E; ++I)
489 if (!I->second.AsmString.empty())
490 Instructions.push_back(AsmWriterInst(I->second, Variant));
492 // Get the instruction numbering.
493 Target.getInstructionsByEnumValue(NumberedInstructions);
495 // Compute the CodeGenInstruction -> AsmWriterInst mapping. Note that not
496 // all machine instructions are necessarily being printed, so there may be
497 // target instructions not in this map.
498 for (unsigned i = 0, e = Instructions.size(); i != e; ++i)
499 CGIAWIMap.insert(std::make_pair(Instructions[i].CGI, &Instructions[i]));
501 // Build an aggregate string, and build a table of offsets into it.
502 std::map<std::string, unsigned> StringOffset;
503 std::string AggregateString;
504 AggregateString.push_back(0); // "\0"
505 AggregateString.push_back(0); // "\0"
507 /// OpcodeInfo - This encodes the index of the string to use for the first
508 /// chunk of the output as well as indices used for operand printing.
509 std::vector<unsigned> OpcodeInfo;
511 unsigned MaxStringIdx = 0;
512 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
513 AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions[i]];
516 // Something not handled by the asmwriter printer.
518 } else if (AWI->Operands[0].OperandType !=
519 AsmWriterOperand::isLiteralTextOperand ||
520 AWI->Operands[0].Str.empty()) {
521 // Something handled by the asmwriter printer, but with no leading string.
524 unsigned &Entry = StringOffset[AWI->Operands[0].Str];
526 // Add the string to the aggregate if this is the first time found.
527 MaxStringIdx = Entry = AggregateString.size();
528 std::string Str = AWI->Operands[0].Str;
530 AggregateString += Str;
531 AggregateString += '\0';
535 // Nuke the string from the operand list. It is now handled!
536 AWI->Operands.erase(AWI->Operands.begin());
538 OpcodeInfo.push_back(Idx);
541 // Figure out how many bits we used for the string index.
542 unsigned AsmStrBits = Log2_32_Ceil(MaxStringIdx+1);
544 // To reduce code size, we compactify common instructions into a few bits
545 // in the opcode-indexed table.
546 unsigned BitsLeft = 32-AsmStrBits;
548 std::vector<std::vector<std::string> > TableDrivenOperandPrinters;
552 std::vector<std::string> UniqueOperandCommands;
554 // For the first operand check, add a default value for instructions with
555 // just opcode strings to use.
557 UniqueOperandCommands.push_back(" return true;\n");
561 std::vector<unsigned> InstIdxs;
562 std::vector<unsigned> NumInstOpsHandled;
563 FindUniqueOperandCommands(UniqueOperandCommands, InstIdxs,
566 // If we ran out of operands to print, we're done.
567 if (UniqueOperandCommands.empty()) break;
569 // Compute the number of bits we need to represent these cases, this is
570 // ceil(log2(numentries)).
571 unsigned NumBits = Log2_32_Ceil(UniqueOperandCommands.size());
573 // If we don't have enough bits for this operand, don't include it.
574 if (NumBits > BitsLeft) {
575 DOUT << "Not enough bits to densely encode " << NumBits
580 // Otherwise, we can include this in the initial lookup table. Add it in.
582 for (unsigned i = 0, e = InstIdxs.size(); i != e; ++i)
583 if (InstIdxs[i] != ~0U)
584 OpcodeInfo[i] |= InstIdxs[i] << (BitsLeft+AsmStrBits);
586 // Remove the info about this operand.
587 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
588 if (AsmWriterInst *Inst = getAsmWriterInstByID(i))
589 if (!Inst->Operands.empty()) {
590 unsigned NumOps = NumInstOpsHandled[InstIdxs[i]];
591 assert(NumOps <= Inst->Operands.size() &&
592 "Can't remove this many ops!");
593 Inst->Operands.erase(Inst->Operands.begin(),
594 Inst->Operands.begin()+NumOps);
598 // Remember the handlers for this set of operands.
599 TableDrivenOperandPrinters.push_back(UniqueOperandCommands);
604 O<<" static const unsigned OpInfo[] = {\n";
605 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
606 O << " " << OpcodeInfo[i] << "U,\t// "
607 << NumberedInstructions[i]->TheDef->getName() << "\n";
609 // Add a dummy entry so the array init doesn't end with a comma.
613 // Emit the string itself.
614 O << " const char *AsmStrs = \n \"";
615 unsigned CharsPrinted = 0;
616 EscapeString(AggregateString);
617 for (unsigned i = 0, e = AggregateString.size(); i != e; ++i) {
618 if (CharsPrinted > 70) {
622 O << AggregateString[i];
625 // Print escape sequences all together.
626 if (AggregateString[i] == '\\') {
627 assert(i+1 < AggregateString.size() && "Incomplete escape sequence!");
628 if (isdigit(AggregateString[i+1])) {
629 assert(isdigit(AggregateString[i+2]) && isdigit(AggregateString[i+3]) &&
630 "Expected 3 digit octal escape!");
631 O << AggregateString[++i];
632 O << AggregateString[++i];
633 O << AggregateString[++i];
636 O << AggregateString[++i];
643 O << " if (MI->getOpcode() == TargetInstrInfo::INLINEASM) {\n"
644 << " O << \"\\t\";\n"
645 << " printInlineAsm(MI);\n"
647 << " } else if (MI->isLabel()) {\n"
648 << " printLabel(MI);\n"
650 << " } else if (MI->getOpcode() == TargetInstrInfo::DECLARE) {\n"
651 << " printDeclare(MI);\n"
653 << " } else if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {\n"
654 << " printImplicitDef(MI);\n"
658 O << " O << \"\\t\";\n\n";
660 O << " // Emit the opcode for the instruction.\n"
661 << " unsigned Bits = OpInfo[MI->getOpcode()];\n"
662 << " if (Bits == 0) return false;\n"
663 << " O << AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << ");\n\n";
665 // Output the table driven operand information.
666 BitsLeft = 32-AsmStrBits;
667 for (unsigned i = 0, e = TableDrivenOperandPrinters.size(); i != e; ++i) {
668 std::vector<std::string> &Commands = TableDrivenOperandPrinters[i];
670 // Compute the number of bits we need to represent these cases, this is
671 // ceil(log2(numentries)).
672 unsigned NumBits = Log2_32_Ceil(Commands.size());
673 assert(NumBits <= BitsLeft && "consistency error");
675 // Emit code to extract this field from Bits.
678 O << "\n // Fragment " << i << " encoded into " << NumBits
679 << " bits for " << Commands.size() << " unique commands.\n";
681 if (Commands.size() == 2) {
682 // Emit two possibilitys with if/else.
683 O << " if ((Bits >> " << (BitsLeft+AsmStrBits) << ") & "
684 << ((1 << NumBits)-1) << ") {\n"
690 O << " switch ((Bits >> " << (BitsLeft+AsmStrBits) << ") & "
691 << ((1 << NumBits)-1) << ") {\n"
692 << " default: // unreachable.\n";
694 // Print out all the cases.
695 for (unsigned i = 0, e = Commands.size(); i != e; ++i) {
696 O << " case " << i << ":\n";
704 // Okay, delete instructions with no operand info left.
705 for (unsigned i = 0, e = Instructions.size(); i != e; ++i) {
706 // Entire instruction has been emitted?
707 AsmWriterInst &Inst = Instructions[i];
708 if (Inst.Operands.empty()) {
709 Instructions.erase(Instructions.begin()+i);
715 // Because this is a vector, we want to emit from the end. Reverse all of the
716 // elements in the vector.
717 std::reverse(Instructions.begin(), Instructions.end());
719 if (!Instructions.empty()) {
720 // Find the opcode # of inline asm.
721 O << " switch (MI->getOpcode()) {\n";
722 while (!Instructions.empty())
723 EmitInstructions(Instructions, O);
726 O << " return true;\n";