1 //===- AsmWriterEmitter.cpp - Generate an assembly writer -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is emits an assembly printer for the current target.
11 // Note that this is currently fairly skeletal, but will grow over time.
13 //===----------------------------------------------------------------------===//
15 #include "AsmWriterEmitter.h"
16 #include "CodeGenTarget.h"
18 #include "llvm/ADT/StringExtras.h"
19 #include "llvm/Support/Debug.h"
20 #include "llvm/Support/MathExtras.h"
26 static bool isIdentChar(char C) {
27 return (C >= 'a' && C <= 'z') ||
28 (C >= 'A' && C <= 'Z') ||
29 (C >= '0' && C <= '9') ||
33 // This should be an anon namespace, this works around a GCC warning.
35 struct AsmWriterOperand {
37 // Output this text surrounded by quotes to the asm.
39 // This is the name of a routine to call to print the operand.
40 isMachineInstrOperand,
41 // Output this text verbatim to the asm writer. It is code that
42 // will output some text to the asm.
43 isLiteralStatementOperand
46 /// Str - For isLiteralTextOperand, this IS the literal text. For
47 /// isMachineInstrOperand, this is the PrinterMethodName for the operand..
48 /// For isLiteralStatementOperand, this is the code to insert verbatim
49 /// into the asm writer.
52 /// MiOpNo - For isMachineInstrOperand, this is the operand number of the
53 /// machine instruction.
56 /// MiModifier - For isMachineInstrOperand, this is the modifier string for
57 /// an operand, specified with syntax like ${opname:modifier}.
58 std::string MiModifier;
60 // To make VS STL happy
61 AsmWriterOperand(OpType op = isLiteralTextOperand):OperandType(op) {}
63 AsmWriterOperand(const std::string &LitStr,
64 OpType op = isLiteralTextOperand)
65 : OperandType(op), Str(LitStr) {}
67 AsmWriterOperand(const std::string &Printer, unsigned OpNo,
68 const std::string &Modifier,
69 OpType op = isMachineInstrOperand)
70 : OperandType(op), Str(Printer), MIOpNo(OpNo),
71 MiModifier(Modifier) {}
73 bool operator!=(const AsmWriterOperand &Other) const {
74 if (OperandType != Other.OperandType || Str != Other.Str) return true;
75 if (OperandType == isMachineInstrOperand)
76 return MIOpNo != Other.MIOpNo || MiModifier != Other.MiModifier;
79 bool operator==(const AsmWriterOperand &Other) const {
80 return !operator!=(Other);
83 /// getCode - Return the code that prints this operand.
84 std::string getCode() const;
91 std::vector<AsmWriterOperand> Operands;
92 const CodeGenInstruction *CGI;
94 AsmWriterInst(const CodeGenInstruction &CGI, Record *AsmWriter);
96 /// MatchesAllButOneOp - If this instruction is exactly identical to the
97 /// specified instruction except for one differing operand, return the
98 /// differing operand number. Otherwise return ~0.
99 unsigned MatchesAllButOneOp(const AsmWriterInst &Other) const;
102 void AddLiteralString(const std::string &Str) {
103 // If the last operand was already a literal text string, append this to
104 // it, otherwise add a new operand.
105 if (!Operands.empty() &&
106 Operands.back().OperandType == AsmWriterOperand::isLiteralTextOperand)
107 Operands.back().Str.append(Str);
109 Operands.push_back(AsmWriterOperand(Str));
115 std::string AsmWriterOperand::getCode() const {
116 if (OperandType == isLiteralTextOperand) {
118 return "O << '" + Str + "'; ";
119 return "O << \"" + Str + "\"; ";
122 if (OperandType == isLiteralStatementOperand)
125 std::string Result = Str + "(MI";
127 Result += ", " + utostr(MIOpNo);
128 if (!MiModifier.empty())
129 Result += ", \"" + MiModifier + '"';
130 return Result + "); ";
134 /// ParseAsmString - Parse the specified Instruction's AsmString into this
137 AsmWriterInst::AsmWriterInst(const CodeGenInstruction &CGI, Record *AsmWriter) {
140 unsigned Variant = AsmWriter->getValueAsInt("Variant");
141 int FirstOperandColumn = AsmWriter->getValueAsInt("FirstOperandColumn");
142 int OperandSpacing = AsmWriter->getValueAsInt("OperandSpacing");
144 unsigned CurVariant = ~0U; // ~0 if we are outside a {.|.|.} region, other #.
146 // This is the number of tabs we've seen if we're doing columnar layout.
147 unsigned CurColumn = 0;
150 // NOTE: Any extensions to this code need to be mirrored in the
151 // AsmPrinter::printInlineAsm code that executes as compile time (assuming
152 // that inline asm strings should also get the new feature)!
153 const std::string &AsmString = CGI.AsmString;
154 std::string::size_type LastEmitted = 0;
155 while (LastEmitted != AsmString.size()) {
156 std::string::size_type DollarPos =
157 AsmString.find_first_of("${|}\\", LastEmitted);
158 if (DollarPos == std::string::npos) DollarPos = AsmString.size();
160 // Emit a constant string fragment.
162 if (DollarPos != LastEmitted) {
163 if (CurVariant == Variant || CurVariant == ~0U) {
164 for (; LastEmitted != DollarPos; ++LastEmitted)
165 switch (AsmString[LastEmitted]) {
167 AddLiteralString("\\n");
170 // If the asm writer is not using a columnar layout, \t is not
172 if (FirstOperandColumn == -1 || OperandSpacing == -1) {
173 AddLiteralString("\\t");
175 // We recognize a tab as an operand delimeter.
176 unsigned DestColumn = FirstOperandColumn +
177 CurColumn++ * OperandSpacing;
179 AsmWriterOperand("O.PadToColumn(" +
180 utostr(DestColumn) + ");\n",
181 AsmWriterOperand::isLiteralStatementOperand));
185 AddLiteralString("\\\"");
188 AddLiteralString("\\\\");
191 AddLiteralString(std::string(1, AsmString[LastEmitted]));
195 LastEmitted = DollarPos;
197 } else if (AsmString[DollarPos] == '\\') {
198 if (DollarPos+1 != AsmString.size() &&
199 (CurVariant == Variant || CurVariant == ~0U)) {
200 if (AsmString[DollarPos+1] == 'n') {
201 AddLiteralString("\\n");
202 } else if (AsmString[DollarPos+1] == 't') {
203 // If the asm writer is not using a columnar layout, \t is not
205 if (FirstOperandColumn == -1 || OperandSpacing == -1) {
206 AddLiteralString("\\t");
210 // We recognize a tab as an operand delimeter.
211 unsigned DestColumn = FirstOperandColumn +
212 CurColumn++ * OperandSpacing;
214 AsmWriterOperand("O.PadToColumn(" + utostr(DestColumn) + ");\n",
215 AsmWriterOperand::isLiteralStatementOperand));
217 } else if (std::string("${|}\\").find(AsmString[DollarPos+1])
218 != std::string::npos) {
219 AddLiteralString(std::string(1, AsmString[DollarPos+1]));
221 throw "Non-supported escaped character found in instruction '" +
222 CGI.TheDef->getName() + "'!";
224 LastEmitted = DollarPos+2;
227 } else if (AsmString[DollarPos] == '{') {
228 if (CurVariant != ~0U)
229 throw "Nested variants found for instruction '" +
230 CGI.TheDef->getName() + "'!";
231 LastEmitted = DollarPos+1;
232 CurVariant = 0; // We are now inside of the variant!
233 } else if (AsmString[DollarPos] == '|') {
234 if (CurVariant == ~0U)
235 throw "'|' character found outside of a variant in instruction '"
236 + CGI.TheDef->getName() + "'!";
239 } else if (AsmString[DollarPos] == '}') {
240 if (CurVariant == ~0U)
241 throw "'}' character found outside of a variant in instruction '"
242 + CGI.TheDef->getName() + "'!";
245 } else if (DollarPos+1 != AsmString.size() &&
246 AsmString[DollarPos+1] == '$') {
247 if (CurVariant == Variant || CurVariant == ~0U) {
248 AddLiteralString("$"); // "$$" -> $
250 LastEmitted = DollarPos+2;
252 // Get the name of the variable.
253 std::string::size_type VarEnd = DollarPos+1;
255 // handle ${foo}bar as $foo by detecting whether the character following
256 // the dollar sign is a curly brace. If so, advance VarEnd and DollarPos
257 // so the variable name does not contain the leading curly brace.
258 bool hasCurlyBraces = false;
259 if (VarEnd < AsmString.size() && '{' == AsmString[VarEnd]) {
260 hasCurlyBraces = true;
265 while (VarEnd < AsmString.size() && isIdentChar(AsmString[VarEnd]))
267 std::string VarName(AsmString.begin()+DollarPos+1,
268 AsmString.begin()+VarEnd);
270 // Modifier - Support ${foo:modifier} syntax, where "modifier" is passed
271 // into printOperand. Also support ${:feature}, which is passed into
273 std::string Modifier;
275 // In order to avoid starting the next string at the terminating curly
276 // brace, advance the end position past it if we found an opening curly
278 if (hasCurlyBraces) {
279 if (VarEnd >= AsmString.size())
280 throw "Reached end of string before terminating curly brace in '"
281 + CGI.TheDef->getName() + "'";
283 // Look for a modifier string.
284 if (AsmString[VarEnd] == ':') {
286 if (VarEnd >= AsmString.size())
287 throw "Reached end of string before terminating curly brace in '"
288 + CGI.TheDef->getName() + "'";
290 unsigned ModifierStart = VarEnd;
291 while (VarEnd < AsmString.size() && isIdentChar(AsmString[VarEnd]))
293 Modifier = std::string(AsmString.begin()+ModifierStart,
294 AsmString.begin()+VarEnd);
295 if (Modifier.empty())
296 throw "Bad operand modifier name in '"+ CGI.TheDef->getName() + "'";
299 if (AsmString[VarEnd] != '}')
300 throw "Variable name beginning with '{' did not end with '}' in '"
301 + CGI.TheDef->getName() + "'";
304 if (VarName.empty() && Modifier.empty())
305 throw "Stray '$' in '" + CGI.TheDef->getName() +
306 "' asm string, maybe you want $$?";
308 if (VarName.empty()) {
309 // Just a modifier, pass this into PrintSpecial.
310 Operands.push_back(AsmWriterOperand("PrintSpecial", ~0U, Modifier));
312 // Otherwise, normal operand.
313 unsigned OpNo = CGI.getOperandNamed(VarName);
314 CodeGenInstruction::OperandInfo OpInfo = CGI.OperandList[OpNo];
316 if (CurVariant == Variant || CurVariant == ~0U) {
317 unsigned MIOp = OpInfo.MIOperandNo;
318 Operands.push_back(AsmWriterOperand(OpInfo.PrinterMethodName, MIOp,
322 LastEmitted = VarEnd;
327 AsmWriterOperand("EmitComments(*MI);\n",
328 AsmWriterOperand::isLiteralStatementOperand));
329 AddLiteralString("\\n");
332 /// MatchesAllButOneOp - If this instruction is exactly identical to the
333 /// specified instruction except for one differing operand, return the differing
334 /// operand number. If more than one operand mismatches, return ~1, otherwise
335 /// if the instructions are identical return ~0.
336 unsigned AsmWriterInst::MatchesAllButOneOp(const AsmWriterInst &Other)const{
337 if (Operands.size() != Other.Operands.size()) return ~1;
339 unsigned MismatchOperand = ~0U;
340 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
341 if (Operands[i] != Other.Operands[i]) {
342 if (MismatchOperand != ~0U) // Already have one mismatch?
348 return MismatchOperand;
351 static void PrintCases(std::vector<std::pair<std::string,
352 AsmWriterOperand> > &OpsToPrint, raw_ostream &O) {
353 O << " case " << OpsToPrint.back().first << ": ";
354 AsmWriterOperand TheOp = OpsToPrint.back().second;
355 OpsToPrint.pop_back();
357 // Check to see if any other operands are identical in this list, and if so,
358 // emit a case label for them.
359 for (unsigned i = OpsToPrint.size(); i != 0; --i)
360 if (OpsToPrint[i-1].second == TheOp) {
361 O << "\n case " << OpsToPrint[i-1].first << ": ";
362 OpsToPrint.erase(OpsToPrint.begin()+i-1);
365 // Finally, emit the code.
366 O << TheOp.getCode();
371 /// EmitInstructions - Emit the last instruction in the vector and any other
372 /// instructions that are suitably similar to it.
373 static void EmitInstructions(std::vector<AsmWriterInst> &Insts,
375 AsmWriterInst FirstInst = Insts.back();
378 std::vector<AsmWriterInst> SimilarInsts;
379 unsigned DifferingOperand = ~0;
380 for (unsigned i = Insts.size(); i != 0; --i) {
381 unsigned DiffOp = Insts[i-1].MatchesAllButOneOp(FirstInst);
383 if (DifferingOperand == ~0U) // First match!
384 DifferingOperand = DiffOp;
386 // If this differs in the same operand as the rest of the instructions in
387 // this class, move it to the SimilarInsts list.
388 if (DifferingOperand == DiffOp || DiffOp == ~0U) {
389 SimilarInsts.push_back(Insts[i-1]);
390 Insts.erase(Insts.begin()+i-1);
395 O << " case " << FirstInst.CGI->Namespace << "::"
396 << FirstInst.CGI->TheDef->getName() << ":\n";
397 for (unsigned i = 0, e = SimilarInsts.size(); i != e; ++i)
398 O << " case " << SimilarInsts[i].CGI->Namespace << "::"
399 << SimilarInsts[i].CGI->TheDef->getName() << ":\n";
400 for (unsigned i = 0, e = FirstInst.Operands.size(); i != e; ++i) {
401 if (i != DifferingOperand) {
402 // If the operand is the same for all instructions, just print it.
403 O << " " << FirstInst.Operands[i].getCode();
405 // If this is the operand that varies between all of the instructions,
406 // emit a switch for just this operand now.
407 O << " switch (MI->getOpcode()) {\n";
408 std::vector<std::pair<std::string, AsmWriterOperand> > OpsToPrint;
409 OpsToPrint.push_back(std::make_pair(FirstInst.CGI->Namespace + "::" +
410 FirstInst.CGI->TheDef->getName(),
411 FirstInst.Operands[i]));
413 for (unsigned si = 0, e = SimilarInsts.size(); si != e; ++si) {
414 AsmWriterInst &AWI = SimilarInsts[si];
415 OpsToPrint.push_back(std::make_pair(AWI.CGI->Namespace+"::"+
416 AWI.CGI->TheDef->getName(),
419 std::reverse(OpsToPrint.begin(), OpsToPrint.end());
420 while (!OpsToPrint.empty())
421 PrintCases(OpsToPrint, O);
429 void AsmWriterEmitter::
430 FindUniqueOperandCommands(std::vector<std::string> &UniqueOperandCommands,
431 std::vector<unsigned> &InstIdxs,
432 std::vector<unsigned> &InstOpsUsed) const {
433 InstIdxs.assign(NumberedInstructions.size(), ~0U);
435 // This vector parallels UniqueOperandCommands, keeping track of which
436 // instructions each case are used for. It is a comma separated string of
438 std::vector<std::string> InstrsForCase;
439 InstrsForCase.resize(UniqueOperandCommands.size());
440 InstOpsUsed.assign(UniqueOperandCommands.size(), 0);
442 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
443 const AsmWriterInst *Inst = getAsmWriterInstByID(i);
444 if (Inst == 0) continue; // PHI, INLINEASM, DBG_LABEL, etc.
447 if (Inst->Operands.empty())
448 continue; // Instruction already done.
450 Command = " " + Inst->Operands[0].getCode() + "\n";
452 // If this is the last operand, emit a return.
453 if (Inst->Operands.size() == 1)
454 Command += " return;\n";
456 // Check to see if we already have 'Command' in UniqueOperandCommands.
458 bool FoundIt = false;
459 for (unsigned idx = 0, e = UniqueOperandCommands.size(); idx != e; ++idx)
460 if (UniqueOperandCommands[idx] == Command) {
462 InstrsForCase[idx] += ", ";
463 InstrsForCase[idx] += Inst->CGI->TheDef->getName();
468 InstIdxs[i] = UniqueOperandCommands.size();
469 UniqueOperandCommands.push_back(Command);
470 InstrsForCase.push_back(Inst->CGI->TheDef->getName());
472 // This command matches one operand so far.
473 InstOpsUsed.push_back(1);
477 // For each entry of UniqueOperandCommands, there is a set of instructions
478 // that uses it. If the next command of all instructions in the set are
479 // identical, fold it into the command.
480 for (unsigned CommandIdx = 0, e = UniqueOperandCommands.size();
481 CommandIdx != e; ++CommandIdx) {
483 for (unsigned Op = 1; ; ++Op) {
484 // Scan for the first instruction in the set.
485 std::vector<unsigned>::iterator NIT =
486 std::find(InstIdxs.begin(), InstIdxs.end(), CommandIdx);
487 if (NIT == InstIdxs.end()) break; // No commonality.
489 // If this instruction has no more operands, we isn't anything to merge
490 // into this command.
491 const AsmWriterInst *FirstInst =
492 getAsmWriterInstByID(NIT-InstIdxs.begin());
493 if (!FirstInst || FirstInst->Operands.size() == Op)
496 // Otherwise, scan to see if all of the other instructions in this command
497 // set share the operand.
499 // Keep track of the maximum, number of operands or any
500 // instruction we see in the group.
501 size_t MaxSize = FirstInst->Operands.size();
503 for (NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx);
504 NIT != InstIdxs.end();
505 NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx)) {
506 // Okay, found another instruction in this command set. If the operand
507 // matches, we're ok, otherwise bail out.
508 const AsmWriterInst *OtherInst =
509 getAsmWriterInstByID(NIT-InstIdxs.begin());
512 OtherInst->Operands.size() > FirstInst->Operands.size())
513 MaxSize = std::max(MaxSize, OtherInst->Operands.size());
515 if (!OtherInst || OtherInst->Operands.size() == Op ||
516 OtherInst->Operands[Op] != FirstInst->Operands[Op]) {
523 // Okay, everything in this command set has the same next operand. Add it
524 // to UniqueOperandCommands and remember that it was consumed.
525 std::string Command = " " + FirstInst->Operands[Op].getCode() + "\n";
527 // If this is the last operand, emit a return after the code.
528 if (FirstInst->Operands.size() == Op+1 &&
529 // Don't early-out too soon. Other instructions in this
530 // group may have more operands.
531 FirstInst->Operands.size() == MaxSize) {
532 Command += " return;\n";
535 UniqueOperandCommands[CommandIdx] += Command;
536 InstOpsUsed[CommandIdx]++;
540 // Prepend some of the instructions each case is used for onto the case val.
541 for (unsigned i = 0, e = InstrsForCase.size(); i != e; ++i) {
542 std::string Instrs = InstrsForCase[i];
543 if (Instrs.size() > 70) {
544 Instrs.erase(Instrs.begin()+70, Instrs.end());
549 UniqueOperandCommands[i] = " // " + Instrs + "\n" +
550 UniqueOperandCommands[i];
556 void AsmWriterEmitter::run(raw_ostream &O) {
557 EmitSourceFileHeader("Assembly Writer Source Fragment", O);
559 CodeGenTarget Target;
560 Record *AsmWriter = Target.getAsmWriter();
561 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
564 "/// printInstruction - This method is automatically generated by tablegen\n"
565 "/// from the instruction set description. This method returns true if the\n"
566 "/// machine instruction was sufficiently described to print it, otherwise\n"
567 "/// it returns false.\n"
568 "void " << Target.getName() << ClassName
569 << "::printInstruction(const MachineInstr *MI) {\n";
571 std::vector<AsmWriterInst> Instructions;
573 for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
574 E = Target.inst_end(); I != E; ++I)
575 if (!I->second.AsmString.empty())
576 Instructions.push_back(AsmWriterInst(I->second, AsmWriter));
578 // Get the instruction numbering.
579 Target.getInstructionsByEnumValue(NumberedInstructions);
581 // Compute the CodeGenInstruction -> AsmWriterInst mapping. Note that not
582 // all machine instructions are necessarily being printed, so there may be
583 // target instructions not in this map.
584 for (unsigned i = 0, e = Instructions.size(); i != e; ++i)
585 CGIAWIMap.insert(std::make_pair(Instructions[i].CGI, &Instructions[i]));
587 // Build an aggregate string, and build a table of offsets into it.
588 std::map<std::string, unsigned> StringOffset;
589 std::string AggregateString;
590 AggregateString.push_back(0); // "\0"
591 AggregateString.push_back(0); // "\0"
593 /// OpcodeInfo - This encodes the index of the string to use for the first
594 /// chunk of the output as well as indices used for operand printing.
595 std::vector<unsigned> OpcodeInfo;
597 unsigned MaxStringIdx = 0;
598 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
599 AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions[i]];
602 // Something not handled by the asmwriter printer.
604 } else if (AWI->Operands[0].OperandType !=
605 AsmWriterOperand::isLiteralTextOperand ||
606 AWI->Operands[0].Str.empty()) {
607 // Something handled by the asmwriter printer, but with no leading string.
610 unsigned &Entry = StringOffset[AWI->Operands[0].Str];
612 // Add the string to the aggregate if this is the first time found.
613 MaxStringIdx = Entry = AggregateString.size();
614 std::string Str = AWI->Operands[0].Str;
616 AggregateString += Str;
617 AggregateString += '\0';
621 // Nuke the string from the operand list. It is now handled!
622 AWI->Operands.erase(AWI->Operands.begin());
624 OpcodeInfo.push_back(Idx);
627 // Figure out how many bits we used for the string index.
628 unsigned AsmStrBits = Log2_32_Ceil(MaxStringIdx+1);
630 // To reduce code size, we compactify common instructions into a few bits
631 // in the opcode-indexed table.
632 unsigned BitsLeft = 32-AsmStrBits;
634 std::vector<std::vector<std::string> > TableDrivenOperandPrinters;
638 std::vector<std::string> UniqueOperandCommands;
640 // For the first operand check, add a default value for instructions with
641 // just opcode strings to use.
643 UniqueOperandCommands.push_back(" return;\n");
647 std::vector<unsigned> InstIdxs;
648 std::vector<unsigned> NumInstOpsHandled;
649 FindUniqueOperandCommands(UniqueOperandCommands, InstIdxs,
652 // If we ran out of operands to print, we're done.
653 if (UniqueOperandCommands.empty()) break;
655 // Compute the number of bits we need to represent these cases, this is
656 // ceil(log2(numentries)).
657 unsigned NumBits = Log2_32_Ceil(UniqueOperandCommands.size());
659 // If we don't have enough bits for this operand, don't include it.
660 if (NumBits > BitsLeft) {
661 DOUT << "Not enough bits to densely encode " << NumBits
666 // Otherwise, we can include this in the initial lookup table. Add it in.
668 for (unsigned i = 0, e = InstIdxs.size(); i != e; ++i)
669 if (InstIdxs[i] != ~0U)
670 OpcodeInfo[i] |= InstIdxs[i] << (BitsLeft+AsmStrBits);
672 // Remove the info about this operand.
673 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
674 if (AsmWriterInst *Inst = getAsmWriterInstByID(i))
675 if (!Inst->Operands.empty()) {
676 unsigned NumOps = NumInstOpsHandled[InstIdxs[i]];
677 assert(NumOps <= Inst->Operands.size() &&
678 "Can't remove this many ops!");
679 Inst->Operands.erase(Inst->Operands.begin(),
680 Inst->Operands.begin()+NumOps);
684 // Remember the handlers for this set of operands.
685 TableDrivenOperandPrinters.push_back(UniqueOperandCommands);
690 O<<" static const unsigned OpInfo[] = {\n";
691 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
692 O << " " << OpcodeInfo[i] << "U,\t// "
693 << NumberedInstructions[i]->TheDef->getName() << "\n";
695 // Add a dummy entry so the array init doesn't end with a comma.
699 // Emit the string itself.
700 O << " const char *AsmStrs = \n \"";
701 unsigned CharsPrinted = 0;
702 EscapeString(AggregateString);
703 for (unsigned i = 0, e = AggregateString.size(); i != e; ++i) {
704 if (CharsPrinted > 70) {
708 O << AggregateString[i];
711 // Print escape sequences all together.
712 if (AggregateString[i] == '\\') {
713 assert(i+1 < AggregateString.size() && "Incomplete escape sequence!");
714 if (isdigit(AggregateString[i+1])) {
715 assert(isdigit(AggregateString[i+2]) && isdigit(AggregateString[i+3]) &&
716 "Expected 3 digit octal escape!");
717 O << AggregateString[++i];
718 O << AggregateString[++i];
719 O << AggregateString[++i];
722 O << AggregateString[++i];
729 O << " processDebugLoc(MI->getDebugLoc());\n\n";
731 O << "\n#ifndef NO_ASM_WRITER_BOILERPLATE\n";
733 O << " if (MI->getOpcode() == TargetInstrInfo::INLINEASM) {\n"
734 << " O << \"\\t\";\n"
735 << " printInlineAsm(MI);\n"
737 << " } else if (MI->isLabel()) {\n"
738 << " printLabel(MI);\n"
740 << " } else if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {\n"
741 << " printImplicitDef(MI);\n"
747 O << " O << \"\\t\";\n\n";
749 O << " // Emit the opcode for the instruction.\n"
750 << " unsigned Bits = OpInfo[MI->getOpcode()];\n"
751 << " assert(Bits != 0 && \"Cannot print this instruction.\");\n"
752 << " O << AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << ");\n\n";
754 // Output the table driven operand information.
755 BitsLeft = 32-AsmStrBits;
756 for (unsigned i = 0, e = TableDrivenOperandPrinters.size(); i != e; ++i) {
757 std::vector<std::string> &Commands = TableDrivenOperandPrinters[i];
759 // Compute the number of bits we need to represent these cases, this is
760 // ceil(log2(numentries)).
761 unsigned NumBits = Log2_32_Ceil(Commands.size());
762 assert(NumBits <= BitsLeft && "consistency error");
764 // Emit code to extract this field from Bits.
767 O << "\n // Fragment " << i << " encoded into " << NumBits
768 << " bits for " << Commands.size() << " unique commands.\n";
770 if (Commands.size() == 2) {
771 // Emit two possibilitys with if/else.
772 O << " if ((Bits >> " << (BitsLeft+AsmStrBits) << ") & "
773 << ((1 << NumBits)-1) << ") {\n"
779 O << " switch ((Bits >> " << (BitsLeft+AsmStrBits) << ") & "
780 << ((1 << NumBits)-1) << ") {\n"
781 << " default: // unreachable.\n";
783 // Print out all the cases.
784 for (unsigned i = 0, e = Commands.size(); i != e; ++i) {
785 O << " case " << i << ":\n";
793 // Okay, delete instructions with no operand info left.
794 for (unsigned i = 0, e = Instructions.size(); i != e; ++i) {
795 // Entire instruction has been emitted?
796 AsmWriterInst &Inst = Instructions[i];
797 if (Inst.Operands.empty()) {
798 Instructions.erase(Instructions.begin()+i);
804 // Because this is a vector, we want to emit from the end. Reverse all of the
805 // elements in the vector.
806 std::reverse(Instructions.begin(), Instructions.end());
808 if (!Instructions.empty()) {
809 // Find the opcode # of inline asm.
810 O << " switch (MI->getOpcode()) {\n";
811 while (!Instructions.empty())
812 EmitInstructions(Instructions, O);