1 //===- AsmWriterEmitter.cpp - Generate an assembly writer -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is emits an assembly printer for the current target.
11 // Note that this is currently fairly skeletal, but will grow over time.
13 //===----------------------------------------------------------------------===//
15 #include "AsmWriterEmitter.h"
16 #include "AsmWriterInst.h"
17 #include "CodeGenTarget.h"
18 #include "StringToOffsetTable.h"
19 #include "SequenceToOffsetTable.h"
20 #include "llvm/ADT/Twine.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/MathExtras.h"
23 #include "llvm/TableGen/Error.h"
24 #include "llvm/TableGen/Record.h"
28 static void PrintCases(std::vector<std::pair<std::string,
29 AsmWriterOperand> > &OpsToPrint, raw_ostream &O) {
30 O << " case " << OpsToPrint.back().first << ": ";
31 AsmWriterOperand TheOp = OpsToPrint.back().second;
32 OpsToPrint.pop_back();
34 // Check to see if any other operands are identical in this list, and if so,
35 // emit a case label for them.
36 for (unsigned i = OpsToPrint.size(); i != 0; --i)
37 if (OpsToPrint[i-1].second == TheOp) {
38 O << "\n case " << OpsToPrint[i-1].first << ": ";
39 OpsToPrint.erase(OpsToPrint.begin()+i-1);
42 // Finally, emit the code.
48 /// EmitInstructions - Emit the last instruction in the vector and any other
49 /// instructions that are suitably similar to it.
50 static void EmitInstructions(std::vector<AsmWriterInst> &Insts,
52 AsmWriterInst FirstInst = Insts.back();
55 std::vector<AsmWriterInst> SimilarInsts;
56 unsigned DifferingOperand = ~0;
57 for (unsigned i = Insts.size(); i != 0; --i) {
58 unsigned DiffOp = Insts[i-1].MatchesAllButOneOp(FirstInst);
60 if (DifferingOperand == ~0U) // First match!
61 DifferingOperand = DiffOp;
63 // If this differs in the same operand as the rest of the instructions in
64 // this class, move it to the SimilarInsts list.
65 if (DifferingOperand == DiffOp || DiffOp == ~0U) {
66 SimilarInsts.push_back(Insts[i-1]);
67 Insts.erase(Insts.begin()+i-1);
72 O << " case " << FirstInst.CGI->Namespace << "::"
73 << FirstInst.CGI->TheDef->getName() << ":\n";
74 for (unsigned i = 0, e = SimilarInsts.size(); i != e; ++i)
75 O << " case " << SimilarInsts[i].CGI->Namespace << "::"
76 << SimilarInsts[i].CGI->TheDef->getName() << ":\n";
77 for (unsigned i = 0, e = FirstInst.Operands.size(); i != e; ++i) {
78 if (i != DifferingOperand) {
79 // If the operand is the same for all instructions, just print it.
80 O << " " << FirstInst.Operands[i].getCode();
82 // If this is the operand that varies between all of the instructions,
83 // emit a switch for just this operand now.
84 O << " switch (MI->getOpcode()) {\n";
85 std::vector<std::pair<std::string, AsmWriterOperand> > OpsToPrint;
86 OpsToPrint.push_back(std::make_pair(FirstInst.CGI->Namespace + "::" +
87 FirstInst.CGI->TheDef->getName(),
88 FirstInst.Operands[i]));
90 for (unsigned si = 0, e = SimilarInsts.size(); si != e; ++si) {
91 AsmWriterInst &AWI = SimilarInsts[si];
92 OpsToPrint.push_back(std::make_pair(AWI.CGI->Namespace+"::"+
93 AWI.CGI->TheDef->getName(),
96 std::reverse(OpsToPrint.begin(), OpsToPrint.end());
97 while (!OpsToPrint.empty())
98 PrintCases(OpsToPrint, O);
106 void AsmWriterEmitter::
107 FindUniqueOperandCommands(std::vector<std::string> &UniqueOperandCommands,
108 std::vector<unsigned> &InstIdxs,
109 std::vector<unsigned> &InstOpsUsed) const {
110 InstIdxs.assign(NumberedInstructions.size(), ~0U);
112 // This vector parallels UniqueOperandCommands, keeping track of which
113 // instructions each case are used for. It is a comma separated string of
115 std::vector<std::string> InstrsForCase;
116 InstrsForCase.resize(UniqueOperandCommands.size());
117 InstOpsUsed.assign(UniqueOperandCommands.size(), 0);
119 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
120 const AsmWriterInst *Inst = getAsmWriterInstByID(i);
121 if (Inst == 0) continue; // PHI, INLINEASM, PROLOG_LABEL, etc.
124 if (Inst->Operands.empty())
125 continue; // Instruction already done.
127 Command = " " + Inst->Operands[0].getCode() + "\n";
129 // Check to see if we already have 'Command' in UniqueOperandCommands.
131 bool FoundIt = false;
132 for (unsigned idx = 0, e = UniqueOperandCommands.size(); idx != e; ++idx)
133 if (UniqueOperandCommands[idx] == Command) {
135 InstrsForCase[idx] += ", ";
136 InstrsForCase[idx] += Inst->CGI->TheDef->getName();
141 InstIdxs[i] = UniqueOperandCommands.size();
142 UniqueOperandCommands.push_back(Command);
143 InstrsForCase.push_back(Inst->CGI->TheDef->getName());
145 // This command matches one operand so far.
146 InstOpsUsed.push_back(1);
150 // For each entry of UniqueOperandCommands, there is a set of instructions
151 // that uses it. If the next command of all instructions in the set are
152 // identical, fold it into the command.
153 for (unsigned CommandIdx = 0, e = UniqueOperandCommands.size();
154 CommandIdx != e; ++CommandIdx) {
156 for (unsigned Op = 1; ; ++Op) {
157 // Scan for the first instruction in the set.
158 std::vector<unsigned>::iterator NIT =
159 std::find(InstIdxs.begin(), InstIdxs.end(), CommandIdx);
160 if (NIT == InstIdxs.end()) break; // No commonality.
162 // If this instruction has no more operands, we isn't anything to merge
163 // into this command.
164 const AsmWriterInst *FirstInst =
165 getAsmWriterInstByID(NIT-InstIdxs.begin());
166 if (!FirstInst || FirstInst->Operands.size() == Op)
169 // Otherwise, scan to see if all of the other instructions in this command
170 // set share the operand.
172 // Keep track of the maximum, number of operands or any
173 // instruction we see in the group.
174 size_t MaxSize = FirstInst->Operands.size();
176 for (NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx);
177 NIT != InstIdxs.end();
178 NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx)) {
179 // Okay, found another instruction in this command set. If the operand
180 // matches, we're ok, otherwise bail out.
181 const AsmWriterInst *OtherInst =
182 getAsmWriterInstByID(NIT-InstIdxs.begin());
185 OtherInst->Operands.size() > FirstInst->Operands.size())
186 MaxSize = std::max(MaxSize, OtherInst->Operands.size());
188 if (!OtherInst || OtherInst->Operands.size() == Op ||
189 OtherInst->Operands[Op] != FirstInst->Operands[Op]) {
196 // Okay, everything in this command set has the same next operand. Add it
197 // to UniqueOperandCommands and remember that it was consumed.
198 std::string Command = " " + FirstInst->Operands[Op].getCode() + "\n";
200 UniqueOperandCommands[CommandIdx] += Command;
201 InstOpsUsed[CommandIdx]++;
205 // Prepend some of the instructions each case is used for onto the case val.
206 for (unsigned i = 0, e = InstrsForCase.size(); i != e; ++i) {
207 std::string Instrs = InstrsForCase[i];
208 if (Instrs.size() > 70) {
209 Instrs.erase(Instrs.begin()+70, Instrs.end());
214 UniqueOperandCommands[i] = " // " + Instrs + "\n" +
215 UniqueOperandCommands[i];
220 static void UnescapeString(std::string &Str) {
221 for (unsigned i = 0; i != Str.size(); ++i) {
222 if (Str[i] == '\\' && i != Str.size()-1) {
224 default: continue; // Don't execute the code after the switch.
225 case 'a': Str[i] = '\a'; break;
226 case 'b': Str[i] = '\b'; break;
227 case 'e': Str[i] = 27; break;
228 case 'f': Str[i] = '\f'; break;
229 case 'n': Str[i] = '\n'; break;
230 case 'r': Str[i] = '\r'; break;
231 case 't': Str[i] = '\t'; break;
232 case 'v': Str[i] = '\v'; break;
233 case '"': Str[i] = '\"'; break;
234 case '\'': Str[i] = '\''; break;
235 case '\\': Str[i] = '\\'; break;
237 // Nuke the second character.
238 Str.erase(Str.begin()+i+1);
243 /// EmitPrintInstruction - Generate the code for the "printInstruction" method
245 void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) {
246 CodeGenTarget Target(Records);
247 Record *AsmWriter = Target.getAsmWriter();
248 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
249 bool isMC = AsmWriter->getValueAsBit("isMCAsmWriter");
250 const char *MachineInstrClassName = isMC ? "MCInst" : "MachineInstr";
253 "/// printInstruction - This method is automatically generated by tablegen\n"
254 "/// from the instruction set description.\n"
255 "void " << Target.getName() << ClassName
256 << "::printInstruction(const " << MachineInstrClassName
257 << " *MI, raw_ostream &O) {\n";
259 std::vector<AsmWriterInst> Instructions;
261 for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
262 E = Target.inst_end(); I != E; ++I)
263 if (!(*I)->AsmString.empty() &&
264 (*I)->TheDef->getName() != "PHI")
265 Instructions.push_back(
267 AsmWriter->getValueAsInt("Variant"),
268 AsmWriter->getValueAsInt("FirstOperandColumn"),
269 AsmWriter->getValueAsInt("OperandSpacing")));
271 // Get the instruction numbering.
272 NumberedInstructions = Target.getInstructionsByEnumValue();
274 // Compute the CodeGenInstruction -> AsmWriterInst mapping. Note that not
275 // all machine instructions are necessarily being printed, so there may be
276 // target instructions not in this map.
277 for (unsigned i = 0, e = Instructions.size(); i != e; ++i)
278 CGIAWIMap.insert(std::make_pair(Instructions[i].CGI, &Instructions[i]));
280 // Build an aggregate string, and build a table of offsets into it.
281 SequenceToOffsetTable<std::string> StringTable;
283 /// OpcodeInfo - This encodes the index of the string to use for the first
284 /// chunk of the output as well as indices used for operand printing.
285 std::vector<unsigned> OpcodeInfo;
287 // Add all strings to the string table upfront so it can generate an optimized
289 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
290 AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions[i]];
292 AWI->Operands[0].OperandType == AsmWriterOperand::isLiteralTextOperand &&
293 !AWI->Operands[0].Str.empty()) {
294 std::string Str = AWI->Operands[0].Str;
296 StringTable.add(Str);
300 StringTable.layout();
302 unsigned MaxStringIdx = 0;
303 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
304 AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions[i]];
307 // Something not handled by the asmwriter printer.
309 } else if (AWI->Operands[0].OperandType !=
310 AsmWriterOperand::isLiteralTextOperand ||
311 AWI->Operands[0].Str.empty()) {
312 // Something handled by the asmwriter printer, but with no leading string.
313 Idx = StringTable.get("");
315 std::string Str = AWI->Operands[0].Str;
317 Idx = StringTable.get(Str);
318 MaxStringIdx = std::max(MaxStringIdx, Idx);
320 // Nuke the string from the operand list. It is now handled!
321 AWI->Operands.erase(AWI->Operands.begin());
324 // Bias offset by one since we want 0 as a sentinel.
325 OpcodeInfo.push_back(Idx+1);
328 // Figure out how many bits we used for the string index.
329 unsigned AsmStrBits = Log2_32_Ceil(MaxStringIdx+2);
331 // To reduce code size, we compactify common instructions into a few bits
332 // in the opcode-indexed table.
333 unsigned BitsLeft = 32-AsmStrBits;
335 std::vector<std::vector<std::string> > TableDrivenOperandPrinters;
338 std::vector<std::string> UniqueOperandCommands;
339 std::vector<unsigned> InstIdxs;
340 std::vector<unsigned> NumInstOpsHandled;
341 FindUniqueOperandCommands(UniqueOperandCommands, InstIdxs,
344 // If we ran out of operands to print, we're done.
345 if (UniqueOperandCommands.empty()) break;
347 // Compute the number of bits we need to represent these cases, this is
348 // ceil(log2(numentries)).
349 unsigned NumBits = Log2_32_Ceil(UniqueOperandCommands.size());
351 // If we don't have enough bits for this operand, don't include it.
352 if (NumBits > BitsLeft) {
353 DEBUG(errs() << "Not enough bits to densely encode " << NumBits
358 // Otherwise, we can include this in the initial lookup table. Add it in.
360 for (unsigned i = 0, e = InstIdxs.size(); i != e; ++i)
361 if (InstIdxs[i] != ~0U)
362 OpcodeInfo[i] |= InstIdxs[i] << (BitsLeft+AsmStrBits);
364 // Remove the info about this operand.
365 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
366 if (AsmWriterInst *Inst = getAsmWriterInstByID(i))
367 if (!Inst->Operands.empty()) {
368 unsigned NumOps = NumInstOpsHandled[InstIdxs[i]];
369 assert(NumOps <= Inst->Operands.size() &&
370 "Can't remove this many ops!");
371 Inst->Operands.erase(Inst->Operands.begin(),
372 Inst->Operands.begin()+NumOps);
376 // Remember the handlers for this set of operands.
377 TableDrivenOperandPrinters.push_back(UniqueOperandCommands);
382 O<<" static const unsigned OpInfo[] = {\n";
383 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
384 O << " " << OpcodeInfo[i] << "U,\t// "
385 << NumberedInstructions[i]->TheDef->getName() << "\n";
387 // Add a dummy entry so the array init doesn't end with a comma.
391 // Emit the string itself.
392 O << " const char AsmStrs[] = {\n";
393 StringTable.emit(O, printChar);
396 O << " O << \"\\t\";\n\n";
398 O << " // Emit the opcode for the instruction.\n"
399 << " unsigned Bits = OpInfo[MI->getOpcode()];\n"
400 << " assert(Bits != 0 && \"Cannot print this instruction.\");\n"
401 << " O << AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << ")-1;\n\n";
403 // Output the table driven operand information.
404 BitsLeft = 32-AsmStrBits;
405 for (unsigned i = 0, e = TableDrivenOperandPrinters.size(); i != e; ++i) {
406 std::vector<std::string> &Commands = TableDrivenOperandPrinters[i];
408 // Compute the number of bits we need to represent these cases, this is
409 // ceil(log2(numentries)).
410 unsigned NumBits = Log2_32_Ceil(Commands.size());
411 assert(NumBits <= BitsLeft && "consistency error");
413 // Emit code to extract this field from Bits.
416 O << "\n // Fragment " << i << " encoded into " << NumBits
417 << " bits for " << Commands.size() << " unique commands.\n";
419 if (Commands.size() == 2) {
420 // Emit two possibilitys with if/else.
421 O << " if ((Bits >> " << (BitsLeft+AsmStrBits) << ") & "
422 << ((1 << NumBits)-1) << ") {\n"
427 } else if (Commands.size() == 1) {
428 // Emit a single possibility.
429 O << Commands[0] << "\n\n";
431 O << " switch ((Bits >> " << (BitsLeft+AsmStrBits) << ") & "
432 << ((1 << NumBits)-1) << ") {\n"
433 << " default: // unreachable.\n";
435 // Print out all the cases.
436 for (unsigned i = 0, e = Commands.size(); i != e; ++i) {
437 O << " case " << i << ":\n";
445 // Okay, delete instructions with no operand info left.
446 for (unsigned i = 0, e = Instructions.size(); i != e; ++i) {
447 // Entire instruction has been emitted?
448 AsmWriterInst &Inst = Instructions[i];
449 if (Inst.Operands.empty()) {
450 Instructions.erase(Instructions.begin()+i);
456 // Because this is a vector, we want to emit from the end. Reverse all of the
457 // elements in the vector.
458 std::reverse(Instructions.begin(), Instructions.end());
461 // Now that we've emitted all of the operand info that fit into 32 bits, emit
462 // information for those instructions that are left. This is a less dense
463 // encoding, but we expect the main 32-bit table to handle the majority of
465 if (!Instructions.empty()) {
466 // Find the opcode # of inline asm.
467 O << " switch (MI->getOpcode()) {\n";
468 while (!Instructions.empty())
469 EmitInstructions(Instructions, O);
479 emitRegisterNameString(raw_ostream &O, StringRef AltName,
480 const std::vector<CodeGenRegister*> &Registers) {
481 SequenceToOffsetTable<std::string> StringTable;
482 SmallVector<std::string, 4> AsmNames(Registers.size());
483 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
484 const CodeGenRegister &Reg = *Registers[i];
485 std::string &AsmName = AsmNames[i];
487 // "NoRegAltName" is special. We don't need to do a lookup for that,
488 // as it's just a reference to the default register name.
489 if (AltName == "" || AltName == "NoRegAltName") {
490 AsmName = Reg.TheDef->getValueAsString("AsmName");
492 AsmName = Reg.getName();
494 // Make sure the register has an alternate name for this index.
495 std::vector<Record*> AltNameList =
496 Reg.TheDef->getValueAsListOfDefs("RegAltNameIndices");
498 for (e = AltNameList.size();
499 Idx < e && (AltNameList[Idx]->getName() != AltName);
502 // If the register has an alternate name for this index, use it.
503 // Otherwise, leave it empty as an error flag.
505 std::vector<std::string> AltNames =
506 Reg.TheDef->getValueAsListOfStrings("AltNames");
507 if (AltNames.size() <= Idx)
508 throw TGError(Reg.TheDef->getLoc(),
509 (Twine("Register definition missing alt name for '") +
510 AltName + "'.").str());
511 AsmName = AltNames[Idx];
514 StringTable.add(AsmName);
517 StringTable.layout();
518 O << " static const char AsmStrs" << AltName << "[] = {\n";
519 StringTable.emit(O, printChar);
522 O << " static const unsigned RegAsmOffset" << AltName << "[] = {";
523 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
526 O << StringTable.get(AsmNames[i]) << ", ";
532 void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) {
533 CodeGenTarget Target(Records);
534 Record *AsmWriter = Target.getAsmWriter();
535 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
536 const std::vector<CodeGenRegister*> &Registers =
537 Target.getRegBank().getRegisters();
538 std::vector<Record*> AltNameIndices = Target.getRegAltNameIndices();
539 bool hasAltNames = AltNameIndices.size() > 1;
542 "\n\n/// getRegisterName - This method is automatically generated by tblgen\n"
543 "/// from the register set description. This returns the assembler name\n"
544 "/// for the specified register.\n"
545 "const char *" << Target.getName() << ClassName << "::";
547 O << "\ngetRegisterName(unsigned RegNo, unsigned AltIdx) {\n";
549 O << "getRegisterName(unsigned RegNo) {\n";
550 O << " assert(RegNo && RegNo < " << (Registers.size()+1)
551 << " && \"Invalid register number!\");\n"
555 for (unsigned i = 0, e = AltNameIndices.size(); i < e; ++i)
556 emitRegisterNameString(O, AltNameIndices[i]->getName(), Registers);
558 emitRegisterNameString(O, "", Registers);
561 O << " const unsigned *RegAsmOffset;\n"
562 << " const char *AsmStrs;\n"
563 << " switch(AltIdx) {\n"
564 << " default: llvm_unreachable(\"Invalid register alt name index!\");\n";
565 for (unsigned i = 0, e = AltNameIndices.size(); i < e; ++i) {
566 StringRef Namespace = AltNameIndices[1]->getValueAsString("Namespace");
567 StringRef AltName(AltNameIndices[i]->getName());
568 O << " case " << Namespace << "::" << AltName
570 << " AsmStrs = AsmStrs" << AltName << ";\n"
571 << " RegAsmOffset = RegAsmOffset" << AltName << ";\n"
577 O << " assert (*(AsmStrs+RegAsmOffset[RegNo-1]) &&\n"
578 << " \"Invalid alt name index for register!\");\n"
579 << " return AsmStrs+RegAsmOffset[RegNo-1];\n"
584 // IAPrinter - Holds information about an InstAlias. Two InstAliases match if
585 // they both have the same conditionals. In which case, we cannot print out the
586 // alias for that pattern.
588 std::vector<std::string> Conds;
589 std::map<StringRef, unsigned> OpMap;
591 std::string AsmString;
592 std::vector<Record*> ReqFeatures;
594 IAPrinter(std::string R, std::string AS)
595 : Result(R), AsmString(AS) {}
597 void addCond(const std::string &C) { Conds.push_back(C); }
599 void addOperand(StringRef Op, unsigned Idx) { OpMap[Op] = Idx; }
600 unsigned getOpIndex(StringRef Op) { return OpMap[Op]; }
601 bool isOpMapped(StringRef Op) { return OpMap.find(Op) != OpMap.end(); }
603 void print(raw_ostream &O) {
604 if (Conds.empty() && ReqFeatures.empty()) {
605 O.indent(6) << "return true;\n";
611 for (std::vector<std::string>::iterator
612 I = Conds.begin(), E = Conds.end(); I != E; ++I) {
613 if (I != Conds.begin()) {
622 O.indent(6) << "// " << Result << "\n";
623 O.indent(6) << "AsmString = \"" << AsmString << "\";\n";
625 for (std::map<StringRef, unsigned>::iterator
626 I = OpMap.begin(), E = OpMap.end(); I != E; ++I)
627 O.indent(6) << "OpMap.push_back(std::make_pair(\"" << I->first << "\", "
628 << I->second << "));\n";
630 O.indent(6) << "break;\n";
634 bool operator==(const IAPrinter &RHS) {
635 if (Conds.size() != RHS.Conds.size())
639 for (std::vector<std::string>::iterator
640 I = Conds.begin(), E = Conds.end(); I != E; ++I)
641 if (*I != RHS.Conds[Idx++])
647 bool operator()(const IAPrinter &RHS) {
648 if (Conds.size() < RHS.Conds.size())
652 for (std::vector<std::string>::iterator
653 I = Conds.begin(), E = Conds.end(); I != E; ++I)
654 if (*I != RHS.Conds[Idx++])
655 return *I < RHS.Conds[Idx++];
661 } // end anonymous namespace
663 static void EmitGetMapOperandNumber(raw_ostream &O) {
664 O << "static unsigned getMapOperandNumber("
665 << "const SmallVectorImpl<std::pair<StringRef, unsigned> > &OpMap,\n";
666 O << " StringRef Name) {\n";
667 O << " for (SmallVectorImpl<std::pair<StringRef, unsigned> >::"
668 << "const_iterator\n";
669 O << " I = OpMap.begin(), E = OpMap.end(); I != E; ++I)\n";
670 O << " if (I->first == Name)\n";
671 O << " return I->second;\n";
672 O << " assert(false && \"Operand not in map!\");\n";
677 static unsigned CountNumOperands(StringRef AsmString) {
679 std::pair<StringRef, StringRef> ASM = AsmString.split(' ');
681 while (!ASM.second.empty()) {
683 ASM = ASM.second.split(' ');
689 static unsigned CountResultNumOperands(StringRef AsmString) {
691 std::pair<StringRef, StringRef> ASM = AsmString.split('\t');
693 if (!ASM.second.empty()) {
694 size_t I = ASM.second.find('{');
695 StringRef Str = ASM.second;
696 if (I != StringRef::npos)
697 Str = ASM.second.substr(I, ASM.second.find('|', I));
699 ASM = Str.split(' ');
703 ASM = ASM.second.split(' ');
704 } while (!ASM.second.empty());
710 void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
711 CodeGenTarget Target(Records);
712 Record *AsmWriter = Target.getAsmWriter();
714 if (!AsmWriter->getValueAsBit("isMCAsmWriter"))
717 O << "\n#ifdef PRINT_ALIAS_INSTR\n";
718 O << "#undef PRINT_ALIAS_INSTR\n\n";
720 // Emit the method that prints the alias instruction.
721 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
723 std::vector<Record*> AllInstAliases =
724 Records.getAllDerivedDefinitions("InstAlias");
726 // Create a map from the qualified name to a list of potential matches.
727 std::map<std::string, std::vector<CodeGenInstAlias*> > AliasMap;
728 for (std::vector<Record*>::iterator
729 I = AllInstAliases.begin(), E = AllInstAliases.end(); I != E; ++I) {
730 CodeGenInstAlias *Alias = new CodeGenInstAlias(*I, Target);
731 const Record *R = *I;
732 if (!R->getValueAsBit("EmitAlias"))
733 continue; // We were told not to emit the alias, but to emit the aliasee.
734 const DagInit *DI = R->getValueAsDag("ResultInst");
735 const DefInit *Op = dynamic_cast<const DefInit*>(DI->getOperator());
736 AliasMap[getQualifiedName(Op->getDef())].push_back(Alias);
739 // A map of which conditions need to be met for each instruction operand
740 // before it can be matched to the mnemonic.
741 std::map<std::string, std::vector<IAPrinter*> > IAPrinterMap;
743 for (std::map<std::string, std::vector<CodeGenInstAlias*> >::iterator
744 I = AliasMap.begin(), E = AliasMap.end(); I != E; ++I) {
745 std::vector<CodeGenInstAlias*> &Aliases = I->second;
747 for (std::vector<CodeGenInstAlias*>::iterator
748 II = Aliases.begin(), IE = Aliases.end(); II != IE; ++II) {
749 const CodeGenInstAlias *CGA = *II;
750 unsigned LastOpNo = CGA->ResultInstOperandIndex.size();
751 unsigned NumResultOps =
752 CountResultNumOperands(CGA->ResultInst->AsmString);
754 // Don't emit the alias if it has more operands than what it's aliasing.
755 if (NumResultOps < CountNumOperands(CGA->AsmString))
758 IAPrinter *IAP = new IAPrinter(CGA->Result->getAsString(),
762 Cond = std::string("MI->getNumOperands() == ") + llvm::utostr(LastOpNo);
765 std::map<StringRef, unsigned> OpMap;
766 bool CantHandle = false;
768 for (unsigned i = 0, e = LastOpNo; i != e; ++i) {
769 const CodeGenInstAlias::ResultOperand &RO = CGA->ResultOperands[i];
772 case CodeGenInstAlias::ResultOperand::K_Record: {
773 const Record *Rec = RO.getRecord();
774 StringRef ROName = RO.getName();
777 if (Rec->isSubClassOf("RegisterOperand"))
778 Rec = Rec->getValueAsDef("RegClass");
779 if (Rec->isSubClassOf("RegisterClass")) {
780 Cond = std::string("MI->getOperand(")+llvm::utostr(i)+").isReg()";
783 if (!IAP->isOpMapped(ROName)) {
784 IAP->addOperand(ROName, i);
785 Cond = std::string("MRI.getRegClass(") + Target.getName() + "::" +
786 CGA->ResultOperands[i].getRecord()->getName() + "RegClassID)"
787 ".contains(MI->getOperand(" + llvm::utostr(i) + ").getReg())";
790 Cond = std::string("MI->getOperand(") +
791 llvm::utostr(i) + ").getReg() == MI->getOperand(" +
792 llvm::utostr(IAP->getOpIndex(ROName)) + ").getReg()";
796 assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
797 // FIXME: We may need to handle these situations.
806 case CodeGenInstAlias::ResultOperand::K_Imm:
807 Cond = std::string("MI->getOperand(") +
808 llvm::utostr(i) + ").getImm() == " +
809 llvm::utostr(CGA->ResultOperands[i].getImm());
812 case CodeGenInstAlias::ResultOperand::K_Reg:
813 // If this is zero_reg, something's playing tricks we're not
814 // equipped to handle.
815 if (!CGA->ResultOperands[i].getRegister()) {
820 Cond = std::string("MI->getOperand(") +
821 llvm::utostr(i) + ").getReg() == " + Target.getName() +
822 "::" + CGA->ResultOperands[i].getRegister()->getName();
830 if (CantHandle) continue;
831 IAPrinterMap[I->first].push_back(IAP);
836 raw_string_ostream HeaderO(Header);
838 HeaderO << "bool " << Target.getName() << ClassName
839 << "::printAliasInstr(const MCInst"
840 << " *MI, raw_ostream &OS) {\n";
843 raw_string_ostream CasesO(Cases);
845 for (std::map<std::string, std::vector<IAPrinter*> >::iterator
846 I = IAPrinterMap.begin(), E = IAPrinterMap.end(); I != E; ++I) {
847 std::vector<IAPrinter*> &IAPs = I->second;
848 std::vector<IAPrinter*> UniqueIAPs;
850 for (std::vector<IAPrinter*>::iterator
851 II = IAPs.begin(), IE = IAPs.end(); II != IE; ++II) {
852 IAPrinter *LHS = *II;
854 for (std::vector<IAPrinter*>::iterator
855 III = IAPs.begin(), IIE = IAPs.end(); III != IIE; ++III) {
856 IAPrinter *RHS = *III;
857 if (LHS != RHS && *LHS == *RHS) {
863 if (!IsDup) UniqueIAPs.push_back(LHS);
866 if (UniqueIAPs.empty()) continue;
868 CasesO.indent(2) << "case " << I->first << ":\n";
870 for (std::vector<IAPrinter*>::iterator
871 II = UniqueIAPs.begin(), IE = UniqueIAPs.end(); II != IE; ++II) {
872 IAPrinter *IAP = *II;
878 CasesO.indent(4) << "return false;\n";
881 if (CasesO.str().empty()) {
883 O << " return false;\n";
885 O << "#endif // PRINT_ALIAS_INSTR\n";
889 EmitGetMapOperandNumber(O);
892 O.indent(2) << "StringRef AsmString;\n";
893 O.indent(2) << "SmallVector<std::pair<StringRef, unsigned>, 4> OpMap;\n";
894 O.indent(2) << "switch (MI->getOpcode()) {\n";
895 O.indent(2) << "default: return false;\n";
897 O.indent(2) << "}\n\n";
899 // Code that prints the alias, replacing the operands with the ones from the
901 O << " std::pair<StringRef, StringRef> ASM = AsmString.split(' ');\n";
902 O << " OS << '\\t' << ASM.first;\n";
904 O << " if (!ASM.second.empty()) {\n";
905 O << " OS << '\\t';\n";
906 O << " for (StringRef::iterator\n";
907 O << " I = ASM.second.begin(), E = ASM.second.end(); I != E; ) {\n";
908 O << " if (*I == '$') {\n";
909 O << " StringRef::iterator Start = ++I;\n";
910 O << " while (I != E &&\n";
911 O << " ((*I >= 'a' && *I <= 'z') ||\n";
912 O << " (*I >= 'A' && *I <= 'Z') ||\n";
913 O << " (*I >= '0' && *I <= '9') ||\n";
914 O << " *I == '_'))\n";
916 O << " StringRef Name(Start, I - Start);\n";
917 O << " printOperand(MI, getMapOperandNumber(OpMap, Name), OS);\n";
919 O << " OS << *I++;\n";
924 O << " return true;\n";
927 O << "#endif // PRINT_ALIAS_INSTR\n";
930 void AsmWriterEmitter::run(raw_ostream &O) {
931 EmitSourceFileHeader("Assembly Writer Source Fragment", O);
933 EmitPrintInstruction(O);
934 EmitGetRegisterName(O);
935 EmitPrintAliasInstruction(O);