1 //===- AsmWriterEmitter.cpp - Generate an assembly writer -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is emits an assembly printer for the current target.
11 // Note that this is currently fairly skeletal, but will grow over time.
13 //===----------------------------------------------------------------------===//
15 #include "AsmWriterInst.h"
16 #include "CodeGenTarget.h"
17 #include "SequenceToOffsetTable.h"
18 #include "llvm/ADT/SmallString.h"
19 #include "llvm/ADT/StringExtras.h"
20 #include "llvm/ADT/Twine.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/Format.h"
23 #include "llvm/Support/MathExtras.h"
24 #include "llvm/TableGen/Error.h"
25 #include "llvm/TableGen/Record.h"
26 #include "llvm/TableGen/TableGenBackend.h"
33 #define DEBUG_TYPE "asm-writer-emitter"
36 class AsmWriterEmitter {
37 RecordKeeper &Records;
39 std::map<const CodeGenInstruction*, AsmWriterInst*> CGIAWIMap;
40 const std::vector<const CodeGenInstruction*> *NumberedInstructions;
41 std::vector<AsmWriterInst> Instructions;
42 std::vector<std::string> PrintMethods;
44 AsmWriterEmitter(RecordKeeper &R);
46 void run(raw_ostream &o);
49 void EmitPrintInstruction(raw_ostream &o);
50 void EmitGetRegisterName(raw_ostream &o);
51 void EmitPrintAliasInstruction(raw_ostream &O);
53 AsmWriterInst *getAsmWriterInstByID(unsigned ID) const {
54 assert(ID < NumberedInstructions->size());
55 std::map<const CodeGenInstruction*, AsmWriterInst*>::const_iterator I =
56 CGIAWIMap.find(NumberedInstructions->at(ID));
57 assert(I != CGIAWIMap.end() && "Didn't find inst!");
60 void FindUniqueOperandCommands(std::vector<std::string> &UOC,
61 std::vector<unsigned> &InstIdxs,
62 std::vector<unsigned> &InstOpsUsed) const;
64 } // end anonymous namespace
66 static void PrintCases(std::vector<std::pair<std::string,
67 AsmWriterOperand> > &OpsToPrint, raw_ostream &O) {
68 O << " case " << OpsToPrint.back().first << ": ";
69 AsmWriterOperand TheOp = OpsToPrint.back().second;
70 OpsToPrint.pop_back();
72 // Check to see if any other operands are identical in this list, and if so,
73 // emit a case label for them.
74 for (unsigned i = OpsToPrint.size(); i != 0; --i)
75 if (OpsToPrint[i-1].second == TheOp) {
76 O << "\n case " << OpsToPrint[i-1].first << ": ";
77 OpsToPrint.erase(OpsToPrint.begin()+i-1);
80 // Finally, emit the code.
86 /// EmitInstructions - Emit the last instruction in the vector and any other
87 /// instructions that are suitably similar to it.
88 static void EmitInstructions(std::vector<AsmWriterInst> &Insts,
90 AsmWriterInst FirstInst = Insts.back();
93 std::vector<AsmWriterInst> SimilarInsts;
94 unsigned DifferingOperand = ~0;
95 for (unsigned i = Insts.size(); i != 0; --i) {
96 unsigned DiffOp = Insts[i-1].MatchesAllButOneOp(FirstInst);
98 if (DifferingOperand == ~0U) // First match!
99 DifferingOperand = DiffOp;
101 // If this differs in the same operand as the rest of the instructions in
102 // this class, move it to the SimilarInsts list.
103 if (DifferingOperand == DiffOp || DiffOp == ~0U) {
104 SimilarInsts.push_back(Insts[i-1]);
105 Insts.erase(Insts.begin()+i-1);
110 O << " case " << FirstInst.CGI->Namespace << "::"
111 << FirstInst.CGI->TheDef->getName() << ":\n";
112 for (unsigned i = 0, e = SimilarInsts.size(); i != e; ++i)
113 O << " case " << SimilarInsts[i].CGI->Namespace << "::"
114 << SimilarInsts[i].CGI->TheDef->getName() << ":\n";
115 for (unsigned i = 0, e = FirstInst.Operands.size(); i != e; ++i) {
116 if (i != DifferingOperand) {
117 // If the operand is the same for all instructions, just print it.
118 O << " " << FirstInst.Operands[i].getCode();
120 // If this is the operand that varies between all of the instructions,
121 // emit a switch for just this operand now.
122 O << " switch (MI->getOpcode()) {\n";
123 std::vector<std::pair<std::string, AsmWriterOperand> > OpsToPrint;
124 OpsToPrint.push_back(std::make_pair(FirstInst.CGI->Namespace + "::" +
125 FirstInst.CGI->TheDef->getName(),
126 FirstInst.Operands[i]));
128 for (unsigned si = 0, e = SimilarInsts.size(); si != e; ++si) {
129 AsmWriterInst &AWI = SimilarInsts[si];
130 OpsToPrint.push_back(std::make_pair(AWI.CGI->Namespace+"::"+
131 AWI.CGI->TheDef->getName(),
134 std::reverse(OpsToPrint.begin(), OpsToPrint.end());
135 while (!OpsToPrint.empty())
136 PrintCases(OpsToPrint, O);
144 void AsmWriterEmitter::
145 FindUniqueOperandCommands(std::vector<std::string> &UniqueOperandCommands,
146 std::vector<unsigned> &InstIdxs,
147 std::vector<unsigned> &InstOpsUsed) const {
148 InstIdxs.assign(NumberedInstructions->size(), ~0U);
150 // This vector parallels UniqueOperandCommands, keeping track of which
151 // instructions each case are used for. It is a comma separated string of
153 std::vector<std::string> InstrsForCase;
154 InstrsForCase.resize(UniqueOperandCommands.size());
155 InstOpsUsed.assign(UniqueOperandCommands.size(), 0);
157 for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) {
158 const AsmWriterInst *Inst = getAsmWriterInstByID(i);
160 continue; // PHI, INLINEASM, CFI_INSTRUCTION, etc.
162 if (Inst->Operands.empty())
163 continue; // Instruction already done.
165 std::string Command = " " + Inst->Operands[0].getCode() + "\n";
167 // Check to see if we already have 'Command' in UniqueOperandCommands.
169 bool FoundIt = false;
170 for (unsigned idx = 0, e = UniqueOperandCommands.size(); idx != e; ++idx)
171 if (UniqueOperandCommands[idx] == Command) {
173 InstrsForCase[idx] += ", ";
174 InstrsForCase[idx] += Inst->CGI->TheDef->getName();
179 InstIdxs[i] = UniqueOperandCommands.size();
180 UniqueOperandCommands.push_back(std::move(Command));
181 InstrsForCase.push_back(Inst->CGI->TheDef->getName());
183 // This command matches one operand so far.
184 InstOpsUsed.push_back(1);
188 // For each entry of UniqueOperandCommands, there is a set of instructions
189 // that uses it. If the next command of all instructions in the set are
190 // identical, fold it into the command.
191 for (unsigned CommandIdx = 0, e = UniqueOperandCommands.size();
192 CommandIdx != e; ++CommandIdx) {
194 for (unsigned Op = 1; ; ++Op) {
195 // Scan for the first instruction in the set.
196 std::vector<unsigned>::iterator NIT =
197 std::find(InstIdxs.begin(), InstIdxs.end(), CommandIdx);
198 if (NIT == InstIdxs.end()) break; // No commonality.
200 // If this instruction has no more operands, we isn't anything to merge
201 // into this command.
202 const AsmWriterInst *FirstInst =
203 getAsmWriterInstByID(NIT-InstIdxs.begin());
204 if (!FirstInst || FirstInst->Operands.size() == Op)
207 // Otherwise, scan to see if all of the other instructions in this command
208 // set share the operand.
211 for (NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx);
212 NIT != InstIdxs.end();
213 NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx)) {
214 // Okay, found another instruction in this command set. If the operand
215 // matches, we're ok, otherwise bail out.
216 const AsmWriterInst *OtherInst =
217 getAsmWriterInstByID(NIT-InstIdxs.begin());
219 if (!OtherInst || OtherInst->Operands.size() == Op ||
220 OtherInst->Operands[Op] != FirstInst->Operands[Op]) {
227 // Okay, everything in this command set has the same next operand. Add it
228 // to UniqueOperandCommands and remember that it was consumed.
229 std::string Command = " " + FirstInst->Operands[Op].getCode() + "\n";
231 UniqueOperandCommands[CommandIdx] += Command;
232 InstOpsUsed[CommandIdx]++;
236 // Prepend some of the instructions each case is used for onto the case val.
237 for (unsigned i = 0, e = InstrsForCase.size(); i != e; ++i) {
238 std::string Instrs = InstrsForCase[i];
239 if (Instrs.size() > 70) {
240 Instrs.erase(Instrs.begin()+70, Instrs.end());
245 UniqueOperandCommands[i] = " // " + Instrs + "\n" +
246 UniqueOperandCommands[i];
251 static void UnescapeString(std::string &Str) {
252 for (unsigned i = 0; i != Str.size(); ++i) {
253 if (Str[i] == '\\' && i != Str.size()-1) {
255 default: continue; // Don't execute the code after the switch.
256 case 'a': Str[i] = '\a'; break;
257 case 'b': Str[i] = '\b'; break;
258 case 'e': Str[i] = 27; break;
259 case 'f': Str[i] = '\f'; break;
260 case 'n': Str[i] = '\n'; break;
261 case 'r': Str[i] = '\r'; break;
262 case 't': Str[i] = '\t'; break;
263 case 'v': Str[i] = '\v'; break;
264 case '"': Str[i] = '\"'; break;
265 case '\'': Str[i] = '\''; break;
266 case '\\': Str[i] = '\\'; break;
268 // Nuke the second character.
269 Str.erase(Str.begin()+i+1);
274 /// EmitPrintInstruction - Generate the code for the "printInstruction" method
275 /// implementation. Destroys all instances of AsmWriterInst information, by
276 /// clearing the Instructions vector.
277 void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) {
278 Record *AsmWriter = Target.getAsmWriter();
279 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
280 unsigned PassSubtarget = AsmWriter->getValueAsInt("PassSubtarget");
283 "/// printInstruction - This method is automatically generated by tablegen\n"
284 "/// from the instruction set description.\n"
285 "void " << Target.getName() << ClassName
286 << "::printInstruction(const MCInst *MI, "
287 << (PassSubtarget ? "const MCSubtargetInfo &STI, " : "")
288 << "raw_ostream &O) {\n";
290 // Build an aggregate string, and build a table of offsets into it.
291 SequenceToOffsetTable<std::string> StringTable;
293 /// OpcodeInfo - This encodes the index of the string to use for the first
294 /// chunk of the output as well as indices used for operand printing.
295 /// To reduce the number of unhandled cases, we expand the size from 32-bit
296 /// to 32+16 = 48-bit.
297 std::vector<uint64_t> OpcodeInfo;
299 // Add all strings to the string table upfront so it can generate an optimized
301 for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) {
302 AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions->at(i)];
304 AWI->Operands[0].OperandType ==
305 AsmWriterOperand::isLiteralTextOperand &&
306 !AWI->Operands[0].Str.empty()) {
307 std::string Str = AWI->Operands[0].Str;
309 StringTable.add(Str);
313 StringTable.layout();
315 unsigned MaxStringIdx = 0;
316 for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) {
317 AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions->at(i)];
320 // Something not handled by the asmwriter printer.
322 } else if (AWI->Operands[0].OperandType !=
323 AsmWriterOperand::isLiteralTextOperand ||
324 AWI->Operands[0].Str.empty()) {
325 // Something handled by the asmwriter printer, but with no leading string.
326 Idx = StringTable.get("");
328 std::string Str = AWI->Operands[0].Str;
330 Idx = StringTable.get(Str);
331 MaxStringIdx = std::max(MaxStringIdx, Idx);
333 // Nuke the string from the operand list. It is now handled!
334 AWI->Operands.erase(AWI->Operands.begin());
337 // Bias offset by one since we want 0 as a sentinel.
338 OpcodeInfo.push_back(Idx+1);
341 // Figure out how many bits we used for the string index.
342 unsigned AsmStrBits = Log2_32_Ceil(MaxStringIdx+2);
344 // To reduce code size, we compactify common instructions into a few bits
345 // in the opcode-indexed table.
346 unsigned BitsLeft = 64-AsmStrBits;
348 std::vector<std::vector<std::string>> TableDrivenOperandPrinters;
351 std::vector<std::string> UniqueOperandCommands;
352 std::vector<unsigned> InstIdxs;
353 std::vector<unsigned> NumInstOpsHandled;
354 FindUniqueOperandCommands(UniqueOperandCommands, InstIdxs,
357 // If we ran out of operands to print, we're done.
358 if (UniqueOperandCommands.empty()) break;
360 // Compute the number of bits we need to represent these cases, this is
361 // ceil(log2(numentries)).
362 unsigned NumBits = Log2_32_Ceil(UniqueOperandCommands.size());
364 // If we don't have enough bits for this operand, don't include it.
365 if (NumBits > BitsLeft) {
366 DEBUG(errs() << "Not enough bits to densely encode " << NumBits
371 // Otherwise, we can include this in the initial lookup table. Add it in.
372 for (unsigned i = 0, e = InstIdxs.size(); i != e; ++i)
373 if (InstIdxs[i] != ~0U) {
374 OpcodeInfo[i] |= (uint64_t)InstIdxs[i] << (64-BitsLeft);
378 // Remove the info about this operand.
379 for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) {
380 if (AsmWriterInst *Inst = getAsmWriterInstByID(i))
381 if (!Inst->Operands.empty()) {
382 unsigned NumOps = NumInstOpsHandled[InstIdxs[i]];
383 assert(NumOps <= Inst->Operands.size() &&
384 "Can't remove this many ops!");
385 Inst->Operands.erase(Inst->Operands.begin(),
386 Inst->Operands.begin()+NumOps);
390 // Remember the handlers for this set of operands.
391 TableDrivenOperandPrinters.push_back(std::move(UniqueOperandCommands));
395 // We always emit at least one 32-bit table. A second table is emitted if
396 // more bits are needed.
397 O<<" static const uint32_t OpInfo[] = {\n";
398 for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) {
399 O << " " << (OpcodeInfo[i] & 0xffffffff) << "U,\t// "
400 << NumberedInstructions->at(i)->TheDef->getName() << "\n";
402 // Add a dummy entry so the array init doesn't end with a comma.
407 // Add a second OpInfo table only when it is necessary.
408 // Adjust the type of the second table based on the number of bits needed.
409 O << " static const uint"
410 << ((BitsLeft < 16) ? "32" : (BitsLeft < 24) ? "16" : "8")
411 << "_t OpInfo2[] = {\n";
412 for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) {
413 O << " " << (OpcodeInfo[i] >> 32) << "U,\t// "
414 << NumberedInstructions->at(i)->TheDef->getName() << "\n";
416 // Add a dummy entry so the array init doesn't end with a comma.
421 // Emit the string itself.
422 O << " static const char AsmStrs[] = {\n";
423 StringTable.emit(O, printChar);
426 O << " O << \"\\t\";\n\n";
428 O << " // Emit the opcode for the instruction.\n";
430 // If we have two tables then we need to perform two lookups and combine
431 // the results into a single 64-bit value.
432 O << " uint64_t Bits1 = OpInfo[MI->getOpcode()];\n"
433 << " uint64_t Bits2 = OpInfo2[MI->getOpcode()];\n"
434 << " uint64_t Bits = (Bits2 << 32) | Bits1;\n";
436 // If only one table is used we just need to perform a single lookup.
437 O << " uint32_t Bits = OpInfo[MI->getOpcode()];\n";
439 O << " assert(Bits != 0 && \"Cannot print this instruction.\");\n"
440 << " O << AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << ")-1;\n\n";
442 // Output the table driven operand information.
443 BitsLeft = 64-AsmStrBits;
444 for (unsigned i = 0, e = TableDrivenOperandPrinters.size(); i != e; ++i) {
445 std::vector<std::string> &Commands = TableDrivenOperandPrinters[i];
447 // Compute the number of bits we need to represent these cases, this is
448 // ceil(log2(numentries)).
449 unsigned NumBits = Log2_32_Ceil(Commands.size());
450 assert(NumBits <= BitsLeft && "consistency error");
452 // Emit code to extract this field from Bits.
453 O << "\n // Fragment " << i << " encoded into " << NumBits
454 << " bits for " << Commands.size() << " unique commands.\n";
456 if (Commands.size() == 2) {
457 // Emit two possibilitys with if/else.
458 O << " if ((Bits >> "
459 << (64-BitsLeft) << ") & "
460 << ((1 << NumBits)-1) << ") {\n"
465 } else if (Commands.size() == 1) {
466 // Emit a single possibility.
467 O << Commands[0] << "\n\n";
469 O << " switch ((Bits >> "
470 << (64-BitsLeft) << ") & "
471 << ((1 << NumBits)-1) << ") {\n"
472 << " default: llvm_unreachable(\"Invalid command number.\");\n";
474 // Print out all the cases.
475 for (unsigned i = 0, e = Commands.size(); i != e; ++i) {
476 O << " case " << i << ":\n";
485 // Okay, delete instructions with no operand info left.
486 for (unsigned i = 0, e = Instructions.size(); i != e; ++i) {
487 // Entire instruction has been emitted?
488 AsmWriterInst &Inst = Instructions[i];
489 if (Inst.Operands.empty()) {
490 Instructions.erase(Instructions.begin()+i);
496 // Because this is a vector, we want to emit from the end. Reverse all of the
497 // elements in the vector.
498 std::reverse(Instructions.begin(), Instructions.end());
501 // Now that we've emitted all of the operand info that fit into 32 bits, emit
502 // information for those instructions that are left. This is a less dense
503 // encoding, but we expect the main 32-bit table to handle the majority of
505 if (!Instructions.empty()) {
506 // Find the opcode # of inline asm.
507 O << " switch (MI->getOpcode()) {\n";
508 while (!Instructions.empty())
509 EmitInstructions(Instructions, O);
518 static const char *getMinimalTypeForRange(uint64_t Range) {
519 assert(Range < 0xFFFFFFFFULL && "Enum too large");
528 emitRegisterNameString(raw_ostream &O, StringRef AltName,
529 const std::deque<CodeGenRegister> &Registers) {
530 SequenceToOffsetTable<std::string> StringTable;
531 SmallVector<std::string, 4> AsmNames(Registers.size());
533 for (const auto &Reg : Registers) {
534 std::string &AsmName = AsmNames[i++];
536 // "NoRegAltName" is special. We don't need to do a lookup for that,
537 // as it's just a reference to the default register name.
538 if (AltName == "" || AltName == "NoRegAltName") {
539 AsmName = Reg.TheDef->getValueAsString("AsmName");
541 AsmName = Reg.getName();
543 // Make sure the register has an alternate name for this index.
544 std::vector<Record*> AltNameList =
545 Reg.TheDef->getValueAsListOfDefs("RegAltNameIndices");
547 for (e = AltNameList.size();
548 Idx < e && (AltNameList[Idx]->getName() != AltName);
551 // If the register has an alternate name for this index, use it.
552 // Otherwise, leave it empty as an error flag.
554 std::vector<std::string> AltNames =
555 Reg.TheDef->getValueAsListOfStrings("AltNames");
556 if (AltNames.size() <= Idx)
557 PrintFatalError(Reg.TheDef->getLoc(),
558 "Register definition missing alt name for '" +
560 AsmName = AltNames[Idx];
563 StringTable.add(AsmName);
566 StringTable.layout();
567 O << " static const char AsmStrs" << AltName << "[] = {\n";
568 StringTable.emit(O, printChar);
571 O << " static const " << getMinimalTypeForRange(StringTable.size()-1)
572 << " RegAsmOffset" << AltName << "[] = {";
573 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
576 O << StringTable.get(AsmNames[i]) << ", ";
582 void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) {
583 Record *AsmWriter = Target.getAsmWriter();
584 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
585 const auto &Registers = Target.getRegBank().getRegisters();
586 std::vector<Record*> AltNameIndices = Target.getRegAltNameIndices();
587 bool hasAltNames = AltNameIndices.size() > 1;
588 std::string Namespace =
589 Registers.front().TheDef->getValueAsString("Namespace");
592 "\n\n/// getRegisterName - This method is automatically generated by tblgen\n"
593 "/// from the register set description. This returns the assembler name\n"
594 "/// for the specified register.\n"
595 "const char *" << Target.getName() << ClassName << "::";
597 O << "\ngetRegisterName(unsigned RegNo, unsigned AltIdx) {\n";
599 O << "getRegisterName(unsigned RegNo) {\n";
600 O << " assert(RegNo && RegNo < " << (Registers.size()+1)
601 << " && \"Invalid register number!\");\n"
605 for (unsigned i = 0, e = AltNameIndices.size(); i < e; ++i)
606 emitRegisterNameString(O, AltNameIndices[i]->getName(), Registers);
608 emitRegisterNameString(O, "", Registers);
611 O << " switch(AltIdx) {\n"
612 << " default: llvm_unreachable(\"Invalid register alt name index!\");\n";
613 for (unsigned i = 0, e = AltNameIndices.size(); i < e; ++i) {
614 std::string AltName(AltNameIndices[i]->getName());
615 std::string Prefix = !Namespace.empty() ? Namespace + "::" : "";
616 O << " case " << Prefix << AltName << ":\n"
617 << " assert(*(AsmStrs" << AltName << "+RegAsmOffset"
618 << AltName << "[RegNo-1]) &&\n"
619 << " \"Invalid alt name index for register!\");\n"
620 << " return AsmStrs" << AltName << "+RegAsmOffset"
621 << AltName << "[RegNo-1];\n";
625 O << " assert (*(AsmStrs+RegAsmOffset[RegNo-1]) &&\n"
626 << " \"Invalid alt name index for register!\");\n"
627 << " return AsmStrs+RegAsmOffset[RegNo-1];\n";
633 // IAPrinter - Holds information about an InstAlias. Two InstAliases match if
634 // they both have the same conditionals. In which case, we cannot print out the
635 // alias for that pattern.
637 std::vector<std::string> Conds;
638 std::map<StringRef, std::pair<int, int>> OpMap;
639 SmallVector<Record*, 4> ReqFeatures;
642 std::string AsmString;
644 IAPrinter(std::string R, std::string AS) : Result(R), AsmString(AS) {}
646 void addCond(const std::string &C) { Conds.push_back(C); }
648 void addOperand(StringRef Op, int OpIdx, int PrintMethodIdx = -1) {
649 assert(OpIdx >= 0 && OpIdx < 0xFE && "Idx out of range");
650 assert(PrintMethodIdx >= -1 && PrintMethodIdx < 0xFF &&
652 OpMap[Op] = std::make_pair(OpIdx, PrintMethodIdx);
655 bool isOpMapped(StringRef Op) { return OpMap.find(Op) != OpMap.end(); }
656 int getOpIndex(StringRef Op) { return OpMap[Op].first; }
657 std::pair<int, int> &getOpData(StringRef Op) { return OpMap[Op]; }
659 std::pair<StringRef, StringRef::iterator> parseName(StringRef::iterator Start,
660 StringRef::iterator End) {
661 StringRef::iterator I = Start;
662 StringRef::iterator Next;
666 while (I != End && *I != '}')
673 // $name, just eat the usual suspects.
675 ((*I >= 'a' && *I <= 'z') || (*I >= 'A' && *I <= 'Z') ||
676 (*I >= '0' && *I <= '9') || *I == '_'))
681 return std::make_pair(StringRef(Start, I - Start), Next);
684 void print(raw_ostream &O) {
685 if (Conds.empty() && ReqFeatures.empty()) {
686 O.indent(6) << "return true;\n";
692 for (std::vector<std::string>::iterator
693 I = Conds.begin(), E = Conds.end(); I != E; ++I) {
694 if (I != Conds.begin()) {
703 O.indent(6) << "// " << Result << "\n";
705 // Directly mangle mapped operands into the string. Each operand is
706 // identified by a '$' sign followed by a byte identifying the number of the
707 // operand. We add one to the index to avoid zero bytes.
708 StringRef ASM(AsmString);
709 SmallString<128> OutString;
710 raw_svector_ostream OS(OutString);
711 for (StringRef::iterator I = ASM.begin(), E = ASM.end(); I != E;) {
715 std::tie(Name, I) = parseName(++I, E);
716 assert(isOpMapped(Name) && "Unmapped operand!");
718 int OpIndex, PrintIndex;
719 std::tie(OpIndex, PrintIndex) = getOpData(Name);
720 if (PrintIndex == -1) {
721 // Can use the default printOperand route.
722 OS << format("\\x%02X", (unsigned char)OpIndex + 1);
724 // 3 bytes if a PrintMethod is needed: 0xFF, the MCInst operand
725 // number, and which of our pre-detected Methods to call.
726 OS << format("\\xFF\\x%02X\\x%02X", OpIndex + 1, PrintIndex + 1);
733 O.indent(6) << "AsmString = \"" << OutString << "\";\n";
735 O.indent(6) << "break;\n";
739 bool operator==(const IAPrinter &RHS) const {
740 if (Conds.size() != RHS.Conds.size())
744 for (const auto &str : Conds)
745 if (str != RHS.Conds[Idx++])
752 } // end anonymous namespace
754 static unsigned CountNumOperands(StringRef AsmString, unsigned Variant) {
755 std::string FlatAsmString =
756 CodeGenInstruction::FlattenAsmStringVariants(AsmString, Variant);
757 AsmString = FlatAsmString;
759 return AsmString.count(' ') + AsmString.count('\t');
763 struct AliasPriorityComparator {
764 typedef std::pair<CodeGenInstAlias, int> ValueType;
765 bool operator()(const ValueType &LHS, const ValueType &RHS) {
766 if (LHS.second == RHS.second) {
767 // We don't actually care about the order, but for consistency it
768 // shouldn't depend on pointer comparisons.
769 return LHS.first.TheDef->getName() < RHS.first.TheDef->getName();
772 // Aliases with larger priorities should be considered first.
773 return LHS.second > RHS.second;
779 void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
780 Record *AsmWriter = Target.getAsmWriter();
782 O << "\n#ifdef PRINT_ALIAS_INSTR\n";
783 O << "#undef PRINT_ALIAS_INSTR\n\n";
785 //////////////////////////////
786 // Gather information about aliases we need to print
787 //////////////////////////////
789 // Emit the method that prints the alias instruction.
790 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
791 unsigned Variant = AsmWriter->getValueAsInt("Variant");
792 unsigned PassSubtarget = AsmWriter->getValueAsInt("PassSubtarget");
794 std::vector<Record*> AllInstAliases =
795 Records.getAllDerivedDefinitions("InstAlias");
797 // Create a map from the qualified name to a list of potential matches.
798 typedef std::set<std::pair<CodeGenInstAlias, int>, AliasPriorityComparator>
800 std::map<std::string, AliasWithPriority> AliasMap;
801 for (std::vector<Record*>::iterator
802 I = AllInstAliases.begin(), E = AllInstAliases.end(); I != E; ++I) {
803 const Record *R = *I;
804 int Priority = R->getValueAsInt("EmitPriority");
806 continue; // Aliases with priority 0 are never emitted.
808 const DagInit *DI = R->getValueAsDag("ResultInst");
809 const DefInit *Op = cast<DefInit>(DI->getOperator());
810 AliasMap[getQualifiedName(Op->getDef())].insert(
811 std::make_pair(CodeGenInstAlias(*I, Variant, Target), Priority));
814 // A map of which conditions need to be met for each instruction operand
815 // before it can be matched to the mnemonic.
816 std::map<std::string, std::vector<IAPrinter>> IAPrinterMap;
818 // A list of MCOperandPredicates for all operands in use, and the reverse map
819 std::vector<const Record*> MCOpPredicates;
820 DenseMap<const Record*, unsigned> MCOpPredicateMap;
822 for (auto &Aliases : AliasMap) {
823 for (auto &Alias : Aliases.second) {
824 const CodeGenInstAlias &CGA = Alias.first;
825 unsigned LastOpNo = CGA.ResultInstOperandIndex.size();
826 unsigned NumResultOps =
827 CountNumOperands(CGA.ResultInst->AsmString, Variant);
829 // Don't emit the alias if it has more operands than what it's aliasing.
830 if (NumResultOps < CountNumOperands(CGA.AsmString, Variant))
833 IAPrinter IAP(CGA.Result->getAsString(), CGA.AsmString);
835 unsigned NumMIOps = 0;
836 for (auto &Operand : CGA.ResultOperands)
837 NumMIOps += Operand.getMINumOperands();
840 Cond = std::string("MI->getNumOperands() == ") + llvm::utostr(NumMIOps);
843 bool CantHandle = false;
845 unsigned MIOpNum = 0;
846 for (unsigned i = 0, e = LastOpNo; i != e; ++i) {
847 std::string Op = "MI->getOperand(" + llvm::utostr(MIOpNum) + ")";
849 const CodeGenInstAlias::ResultOperand &RO = CGA.ResultOperands[i];
852 case CodeGenInstAlias::ResultOperand::K_Record: {
853 const Record *Rec = RO.getRecord();
854 StringRef ROName = RO.getName();
855 int PrintMethodIdx = -1;
857 // These two may have a PrintMethod, which we want to record (if it's
858 // the first time we've seen it) and provide an index for the aliasing
860 if (Rec->isSubClassOf("RegisterOperand") ||
861 Rec->isSubClassOf("Operand")) {
862 std::string PrintMethod = Rec->getValueAsString("PrintMethod");
863 if (PrintMethod != "" && PrintMethod != "printOperand") {
864 PrintMethodIdx = std::find(PrintMethods.begin(),
865 PrintMethods.end(), PrintMethod) -
866 PrintMethods.begin();
867 if (static_cast<unsigned>(PrintMethodIdx) == PrintMethods.size())
868 PrintMethods.push_back(PrintMethod);
872 if (Rec->isSubClassOf("RegisterOperand"))
873 Rec = Rec->getValueAsDef("RegClass");
874 if (Rec->isSubClassOf("RegisterClass")) {
875 IAP.addCond(Op + ".isReg()");
877 if (!IAP.isOpMapped(ROName)) {
878 IAP.addOperand(ROName, MIOpNum, PrintMethodIdx);
879 Record *R = CGA.ResultOperands[i].getRecord();
880 if (R->isSubClassOf("RegisterOperand"))
881 R = R->getValueAsDef("RegClass");
882 Cond = std::string("MRI.getRegClass(") + Target.getName() + "::" +
883 R->getName() + "RegClassID)"
884 ".contains(" + Op + ".getReg())";
886 Cond = Op + ".getReg() == MI->getOperand(" +
887 llvm::utostr(IAP.getOpIndex(ROName)) + ").getReg()";
890 // Assume all printable operands are desired for now. This can be
891 // overridden in the InstAlias instantiation if necessary.
892 IAP.addOperand(ROName, MIOpNum, PrintMethodIdx);
894 // There might be an additional predicate on the MCOperand
895 unsigned Entry = MCOpPredicateMap[Rec];
897 if (!Rec->isValueUnset("MCOperandPredicate")) {
898 MCOpPredicates.push_back(Rec);
899 Entry = MCOpPredicates.size();
900 MCOpPredicateMap[Rec] = Entry;
902 break; // No conditions on this operand at all
904 Cond = Target.getName() + ClassName + "ValidateMCOperand(" +
905 Op + ", STI, " + llvm::utostr(Entry) + ")";
907 // for all subcases of ResultOperand::K_Record:
911 case CodeGenInstAlias::ResultOperand::K_Imm: {
912 // Just because the alias has an immediate result, doesn't mean the
913 // MCInst will. An MCExpr could be present, for example.
914 IAP.addCond(Op + ".isImm()");
916 Cond = Op + ".getImm() == " +
917 llvm::utostr(CGA.ResultOperands[i].getImm());
921 case CodeGenInstAlias::ResultOperand::K_Reg:
922 // If this is zero_reg, something's playing tricks we're not
923 // equipped to handle.
924 if (!CGA.ResultOperands[i].getRegister()) {
929 Cond = Op + ".getReg() == " + Target.getName() + "::" +
930 CGA.ResultOperands[i].getRegister()->getName();
935 MIOpNum += RO.getMINumOperands();
938 if (CantHandle) continue;
939 IAPrinterMap[Aliases.first].push_back(std::move(IAP));
943 //////////////////////////////
944 // Write out the printAliasInstr function
945 //////////////////////////////
948 raw_string_ostream HeaderO(Header);
950 HeaderO << "bool " << Target.getName() << ClassName
951 << "::printAliasInstr(const MCInst"
952 << " *MI, " << (PassSubtarget ? "const MCSubtargetInfo &STI, " : "")
953 << "raw_ostream &OS) {\n";
956 raw_string_ostream CasesO(Cases);
958 for (auto &Entry : IAPrinterMap) {
959 std::vector<IAPrinter> &IAPs = Entry.second;
960 std::vector<IAPrinter*> UniqueIAPs;
962 for (auto &LHS : IAPs) {
964 for (const auto &RHS : IAPs) {
965 if (&LHS != &RHS && LHS == RHS) {
972 UniqueIAPs.push_back(&LHS);
975 if (UniqueIAPs.empty()) continue;
977 CasesO.indent(2) << "case " << Entry.first << ":\n";
979 for (std::vector<IAPrinter*>::iterator
980 II = UniqueIAPs.begin(), IE = UniqueIAPs.end(); II != IE; ++II) {
981 IAPrinter *IAP = *II;
987 CasesO.indent(4) << "return false;\n";
990 if (CasesO.str().empty()) {
992 O << " return false;\n";
994 O << "#endif // PRINT_ALIAS_INSTR\n";
998 if (!MCOpPredicates.empty())
999 O << "static bool " << Target.getName() << ClassName
1000 << "ValidateMCOperand(const MCOperand &MCOp,\n"
1001 << " const MCSubtargetInfo &STI,\n"
1002 << " unsigned PredicateIndex);\n";
1005 O.indent(2) << "const char *AsmString;\n";
1006 O.indent(2) << "switch (MI->getOpcode()) {\n";
1007 O.indent(2) << "default: return false;\n";
1009 O.indent(2) << "}\n\n";
1011 // Code that prints the alias, replacing the operands with the ones from the
1013 O << " unsigned I = 0;\n";
1014 O << " while (AsmString[I] != ' ' && AsmString[I] != '\t' &&\n";
1015 O << " AsmString[I] != '\\0')\n";
1017 O << " OS << '\\t' << StringRef(AsmString, I);\n";
1019 O << " if (AsmString[I] != '\\0') {\n";
1020 O << " OS << '\\t';\n";
1022 O << " if (AsmString[I] == '$') {\n";
1024 O << " if (AsmString[I] == (char)0xff) {\n";
1026 O << " int OpIdx = AsmString[I++] - 1;\n";
1027 O << " int PrintMethodIdx = AsmString[I++] - 1;\n";
1028 O << " printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, ";
1029 O << (PassSubtarget ? "STI, " : "");
1032 O << " printOperand(MI, unsigned(AsmString[I++]) - 1, ";
1033 O << (PassSubtarget ? "STI, " : "");
1036 O << " OS << AsmString[I++];\n";
1038 O << " } while (AsmString[I] != '\\0');\n";
1041 O << " return true;\n";
1044 //////////////////////////////
1045 // Write out the printCustomAliasOperand function
1046 //////////////////////////////
1048 O << "void " << Target.getName() << ClassName << "::"
1049 << "printCustomAliasOperand(\n"
1050 << " const MCInst *MI, unsigned OpIdx,\n"
1051 << " unsigned PrintMethodIdx,\n"
1052 << (PassSubtarget ? " const MCSubtargetInfo &STI,\n" : "")
1053 << " raw_ostream &OS) {\n";
1054 if (PrintMethods.empty())
1055 O << " llvm_unreachable(\"Unknown PrintMethod kind\");\n";
1057 O << " switch (PrintMethodIdx) {\n"
1059 << " llvm_unreachable(\"Unknown PrintMethod kind\");\n"
1062 for (unsigned i = 0; i < PrintMethods.size(); ++i) {
1063 O << " case " << i << ":\n"
1064 << " " << PrintMethods[i] << "(MI, OpIdx, "
1065 << (PassSubtarget ? "STI, " : "") << "OS);\n"
1072 if (!MCOpPredicates.empty()) {
1073 O << "static bool " << Target.getName() << ClassName
1074 << "ValidateMCOperand(const MCOperand &MCOp,\n"
1075 << " const MCSubtargetInfo &STI,\n"
1076 << " unsigned PredicateIndex) {\n"
1077 << " switch (PredicateIndex) {\n"
1079 << " llvm_unreachable(\"Unknown MCOperandPredicate kind\");\n"
1082 for (unsigned i = 0; i < MCOpPredicates.size(); ++i) {
1083 Init *MCOpPred = MCOpPredicates[i]->getValueInit("MCOperandPredicate");
1084 if (StringInit *SI = dyn_cast<StringInit>(MCOpPred)) {
1085 O << " case " << i + 1 << ": {\n"
1086 << SI->getValue() << "\n"
1089 llvm_unreachable("Unexpected MCOperandPredicate field!");
1095 O << "#endif // PRINT_ALIAS_INSTR\n";
1098 AsmWriterEmitter::AsmWriterEmitter(RecordKeeper &R) : Records(R), Target(R) {
1099 Record *AsmWriter = Target.getAsmWriter();
1100 for (const CodeGenInstruction *I : Target.instructions())
1101 if (!I->AsmString.empty() && I->TheDef->getName() != "PHI")
1102 Instructions.emplace_back(*I, AsmWriter->getValueAsInt("Variant"),
1103 AsmWriter->getValueAsInt("PassSubtarget"));
1105 // Get the instruction numbering.
1106 NumberedInstructions = &Target.getInstructionsByEnumValue();
1108 // Compute the CodeGenInstruction -> AsmWriterInst mapping. Note that not
1109 // all machine instructions are necessarily being printed, so there may be
1110 // target instructions not in this map.
1111 for (unsigned i = 0, e = Instructions.size(); i != e; ++i)
1112 CGIAWIMap.insert(std::make_pair(Instructions[i].CGI, &Instructions[i]));
1115 void AsmWriterEmitter::run(raw_ostream &O) {
1116 EmitPrintInstruction(O);
1117 EmitGetRegisterName(O);
1118 EmitPrintAliasInstruction(O);
1124 void EmitAsmWriter(RecordKeeper &RK, raw_ostream &OS) {
1125 emitSourceFileHeader("Assembly Writer Source Fragment", OS);
1126 AsmWriterEmitter(RK).run(OS);
1129 } // End llvm namespace