1 //===- CodeEmitterGen.cpp - Code Emitter Generator ------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // CodeEmitterGen uses the descriptions of instructions and their fields to
11 // construct an automated code emitter: a function that, given a MachineInstr,
12 // returns the (currently, 32-bit unsigned) value of the instruction.
14 //===----------------------------------------------------------------------===//
16 #include "CodeEmitterGen.h"
17 #include "CodeGenTarget.h"
19 #include "llvm/ADT/StringExtras.h"
20 #include "llvm/Support/Debug.h"
23 void CodeEmitterGen::reverseBits(std::vector<Record*> &Insts) {
24 for (std::vector<Record*>::iterator I = Insts.begin(), E = Insts.end();
27 if (R->getName() == "PHI" ||
28 R->getName() == "INLINEASM" ||
29 R->getName() == "LABEL") continue;
31 BitsInit *BI = R->getValueAsBitsInit("Inst");
33 unsigned numBits = BI->getNumBits();
34 BitsInit *NewBI = new BitsInit(numBits);
35 for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) {
36 unsigned bitSwapIdx = numBits - bit - 1;
37 Init *OrigBit = BI->getBit(bit);
38 Init *BitSwap = BI->getBit(bitSwapIdx);
39 NewBI->setBit(bit, BitSwap);
40 NewBI->setBit(bitSwapIdx, OrigBit);
43 unsigned middle = (numBits + 1) / 2;
44 NewBI->setBit(middle, BI->getBit(middle));
47 // Update the bits in reversed order so that emitInstrOpBits will get the
48 // correct endianness.
49 R->getValue("Inst")->setValue(NewBI);
54 // If the VarBitInit at position 'bit' matches the specified variable then
55 // return the variable bit position. Otherwise return -1.
56 int CodeEmitterGen::getVariableBit(const std::string &VarName,
57 BitsInit *BI, int bit) {
58 if (VarBitInit *VBI = dynamic_cast<VarBitInit*>(BI->getBit(bit))) {
59 TypedInit *TI = VBI->getVariable();
61 if (VarInit *VI = dynamic_cast<VarInit*>(TI)) {
62 if (VI->getName() == VarName) return VBI->getBitNum();
70 void CodeEmitterGen::run(std::ostream &o) {
72 std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
74 // For little-endian instruction bit encodings, reverse the bit order
75 if (Target.isLittleEndianEncoding()) reverseBits(Insts);
77 EmitSourceFileHeader("Machine Code Emitter", o);
78 std::string Namespace = Insts[0]->getValueAsString("Namespace") + "::";
80 std::vector<const CodeGenInstruction*> NumberedInstructions;
81 Target.getInstructionsByEnumValue(NumberedInstructions);
83 // Emit function declaration
84 o << "unsigned " << Target.getName() << "CodeEmitter::"
85 << "getBinaryCodeForInstr(MachineInstr &MI) {\n";
87 // Emit instruction base values
88 o << " static const unsigned InstBits[] = {\n";
89 for (std::vector<const CodeGenInstruction*>::iterator
90 IN = NumberedInstructions.begin(),
91 EN = NumberedInstructions.end();
93 const CodeGenInstruction *CGI = *IN;
94 Record *R = CGI->TheDef;
96 if (IN != NumberedInstructions.begin()) o << ",\n";
98 if (R->getName() == "PHI" ||
99 R->getName() == "INLINEASM" ||
100 R->getName() == "LABEL") {
105 BitsInit *BI = R->getValueAsBitsInit("Inst");
107 // Start by filling in fixed values...
109 for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i) {
110 if (BitInit *B = dynamic_cast<BitInit*>(BI->getBit(e-i-1))) {
111 Value |= B->getValue() << (e-i-1);
114 o << " " << Value << "U";
118 // Map to accumulate all the cases.
119 std::map<std::string, std::vector<std::string> > CaseMap;
121 // Construct all cases statement for each opcode
122 for (std::vector<Record*>::iterator IC = Insts.begin(), EC = Insts.end();
125 const std::string &InstName = R->getName();
126 std::string Case("");
128 if (InstName == "PHI" ||
129 InstName == "INLINEASM" ||
130 InstName == "LABEL") continue;
132 BitsInit *BI = R->getValueAsBitsInit("Inst");
133 const std::vector<RecordVal> &Vals = R->getValues();
134 CodeGenInstruction &CGI = Target.getInstruction(InstName);
136 // Loop over all of the fields in the instruction, determining which are the
137 // operands to the instruction.
139 for (unsigned i = 0, e = Vals.size(); i != e; ++i) {
140 if (!Vals[i].getPrefix() && !Vals[i].getValue()->isComplete()) {
141 // Is the operand continuous? If so, we can just mask and OR it in
142 // instead of doing it bit-by-bit, saving a lot in runtime cost.
143 const std::string &VarName = Vals[i].getName();
146 for (int bit = BI->getNumBits()-1; bit >= 0; ) {
147 int varBit = getVariableBit(VarName, BI, bit);
152 int beginInstBit = bit;
153 int beginVarBit = varBit;
156 for (--bit; bit >= 0;) {
157 varBit = getVariableBit(VarName, BI, bit);
158 if (varBit == -1 || varBit != (beginVarBit - N)) break;
164 /// If this operand is not supposed to be emitted by the generated
165 /// emitter, skip it.
166 while (CGI.isFlatOperandNotEmitted(op))
169 Case += " // op: " + VarName + "\n"
170 + " op = getMachineOpValue(MI, MI.getOperand("
171 + utostr(op++) + "));\n";
175 unsigned opMask = (1 << N) - 1;
176 int opShift = beginVarBit - N + 1;
178 opShift = beginInstBit - beginVarBit;
181 Case += " Value |= (op & " + utostr(opMask) + "U) << "
182 + itostr(opShift) + ";\n";
183 } else if (opShift < 0) {
184 Case += " Value |= (op & " + utostr(opMask) + "U) >> "
185 + itostr(-opShift) + ";\n";
187 Case += " Value |= op & " + utostr(opMask) + "U;\n";
194 std::vector<std::string> &InstList = CaseMap[Case];
195 InstList.push_back(InstName);
199 // Emit initial function code
200 o << " const unsigned opcode = MI.getOpcode();\n"
201 << " unsigned Value = InstBits[opcode];\n"
203 << " switch (opcode) {\n";
205 // Emit each case statement
206 std::map<std::string, std::vector<std::string> >::iterator IE, EE;
207 for (IE = CaseMap.begin(), EE = CaseMap.end(); IE != EE; ++IE) {
208 const std::string &Case = IE->first;
209 std::vector<std::string> &InstList = IE->second;
211 for (int i = 0, N = InstList.size(); i < N; i++) {
213 o << " case " << Namespace << InstList[i] << ":";
221 // Default case: unhandled opcode
223 << " cerr << \"Not supported instr: \" << MI << \"\\n\";\n"
226 << " return Value;\n"