1 //===- CodeEmitterGen.cpp - Code Emitter Generator ------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // CodeEmitterGen uses the descriptions of instructions and their fields to
11 // construct an automated code emitter: a function that, given a MachineInstr,
12 // returns the (currently, 32-bit unsigned) value of the instruction.
14 //===----------------------------------------------------------------------===//
16 #include "CodeEmitterGen.h"
17 #include "CodeGenTarget.h"
19 #include "llvm/ADT/StringExtras.h"
20 #include "llvm/Support/Debug.h"
23 void CodeEmitterGen::reverseBits(std::vector<Record*> &Insts) {
24 for (std::vector<Record*>::iterator I = Insts.begin(), E = Insts.end();
27 if (R->getName() == "PHI" ||
28 R->getName() == "INLINEASM" ||
29 R->getName() == "DBG_LABEL" ||
30 R->getName() == "EH_LABEL" ||
31 R->getName() == "GC_LABEL" ||
32 R->getName() == "KILL" ||
33 R->getName() == "EXTRACT_SUBREG" ||
34 R->getName() == "INSERT_SUBREG" ||
35 R->getName() == "IMPLICIT_DEF" ||
36 R->getName() == "SUBREG_TO_REG" ||
37 R->getName() == "COPY_TO_REGCLASS" ||
38 R->getName() == "DEBUG_VALUE") continue;
40 BitsInit *BI = R->getValueAsBitsInit("Inst");
42 unsigned numBits = BI->getNumBits();
43 BitsInit *NewBI = new BitsInit(numBits);
44 for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) {
45 unsigned bitSwapIdx = numBits - bit - 1;
46 Init *OrigBit = BI->getBit(bit);
47 Init *BitSwap = BI->getBit(bitSwapIdx);
48 NewBI->setBit(bit, BitSwap);
49 NewBI->setBit(bitSwapIdx, OrigBit);
52 unsigned middle = (numBits + 1) / 2;
53 NewBI->setBit(middle, BI->getBit(middle));
56 // Update the bits in reversed order so that emitInstrOpBits will get the
57 // correct endianness.
58 R->getValue("Inst")->setValue(NewBI);
63 // If the VarBitInit at position 'bit' matches the specified variable then
64 // return the variable bit position. Otherwise return -1.
65 int CodeEmitterGen::getVariableBit(const std::string &VarName,
66 BitsInit *BI, int bit) {
67 if (VarBitInit *VBI = dynamic_cast<VarBitInit*>(BI->getBit(bit))) {
68 TypedInit *TI = VBI->getVariable();
70 if (VarInit *VI = dynamic_cast<VarInit*>(TI)) {
71 if (VI->getName() == VarName) return VBI->getBitNum();
79 void CodeEmitterGen::run(raw_ostream &o) {
81 std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
83 // For little-endian instruction bit encodings, reverse the bit order
84 if (Target.isLittleEndianEncoding()) reverseBits(Insts);
86 EmitSourceFileHeader("Machine Code Emitter", o);
87 std::string Namespace = Insts[0]->getValueAsString("Namespace") + "::";
89 std::vector<const CodeGenInstruction*> NumberedInstructions;
90 Target.getInstructionsByEnumValue(NumberedInstructions);
92 // Emit function declaration
93 o << "unsigned " << Target.getName() << "CodeEmitter::"
94 << "getBinaryCodeForInstr(const MachineInstr &MI) {\n";
96 // Emit instruction base values
97 o << " static const unsigned InstBits[] = {\n";
98 for (std::vector<const CodeGenInstruction*>::iterator
99 IN = NumberedInstructions.begin(),
100 EN = NumberedInstructions.end();
102 const CodeGenInstruction *CGI = *IN;
103 Record *R = CGI->TheDef;
105 if (R->getName() == "PHI" ||
106 R->getName() == "INLINEASM" ||
107 R->getName() == "DBG_LABEL" ||
108 R->getName() == "EH_LABEL" ||
109 R->getName() == "GC_LABEL" ||
110 R->getName() == "KILL" ||
111 R->getName() == "EXTRACT_SUBREG" ||
112 R->getName() == "INSERT_SUBREG" ||
113 R->getName() == "IMPLICIT_DEF" ||
114 R->getName() == "SUBREG_TO_REG" ||
115 R->getName() == "COPY_TO_REGCLASS" ||
116 R->getName() == "DEBUG_VALUE") {
121 BitsInit *BI = R->getValueAsBitsInit("Inst");
123 // Start by filling in fixed values...
125 for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i) {
126 if (BitInit *B = dynamic_cast<BitInit*>(BI->getBit(e-i-1))) {
127 Value |= B->getValue() << (e-i-1);
130 o << " " << Value << "U," << '\t' << "// " << R->getName() << "\n";
134 // Map to accumulate all the cases.
135 std::map<std::string, std::vector<std::string> > CaseMap;
137 // Construct all cases statement for each opcode
138 for (std::vector<Record*>::iterator IC = Insts.begin(), EC = Insts.end();
141 const std::string &InstName = R->getName();
142 std::string Case("");
144 if (InstName == "PHI" ||
145 InstName == "INLINEASM" ||
146 InstName == "DBG_LABEL"||
147 InstName == "EH_LABEL"||
148 InstName == "GC_LABEL"||
150 InstName == "EXTRACT_SUBREG" ||
151 InstName == "INSERT_SUBREG" ||
152 InstName == "IMPLICIT_DEF" ||
153 InstName == "SUBREG_TO_REG" ||
154 InstName == "COPY_TO_REGCLASS" ||
155 InstName == "DEBUG_VALUE") continue;
157 BitsInit *BI = R->getValueAsBitsInit("Inst");
158 const std::vector<RecordVal> &Vals = R->getValues();
159 CodeGenInstruction &CGI = Target.getInstruction(InstName);
161 // Loop over all of the fields in the instruction, determining which are the
162 // operands to the instruction.
164 for (unsigned i = 0, e = Vals.size(); i != e; ++i) {
165 if (!Vals[i].getPrefix() && !Vals[i].getValue()->isComplete()) {
166 // Is the operand continuous? If so, we can just mask and OR it in
167 // instead of doing it bit-by-bit, saving a lot in runtime cost.
168 const std::string &VarName = Vals[i].getName();
171 for (int bit = BI->getNumBits()-1; bit >= 0; ) {
172 int varBit = getVariableBit(VarName, BI, bit);
177 int beginInstBit = bit;
178 int beginVarBit = varBit;
181 for (--bit; bit >= 0;) {
182 varBit = getVariableBit(VarName, BI, bit);
183 if (varBit == -1 || varBit != (beginVarBit - N)) break;
189 /// If this operand is not supposed to be emitted by the generated
190 /// emitter, skip it.
191 while (CGI.isFlatOperandNotEmitted(op))
194 Case += " // op: " + VarName + "\n"
195 + " op = getMachineOpValue(MI, MI.getOperand("
196 + utostr(op++) + "));\n";
200 unsigned opMask = ~0U >> (32-N);
201 int opShift = beginVarBit - N + 1;
203 opShift = beginInstBit - beginVarBit;
206 Case += " Value |= (op & " + utostr(opMask) + "U) << "
207 + itostr(opShift) + ";\n";
208 } else if (opShift < 0) {
209 Case += " Value |= (op & " + utostr(opMask) + "U) >> "
210 + itostr(-opShift) + ";\n";
212 Case += " Value |= op & " + utostr(opMask) + "U;\n";
219 std::vector<std::string> &InstList = CaseMap[Case];
220 InstList.push_back(InstName);
224 // Emit initial function code
225 o << " const unsigned opcode = MI.getOpcode();\n"
226 << " unsigned Value = InstBits[opcode];\n"
227 << " unsigned op = 0;\n"
228 << " op = op; // suppress warning\n"
229 << " switch (opcode) {\n";
231 // Emit each case statement
232 std::map<std::string, std::vector<std::string> >::iterator IE, EE;
233 for (IE = CaseMap.begin(), EE = CaseMap.end(); IE != EE; ++IE) {
234 const std::string &Case = IE->first;
235 std::vector<std::string> &InstList = IE->second;
237 for (int i = 0, N = InstList.size(); i < N; i++) {
239 o << " case " << Namespace << InstList[i] << ":";
247 // Default case: unhandled opcode
249 << " std::string msg;\n"
250 << " raw_string_ostream Msg(msg);\n"
251 << " Msg << \"Not supported instr: \" << MI;\n"
252 << " llvm_report_error(Msg.str());\n"
254 << " return Value;\n"