1 //===- CodeEmitterGen.cpp - Code Emitter Generator ------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // CodeEmitterGen uses the descriptions of instructions and their fields to
11 // construct an automated code emitter: a function that, given a MachineInstr,
12 // returns the (currently, 32-bit unsigned) value of the instruction.
14 //===----------------------------------------------------------------------===//
16 #include "CodeEmitterGen.h"
17 #include "CodeGenTarget.h"
19 #include "llvm/Support/Debug.h"
22 void CodeEmitterGen::emitInstrOpBits(std::ostream &o,
23 const std::vector<RecordVal> &Vals,
24 std::map<std::string, unsigned> &OpOrder,
25 std::map<std::string, bool> &OpContinuous)
27 for (unsigned f = 0, e = Vals.size(); f != e; ++f) {
28 if (Vals[f].getPrefix()) {
29 BitsInit *FieldInitializer = (BitsInit*)Vals[f].getValue();
31 // Scan through the field looking for bit initializers of the current
33 for (int i = FieldInitializer->getNumBits()-1; i >= 0; --i) {
34 Init *I = FieldInitializer->getBit(i);
35 if (BitInit *BI = dynamic_cast<BitInit*>(I)) {
36 DEBUG(o << " // bit init: f: " << f << ", i: " << i << "\n");
37 } else if (UnsetInit *UI = dynamic_cast<UnsetInit*>(I)) {
38 DEBUG(o << " // unset init: f: " << f << ", i: " << i << "\n");
39 } else if (VarBitInit *VBI = dynamic_cast<VarBitInit*>(I)) {
40 TypedInit *TI = VBI->getVariable();
41 if (VarInit *VI = dynamic_cast<VarInit*>(TI)) {
42 // If the bits of the field are laid out consecutively in the
43 // instruction, then instead of separately ORing in bits, just
44 // mask and shift the entire field for efficiency.
45 if (OpContinuous[VI->getName()]) {
46 // already taken care of in the loop above, thus there is no
47 // need to individually OR in the bits
49 // for debugging, output the regular version anyway, commented
50 DEBUG(o << " // Value |= getValueBit(op"
51 << OpOrder[VI->getName()] << ", " << VBI->getBitNum()
52 << ")" << " << " << i << ";\n");
54 o << " Value |= getValueBit(op" << OpOrder[VI->getName()]
55 << ", " << VBI->getBitNum()
56 << ")" << " << " << i << ";\n";
58 } else if (FieldInit *FI = dynamic_cast<FieldInit*>(TI)) {
59 // FIXME: implement this!
60 std::cerr << "Error: FieldInit not implemented!\n";
63 std::cerr << "Error: unimplemented case in "
64 << "CodeEmitterGen::emitInstrOpBits()\n";
74 void CodeEmitterGen::run(std::ostream &o) {
76 std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
78 EmitSourceFileHeader("Machine Code Emitter", o);
79 o << "namespace llvm {\n\n";
80 std::string Namespace = Insts[0]->getValueAsString("Namespace") + "::";
82 // Emit function declaration
83 o << "unsigned " << Target.getName() << "CodeEmitter::"
84 << "getBinaryCodeForInstr(MachineInstr &MI) {\n"
85 << " unsigned Value = 0;\n"
86 << " DEBUG(std::cerr << MI);\n"
87 << " switch (MI.getOpcode()) {\n";
89 // Emit a case statement for each opcode
90 for (std::vector<Record*>::iterator I = Insts.begin(), E = Insts.end();
93 o << " case " << Namespace << R->getName() << ": {\n"
94 << " DEBUG(std::cerr << \"Emitting " << R->getName() << "\\n\");\n";
96 BitsInit *BI = R->getValueAsBitsInit("Inst");
98 // For little-endian instruction bit encodings, reverse the bit order
99 if (Target.isLittleEndianEncoding()) {
100 unsigned numBits = BI->getNumBits();
101 BitsInit *NewBI = new BitsInit(numBits);
102 for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) {
103 unsigned bitSwapIdx = numBits - bit - 1;
104 Init *OrigBit = BI->getBit(bit);
105 Init *BitSwap = BI->getBit(bitSwapIdx);
106 NewBI->setBit(bit, BitSwap);
107 NewBI->setBit(bitSwapIdx, OrigBit);
110 unsigned middle = (numBits + 1) / 2;
111 NewBI->setBit(middle, BI->getBit(middle));
117 const std::vector<RecordVal> &Vals = R->getValues();
119 DEBUG(o << " // prefilling: ");
120 // Start by filling in fixed values...
121 for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i) {
122 if (BitInit *B = dynamic_cast<BitInit*>(BI->getBit(e-i-1))) {
123 Value |= B->getValue() << (e-i-1);
124 DEBUG(o << B->getValue());
131 DEBUG(o << " // " << *R->getValue("Inst") << "\n");
132 o << " Value = " << Value << "U;\n\n";
134 // Loop over all of the fields in the instruction, determining which are the
135 // operands to the instruction.
137 std::map<std::string, unsigned> OpOrder;
138 std::map<std::string, bool> OpContinuous;
139 for (unsigned i = 0, e = Vals.size(); i != e; ++i) {
140 if (!Vals[i].getPrefix() && !Vals[i].getValue()->isComplete()) {
141 // Is the operand continuous? If so, we can just mask and OR it in
142 // instead of doing it bit-by-bit, saving a lot in runtime cost.
143 BitsInit *InstInit = BI;
144 int beginBitInVar = -1, endBitInVar = -1;
145 int beginBitInInst = -1, endBitInInst = -1;
146 bool continuous = true;
148 for (int bit = InstInit->getNumBits()-1; bit >= 0; --bit) {
149 if (VarBitInit *VBI =
150 dynamic_cast<VarBitInit*>(InstInit->getBit(bit))) {
151 TypedInit *TI = VBI->getVariable();
152 if (VarInit *VI = dynamic_cast<VarInit*>(TI)) {
153 // only process the current variable
154 if (VI->getName() != Vals[i].getName())
157 if (beginBitInVar == -1)
158 beginBitInVar = VBI->getBitNum();
160 if (endBitInVar == -1)
161 endBitInVar = VBI->getBitNum();
163 if (endBitInVar == (int)VBI->getBitNum() + 1)
164 endBitInVar = VBI->getBitNum();
171 if (beginBitInInst == -1)
172 beginBitInInst = bit;
173 if (endBitInInst == -1)
176 if (endBitInInst == bit + 1)
184 // maintain same distance between bits in field and bits in
185 // instruction. if the relative distances stay the same
187 if (beginBitInVar - (int)VBI->getBitNum() !=
188 beginBitInInst - bit) {
196 // If we have found no bit in "Inst" which comes from this field, then
197 // this is not an operand!!
198 if (beginBitInInst != -1) {
199 o << " // op" << op << ": " << Vals[i].getName() << "\n"
200 << " int64_t op" << op
201 <<" = getMachineOpValue(MI, MI.getOperand("<<op<<"));\n";
202 //<< " MachineOperand &op" << op <<" = MI.getOperand("<<op<<");\n";
203 OpOrder[Vals[i].getName()] = op++;
205 DEBUG(o << " // Var: begin = " << beginBitInVar
206 << ", end = " << endBitInVar
207 << "; Inst: begin = " << beginBitInInst
208 << ", end = " << endBitInInst << "\n");
211 DEBUG(o << " // continuous: op" << OpOrder[Vals[i].getName()]
214 // Mask off the right bits
215 // Low mask (ie. shift, if necessary)
216 assert(endBitInVar >= 0 && "Negative shift amount in masking!");
217 if (endBitInVar != 0) {
218 o << " op" << OpOrder[Vals[i].getName()]
219 << " >>= " << endBitInVar << ";\n";
220 beginBitInVar -= endBitInVar;
225 o << " op" << OpOrder[Vals[i].getName()]
226 << " &= (1<<" << beginBitInVar+1 << ") - 1;\n";
228 // Shift the value to the correct place (according to place in inst)
229 assert(endBitInInst >= 0 && "Negative shift amount!");
230 if (endBitInInst != 0)
231 o << " op" << OpOrder[Vals[i].getName()]
232 << " <<= " << endBitInInst << ";\n";
234 // Just OR in the result
235 o << " Value |= op" << OpOrder[Vals[i].getName()] << ";\n";
238 // otherwise, will be taken care of in the loop below using this
240 OpContinuous[Vals[i].getName()] = continuous;
245 emitInstrOpBits(o, Vals, OpOrder, OpContinuous);
251 // Default case: unhandled opcode
253 << " std::cerr << \"Not supported instr: \" << MI << \"\\n\";\n"
256 << " return Value;\n"
259 o << "} // End llvm namespace \n";