1 //===- CodeEmitterGen.cpp - Code Emitter Generator ------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // CodeEmitterGen uses the descriptions of instructions and their fields to
11 // construct an automated code emitter: a function that, given a MachineInstr,
12 // returns the (currently, 32-bit unsigned) value of the instruction.
14 //===----------------------------------------------------------------------===//
16 #include "CodeGenTarget.h"
17 #include "llvm/ADT/StringExtras.h"
18 #include "llvm/Support/CommandLine.h"
19 #include "llvm/Support/Debug.h"
20 #include "llvm/TableGen/Record.h"
21 #include "llvm/TableGen/TableGenBackend.h"
27 // FIXME: Somewhat hackish to use a command line option for this. There should
28 // be a CodeEmitter class in the Target.td that controls this sort of thing
31 MCEmitter("mc-emitter",
32 cl::desc("Generate CodeEmitter for use with the MC library."),
37 class CodeEmitterGen {
38 RecordKeeper &Records;
40 CodeEmitterGen(RecordKeeper &R) : Records(R) {}
42 void run(raw_ostream &o);
44 void emitMachineOpEmitter(raw_ostream &o, const std::string &Namespace);
45 void emitGetValueBit(raw_ostream &o, const std::string &Namespace);
46 int getVariableBit(const std::string &VarName, BitsInit *BI, int bit);
47 std::string getInstructionCase(Record *R, CodeGenTarget &Target);
48 void AddCodeToMergeInOperand(Record *R, BitsInit *BI,
49 const std::string &VarName,
51 std::string &Case, CodeGenTarget &Target);
55 // If the VarBitInit at position 'bit' matches the specified variable then
56 // return the variable bit position. Otherwise return -1.
57 int CodeEmitterGen::getVariableBit(const std::string &VarName,
58 BitsInit *BI, int bit) {
59 if (VarBitInit *VBI = dyn_cast<VarBitInit>(BI->getBit(bit))) {
60 if (VarInit *VI = dyn_cast<VarInit>(VBI->getBitVar()))
61 if (VI->getName() == VarName)
62 return VBI->getBitNum();
63 } else if (VarInit *VI = dyn_cast<VarInit>(BI->getBit(bit))) {
64 if (VI->getName() == VarName)
72 AddCodeToMergeInOperand(Record *R, BitsInit *BI, const std::string &VarName,
74 std::string &Case, CodeGenTarget &Target) {
75 CodeGenInstruction &CGI = Target.getInstruction(R);
77 // Determine if VarName actually contributes to the Inst encoding.
78 int bit = BI->getNumBits()-1;
80 // Scan for a bit that this contributed to.
82 if (getVariableBit(VarName, BI, bit) != -1)
88 // If we found no bits, ignore this value, otherwise emit the call to get the
92 // If the operand matches by name, reference according to that
93 // operand number. Non-matching operands are assumed to be in
96 if (CGI.Operands.hasOperandNamed(VarName, OpIdx)) {
97 // Get the machine operand number for the indicated operand.
98 OpIdx = CGI.Operands[OpIdx].MIOperandNo;
99 assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) &&
100 "Explicitly used operand also marked as not emitted!");
102 unsigned NumberOps = CGI.Operands.size();
103 /// If this operand is not supposed to be emitted by the
104 /// generated emitter, skip it.
105 while (NumberedOp < NumberOps &&
106 CGI.Operands.isFlatOperandNotEmitted(NumberedOp))
109 OpIdx = NumberedOp++;
112 std::pair<unsigned, unsigned> SO = CGI.Operands.getSubOperandNumber(OpIdx);
113 std::string &EncoderMethodName = CGI.Operands[SO.first].EncoderMethodName;
115 // If the source operand has a custom encoder, use it. This will
116 // get the encoding for all of the suboperands.
117 if (!EncoderMethodName.empty()) {
118 // A custom encoder has all of the information for the
119 // sub-operands, if there are more than one, so only
120 // query the encoder once per source operand.
121 if (SO.second == 0) {
122 Case += " // op: " + VarName + "\n" +
123 " op = " + EncoderMethodName + "(MI, " + utostr(OpIdx);
129 Case += " // op: " + VarName + "\n" +
130 " op = getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")";
137 int varBit = getVariableBit(VarName, BI, bit);
139 // If this bit isn't from a variable, skip it.
145 // Figure out the consecutive range of bits covered by this operand, in
146 // order to generate better encoding code.
147 int beginInstBit = bit;
148 int beginVarBit = varBit;
150 for (--bit; bit >= 0;) {
151 varBit = getVariableBit(VarName, BI, bit);
152 if (varBit == -1 || varBit != (beginVarBit - N)) break;
157 uint64_t opMask = ~(uint64_t)0 >> (64-N);
158 int opShift = beginVarBit - N + 1;
160 opShift = beginInstBit - beginVarBit;
163 Case += " Value |= (op & UINT64_C(" + utostr(opMask) + ")) << " +
164 itostr(opShift) + ";\n";
165 } else if (opShift < 0) {
166 Case += " Value |= (op & UINT64_C(" + utostr(opMask) + ")) >> " +
167 itostr(-opShift) + ";\n";
169 Case += " Value |= op & UINT64_C(" + utostr(opMask) + ");\n";
175 std::string CodeEmitterGen::getInstructionCase(Record *R,
176 CodeGenTarget &Target) {
179 BitsInit *BI = R->getValueAsBitsInit("Inst");
180 const std::vector<RecordVal> &Vals = R->getValues();
181 unsigned NumberedOp = 0;
183 // Loop over all of the fields in the instruction, determining which are the
184 // operands to the instruction.
185 for (unsigned i = 0, e = Vals.size(); i != e; ++i) {
186 // Ignore fixed fields in the record, we're looking for values like:
187 // bits<5> RST = { ?, ?, ?, ?, ? };
188 if (Vals[i].getPrefix() || Vals[i].getValue()->isComplete())
191 AddCodeToMergeInOperand(R, BI, Vals[i].getName(), NumberedOp, Case, Target);
194 std::string PostEmitter = R->getValueAsString("PostEncoderMethod");
195 if (!PostEmitter.empty())
196 Case += " Value = " + PostEmitter + "(MI, Value);\n";
201 void CodeEmitterGen::run(raw_ostream &o) {
202 CodeGenTarget Target(Records);
203 std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
205 // For little-endian instruction bit encodings, reverse the bit order
206 Target.reverseBitsForLittleEndianEncoding();
208 const std::vector<const CodeGenInstruction*> &NumberedInstructions =
209 Target.getInstructionsByEnumValue();
211 // Emit function declaration
212 o << "uint64_t " << Target.getName();
214 o << "MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,\n"
215 << " SmallVectorImpl<MCFixup> &Fixups) const {\n";
217 o << "CodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) const {\n";
219 // Emit instruction base values
220 o << " static const uint64_t InstBits[] = {\n";
221 for (std::vector<const CodeGenInstruction*>::const_iterator
222 IN = NumberedInstructions.begin(),
223 EN = NumberedInstructions.end();
225 const CodeGenInstruction *CGI = *IN;
226 Record *R = CGI->TheDef;
228 if (R->getValueAsString("Namespace") == "TargetOpcode" ||
229 R->getValueAsBit("isPseudo")) {
230 o << " UINT64_C(0),\n";
234 BitsInit *BI = R->getValueAsBitsInit("Inst");
236 // Start by filling in fixed values.
238 for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i) {
239 if (BitInit *B = dyn_cast<BitInit>(BI->getBit(e-i-1)))
240 Value |= (uint64_t)B->getValue() << (e-i-1);
242 o << " UINT64_C(" << Value << ")," << '\t' << "// " << R->getName() << "\n";
244 o << " UINT64_C(0)\n };\n";
246 // Map to accumulate all the cases.
247 std::map<std::string, std::vector<std::string> > CaseMap;
249 // Construct all cases statement for each opcode
250 for (std::vector<Record*>::iterator IC = Insts.begin(), EC = Insts.end();
253 if (R->getValueAsString("Namespace") == "TargetOpcode" ||
254 R->getValueAsBit("isPseudo"))
256 const std::string &InstName = R->getValueAsString("Namespace") + "::"
258 std::string Case = getInstructionCase(R, Target);
260 CaseMap[Case].push_back(InstName);
263 // Emit initial function code
264 o << " const unsigned opcode = MI.getOpcode();\n"
265 << " uint64_t Value = InstBits[opcode];\n"
266 << " uint64_t op = 0;\n"
267 << " (void)op; // suppress warning\n"
268 << " switch (opcode) {\n";
270 // Emit each case statement
271 std::map<std::string, std::vector<std::string> >::iterator IE, EE;
272 for (IE = CaseMap.begin(), EE = CaseMap.end(); IE != EE; ++IE) {
273 const std::string &Case = IE->first;
274 std::vector<std::string> &InstList = IE->second;
276 for (int i = 0, N = InstList.size(); i < N; i++) {
278 o << " case " << InstList[i] << ":";
286 // Default case: unhandled opcode
288 << " std::string msg;\n"
289 << " raw_string_ostream Msg(msg);\n"
290 << " Msg << \"Not supported instr: \" << MI;\n"
291 << " report_fatal_error(Msg.str());\n"
293 << " return Value;\n"
297 } // End anonymous namespace
301 void EmitCodeEmitter(RecordKeeper &RK, raw_ostream &OS) {
302 emitSourceFileHeader("Machine Code Emitter", OS);
303 CodeEmitterGen(RK).run(OS);
306 } // End llvm namespace