1 //===- CodeEmitterGen.cpp - Code Emitter Generator ------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // CodeEmitterGen uses the descriptions of instructions and their fields to
11 // construct an automated code emitter: a function that, given a MachineInstr,
12 // returns the (currently, 32-bit unsigned) value of the instruction.
14 //===----------------------------------------------------------------------===//
16 #include "CodeGenTarget.h"
17 #include "llvm/ADT/StringExtras.h"
18 #include "llvm/Support/CommandLine.h"
19 #include "llvm/Support/Debug.h"
20 #include "llvm/TableGen/Record.h"
21 #include "llvm/TableGen/TableGenBackend.h"
27 // FIXME: Somewhat hackish to use a command line option for this. There should
28 // be a CodeEmitter class in the Target.td that controls this sort of thing
31 MCEmitter("mc-emitter",
32 cl::desc("Generate CodeEmitter for use with the MC library."),
37 class CodeEmitterGen {
38 RecordKeeper &Records;
40 CodeEmitterGen(RecordKeeper &R) : Records(R) {}
42 void run(raw_ostream &o);
44 void emitMachineOpEmitter(raw_ostream &o, const std::string &Namespace);
45 void emitGetValueBit(raw_ostream &o, const std::string &Namespace);
46 int getVariableBit(const std::string &VarName, BitsInit *BI, int bit);
47 std::string getInstructionCase(Record *R, CodeGenTarget &Target);
48 void AddCodeToMergeInOperand(Record *R, BitsInit *BI,
49 const std::string &VarName,
51 std::set<unsigned> &NamedOpIndices,
52 std::string &Case, CodeGenTarget &Target);
56 // If the VarBitInit at position 'bit' matches the specified variable then
57 // return the variable bit position. Otherwise return -1.
58 int CodeEmitterGen::getVariableBit(const std::string &VarName,
59 BitsInit *BI, int bit) {
60 if (VarBitInit *VBI = dyn_cast<VarBitInit>(BI->getBit(bit))) {
61 if (VarInit *VI = dyn_cast<VarInit>(VBI->getBitVar()))
62 if (VI->getName() == VarName)
63 return VBI->getBitNum();
64 } else if (VarInit *VI = dyn_cast<VarInit>(BI->getBit(bit))) {
65 if (VI->getName() == VarName)
73 AddCodeToMergeInOperand(Record *R, BitsInit *BI, const std::string &VarName,
75 std::set<unsigned> &NamedOpIndices,
76 std::string &Case, CodeGenTarget &Target) {
77 CodeGenInstruction &CGI = Target.getInstruction(R);
79 // Determine if VarName actually contributes to the Inst encoding.
80 int bit = BI->getNumBits()-1;
82 // Scan for a bit that this contributed to.
84 if (getVariableBit(VarName, BI, bit) != -1)
90 // If we found no bits, ignore this value, otherwise emit the call to get the
94 // If the operand matches by name, reference according to that
95 // operand number. Non-matching operands are assumed to be in
98 if (CGI.Operands.hasOperandNamed(VarName, OpIdx)) {
99 // Get the machine operand number for the indicated operand.
100 OpIdx = CGI.Operands[OpIdx].MIOperandNo;
101 assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) &&
102 "Explicitly used operand also marked as not emitted!");
104 unsigned NumberOps = CGI.Operands.size();
105 /// If this operand is not supposed to be emitted by the
106 /// generated emitter, skip it.
107 while (NumberedOp < NumberOps &&
108 (CGI.Operands.isFlatOperandNotEmitted(NumberedOp) ||
109 (NamedOpIndices.size() && NamedOpIndices.count(
110 CGI.Operands.getSubOperandNumber(NumberedOp).first)))) {
113 if (NumberedOp >= CGI.Operands.back().MIOperandNo +
114 CGI.Operands.back().MINumOperands) {
115 errs() << "Too few operands in record " << R->getName() <<
116 " (no match for variable " << VarName << "):\n";
124 OpIdx = NumberedOp++;
127 std::pair<unsigned, unsigned> SO = CGI.Operands.getSubOperandNumber(OpIdx);
128 std::string &EncoderMethodName = CGI.Operands[SO.first].EncoderMethodName;
130 // If the source operand has a custom encoder, use it. This will
131 // get the encoding for all of the suboperands.
132 if (!EncoderMethodName.empty()) {
133 // A custom encoder has all of the information for the
134 // sub-operands, if there are more than one, so only
135 // query the encoder once per source operand.
136 if (SO.second == 0) {
137 Case += " // op: " + VarName + "\n" +
138 " op = " + EncoderMethodName + "(MI, " + utostr(OpIdx);
140 Case += ", Fixups, STI";
144 Case += " // op: " + VarName + "\n" +
145 " op = getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")";
147 Case += ", Fixups, STI";
152 int varBit = getVariableBit(VarName, BI, bit);
154 // If this bit isn't from a variable, skip it.
160 // Figure out the consecutive range of bits covered by this operand, in
161 // order to generate better encoding code.
162 int beginInstBit = bit;
163 int beginVarBit = varBit;
165 for (--bit; bit >= 0;) {
166 varBit = getVariableBit(VarName, BI, bit);
167 if (varBit == -1 || varBit != (beginVarBit - N)) break;
172 uint64_t opMask = ~(uint64_t)0 >> (64-N);
173 int opShift = beginVarBit - N + 1;
175 opShift = beginInstBit - beginVarBit;
178 Case += " Value |= (op & UINT64_C(" + utostr(opMask) + ")) << " +
179 itostr(opShift) + ";\n";
180 } else if (opShift < 0) {
181 Case += " Value |= (op & UINT64_C(" + utostr(opMask) + ")) >> " +
182 itostr(-opShift) + ";\n";
184 Case += " Value |= op & UINT64_C(" + utostr(opMask) + ");\n";
190 std::string CodeEmitterGen::getInstructionCase(Record *R,
191 CodeGenTarget &Target) {
194 BitsInit *BI = R->getValueAsBitsInit("Inst");
195 const std::vector<RecordVal> &Vals = R->getValues();
196 unsigned NumberedOp = 0;
198 std::set<unsigned> NamedOpIndices;
199 // Collect the set of operand indices that might correspond to named
200 // operand, and skip these when assigning operands based on position.
201 if (Target.getInstructionSet()->
202 getValueAsBit("noNamedPositionallyEncodedOperands")) {
203 CodeGenInstruction &CGI = Target.getInstruction(R);
204 for (unsigned i = 0, e = Vals.size(); i != e; ++i) {
206 if (!CGI.Operands.hasOperandNamed(Vals[i].getName(), OpIdx))
209 NamedOpIndices.insert(OpIdx);
213 // Loop over all of the fields in the instruction, determining which are the
214 // operands to the instruction.
215 for (unsigned i = 0, e = Vals.size(); i != e; ++i) {
216 // Ignore fixed fields in the record, we're looking for values like:
217 // bits<5> RST = { ?, ?, ?, ?, ? };
218 if (Vals[i].getPrefix() || Vals[i].getValue()->isComplete())
221 AddCodeToMergeInOperand(R, BI, Vals[i].getName(), NumberedOp,
222 NamedOpIndices, Case, Target);
225 std::string PostEmitter = R->getValueAsString("PostEncoderMethod");
226 if (!PostEmitter.empty()) {
227 Case += " Value = " + PostEmitter + "(MI, Value";
236 void CodeEmitterGen::run(raw_ostream &o) {
237 CodeGenTarget Target(Records);
238 std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
240 // For little-endian instruction bit encodings, reverse the bit order
241 Target.reverseBitsForLittleEndianEncoding();
243 const std::vector<const CodeGenInstruction*> &NumberedInstructions =
244 Target.getInstructionsByEnumValue();
246 // Emit function declaration
247 o << "uint64_t " << Target.getName();
249 o << "MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,\n"
250 << " SmallVectorImpl<MCFixup> &Fixups,\n"
251 << " const MCSubtargetInfo &STI) const {\n";
253 o << "CodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) const {\n";
255 // Emit instruction base values
256 o << " static const uint64_t InstBits[] = {\n";
257 for (std::vector<const CodeGenInstruction*>::const_iterator
258 IN = NumberedInstructions.begin(),
259 EN = NumberedInstructions.end();
261 const CodeGenInstruction *CGI = *IN;
262 Record *R = CGI->TheDef;
264 if (R->getValueAsString("Namespace") == "TargetOpcode" ||
265 R->getValueAsBit("isPseudo")) {
266 o << " UINT64_C(0),\n";
270 BitsInit *BI = R->getValueAsBitsInit("Inst");
272 // Start by filling in fixed values.
274 for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i) {
275 if (BitInit *B = dyn_cast<BitInit>(BI->getBit(e-i-1)))
276 Value |= (uint64_t)B->getValue() << (e-i-1);
278 o << " UINT64_C(" << Value << ")," << '\t' << "// " << R->getName() << "\n";
280 o << " UINT64_C(0)\n };\n";
282 // Map to accumulate all the cases.
283 std::map<std::string, std::vector<std::string> > CaseMap;
285 // Construct all cases statement for each opcode
286 for (std::vector<Record*>::iterator IC = Insts.begin(), EC = Insts.end();
289 if (R->getValueAsString("Namespace") == "TargetOpcode" ||
290 R->getValueAsBit("isPseudo"))
292 const std::string &InstName = R->getValueAsString("Namespace") + "::"
294 std::string Case = getInstructionCase(R, Target);
296 CaseMap[Case].push_back(InstName);
299 // Emit initial function code
300 o << " const unsigned opcode = MI.getOpcode();\n"
301 << " uint64_t Value = InstBits[opcode];\n"
302 << " uint64_t op = 0;\n"
303 << " (void)op; // suppress warning\n"
304 << " switch (opcode) {\n";
306 // Emit each case statement
307 std::map<std::string, std::vector<std::string> >::iterator IE, EE;
308 for (IE = CaseMap.begin(), EE = CaseMap.end(); IE != EE; ++IE) {
309 const std::string &Case = IE->first;
310 std::vector<std::string> &InstList = IE->second;
312 for (int i = 0, N = InstList.size(); i < N; i++) {
314 o << " case " << InstList[i] << ":";
322 // Default case: unhandled opcode
324 << " std::string msg;\n"
325 << " raw_string_ostream Msg(msg);\n"
326 << " Msg << \"Not supported instr: \" << MI;\n"
327 << " report_fatal_error(Msg.str());\n"
329 << " return Value;\n"
333 } // End anonymous namespace
337 void EmitCodeEmitter(RecordKeeper &RK, raw_ostream &OS) {
338 emitSourceFileHeader("Machine Code Emitter", OS);
339 CodeEmitterGen(RK).run(OS);
342 } // End llvm namespace