1 //===- CodeEmitterGen.cpp - Code Emitter Generator ------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // CodeEmitterGen uses the descriptions of instructions and their fields to
11 // construct an automated code emitter: a function that, given a MachineInstr,
12 // returns the (currently, 32-bit unsigned) value of the instruction.
14 //===----------------------------------------------------------------------===//
16 #include "CodeEmitterGen.h"
17 #include "CodeGenTarget.h"
19 #include "llvm/Support/Debug.h"
22 void CodeEmitterGen::run(std::ostream &o) {
24 std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
26 EmitSourceFileHeader("Machine Code Emitter", o);
27 o << "namespace llvm {\n\n";
28 std::string Namespace = Insts[0]->getValueAsString("Namespace") + "::";
30 // Emit function declaration
31 o << "unsigned " << Target.getName() << "CodeEmitter::"
32 << "getBinaryCodeForInstr(MachineInstr &MI) {\n"
33 << " unsigned Value = 0;\n"
34 << " DEBUG(std::cerr << MI);\n"
35 << " switch (MI.getOpcode()) {\n";
37 // Emit a case statement for each opcode
38 for (std::vector<Record*>::iterator I = Insts.begin(), E = Insts.end();
41 o << " case " << Namespace << R->getName() << ": {\n"
42 << " DEBUG(std::cerr << \"Emitting " << R->getName() << "\\n\");\n";
44 BitsInit *BI = R->getValueAsBitsInit("Inst");
47 const std::vector<RecordVal> &Vals = R->getValues();
49 DEBUG(o << " // prefilling: ");
50 // Start by filling in fixed values...
51 for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i) {
52 if (BitInit *B = dynamic_cast<BitInit*>(BI->getBit(e-i-1))) {
53 Value |= B->getValue() << (e-i-1);
54 DEBUG(o << B->getValue());
61 DEBUG(o << " // " << *R->getValue("Inst") << "\n");
62 o << " Value = " << Value << "U;\n\n";
64 // Loop over all of the fields in the instruction determining which are the
65 // operands to the instruction.
68 std::map<std::string, unsigned> OpOrder;
69 std::map<std::string, bool> OpContinuous;
70 for (unsigned i = 0, e = Vals.size(); i != e; ++i) {
71 if (!Vals[i].getPrefix() && !Vals[i].getValue()->isComplete()) {
72 // Is the operand continuous? If so, we can just mask and OR it in
73 // instead of doing it bit-by-bit, saving a lot in runtime cost.
74 const BitsInit *InstInit = BI;
75 int beginBitInVar = -1, endBitInVar = -1;
76 int beginBitInInst = -1, endBitInInst = -1;
77 bool continuous = true;
79 for (int bit = InstInit->getNumBits()-1; bit >= 0; --bit) {
81 dynamic_cast<VarBitInit*>(InstInit->getBit(bit))) {
82 TypedInit *TI = VBI->getVariable();
83 if (VarInit *VI = dynamic_cast<VarInit*>(TI)) {
84 // only process the current variable
85 if (VI->getName() != Vals[i].getName())
88 if (beginBitInVar == -1)
89 beginBitInVar = VBI->getBitNum();
91 if (endBitInVar == -1)
92 endBitInVar = VBI->getBitNum();
94 if (endBitInVar == (int)VBI->getBitNum() + 1)
95 endBitInVar = VBI->getBitNum();
102 if (beginBitInInst == -1)
103 beginBitInInst = bit;
104 if (endBitInInst == -1)
107 if (endBitInInst == bit + 1)
115 // maintain same distance between bits in field and bits in
116 // instruction. if the relative distances stay the same
118 if (beginBitInVar - (int)VBI->getBitNum() !=
119 beginBitInInst - bit) {
127 // If we have found no bit in "Inst" which comes from this field, then
128 // this is not an operand!!
129 if (beginBitInInst != -1) {
130 o << " // op" << op << ": " << Vals[i].getName() << "\n"
131 << " int64_t op" << op
132 <<" = getMachineOpValue(MI, MI.getOperand("<<op<<"));\n";
133 //<< " MachineOperand &op" << op <<" = MI.getOperand("<<op<<");\n";
134 OpOrder[Vals[i].getName()] = op++;
136 DEBUG(o << " // Var: begin = " << beginBitInVar
137 << ", end = " << endBitInVar
138 << "; Inst: begin = " << beginBitInInst
139 << ", end = " << endBitInInst << "\n");
142 DEBUG(o << " // continuous: op" << OpOrder[Vals[i].getName()]
145 // Mask off the right bits
146 // Low mask (ie. shift, if necessary)
147 assert(endBitInVar >= 0 && "Negative shift amount in masking!");
148 if (endBitInVar != 0) {
149 o << " op" << OpOrder[Vals[i].getName()]
150 << " >>= " << endBitInVar << ";\n";
151 beginBitInVar -= endBitInVar;
156 o << " op" << OpOrder[Vals[i].getName()]
157 << " &= (1<<" << beginBitInVar+1 << ") - 1;\n";
159 // Shift the value to the correct place (according to place in inst)
160 assert(endBitInInst >= 0 && "Negative shift amount!");
161 if (endBitInInst != 0)
162 o << " op" << OpOrder[Vals[i].getName()]
163 << " <<= " << endBitInInst << ";\n";
165 // Just OR in the result
166 o << " Value |= op" << OpOrder[Vals[i].getName()] << ";\n";
169 // otherwise, will be taken care of in the loop below using this
171 OpContinuous[Vals[i].getName()] = continuous;
176 for (unsigned f = 0, e = Vals.size(); f != e; ++f) {
177 if (Vals[f].getPrefix()) {
178 BitsInit *FieldInitializer = (BitsInit*)Vals[f].getValue();
180 // Scan through the field looking for bit initializers of the current
182 for (int i = FieldInitializer->getNumBits()-1; i >= 0; --i) {
183 Init *I = FieldInitializer->getBit(i);
184 if (BitInit *BI = dynamic_cast<BitInit*>(I)) {
185 DEBUG(o << " // bit init: f: " << f << ", i: " << i << "\n");
186 } else if (UnsetInit *UI = dynamic_cast<UnsetInit*>(I)) {
187 DEBUG(o << " // unset init: f: " << f << ", i: " << i << "\n");
188 } else if (VarBitInit *VBI = dynamic_cast<VarBitInit*>(I)) {
189 TypedInit *TI = VBI->getVariable();
190 if (VarInit *VI = dynamic_cast<VarInit*>(TI)) {
191 // If the bits of the field are laid out consecutively in the
192 // instruction, then instead of separately ORing in bits, just
193 // mask and shift the entire field for efficiency.
194 if (OpContinuous[VI->getName()]) {
195 // already taken care of in the loop above, thus there is no
196 // need to individually OR in the bits
198 // for debugging, output the regular version anyway, commented
199 DEBUG(o << " // Value |= getValueBit(op"
200 << OpOrder[VI->getName()] << ", " << VBI->getBitNum()
201 << ")" << " << " << i << ";\n");
203 o << " Value |= getValueBit(op" << OpOrder[VI->getName()]
204 << ", " << VBI->getBitNum()
205 << ")" << " << " << i << ";\n";
207 } else if (FieldInit *FI = dynamic_cast<FieldInit*>(TI)) {
208 // FIXME: implement this!
209 o << "FIELD INIT not implemented yet!\n";
211 o << "Error: UNIMPLEMENTED\n";
223 << " std::cerr << \"Not supported instr: \" << MI << \"\\n\";\n"
226 << " return Value;\n"
229 o << "} // End llvm namespace \n";