1 //===- CodeEmitterGen.cpp - Code Emitter Generator ------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // CodeEmitterGen uses the descriptions of instructions and their fields to
11 // construct an automated code emitter: a function that, given a MachineInstr,
12 // returns the (currently, 32-bit unsigned) value of the instruction.
14 //===----------------------------------------------------------------------===//
16 #include "CodeEmitterGen.h"
17 #include "CodeGenTarget.h"
19 #include "llvm/ADT/StringExtras.h"
20 #include "llvm/Support/Debug.h"
23 void CodeEmitterGen::reverseBits(std::vector<Record*> &Insts) {
24 for (std::vector<Record*>::iterator I = Insts.begin(), E = Insts.end();
27 if (R->getName() == "PHI" ||
28 R->getName() == "INLINEASM" ||
29 R->getName() == "LABEL" ||
30 R->getName() == "DECLARE" ||
31 R->getName() == "EXTRACT_SUBREG" ||
32 R->getName() == "INSERT_SUBREG") continue;
34 BitsInit *BI = R->getValueAsBitsInit("Inst");
36 unsigned numBits = BI->getNumBits();
37 BitsInit *NewBI = new BitsInit(numBits);
38 for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) {
39 unsigned bitSwapIdx = numBits - bit - 1;
40 Init *OrigBit = BI->getBit(bit);
41 Init *BitSwap = BI->getBit(bitSwapIdx);
42 NewBI->setBit(bit, BitSwap);
43 NewBI->setBit(bitSwapIdx, OrigBit);
46 unsigned middle = (numBits + 1) / 2;
47 NewBI->setBit(middle, BI->getBit(middle));
50 // Update the bits in reversed order so that emitInstrOpBits will get the
51 // correct endianness.
52 R->getValue("Inst")->setValue(NewBI);
57 // If the VarBitInit at position 'bit' matches the specified variable then
58 // return the variable bit position. Otherwise return -1.
59 int CodeEmitterGen::getVariableBit(const std::string &VarName,
60 BitsInit *BI, int bit) {
61 if (VarBitInit *VBI = dynamic_cast<VarBitInit*>(BI->getBit(bit))) {
62 TypedInit *TI = VBI->getVariable();
64 if (VarInit *VI = dynamic_cast<VarInit*>(TI)) {
65 if (VI->getName() == VarName) return VBI->getBitNum();
73 void CodeEmitterGen::run(std::ostream &o) {
75 std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
77 // For little-endian instruction bit encodings, reverse the bit order
78 if (Target.isLittleEndianEncoding()) reverseBits(Insts);
80 EmitSourceFileHeader("Machine Code Emitter", o);
81 std::string Namespace = Insts[0]->getValueAsString("Namespace") + "::";
83 std::vector<const CodeGenInstruction*> NumberedInstructions;
84 Target.getInstructionsByEnumValue(NumberedInstructions);
86 // Emit function declaration
87 o << "unsigned " << Target.getName() << "CodeEmitter::"
88 << "getBinaryCodeForInstr(MachineInstr &MI) {\n";
90 // Emit instruction base values
91 o << " static const unsigned InstBits[] = {\n";
92 for (std::vector<const CodeGenInstruction*>::iterator
93 IN = NumberedInstructions.begin(),
94 EN = NumberedInstructions.end();
96 const CodeGenInstruction *CGI = *IN;
97 Record *R = CGI->TheDef;
99 if (IN != NumberedInstructions.begin()) o << ",\n";
101 if (R->getName() == "PHI" ||
102 R->getName() == "INLINEASM" ||
103 R->getName() == "LABEL" ||
104 R->getName() == "DECLARE" ||
105 R->getName() == "EXTRACT_SUBREG" ||
106 R->getName() == "INSERT_SUBREG") {
111 BitsInit *BI = R->getValueAsBitsInit("Inst");
113 // Start by filling in fixed values...
115 for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i) {
116 if (BitInit *B = dynamic_cast<BitInit*>(BI->getBit(e-i-1))) {
117 Value |= B->getValue() << (e-i-1);
120 o << " " << Value << "U";
124 // Map to accumulate all the cases.
125 std::map<std::string, std::vector<std::string> > CaseMap;
127 // Construct all cases statement for each opcode
128 for (std::vector<Record*>::iterator IC = Insts.begin(), EC = Insts.end();
131 const std::string &InstName = R->getName();
132 std::string Case("");
134 if (InstName == "PHI" ||
135 InstName == "INLINEASM" ||
136 InstName == "LABEL"||
137 InstName == "DECLARE"||
138 InstName == "EXTRACT_SUBREG" ||
139 InstName == "INSERT_SUBREG") continue;
141 BitsInit *BI = R->getValueAsBitsInit("Inst");
142 const std::vector<RecordVal> &Vals = R->getValues();
143 CodeGenInstruction &CGI = Target.getInstruction(InstName);
145 // Loop over all of the fields in the instruction, determining which are the
146 // operands to the instruction.
148 for (unsigned i = 0, e = Vals.size(); i != e; ++i) {
149 if (!Vals[i].getPrefix() && !Vals[i].getValue()->isComplete()) {
150 // Is the operand continuous? If so, we can just mask and OR it in
151 // instead of doing it bit-by-bit, saving a lot in runtime cost.
152 const std::string &VarName = Vals[i].getName();
155 for (int bit = BI->getNumBits()-1; bit >= 0; ) {
156 int varBit = getVariableBit(VarName, BI, bit);
161 int beginInstBit = bit;
162 int beginVarBit = varBit;
165 for (--bit; bit >= 0;) {
166 varBit = getVariableBit(VarName, BI, bit);
167 if (varBit == -1 || varBit != (beginVarBit - N)) break;
173 /// If this operand is not supposed to be emitted by the generated
174 /// emitter, skip it.
175 while (CGI.isFlatOperandNotEmitted(op))
178 Case += " // op: " + VarName + "\n"
179 + " op = getMachineOpValue(MI, MI.getOperand("
180 + utostr(op++) + "));\n";
184 unsigned opMask = (1 << N) - 1;
185 int opShift = beginVarBit - N + 1;
187 opShift = beginInstBit - beginVarBit;
190 Case += " Value |= (op & " + utostr(opMask) + "U) << "
191 + itostr(opShift) + ";\n";
192 } else if (opShift < 0) {
193 Case += " Value |= (op & " + utostr(opMask) + "U) >> "
194 + itostr(-opShift) + ";\n";
196 Case += " Value |= op & " + utostr(opMask) + "U;\n";
203 std::vector<std::string> &InstList = CaseMap[Case];
204 InstList.push_back(InstName);
208 // Emit initial function code
209 o << " const unsigned opcode = MI.getOpcode();\n"
210 << " unsigned Value = InstBits[opcode];\n"
212 << " switch (opcode) {\n";
214 // Emit each case statement
215 std::map<std::string, std::vector<std::string> >::iterator IE, EE;
216 for (IE = CaseMap.begin(), EE = CaseMap.end(); IE != EE; ++IE) {
217 const std::string &Case = IE->first;
218 std::vector<std::string> &InstList = IE->second;
220 for (int i = 0, N = InstList.size(); i < N; i++) {
222 o << " case " << Namespace << InstList[i] << ":";
230 // Default case: unhandled opcode
232 << " cerr << \"Not supported instr: \" << MI << \"\\n\";\n"
235 << " return Value;\n"