1 //===- CodeEmitterGen.cpp - Code Emitter Generator ------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // CodeEmitterGen uses the descriptions of instructions and their fields to
11 // construct an automated code emitter: a function that, given a MachineInstr,
12 // returns the (currently, 32-bit unsigned) value of the instruction.
14 //===----------------------------------------------------------------------===//
16 #include "CodeEmitterGen.h"
17 #include "CodeGenTarget.h"
19 #include "llvm/ADT/StringExtras.h"
20 #include "llvm/Support/Debug.h"
23 void CodeEmitterGen::reverseBits(std::vector<Record*> &Insts) {
24 for (std::vector<Record*>::iterator I = Insts.begin(), E = Insts.end();
27 if (R->getName() == "PHI" || R->getName() == "INLINEASM") continue;
29 BitsInit *BI = R->getValueAsBitsInit("Inst");
31 unsigned numBits = BI->getNumBits();
32 BitsInit *NewBI = new BitsInit(numBits);
33 for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) {
34 unsigned bitSwapIdx = numBits - bit - 1;
35 Init *OrigBit = BI->getBit(bit);
36 Init *BitSwap = BI->getBit(bitSwapIdx);
37 NewBI->setBit(bit, BitSwap);
38 NewBI->setBit(bitSwapIdx, OrigBit);
41 unsigned middle = (numBits + 1) / 2;
42 NewBI->setBit(middle, BI->getBit(middle));
45 // Update the bits in reversed order so that emitInstrOpBits will get the
46 // correct endianness.
47 R->getValue("Inst")->setValue(NewBI);
52 // If the VarBitInit at position 'bit' matches the specified variable then
53 // return the variable bit position. Otherwise return -1.
54 int CodeEmitterGen::getVariableBit(const std::string &VarName,
55 BitsInit *BI, int bit) {
56 if (VarBitInit *VBI = dynamic_cast<VarBitInit*>(BI->getBit(bit))) {
57 TypedInit *TI = VBI->getVariable();
59 if (VarInit *VI = dynamic_cast<VarInit*>(TI)) {
60 if (VI->getName() == VarName) return VBI->getBitNum();
68 void CodeEmitterGen::run(std::ostream &o) {
70 std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
72 // For little-endian instruction bit encodings, reverse the bit order
73 if (Target.isLittleEndianEncoding()) reverseBits(Insts);
75 EmitSourceFileHeader("Machine Code Emitter", o);
76 std::string Namespace = Insts[0]->getValueAsString("Namespace") + "::";
78 std::vector<const CodeGenInstruction*> NumberedInstructions;
79 Target.getInstructionsByEnumValue(NumberedInstructions);
81 // Emit function declaration
82 o << "unsigned " << Target.getName() << "CodeEmitter::"
83 << "getBinaryCodeForInstr(MachineInstr &MI) {\n";
85 // Emit instruction base values
86 o << " static const unsigned InstBits[] = {\n";
87 for (std::vector<const CodeGenInstruction*>::iterator
88 IN = NumberedInstructions.begin(),
89 EN = NumberedInstructions.end();
91 const CodeGenInstruction *CGI = *IN;
92 Record *R = CGI->TheDef;
94 if (IN != NumberedInstructions.begin()) o << ",\n";
96 if (R->getName() == "PHI" || R->getName() == "INLINEASM") {
101 BitsInit *BI = R->getValueAsBitsInit("Inst");
103 // Start by filling in fixed values...
105 for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i) {
106 if (BitInit *B = dynamic_cast<BitInit*>(BI->getBit(e-i-1))) {
107 Value |= B->getValue() << (e-i-1);
110 o << " " << Value << "U";
114 // Map to accumulate all the cases.
115 std::map<std::string, std::vector<std::string> > CaseMap;
117 // Construct all cases statement for each opcode
118 for (std::vector<Record*>::iterator IC = Insts.begin(), EC = Insts.end();
121 const std::string &InstName = R->getName();
122 std::string Case("");
124 if (InstName == "PHI" || InstName == "INLINEASM") continue;
126 BitsInit *BI = R->getValueAsBitsInit("Inst");
127 const std::vector<RecordVal> &Vals = R->getValues();
128 CodeGenInstruction &CGI = Target.getInstruction(InstName);
130 // Loop over all of the fields in the instruction, determining which are the
131 // operands to the instruction.
133 for (unsigned i = 0, e = Vals.size(); i != e; ++i) {
134 if (!Vals[i].getPrefix() && !Vals[i].getValue()->isComplete()) {
135 // Is the operand continuous? If so, we can just mask and OR it in
136 // instead of doing it bit-by-bit, saving a lot in runtime cost.
137 const std::string &VarName = Vals[i].getName();
140 for (int bit = BI->getNumBits()-1; bit >= 0; ) {
141 int varBit = getVariableBit(VarName, BI, bit);
146 int beginInstBit = bit;
147 int beginVarBit = varBit;
150 for (--bit; bit >= 0;) {
151 varBit = getVariableBit(VarName, BI, bit);
152 if (varBit == -1 || varBit != (beginVarBit - N)) break;
158 /// If this operand is not supposed to be emitted by the generated
159 /// emitter, skip it.
160 while (CGI.isFlatOperandNotEmitted(op))
163 Case += " // op: " + VarName + "\n"
164 + " op = getMachineOpValue(MI, MI.getOperand("
165 + utostr(op++) + "));\n";
169 unsigned opMask = (1 << N) - 1;
170 int opShift = beginVarBit - N + 1;
172 opShift = beginInstBit - beginVarBit;
175 Case += " Value |= (op & " + utostr(opMask) + "U) << "
176 + itostr(opShift) + ";\n";
177 } else if (opShift < 0) {
178 Case += " Value |= (op & " + utostr(opMask) + "U) >> "
179 + itostr(-opShift) + ";\n";
181 Case += " Value |= op & " + utostr(opMask) + "U;\n";
188 std::vector<std::string> &InstList = CaseMap[Case];
189 InstList.push_back(InstName);
193 // Emit initial function code
194 o << " const unsigned opcode = MI.getOpcode();\n"
195 << " unsigned Value = InstBits[opcode];\n"
197 << " switch (opcode) {\n";
199 // Emit each case statement
200 std::map<std::string, std::vector<std::string> >::iterator IE, EE;
201 for (IE = CaseMap.begin(), EE = CaseMap.end(); IE != EE; ++IE) {
202 const std::string &Case = IE->first;
203 std::vector<std::string> &InstList = IE->second;
205 for (int i = 0, N = InstList.size(); i < N; i++) {
207 o << " case " << Namespace << InstList[i] << ":";
215 // Default case: unhandled opcode
217 << " cerr << \"Not supported instr: \" << MI << \"\\n\";\n"
220 << " return Value;\n"