1 //===- CodeGenRegisters.cpp - Register and RegisterClass Info -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines structures to encapsulate information gleaned from the
11 // target register and register class definitions.
13 //===----------------------------------------------------------------------===//
15 #include "CodeGenRegisters.h"
16 #include "CodeGenTarget.h"
17 #include "llvm/TableGen/Error.h"
18 #include "llvm/ADT/IntEqClasses.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/ADT/Twine.h"
26 //===----------------------------------------------------------------------===//
28 //===----------------------------------------------------------------------===//
30 CodeGenSubRegIndex::CodeGenSubRegIndex(Record *R, unsigned Enum)
31 : TheDef(R), EnumValue(Enum) {
33 if (R->getValue("Namespace"))
34 Namespace = R->getValueAsString("Namespace");
37 CodeGenSubRegIndex::CodeGenSubRegIndex(StringRef N, StringRef Nspace,
39 : TheDef(0), Name(N), Namespace(Nspace), EnumValue(Enum) {
42 std::string CodeGenSubRegIndex::getQualifiedName() const {
43 std::string N = getNamespace();
50 void CodeGenSubRegIndex::updateComponents(CodeGenRegBank &RegBank) {
54 std::vector<Record*> Comps = TheDef->getValueAsListOfDefs("ComposedOf");
56 if (Comps.size() != 2)
57 throw TGError(TheDef->getLoc(), "ComposedOf must have exactly two entries");
58 CodeGenSubRegIndex *A = RegBank.getSubRegIdx(Comps[0]);
59 CodeGenSubRegIndex *B = RegBank.getSubRegIdx(Comps[1]);
60 CodeGenSubRegIndex *X = A->addComposite(B, this);
62 throw TGError(TheDef->getLoc(), "Ambiguous ComposedOf entries");
65 std::vector<Record*> Parts =
66 TheDef->getValueAsListOfDefs("CoveringSubRegIndices");
69 throw TGError(TheDef->getLoc(),
70 "CoveredBySubRegs must have two or more entries");
71 SmallVector<CodeGenSubRegIndex*, 8> IdxParts;
72 for (unsigned i = 0, e = Parts.size(); i != e; ++i)
73 IdxParts.push_back(RegBank.getSubRegIdx(Parts[i]));
74 RegBank.addConcatSubRegIndex(IdxParts, this);
78 void CodeGenSubRegIndex::cleanComposites() {
79 // Clean out redundant mappings of the form this+X -> X.
80 for (CompMap::iterator i = Composed.begin(), e = Composed.end(); i != e;) {
81 CompMap::iterator j = i;
83 if (j->first == j->second)
88 //===----------------------------------------------------------------------===//
90 //===----------------------------------------------------------------------===//
92 CodeGenRegister::CodeGenRegister(Record *R, unsigned Enum)
95 CostPerUse(R->getValueAsInt("CostPerUse")),
96 CoveredBySubRegs(R->getValueAsBit("CoveredBySubRegs")),
98 SubRegsComplete(false),
99 SuperRegsComplete(false),
103 void CodeGenRegister::buildObjectGraph(CodeGenRegBank &RegBank) {
104 std::vector<Record*> SRIs = TheDef->getValueAsListOfDefs("SubRegIndices");
105 std::vector<Record*> SRs = TheDef->getValueAsListOfDefs("SubRegs");
107 if (SRIs.size() != SRs.size())
108 throw TGError(TheDef->getLoc(),
109 "SubRegs and SubRegIndices must have the same size");
111 for (unsigned i = 0, e = SRIs.size(); i != e; ++i) {
112 ExplicitSubRegIndices.push_back(RegBank.getSubRegIdx(SRIs[i]));
113 ExplicitSubRegs.push_back(RegBank.getReg(SRs[i]));
116 // Also compute leading super-registers. Each register has a list of
117 // covered-by-subregs super-registers where it appears as the first explicit
120 // This is used by computeSecondarySubRegs() to find candidates.
121 if (CoveredBySubRegs && !ExplicitSubRegs.empty())
122 ExplicitSubRegs.front()->LeadingSuperRegs.push_back(this);
124 // Add ad hoc alias links. This is a symmetric relationship between two
125 // registers, so build a symmetric graph by adding links in both ends.
126 std::vector<Record*> Aliases = TheDef->getValueAsListOfDefs("Aliases");
127 for (unsigned i = 0, e = Aliases.size(); i != e; ++i) {
128 CodeGenRegister *Reg = RegBank.getReg(Aliases[i]);
129 ExplicitAliases.push_back(Reg);
130 Reg->ExplicitAliases.push_back(this);
134 const std::string &CodeGenRegister::getName() const {
135 return TheDef->getName();
139 // Iterate over all register units in a set of registers.
140 class RegUnitIterator {
141 CodeGenRegister::Set::const_iterator RegI, RegE;
142 CodeGenRegister::RegUnitList::const_iterator UnitI, UnitE;
145 RegUnitIterator(const CodeGenRegister::Set &Regs):
146 RegI(Regs.begin()), RegE(Regs.end()), UnitI(), UnitE() {
149 UnitI = (*RegI)->getRegUnits().begin();
150 UnitE = (*RegI)->getRegUnits().end();
155 bool isValid() const { return UnitI != UnitE; }
157 unsigned operator* () const { assert(isValid()); return *UnitI; }
159 const CodeGenRegister *getReg() const { assert(isValid()); return *RegI; }
161 /// Preincrement. Move to the next unit.
163 assert(isValid() && "Cannot advance beyond the last operand");
170 while (UnitI == UnitE) {
173 UnitI = (*RegI)->getRegUnits().begin();
174 UnitE = (*RegI)->getRegUnits().end();
180 // Merge two RegUnitLists maintaining the order and removing duplicates.
181 // Overwrites MergedRU in the process.
182 static void mergeRegUnits(CodeGenRegister::RegUnitList &MergedRU,
183 const CodeGenRegister::RegUnitList &RRU) {
184 CodeGenRegister::RegUnitList LRU = MergedRU;
186 std::set_union(LRU.begin(), LRU.end(), RRU.begin(), RRU.end(),
187 std::back_inserter(MergedRU));
190 // Return true of this unit appears in RegUnits.
191 static bool hasRegUnit(CodeGenRegister::RegUnitList &RegUnits, unsigned Unit) {
192 return std::count(RegUnits.begin(), RegUnits.end(), Unit);
195 // Inherit register units from subregisters.
196 // Return true if the RegUnits changed.
197 bool CodeGenRegister::inheritRegUnits(CodeGenRegBank &RegBank) {
198 unsigned OldNumUnits = RegUnits.size();
199 for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
201 CodeGenRegister *SR = I->second;
202 // Merge the subregister's units into this register's RegUnits.
203 mergeRegUnits(RegUnits, SR->RegUnits);
205 return OldNumUnits != RegUnits.size();
208 const CodeGenRegister::SubRegMap &
209 CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) {
210 // Only compute this map once.
213 SubRegsComplete = true;
215 // First insert the explicit subregs and make sure they are fully indexed.
216 for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) {
217 CodeGenRegister *SR = ExplicitSubRegs[i];
218 CodeGenSubRegIndex *Idx = ExplicitSubRegIndices[i];
219 if (!SubRegs.insert(std::make_pair(Idx, SR)).second)
220 throw TGError(TheDef->getLoc(), "SubRegIndex " + Idx->getName() +
221 " appears twice in Register " + getName());
222 // Map explicit sub-registers first, so the names take precedence.
223 // The inherited sub-registers are mapped below.
224 SubReg2Idx.insert(std::make_pair(SR, Idx));
227 // Keep track of inherited subregs and how they can be reached.
228 SmallPtrSet<CodeGenRegister*, 8> Orphans;
230 // Clone inherited subregs and place duplicate entries in Orphans.
231 // Here the order is important - earlier subregs take precedence.
232 for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) {
233 CodeGenRegister *SR = ExplicitSubRegs[i];
234 const SubRegMap &Map = SR->computeSubRegs(RegBank);
236 for (SubRegMap::const_iterator SI = Map.begin(), SE = Map.end(); SI != SE;
238 if (!SubRegs.insert(*SI).second)
239 Orphans.insert(SI->second);
243 // Expand any composed subreg indices.
244 // If dsub_2 has ComposedOf = [qsub_1, dsub_0], and this register has a
245 // qsub_1 subreg, add a dsub_2 subreg. Keep growing Indices and process
246 // expanded subreg indices recursively.
247 SmallVector<CodeGenSubRegIndex*, 8> Indices = ExplicitSubRegIndices;
248 for (unsigned i = 0; i != Indices.size(); ++i) {
249 CodeGenSubRegIndex *Idx = Indices[i];
250 const CodeGenSubRegIndex::CompMap &Comps = Idx->getComposites();
251 CodeGenRegister *SR = SubRegs[Idx];
252 const SubRegMap &Map = SR->computeSubRegs(RegBank);
254 // Look at the possible compositions of Idx.
255 // They may not all be supported by SR.
256 for (CodeGenSubRegIndex::CompMap::const_iterator I = Comps.begin(),
257 E = Comps.end(); I != E; ++I) {
258 SubRegMap::const_iterator SRI = Map.find(I->first);
259 if (SRI == Map.end())
260 continue; // Idx + I->first doesn't exist in SR.
261 // Add I->second as a name for the subreg SRI->second, assuming it is
262 // orphaned, and the name isn't already used for something else.
263 if (SubRegs.count(I->second) || !Orphans.erase(SRI->second))
265 // We found a new name for the orphaned sub-register.
266 SubRegs.insert(std::make_pair(I->second, SRI->second));
267 Indices.push_back(I->second);
271 // Now Orphans contains the inherited subregisters without a direct index.
272 // Create inferred indexes for all missing entries.
273 // Work backwards in the Indices vector in order to compose subregs bottom-up.
274 // Consider this subreg sequence:
276 // qsub_1 -> dsub_0 -> ssub_0
278 // The qsub_1 -> dsub_0 composition becomes dsub_2, so the ssub_0 register
279 // can be reached in two different ways:
284 // We pick the latter composition because another register may have [dsub_0,
285 // dsub_1, dsub_2] subregs without necessarily having a qsub_1 subreg. The
286 // dsub_2 -> ssub_0 composition can be shared.
287 while (!Indices.empty() && !Orphans.empty()) {
288 CodeGenSubRegIndex *Idx = Indices.pop_back_val();
289 CodeGenRegister *SR = SubRegs[Idx];
290 const SubRegMap &Map = SR->computeSubRegs(RegBank);
291 for (SubRegMap::const_iterator SI = Map.begin(), SE = Map.end(); SI != SE;
293 if (Orphans.erase(SI->second))
294 SubRegs[RegBank.getCompositeSubRegIndex(Idx, SI->first)] = SI->second;
297 // Compute the inverse SubReg -> Idx map.
298 for (SubRegMap::const_iterator SI = SubRegs.begin(), SE = SubRegs.end();
300 if (SI->second == this) {
303 Loc = TheDef->getLoc();
304 throw TGError(Loc, "Register " + getName() +
305 " has itself as a sub-register");
307 // Ensure that every sub-register has a unique name.
308 DenseMap<const CodeGenRegister*, CodeGenSubRegIndex*>::iterator Ins =
309 SubReg2Idx.insert(std::make_pair(SI->second, SI->first)).first;
310 if (Ins->second == SI->first)
312 // Trouble: Two different names for SI->second.
315 Loc = TheDef->getLoc();
316 throw TGError(Loc, "Sub-register can't have two names: " +
317 SI->second->getName() + " available as " +
318 SI->first->getName() + " and " + Ins->second->getName());
321 // Derive possible names for sub-register concatenations from any explicit
322 // sub-registers. By doing this before computeSecondarySubRegs(), we ensure
323 // that getConcatSubRegIndex() won't invent any concatenated indices that the
324 // user already specified.
325 for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) {
326 CodeGenRegister *SR = ExplicitSubRegs[i];
327 if (!SR->CoveredBySubRegs || SR->ExplicitSubRegs.size() <= 1)
330 // SR is composed of multiple sub-regs. Find their names in this register.
331 SmallVector<CodeGenSubRegIndex*, 8> Parts;
332 for (unsigned j = 0, e = SR->ExplicitSubRegs.size(); j != e; ++j)
333 Parts.push_back(getSubRegIndex(SR->ExplicitSubRegs[j]));
335 // Offer this as an existing spelling for the concatenation of Parts.
336 RegBank.addConcatSubRegIndex(Parts, ExplicitSubRegIndices[i]);
339 // Initialize RegUnitList. Because getSubRegs is called recursively, this
340 // processes the register hierarchy in postorder.
342 // Inherit all sub-register units. It is good enough to look at the explicit
343 // sub-registers, the other registers won't contribute any more units.
344 for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) {
345 CodeGenRegister *SR = ExplicitSubRegs[i];
346 // Explicit sub-registers are usually disjoint, so this is a good way of
347 // computing the union. We may pick up a few duplicates that will be
349 unsigned N = RegUnits.size();
350 RegUnits.append(SR->RegUnits.begin(), SR->RegUnits.end());
351 std::inplace_merge(RegUnits.begin(), RegUnits.begin() + N, RegUnits.end());
353 RegUnits.erase(std::unique(RegUnits.begin(), RegUnits.end()), RegUnits.end());
355 // Absent any ad hoc aliasing, we create one register unit per leaf register.
356 // These units correspond to the maximal cliques in the register overlap
357 // graph which is optimal.
359 // When there is ad hoc aliasing, we simply create one unit per edge in the
360 // undirected ad hoc aliasing graph. Technically, we could do better by
361 // identifying maximal cliques in the ad hoc graph, but cliques larger than 2
362 // are extremely rare anyway (I've never seen one), so we don't bother with
363 // the added complexity.
364 for (unsigned i = 0, e = ExplicitAliases.size(); i != e; ++i) {
365 CodeGenRegister *AR = ExplicitAliases[i];
366 // Only visit each edge once.
367 if (AR->SubRegsComplete)
369 // Create a RegUnit representing this alias edge, and add it to both
371 unsigned Unit = RegBank.newRegUnit(this, AR);
372 RegUnits.push_back(Unit);
373 AR->RegUnits.push_back(Unit);
376 // Finally, create units for leaf registers without ad hoc aliases. Note that
377 // a leaf register with ad hoc aliases doesn't get its own unit - it isn't
378 // necessary. This means the aliasing leaf registers can share a single unit.
379 if (RegUnits.empty())
380 RegUnits.push_back(RegBank.newRegUnit(this));
382 // We have now computed the native register units. More may be adopted later
383 // for balancing purposes.
384 NumNativeRegUnits = RegUnits.size();
389 // In a register that is covered by its sub-registers, try to find redundant
390 // sub-registers. For example:
396 // We can infer that D1_D2 is also a sub-register, even if it wasn't named in
397 // the register definition.
399 // The explicitly specified registers form a tree. This function discovers
400 // sub-register relationships that would force a DAG.
402 void CodeGenRegister::computeSecondarySubRegs(CodeGenRegBank &RegBank) {
403 // Collect new sub-registers first, add them later.
404 SmallVector<SubRegMap::value_type, 8> NewSubRegs;
406 // Look at the leading super-registers of each sub-register. Those are the
407 // candidates for new sub-registers, assuming they are fully contained in
409 for (SubRegMap::iterator I = SubRegs.begin(), E = SubRegs.end(); I != E; ++I){
410 const CodeGenRegister *SubReg = I->second;
411 const CodeGenRegister::SuperRegList &Leads = SubReg->LeadingSuperRegs;
412 for (unsigned i = 0, e = Leads.size(); i != e; ++i) {
413 CodeGenRegister *Cand = const_cast<CodeGenRegister*>(Leads[i]);
414 // Already got this sub-register?
415 if (Cand == this || getSubRegIndex(Cand))
417 // Check if each component of Cand is already a sub-register.
418 // We know that the first component is I->second, and is present with the
420 SmallVector<CodeGenSubRegIndex*, 8> Parts(1, I->first);
421 assert(!Cand->ExplicitSubRegs.empty() &&
422 "Super-register has no sub-registers");
423 for (unsigned j = 1, e = Cand->ExplicitSubRegs.size(); j != e; ++j) {
424 if (CodeGenSubRegIndex *Idx = getSubRegIndex(Cand->ExplicitSubRegs[j]))
425 Parts.push_back(Idx);
427 // Sub-register doesn't exist.
432 // If some Cand sub-register is not part of this register, or if Cand only
433 // has one sub-register, there is nothing to do.
434 if (Parts.size() <= 1)
437 // Each part of Cand is a sub-register of this. Make the full Cand also
438 // a sub-register with a concatenated sub-register index.
439 CodeGenSubRegIndex *Concat= RegBank.getConcatSubRegIndex(Parts);
440 NewSubRegs.push_back(std::make_pair(Concat, Cand));
444 // Now add all the new sub-registers.
445 for (unsigned i = 0, e = NewSubRegs.size(); i != e; ++i) {
446 // Don't add Cand if another sub-register is already using the index.
447 if (!SubRegs.insert(NewSubRegs[i]).second)
450 CodeGenSubRegIndex *NewIdx = NewSubRegs[i].first;
451 CodeGenRegister *NewSubReg = NewSubRegs[i].second;
452 SubReg2Idx.insert(std::make_pair(NewSubReg, NewIdx));
455 // Create sub-register index composition maps for the synthesized indices.
456 for (unsigned i = 0, e = NewSubRegs.size(); i != e; ++i) {
457 CodeGenSubRegIndex *NewIdx = NewSubRegs[i].first;
458 CodeGenRegister *NewSubReg = NewSubRegs[i].second;
459 for (SubRegMap::const_iterator SI = NewSubReg->SubRegs.begin(),
460 SE = NewSubReg->SubRegs.end(); SI != SE; ++SI) {
461 CodeGenSubRegIndex *SubIdx = getSubRegIndex(SI->second);
463 throw TGError(TheDef->getLoc(), "No SubRegIndex for " +
464 SI->second->getName() + " in " + getName());
465 NewIdx->addComposite(SI->first, SubIdx);
470 void CodeGenRegister::computeSuperRegs(CodeGenRegBank &RegBank) {
471 // Only visit each register once.
472 if (SuperRegsComplete)
474 SuperRegsComplete = true;
476 // Make sure all sub-registers have been visited first, so the super-reg
477 // lists will be topologically ordered.
478 for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
480 I->second->computeSuperRegs(RegBank);
482 // Now add this as a super-register on all sub-registers.
483 // Also compute the TopoSigId in post-order.
485 for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
487 // Topological signature computed from SubIdx, TopoId(SubReg).
488 // Loops and idempotent indices have TopoSig = ~0u.
489 Id.push_back(I->first->EnumValue);
490 Id.push_back(I->second->TopoSig);
492 // Don't add duplicate entries.
493 if (!I->second->SuperRegs.empty() && I->second->SuperRegs.back() == this)
495 I->second->SuperRegs.push_back(this);
497 TopoSig = RegBank.getTopoSig(Id);
501 CodeGenRegister::addSubRegsPreOrder(SetVector<const CodeGenRegister*> &OSet,
502 CodeGenRegBank &RegBank) const {
503 assert(SubRegsComplete && "Must precompute sub-registers");
504 for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) {
505 CodeGenRegister *SR = ExplicitSubRegs[i];
507 SR->addSubRegsPreOrder(OSet, RegBank);
509 // Add any secondary sub-registers that weren't part of the explicit tree.
510 for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
512 OSet.insert(I->second);
515 // Compute overlapping registers.
517 // The standard set is all super-registers and all sub-registers, but the
518 // target description can add arbitrary overlapping registers via the 'Aliases'
519 // field. This complicates things, but we can compute overlapping sets using
520 // the following rules:
522 // 1. The relation overlap(A, B) is reflexive and symmetric but not transitive.
524 // 2. overlap(A, B) implies overlap(A, S) for all S in supers(B).
528 // overlap(A, B) iff there exists:
529 // A' in { A, subregs(A) } and B' in { B, subregs(B) } such that:
530 // A' = B' or A' in aliases(B') or B' in aliases(A').
532 // Here subregs(A) is the full flattened sub-register set returned by
533 // A.getSubRegs() while aliases(A) is simply the special 'Aliases' field in the
534 // description of register A.
536 // This also implies that registers with a common sub-register are considered
537 // overlapping. This can happen when forming register pairs:
543 // In this case, we will infer an overlap between P0 and P1 because of the
544 // shared sub-register R1. There is no overlap between P0 and P2.
546 void CodeGenRegister::computeOverlaps(CodeGenRegister::Set &Overlaps,
547 const CodeGenRegBank &RegBank) const {
548 assert(!RegUnits.empty() && "Compute register units before overlaps.");
550 // Register units are assigned such that the overlapping registers are the
551 // super-registers of the root registers of the register units.
552 for (unsigned rui = 0, rue = RegUnits.size(); rui != rue; ++rui) {
553 const RegUnit &RU = RegBank.getRegUnit(RegUnits[rui]);
554 ArrayRef<const CodeGenRegister*> Roots = RU.getRoots();
555 for (unsigned ri = 0, re = Roots.size(); ri != re; ++ri) {
556 const CodeGenRegister *Root = Roots[ri];
557 Overlaps.insert(Root);
558 ArrayRef<const CodeGenRegister*> Supers = Root->getSuperRegs();
559 Overlaps.insert(Supers.begin(), Supers.end());
564 // Get the sum of this register's unit weights.
565 unsigned CodeGenRegister::getWeight(const CodeGenRegBank &RegBank) const {
567 for (RegUnitList::const_iterator I = RegUnits.begin(), E = RegUnits.end();
569 Weight += RegBank.getRegUnit(*I).Weight;
574 //===----------------------------------------------------------------------===//
576 //===----------------------------------------------------------------------===//
578 // A RegisterTuples def is used to generate pseudo-registers from lists of
579 // sub-registers. We provide a SetTheory expander class that returns the new
582 struct TupleExpander : SetTheory::Expander {
583 void expand(SetTheory &ST, Record *Def, SetTheory::RecSet &Elts) {
584 std::vector<Record*> Indices = Def->getValueAsListOfDefs("SubRegIndices");
585 unsigned Dim = Indices.size();
586 ListInit *SubRegs = Def->getValueAsListInit("SubRegs");
587 if (Dim != SubRegs->getSize())
588 throw TGError(Def->getLoc(), "SubRegIndices and SubRegs size mismatch");
590 throw TGError(Def->getLoc(), "Tuples must have at least 2 sub-registers");
592 // Evaluate the sub-register lists to be zipped.
593 unsigned Length = ~0u;
594 SmallVector<SetTheory::RecSet, 4> Lists(Dim);
595 for (unsigned i = 0; i != Dim; ++i) {
596 ST.evaluate(SubRegs->getElement(i), Lists[i]);
597 Length = std::min(Length, unsigned(Lists[i].size()));
603 // Precompute some types.
604 Record *RegisterCl = Def->getRecords().getClass("Register");
605 RecTy *RegisterRecTy = RecordRecTy::get(RegisterCl);
606 StringInit *BlankName = StringInit::get("");
609 for (unsigned n = 0; n != Length; ++n) {
611 Record *Proto = Lists[0][n];
612 std::vector<Init*> Tuple;
613 unsigned CostPerUse = 0;
614 for (unsigned i = 0; i != Dim; ++i) {
615 Record *Reg = Lists[i][n];
617 Name += Reg->getName();
618 Tuple.push_back(DefInit::get(Reg));
619 CostPerUse = std::max(CostPerUse,
620 unsigned(Reg->getValueAsInt("CostPerUse")));
623 // Create a new Record representing the synthesized register. This record
624 // is only for consumption by CodeGenRegister, it is not added to the
626 Record *NewReg = new Record(Name, Def->getLoc(), Def->getRecords());
629 // Copy Proto super-classes.
630 for (unsigned i = 0, e = Proto->getSuperClasses().size(); i != e; ++i)
631 NewReg->addSuperClass(Proto->getSuperClasses()[i]);
633 // Copy Proto fields.
634 for (unsigned i = 0, e = Proto->getValues().size(); i != e; ++i) {
635 RecordVal RV = Proto->getValues()[i];
637 // Skip existing fields, like NAME.
638 if (NewReg->getValue(RV.getNameInit()))
641 StringRef Field = RV.getName();
643 // Replace the sub-register list with Tuple.
644 if (Field == "SubRegs")
645 RV.setValue(ListInit::get(Tuple, RegisterRecTy));
647 // Provide a blank AsmName. MC hacks are required anyway.
648 if (Field == "AsmName")
649 RV.setValue(BlankName);
651 // CostPerUse is aggregated from all Tuple members.
652 if (Field == "CostPerUse")
653 RV.setValue(IntInit::get(CostPerUse));
655 // Composite registers are always covered by sub-registers.
656 if (Field == "CoveredBySubRegs")
657 RV.setValue(BitInit::get(true));
659 // Copy fields from the RegisterTuples def.
660 if (Field == "SubRegIndices" ||
661 Field == "CompositeIndices") {
662 NewReg->addValue(*Def->getValue(Field));
666 // Some fields get their default uninitialized value.
667 if (Field == "DwarfNumbers" ||
668 Field == "DwarfAlias" ||
669 Field == "Aliases") {
670 if (const RecordVal *DefRV = RegisterCl->getValue(Field))
671 NewReg->addValue(*DefRV);
675 // Everything else is copied from Proto.
676 NewReg->addValue(RV);
683 //===----------------------------------------------------------------------===//
684 // CodeGenRegisterClass
685 //===----------------------------------------------------------------------===//
687 CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
690 TopoSigs(RegBank.getNumTopoSigs()),
692 // Rename anonymous register classes.
693 if (R->getName().size() > 9 && R->getName()[9] == '.') {
694 static unsigned AnonCounter = 0;
695 R->setName("AnonRegClass_"+utostr(AnonCounter++));
698 std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes");
699 for (unsigned i = 0, e = TypeList.size(); i != e; ++i) {
700 Record *Type = TypeList[i];
701 if (!Type->isSubClassOf("ValueType"))
702 throw "RegTypes list member '" + Type->getName() +
703 "' does not derive from the ValueType class!";
704 VTs.push_back(getValueType(Type));
706 assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!");
708 // Allocation order 0 is the full set. AltOrders provides others.
709 const SetTheory::RecVec *Elements = RegBank.getSets().expand(R);
710 ListInit *AltOrders = R->getValueAsListInit("AltOrders");
711 Orders.resize(1 + AltOrders->size());
713 // Default allocation order always contains all registers.
714 for (unsigned i = 0, e = Elements->size(); i != e; ++i) {
715 Orders[0].push_back((*Elements)[i]);
716 const CodeGenRegister *Reg = RegBank.getReg((*Elements)[i]);
718 TopoSigs.set(Reg->getTopoSig());
721 // Alternative allocation orders may be subsets.
722 SetTheory::RecSet Order;
723 for (unsigned i = 0, e = AltOrders->size(); i != e; ++i) {
724 RegBank.getSets().evaluate(AltOrders->getElement(i), Order);
725 Orders[1 + i].append(Order.begin(), Order.end());
726 // Verify that all altorder members are regclass members.
727 while (!Order.empty()) {
728 CodeGenRegister *Reg = RegBank.getReg(Order.back());
731 throw TGError(R->getLoc(), " AltOrder register " + Reg->getName() +
732 " is not a class member");
736 // Allow targets to override the size in bits of the RegisterClass.
737 unsigned Size = R->getValueAsInt("Size");
739 Namespace = R->getValueAsString("Namespace");
740 SpillSize = Size ? Size : EVT(VTs[0]).getSizeInBits();
741 SpillAlignment = R->getValueAsInt("Alignment");
742 CopyCost = R->getValueAsInt("CopyCost");
743 Allocatable = R->getValueAsBit("isAllocatable");
744 AltOrderSelect = R->getValueAsString("AltOrderSelect");
747 // Create an inferred register class that was missing from the .td files.
748 // Most properties will be inherited from the closest super-class after the
749 // class structure has been computed.
750 CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank,
751 StringRef Name, Key Props)
752 : Members(*Props.Members),
755 TopoSigs(RegBank.getNumTopoSigs()),
757 SpillSize(Props.SpillSize),
758 SpillAlignment(Props.SpillAlignment),
761 for (CodeGenRegister::Set::iterator I = Members.begin(), E = Members.end();
763 TopoSigs.set((*I)->getTopoSig());
766 // Compute inherited propertied for a synthesized register class.
767 void CodeGenRegisterClass::inheritProperties(CodeGenRegBank &RegBank) {
768 assert(!getDef() && "Only synthesized classes can inherit properties");
769 assert(!SuperClasses.empty() && "Synthesized class without super class");
771 // The last super-class is the smallest one.
772 CodeGenRegisterClass &Super = *SuperClasses.back();
774 // Most properties are copied directly.
775 // Exceptions are members, size, and alignment
776 Namespace = Super.Namespace;
778 CopyCost = Super.CopyCost;
779 Allocatable = Super.Allocatable;
780 AltOrderSelect = Super.AltOrderSelect;
782 // Copy all allocation orders, filter out foreign registers from the larger
784 Orders.resize(Super.Orders.size());
785 for (unsigned i = 0, ie = Super.Orders.size(); i != ie; ++i)
786 for (unsigned j = 0, je = Super.Orders[i].size(); j != je; ++j)
787 if (contains(RegBank.getReg(Super.Orders[i][j])))
788 Orders[i].push_back(Super.Orders[i][j]);
791 bool CodeGenRegisterClass::contains(const CodeGenRegister *Reg) const {
792 return Members.count(Reg);
796 raw_ostream &operator<<(raw_ostream &OS, const CodeGenRegisterClass::Key &K) {
797 OS << "{ S=" << K.SpillSize << ", A=" << K.SpillAlignment;
798 for (CodeGenRegister::Set::const_iterator I = K.Members->begin(),
799 E = K.Members->end(); I != E; ++I)
800 OS << ", " << (*I)->getName();
805 // This is a simple lexicographical order that can be used to search for sets.
806 // It is not the same as the topological order provided by TopoOrderRC.
807 bool CodeGenRegisterClass::Key::
808 operator<(const CodeGenRegisterClass::Key &B) const {
809 assert(Members && B.Members);
810 if (*Members != *B.Members)
811 return *Members < *B.Members;
812 if (SpillSize != B.SpillSize)
813 return SpillSize < B.SpillSize;
814 return SpillAlignment < B.SpillAlignment;
817 // Returns true if RC is a strict subclass.
818 // RC is a sub-class of this class if it is a valid replacement for any
819 // instruction operand where a register of this classis required. It must
820 // satisfy these conditions:
822 // 1. All RC registers are also in this.
823 // 2. The RC spill size must not be smaller than our spill size.
824 // 3. RC spill alignment must be compatible with ours.
826 static bool testSubClass(const CodeGenRegisterClass *A,
827 const CodeGenRegisterClass *B) {
828 return A->SpillAlignment && B->SpillAlignment % A->SpillAlignment == 0 &&
829 A->SpillSize <= B->SpillSize &&
830 std::includes(A->getMembers().begin(), A->getMembers().end(),
831 B->getMembers().begin(), B->getMembers().end(),
832 CodeGenRegister::Less());
835 /// Sorting predicate for register classes. This provides a topological
836 /// ordering that arranges all register classes before their sub-classes.
838 /// Register classes with the same registers, spill size, and alignment form a
839 /// clique. They will be ordered alphabetically.
841 static int TopoOrderRC(const void *PA, const void *PB) {
842 const CodeGenRegisterClass *A = *(const CodeGenRegisterClass* const*)PA;
843 const CodeGenRegisterClass *B = *(const CodeGenRegisterClass* const*)PB;
847 // Order by ascending spill size.
848 if (A->SpillSize < B->SpillSize)
850 if (A->SpillSize > B->SpillSize)
853 // Order by ascending spill alignment.
854 if (A->SpillAlignment < B->SpillAlignment)
856 if (A->SpillAlignment > B->SpillAlignment)
859 // Order by descending set size. Note that the classes' allocation order may
860 // not have been computed yet. The Members set is always vaild.
861 if (A->getMembers().size() > B->getMembers().size())
863 if (A->getMembers().size() < B->getMembers().size())
866 // Finally order by name as a tie breaker.
867 return StringRef(A->getName()).compare(B->getName());
870 std::string CodeGenRegisterClass::getQualifiedName() const {
871 if (Namespace.empty())
874 return Namespace + "::" + getName();
877 // Compute sub-classes of all register classes.
878 // Assume the classes are ordered topologically.
879 void CodeGenRegisterClass::computeSubClasses(CodeGenRegBank &RegBank) {
880 ArrayRef<CodeGenRegisterClass*> RegClasses = RegBank.getRegClasses();
882 // Visit backwards so sub-classes are seen first.
883 for (unsigned rci = RegClasses.size(); rci; --rci) {
884 CodeGenRegisterClass &RC = *RegClasses[rci - 1];
885 RC.SubClasses.resize(RegClasses.size());
886 RC.SubClasses.set(RC.EnumValue);
888 // Normally, all subclasses have IDs >= rci, unless RC is part of a clique.
889 for (unsigned s = rci; s != RegClasses.size(); ++s) {
890 if (RC.SubClasses.test(s))
892 CodeGenRegisterClass *SubRC = RegClasses[s];
893 if (!testSubClass(&RC, SubRC))
895 // SubRC is a sub-class. Grap all its sub-classes so we won't have to
897 RC.SubClasses |= SubRC->SubClasses;
900 // Sweep up missed clique members. They will be immediately preceding RC.
901 for (unsigned s = rci - 1; s && testSubClass(&RC, RegClasses[s - 1]); --s)
902 RC.SubClasses.set(s - 1);
905 // Compute the SuperClasses lists from the SubClasses vectors.
906 for (unsigned rci = 0; rci != RegClasses.size(); ++rci) {
907 const BitVector &SC = RegClasses[rci]->getSubClasses();
908 for (int s = SC.find_first(); s >= 0; s = SC.find_next(s)) {
909 if (unsigned(s) == rci)
911 RegClasses[s]->SuperClasses.push_back(RegClasses[rci]);
915 // With the class hierarchy in place, let synthesized register classes inherit
916 // properties from their closest super-class. The iteration order here can
917 // propagate properties down multiple levels.
918 for (unsigned rci = 0; rci != RegClasses.size(); ++rci)
919 if (!RegClasses[rci]->getDef())
920 RegClasses[rci]->inheritProperties(RegBank);
924 CodeGenRegisterClass::getSuperRegClasses(CodeGenSubRegIndex *SubIdx,
925 BitVector &Out) const {
926 DenseMap<CodeGenSubRegIndex*,
927 SmallPtrSet<CodeGenRegisterClass*, 8> >::const_iterator
928 FindI = SuperRegClasses.find(SubIdx);
929 if (FindI == SuperRegClasses.end())
931 for (SmallPtrSet<CodeGenRegisterClass*, 8>::const_iterator I =
932 FindI->second.begin(), E = FindI->second.end(); I != E; ++I)
933 Out.set((*I)->EnumValue);
936 // Populate a unique sorted list of units from a register set.
937 void CodeGenRegisterClass::buildRegUnitSet(
938 std::vector<unsigned> &RegUnits) const {
939 std::vector<unsigned> TmpUnits;
940 for (RegUnitIterator UnitI(Members); UnitI.isValid(); ++UnitI)
941 TmpUnits.push_back(*UnitI);
942 std::sort(TmpUnits.begin(), TmpUnits.end());
943 std::unique_copy(TmpUnits.begin(), TmpUnits.end(),
944 std::back_inserter(RegUnits));
947 //===----------------------------------------------------------------------===//
949 //===----------------------------------------------------------------------===//
951 CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records) {
952 // Configure register Sets to understand register classes and tuples.
953 Sets.addFieldExpander("RegisterClass", "MemberList");
954 Sets.addFieldExpander("CalleeSavedRegs", "SaveList");
955 Sets.addExpander("RegisterTuples", new TupleExpander());
957 // Read in the user-defined (named) sub-register indices.
958 // More indices will be synthesized later.
959 std::vector<Record*> SRIs = Records.getAllDerivedDefinitions("SubRegIndex");
960 std::sort(SRIs.begin(), SRIs.end(), LessRecord());
961 for (unsigned i = 0, e = SRIs.size(); i != e; ++i)
962 getSubRegIdx(SRIs[i]);
963 // Build composite maps from ComposedOf fields.
964 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i)
965 SubRegIndices[i]->updateComponents(*this);
967 // Read in the register definitions.
968 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
969 std::sort(Regs.begin(), Regs.end(), LessRecord());
970 Registers.reserve(Regs.size());
971 // Assign the enumeration values.
972 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
975 // Expand tuples and number the new registers.
976 std::vector<Record*> Tups =
977 Records.getAllDerivedDefinitions("RegisterTuples");
978 for (unsigned i = 0, e = Tups.size(); i != e; ++i) {
979 const std::vector<Record*> *TupRegs = Sets.expand(Tups[i]);
980 for (unsigned j = 0, je = TupRegs->size(); j != je; ++j)
981 getReg((*TupRegs)[j]);
984 // Now all the registers are known. Build the object graph of explicit
985 // register-register references.
986 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
987 Registers[i]->buildObjectGraph(*this);
989 // Precompute all sub-register maps.
990 // This will create Composite entries for all inferred sub-register indices.
991 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
992 Registers[i]->computeSubRegs(*this);
994 // Infer even more sub-registers by combining leading super-registers.
995 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
996 if (Registers[i]->CoveredBySubRegs)
997 Registers[i]->computeSecondarySubRegs(*this);
999 // After the sub-register graph is complete, compute the topologically
1000 // ordered SuperRegs list.
1001 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
1002 Registers[i]->computeSuperRegs(*this);
1004 // Native register units are associated with a leaf register. They've all been
1006 NumNativeRegUnits = RegUnits.size();
1008 // Read in register class definitions.
1009 std::vector<Record*> RCs = Records.getAllDerivedDefinitions("RegisterClass");
1011 throw std::string("No 'RegisterClass' subclasses defined!");
1013 // Allocate user-defined register classes.
1014 RegClasses.reserve(RCs.size());
1015 for (unsigned i = 0, e = RCs.size(); i != e; ++i)
1016 addToMaps(new CodeGenRegisterClass(*this, RCs[i]));
1018 // Infer missing classes to create a full algebra.
1019 computeInferredRegisterClasses();
1021 // Order register classes topologically and assign enum values.
1022 array_pod_sort(RegClasses.begin(), RegClasses.end(), TopoOrderRC);
1023 for (unsigned i = 0, e = RegClasses.size(); i != e; ++i)
1024 RegClasses[i]->EnumValue = i;
1025 CodeGenRegisterClass::computeSubClasses(*this);
1028 // Create a synthetic CodeGenSubRegIndex without a corresponding Record.
1030 CodeGenRegBank::createSubRegIndex(StringRef Name, StringRef Namespace) {
1031 CodeGenSubRegIndex *Idx = new CodeGenSubRegIndex(Name, Namespace,
1032 SubRegIndices.size() + 1);
1033 SubRegIndices.push_back(Idx);
1037 CodeGenSubRegIndex *CodeGenRegBank::getSubRegIdx(Record *Def) {
1038 CodeGenSubRegIndex *&Idx = Def2SubRegIdx[Def];
1041 Idx = new CodeGenSubRegIndex(Def, SubRegIndices.size() + 1);
1042 SubRegIndices.push_back(Idx);
1046 CodeGenRegister *CodeGenRegBank::getReg(Record *Def) {
1047 CodeGenRegister *&Reg = Def2Reg[Def];
1050 Reg = new CodeGenRegister(Def, Registers.size() + 1);
1051 Registers.push_back(Reg);
1055 void CodeGenRegBank::addToMaps(CodeGenRegisterClass *RC) {
1056 RegClasses.push_back(RC);
1058 if (Record *Def = RC->getDef())
1059 Def2RC.insert(std::make_pair(Def, RC));
1061 // Duplicate classes are rejected by insert().
1062 // That's OK, we only care about the properties handled by CGRC::Key.
1063 CodeGenRegisterClass::Key K(*RC);
1064 Key2RC.insert(std::make_pair(K, RC));
1067 // Create a synthetic sub-class if it is missing.
1068 CodeGenRegisterClass*
1069 CodeGenRegBank::getOrCreateSubClass(const CodeGenRegisterClass *RC,
1070 const CodeGenRegister::Set *Members,
1072 // Synthetic sub-class has the same size and alignment as RC.
1073 CodeGenRegisterClass::Key K(Members, RC->SpillSize, RC->SpillAlignment);
1074 RCKeyMap::const_iterator FoundI = Key2RC.find(K);
1075 if (FoundI != Key2RC.end())
1076 return FoundI->second;
1078 // Sub-class doesn't exist, create a new one.
1079 CodeGenRegisterClass *NewRC = new CodeGenRegisterClass(*this, Name, K);
1084 CodeGenRegisterClass *CodeGenRegBank::getRegClass(Record *Def) {
1085 if (CodeGenRegisterClass *RC = Def2RC[Def])
1088 throw TGError(Def->getLoc(), "Not a known RegisterClass!");
1092 CodeGenRegBank::getCompositeSubRegIndex(CodeGenSubRegIndex *A,
1093 CodeGenSubRegIndex *B) {
1094 // Look for an existing entry.
1095 CodeGenSubRegIndex *Comp = A->compose(B);
1099 // None exists, synthesize one.
1100 std::string Name = A->getName() + "_then_" + B->getName();
1101 Comp = createSubRegIndex(Name, A->getNamespace());
1102 A->addComposite(B, Comp);
1106 CodeGenSubRegIndex *CodeGenRegBank::
1107 getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex*, 8> &Parts) {
1108 assert(Parts.size() > 1 && "Need two parts to concatenate");
1110 // Look for an existing entry.
1111 CodeGenSubRegIndex *&Idx = ConcatIdx[Parts];
1115 // None exists, synthesize one.
1116 std::string Name = Parts.front()->getName();
1117 for (unsigned i = 1, e = Parts.size(); i != e; ++i) {
1119 Name += Parts[i]->getName();
1121 return Idx = createSubRegIndex(Name, Parts.front()->getNamespace());
1124 void CodeGenRegBank::computeComposites() {
1125 // Keep track of TopoSigs visited. We only need to visit each TopoSig once,
1126 // and many registers will share TopoSigs on regular architectures.
1127 BitVector TopoSigs(getNumTopoSigs());
1129 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
1130 CodeGenRegister *Reg1 = Registers[i];
1132 // Skip identical subreg structures already processed.
1133 if (TopoSigs.test(Reg1->getTopoSig()))
1135 TopoSigs.set(Reg1->getTopoSig());
1137 const CodeGenRegister::SubRegMap &SRM1 = Reg1->getSubRegs();
1138 for (CodeGenRegister::SubRegMap::const_iterator i1 = SRM1.begin(),
1139 e1 = SRM1.end(); i1 != e1; ++i1) {
1140 CodeGenSubRegIndex *Idx1 = i1->first;
1141 CodeGenRegister *Reg2 = i1->second;
1142 // Ignore identity compositions.
1145 const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs();
1146 // Try composing Idx1 with another SubRegIndex.
1147 for (CodeGenRegister::SubRegMap::const_iterator i2 = SRM2.begin(),
1148 e2 = SRM2.end(); i2 != e2; ++i2) {
1149 CodeGenSubRegIndex *Idx2 = i2->first;
1150 CodeGenRegister *Reg3 = i2->second;
1151 // Ignore identity compositions.
1154 // OK Reg1:IdxPair == Reg3. Find the index with Reg:Idx == Reg3.
1155 CodeGenSubRegIndex *Idx3 = Reg1->getSubRegIndex(Reg3);
1156 assert(Idx3 && "Sub-register doesn't have an index");
1158 // Conflicting composition? Emit a warning but allow it.
1159 if (CodeGenSubRegIndex *Prev = Idx1->addComposite(Idx2, Idx3))
1160 PrintWarning(Twine("SubRegIndex ") + Idx1->getQualifiedName() +
1161 " and " + Idx2->getQualifiedName() +
1162 " compose ambiguously as " + Prev->getQualifiedName() +
1163 " or " + Idx3->getQualifiedName());
1168 // We don't care about the difference between (Idx1, Idx2) -> Idx2 and invalid
1169 // compositions, so remove any mappings of that form.
1170 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i)
1171 SubRegIndices[i]->cleanComposites();
1175 // UberRegSet is a helper class for computeRegUnitWeights. Each UberRegSet is
1176 // the transitive closure of the union of overlapping register
1177 // classes. Together, the UberRegSets form a partition of the registers. If we
1178 // consider overlapping register classes to be connected, then each UberRegSet
1179 // is a set of connected components.
1181 // An UberRegSet will likely be a horizontal slice of register names of
1182 // the same width. Nontrivial subregisters should then be in a separate
1183 // UberRegSet. But this property isn't required for valid computation of
1184 // register unit weights.
1186 // A Weight field caches the max per-register unit weight in each UberRegSet.
1188 // A set of SingularDeterminants flags single units of some register in this set
1189 // for which the unit weight equals the set weight. These units should not have
1190 // their weight increased.
1192 CodeGenRegister::Set Regs;
1194 CodeGenRegister::RegUnitList SingularDeterminants;
1196 UberRegSet(): Weight(0) {}
1200 // Partition registers into UberRegSets, where each set is the transitive
1201 // closure of the union of overlapping register classes.
1203 // UberRegSets[0] is a special non-allocatable set.
1204 static void computeUberSets(std::vector<UberRegSet> &UberSets,
1205 std::vector<UberRegSet*> &RegSets,
1206 CodeGenRegBank &RegBank) {
1208 const std::vector<CodeGenRegister*> &Registers = RegBank.getRegisters();
1210 // The Register EnumValue is one greater than its index into Registers.
1211 assert(Registers.size() == Registers[Registers.size()-1]->EnumValue &&
1212 "register enum value mismatch");
1214 // For simplicitly make the SetID the same as EnumValue.
1215 IntEqClasses UberSetIDs(Registers.size()+1);
1216 std::set<unsigned> AllocatableRegs;
1217 for (unsigned i = 0, e = RegBank.getRegClasses().size(); i != e; ++i) {
1219 CodeGenRegisterClass *RegClass = RegBank.getRegClasses()[i];
1220 if (!RegClass->Allocatable)
1223 const CodeGenRegister::Set &Regs = RegClass->getMembers();
1227 unsigned USetID = UberSetIDs.findLeader((*Regs.begin())->EnumValue);
1228 assert(USetID && "register number 0 is invalid");
1230 AllocatableRegs.insert((*Regs.begin())->EnumValue);
1231 for (CodeGenRegister::Set::const_iterator I = llvm::next(Regs.begin()),
1232 E = Regs.end(); I != E; ++I) {
1233 AllocatableRegs.insert((*I)->EnumValue);
1234 UberSetIDs.join(USetID, (*I)->EnumValue);
1237 // Combine non-allocatable regs.
1238 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
1239 unsigned RegNum = Registers[i]->EnumValue;
1240 if (AllocatableRegs.count(RegNum))
1243 UberSetIDs.join(0, RegNum);
1245 UberSetIDs.compress();
1247 // Make the first UberSet a special unallocatable set.
1248 unsigned ZeroID = UberSetIDs[0];
1250 // Insert Registers into the UberSets formed by union-find.
1251 // Do not resize after this.
1252 UberSets.resize(UberSetIDs.getNumClasses());
1253 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
1254 const CodeGenRegister *Reg = Registers[i];
1255 unsigned USetID = UberSetIDs[Reg->EnumValue];
1258 else if (USetID == ZeroID)
1261 UberRegSet *USet = &UberSets[USetID];
1262 USet->Regs.insert(Reg);
1267 // Recompute each UberSet weight after changing unit weights.
1268 static void computeUberWeights(std::vector<UberRegSet> &UberSets,
1269 CodeGenRegBank &RegBank) {
1270 // Skip the first unallocatable set.
1271 for (std::vector<UberRegSet>::iterator I = llvm::next(UberSets.begin()),
1272 E = UberSets.end(); I != E; ++I) {
1274 // Initialize all unit weights in this set, and remember the max units/reg.
1275 const CodeGenRegister *Reg = 0;
1276 unsigned MaxWeight = 0, Weight = 0;
1277 for (RegUnitIterator UnitI(I->Regs); UnitI.isValid(); ++UnitI) {
1278 if (Reg != UnitI.getReg()) {
1279 if (Weight > MaxWeight)
1281 Reg = UnitI.getReg();
1284 unsigned UWeight = RegBank.getRegUnit(*UnitI).Weight;
1287 RegBank.increaseRegUnitWeight(*UnitI, UWeight);
1291 if (Weight > MaxWeight)
1294 // Update the set weight.
1295 I->Weight = MaxWeight;
1297 // Find singular determinants.
1298 for (CodeGenRegister::Set::iterator RegI = I->Regs.begin(),
1299 RegE = I->Regs.end(); RegI != RegE; ++RegI) {
1300 if ((*RegI)->getRegUnits().size() == 1
1301 && (*RegI)->getWeight(RegBank) == I->Weight)
1302 mergeRegUnits(I->SingularDeterminants, (*RegI)->getRegUnits());
1307 // normalizeWeight is a computeRegUnitWeights helper that adjusts the weight of
1308 // a register and its subregisters so that they have the same weight as their
1309 // UberSet. Self-recursion processes the subregister tree in postorder so
1310 // subregisters are normalized first.
1313 // - creates new adopted register units
1314 // - causes superregisters to inherit adopted units
1315 // - increases the weight of "singular" units
1316 // - induces recomputation of UberWeights.
1317 static bool normalizeWeight(CodeGenRegister *Reg,
1318 std::vector<UberRegSet> &UberSets,
1319 std::vector<UberRegSet*> &RegSets,
1320 std::set<unsigned> &NormalRegs,
1321 CodeGenRegister::RegUnitList &NormalUnits,
1322 CodeGenRegBank &RegBank) {
1323 bool Changed = false;
1324 if (!NormalRegs.insert(Reg->EnumValue).second)
1327 const CodeGenRegister::SubRegMap &SRM = Reg->getSubRegs();
1328 for (CodeGenRegister::SubRegMap::const_iterator SRI = SRM.begin(),
1329 SRE = SRM.end(); SRI != SRE; ++SRI) {
1330 if (SRI->second == Reg)
1331 continue; // self-cycles happen
1333 Changed |= normalizeWeight(SRI->second, UberSets, RegSets,
1334 NormalRegs, NormalUnits, RegBank);
1336 // Postorder register normalization.
1338 // Inherit register units newly adopted by subregisters.
1339 if (Reg->inheritRegUnits(RegBank))
1340 computeUberWeights(UberSets, RegBank);
1342 // Check if this register is too skinny for its UberRegSet.
1343 UberRegSet *UberSet = RegSets[RegBank.getRegIndex(Reg)];
1345 unsigned RegWeight = Reg->getWeight(RegBank);
1346 if (UberSet->Weight > RegWeight) {
1347 // A register unit's weight can be adjusted only if it is the singular unit
1348 // for this register, has not been used to normalize a subregister's set,
1349 // and has not already been used to singularly determine this UberRegSet.
1350 unsigned AdjustUnit = Reg->getRegUnits().front();
1351 if (Reg->getRegUnits().size() != 1
1352 || hasRegUnit(NormalUnits, AdjustUnit)
1353 || hasRegUnit(UberSet->SingularDeterminants, AdjustUnit)) {
1354 // We don't have an adjustable unit, so adopt a new one.
1355 AdjustUnit = RegBank.newRegUnit(UberSet->Weight - RegWeight);
1356 Reg->adoptRegUnit(AdjustUnit);
1357 // Adopting a unit does not immediately require recomputing set weights.
1360 // Adjust the existing single unit.
1361 RegBank.increaseRegUnitWeight(AdjustUnit, UberSet->Weight - RegWeight);
1362 // The unit may be shared among sets and registers within this set.
1363 computeUberWeights(UberSets, RegBank);
1368 // Mark these units normalized so superregisters can't change their weights.
1369 mergeRegUnits(NormalUnits, Reg->getRegUnits());
1374 // Compute a weight for each register unit created during getSubRegs.
1376 // The goal is that two registers in the same class will have the same weight,
1377 // where each register's weight is defined as sum of its units' weights.
1378 void CodeGenRegBank::computeRegUnitWeights() {
1379 std::vector<UberRegSet> UberSets;
1380 std::vector<UberRegSet*> RegSets(Registers.size());
1381 computeUberSets(UberSets, RegSets, *this);
1382 // UberSets and RegSets are now immutable.
1384 computeUberWeights(UberSets, *this);
1386 // Iterate over each Register, normalizing the unit weights until reaching
1388 unsigned NumIters = 0;
1389 for (bool Changed = true; Changed; ++NumIters) {
1390 assert(NumIters <= NumNativeRegUnits && "Runaway register unit weights");
1392 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
1393 CodeGenRegister::RegUnitList NormalUnits;
1394 std::set<unsigned> NormalRegs;
1395 Changed |= normalizeWeight(Registers[i], UberSets, RegSets,
1396 NormalRegs, NormalUnits, *this);
1401 // Find a set in UniqueSets with the same elements as Set.
1402 // Return an iterator into UniqueSets.
1403 static std::vector<RegUnitSet>::const_iterator
1404 findRegUnitSet(const std::vector<RegUnitSet> &UniqueSets,
1405 const RegUnitSet &Set) {
1406 std::vector<RegUnitSet>::const_iterator
1407 I = UniqueSets.begin(), E = UniqueSets.end();
1409 if (I->Units == Set.Units)
1415 // Return true if the RUSubSet is a subset of RUSuperSet.
1416 static bool isRegUnitSubSet(const std::vector<unsigned> &RUSubSet,
1417 const std::vector<unsigned> &RUSuperSet) {
1418 return std::includes(RUSuperSet.begin(), RUSuperSet.end(),
1419 RUSubSet.begin(), RUSubSet.end());
1422 // Iteratively prune unit sets.
1423 void CodeGenRegBank::pruneUnitSets() {
1424 assert(RegClassUnitSets.empty() && "this invalidates RegClassUnitSets");
1426 // Form an equivalence class of UnitSets with no significant difference.
1427 std::vector<unsigned> SuperSetIDs;
1428 for (unsigned SubIdx = 0, EndIdx = RegUnitSets.size();
1429 SubIdx != EndIdx; ++SubIdx) {
1430 const RegUnitSet &SubSet = RegUnitSets[SubIdx];
1431 unsigned SuperIdx = 0;
1432 for (; SuperIdx != EndIdx; ++SuperIdx) {
1433 if (SuperIdx == SubIdx)
1436 const RegUnitSet &SuperSet = RegUnitSets[SuperIdx];
1437 if (isRegUnitSubSet(SubSet.Units, SuperSet.Units)
1438 && (SubSet.Units.size() + 3 > SuperSet.Units.size())) {
1442 if (SuperIdx == EndIdx)
1443 SuperSetIDs.push_back(SubIdx);
1445 // Populate PrunedUnitSets with each equivalence class's superset.
1446 std::vector<RegUnitSet> PrunedUnitSets(SuperSetIDs.size());
1447 for (unsigned i = 0, e = SuperSetIDs.size(); i != e; ++i) {
1448 unsigned SuperIdx = SuperSetIDs[i];
1449 PrunedUnitSets[i].Name = RegUnitSets[SuperIdx].Name;
1450 PrunedUnitSets[i].Units.swap(RegUnitSets[SuperIdx].Units);
1452 RegUnitSets.swap(PrunedUnitSets);
1455 // Create a RegUnitSet for each RegClass that contains all units in the class
1456 // including adopted units that are necessary to model register pressure. Then
1457 // iteratively compute RegUnitSets such that the union of any two overlapping
1458 // RegUnitSets is repreresented.
1460 // RegisterInfoEmitter will map each RegClass to its RegUnitClass and any
1461 // RegUnitSet that is a superset of that RegUnitClass.
1462 void CodeGenRegBank::computeRegUnitSets() {
1464 // Compute a unique RegUnitSet for each RegClass.
1465 const ArrayRef<CodeGenRegisterClass*> &RegClasses = getRegClasses();
1466 unsigned NumRegClasses = RegClasses.size();
1467 for (unsigned RCIdx = 0, RCEnd = NumRegClasses; RCIdx != RCEnd; ++RCIdx) {
1468 if (!RegClasses[RCIdx]->Allocatable)
1471 // Speculatively grow the RegUnitSets to hold the new set.
1472 RegUnitSets.resize(RegUnitSets.size() + 1);
1473 RegUnitSets.back().Name = RegClasses[RCIdx]->getName();
1475 // Compute a sorted list of units in this class.
1476 RegClasses[RCIdx]->buildRegUnitSet(RegUnitSets.back().Units);
1478 // Find an existing RegUnitSet.
1479 std::vector<RegUnitSet>::const_iterator SetI =
1480 findRegUnitSet(RegUnitSets, RegUnitSets.back());
1481 if (SetI != llvm::prior(RegUnitSets.end()))
1482 RegUnitSets.pop_back();
1485 // Iteratively prune unit sets.
1488 // Iterate over all unit sets, including new ones added by this loop.
1489 unsigned NumRegUnitSubSets = RegUnitSets.size();
1490 for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx) {
1491 // In theory, this is combinatorial. In practice, it needs to be bounded
1492 // by a small number of sets for regpressure to be efficient.
1493 // If the assert is hit, we need to implement pruning.
1494 assert(Idx < (2*NumRegUnitSubSets) && "runaway unit set inference");
1496 // Compare new sets with all original classes.
1497 for (unsigned SearchIdx = (Idx >= NumRegUnitSubSets) ? 0 : Idx+1;
1498 SearchIdx != EndIdx; ++SearchIdx) {
1499 std::set<unsigned> Intersection;
1500 std::set_intersection(RegUnitSets[Idx].Units.begin(),
1501 RegUnitSets[Idx].Units.end(),
1502 RegUnitSets[SearchIdx].Units.begin(),
1503 RegUnitSets[SearchIdx].Units.end(),
1504 std::inserter(Intersection, Intersection.begin()));
1505 if (Intersection.empty())
1508 // Speculatively grow the RegUnitSets to hold the new set.
1509 RegUnitSets.resize(RegUnitSets.size() + 1);
1510 RegUnitSets.back().Name =
1511 RegUnitSets[Idx].Name + "+" + RegUnitSets[SearchIdx].Name;
1513 std::set_union(RegUnitSets[Idx].Units.begin(),
1514 RegUnitSets[Idx].Units.end(),
1515 RegUnitSets[SearchIdx].Units.begin(),
1516 RegUnitSets[SearchIdx].Units.end(),
1517 std::inserter(RegUnitSets.back().Units,
1518 RegUnitSets.back().Units.begin()));
1520 // Find an existing RegUnitSet, or add the union to the unique sets.
1521 std::vector<RegUnitSet>::const_iterator SetI =
1522 findRegUnitSet(RegUnitSets, RegUnitSets.back());
1523 if (SetI != llvm::prior(RegUnitSets.end()))
1524 RegUnitSets.pop_back();
1528 // Iteratively prune unit sets after inferring supersets.
1531 // For each register class, list the UnitSets that are supersets.
1532 RegClassUnitSets.resize(NumRegClasses);
1533 for (unsigned RCIdx = 0, RCEnd = NumRegClasses; RCIdx != RCEnd; ++RCIdx) {
1534 if (!RegClasses[RCIdx]->Allocatable)
1537 // Recompute the sorted list of units in this class.
1538 std::vector<unsigned> RegUnits;
1539 RegClasses[RCIdx]->buildRegUnitSet(RegUnits);
1541 // Don't increase pressure for unallocatable regclasses.
1542 if (RegUnits.empty())
1545 // Find all supersets.
1546 for (unsigned USIdx = 0, USEnd = RegUnitSets.size();
1547 USIdx != USEnd; ++USIdx) {
1548 if (isRegUnitSubSet(RegUnits, RegUnitSets[USIdx].Units))
1549 RegClassUnitSets[RCIdx].push_back(USIdx);
1551 assert(!RegClassUnitSets[RCIdx].empty() && "missing unit set for regclass");
1555 void CodeGenRegBank::computeDerivedInfo() {
1556 computeComposites();
1558 // Compute a weight for each register unit created during getSubRegs.
1559 // This may create adopted register units (with unit # >= NumNativeRegUnits).
1560 computeRegUnitWeights();
1562 // Compute a unique set of RegUnitSets. One for each RegClass and inferred
1563 // supersets for the union of overlapping sets.
1564 computeRegUnitSets();
1568 // Synthesize missing register class intersections.
1570 // Make sure that sub-classes of RC exists such that getCommonSubClass(RC, X)
1571 // returns a maximal register class for all X.
1573 void CodeGenRegBank::inferCommonSubClass(CodeGenRegisterClass *RC) {
1574 for (unsigned rci = 0, rce = RegClasses.size(); rci != rce; ++rci) {
1575 CodeGenRegisterClass *RC1 = RC;
1576 CodeGenRegisterClass *RC2 = RegClasses[rci];
1580 // Compute the set intersection of RC1 and RC2.
1581 const CodeGenRegister::Set &Memb1 = RC1->getMembers();
1582 const CodeGenRegister::Set &Memb2 = RC2->getMembers();
1583 CodeGenRegister::Set Intersection;
1584 std::set_intersection(Memb1.begin(), Memb1.end(),
1585 Memb2.begin(), Memb2.end(),
1586 std::inserter(Intersection, Intersection.begin()),
1587 CodeGenRegister::Less());
1589 // Skip disjoint class pairs.
1590 if (Intersection.empty())
1593 // If RC1 and RC2 have different spill sizes or alignments, use the
1594 // larger size for sub-classing. If they are equal, prefer RC1.
1595 if (RC2->SpillSize > RC1->SpillSize ||
1596 (RC2->SpillSize == RC1->SpillSize &&
1597 RC2->SpillAlignment > RC1->SpillAlignment))
1598 std::swap(RC1, RC2);
1600 getOrCreateSubClass(RC1, &Intersection,
1601 RC1->getName() + "_and_" + RC2->getName());
1606 // Synthesize missing sub-classes for getSubClassWithSubReg().
1608 // Make sure that the set of registers in RC with a given SubIdx sub-register
1609 // form a register class. Update RC->SubClassWithSubReg.
1611 void CodeGenRegBank::inferSubClassWithSubReg(CodeGenRegisterClass *RC) {
1612 // Map SubRegIndex to set of registers in RC supporting that SubRegIndex.
1613 typedef std::map<CodeGenSubRegIndex*, CodeGenRegister::Set,
1614 CodeGenSubRegIndex::Less> SubReg2SetMap;
1616 // Compute the set of registers supporting each SubRegIndex.
1617 SubReg2SetMap SRSets;
1618 for (CodeGenRegister::Set::const_iterator RI = RC->getMembers().begin(),
1619 RE = RC->getMembers().end(); RI != RE; ++RI) {
1620 const CodeGenRegister::SubRegMap &SRM = (*RI)->getSubRegs();
1621 for (CodeGenRegister::SubRegMap::const_iterator I = SRM.begin(),
1622 E = SRM.end(); I != E; ++I)
1623 SRSets[I->first].insert(*RI);
1626 // Find matching classes for all SRSets entries. Iterate in SubRegIndex
1627 // numerical order to visit synthetic indices last.
1628 for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
1629 CodeGenSubRegIndex *SubIdx = SubRegIndices[sri];
1630 SubReg2SetMap::const_iterator I = SRSets.find(SubIdx);
1631 // Unsupported SubRegIndex. Skip it.
1632 if (I == SRSets.end())
1634 // In most cases, all RC registers support the SubRegIndex.
1635 if (I->second.size() == RC->getMembers().size()) {
1636 RC->setSubClassWithSubReg(SubIdx, RC);
1639 // This is a real subset. See if we have a matching class.
1640 CodeGenRegisterClass *SubRC =
1641 getOrCreateSubClass(RC, &I->second,
1642 RC->getName() + "_with_" + I->first->getName());
1643 RC->setSubClassWithSubReg(SubIdx, SubRC);
1648 // Synthesize missing sub-classes of RC for getMatchingSuperRegClass().
1650 // Create sub-classes of RC such that getMatchingSuperRegClass(RC, SubIdx, X)
1651 // has a maximal result for any SubIdx and any X >= FirstSubRegRC.
1654 void CodeGenRegBank::inferMatchingSuperRegClass(CodeGenRegisterClass *RC,
1655 unsigned FirstSubRegRC) {
1656 SmallVector<std::pair<const CodeGenRegister*,
1657 const CodeGenRegister*>, 16> SSPairs;
1658 BitVector TopoSigs(getNumTopoSigs());
1660 // Iterate in SubRegIndex numerical order to visit synthetic indices last.
1661 for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
1662 CodeGenSubRegIndex *SubIdx = SubRegIndices[sri];
1663 // Skip indexes that aren't fully supported by RC's registers. This was
1664 // computed by inferSubClassWithSubReg() above which should have been
1666 if (RC->getSubClassWithSubReg(SubIdx) != RC)
1669 // Build list of (Super, Sub) pairs for this SubIdx.
1672 for (CodeGenRegister::Set::const_iterator RI = RC->getMembers().begin(),
1673 RE = RC->getMembers().end(); RI != RE; ++RI) {
1674 const CodeGenRegister *Super = *RI;
1675 const CodeGenRegister *Sub = Super->getSubRegs().find(SubIdx)->second;
1676 assert(Sub && "Missing sub-register");
1677 SSPairs.push_back(std::make_pair(Super, Sub));
1678 TopoSigs.set(Sub->getTopoSig());
1681 // Iterate over sub-register class candidates. Ignore classes created by
1682 // this loop. They will never be useful.
1683 for (unsigned rci = FirstSubRegRC, rce = RegClasses.size(); rci != rce;
1685 CodeGenRegisterClass *SubRC = RegClasses[rci];
1686 // Topological shortcut: SubRC members have the wrong shape.
1687 if (!TopoSigs.anyCommon(SubRC->getTopoSigs()))
1689 // Compute the subset of RC that maps into SubRC.
1690 CodeGenRegister::Set SubSet;
1691 for (unsigned i = 0, e = SSPairs.size(); i != e; ++i)
1692 if (SubRC->contains(SSPairs[i].second))
1693 SubSet.insert(SSPairs[i].first);
1696 // RC injects completely into SubRC.
1697 if (SubSet.size() == SSPairs.size()) {
1698 SubRC->addSuperRegClass(SubIdx, RC);
1701 // Only a subset of RC maps into SubRC. Make sure it is represented by a
1703 getOrCreateSubClass(RC, &SubSet, RC->getName() +
1704 "_with_" + SubIdx->getName() +
1705 "_in_" + SubRC->getName());
1712 // Infer missing register classes.
1714 void CodeGenRegBank::computeInferredRegisterClasses() {
1715 // When this function is called, the register classes have not been sorted
1716 // and assigned EnumValues yet. That means getSubClasses(),
1717 // getSuperClasses(), and hasSubClass() functions are defunct.
1718 unsigned FirstNewRC = RegClasses.size();
1720 // Visit all register classes, including the ones being added by the loop.
1721 for (unsigned rci = 0; rci != RegClasses.size(); ++rci) {
1722 CodeGenRegisterClass *RC = RegClasses[rci];
1724 // Synthesize answers for getSubClassWithSubReg().
1725 inferSubClassWithSubReg(RC);
1727 // Synthesize answers for getCommonSubClass().
1728 inferCommonSubClass(RC);
1730 // Synthesize answers for getMatchingSuperRegClass().
1731 inferMatchingSuperRegClass(RC);
1733 // New register classes are created while this loop is running, and we need
1734 // to visit all of them. I particular, inferMatchingSuperRegClass needs
1735 // to match old super-register classes with sub-register classes created
1736 // after inferMatchingSuperRegClass was called. At this point,
1737 // inferMatchingSuperRegClass has checked SuperRC = [0..rci] with SubRC =
1738 // [0..FirstNewRC). We need to cover SubRC = [FirstNewRC..rci].
1739 if (rci + 1 == FirstNewRC) {
1740 unsigned NextNewRC = RegClasses.size();
1741 for (unsigned rci2 = 0; rci2 != FirstNewRC; ++rci2)
1742 inferMatchingSuperRegClass(RegClasses[rci2], FirstNewRC);
1743 FirstNewRC = NextNewRC;
1748 /// getRegisterClassForRegister - Find the register class that contains the
1749 /// specified physical register. If the register is not in a register class,
1750 /// return null. If the register is in multiple classes, and the classes have a
1751 /// superset-subset relationship and the same set of types, return the
1752 /// superclass. Otherwise return null.
1753 const CodeGenRegisterClass*
1754 CodeGenRegBank::getRegClassForRegister(Record *R) {
1755 const CodeGenRegister *Reg = getReg(R);
1756 ArrayRef<CodeGenRegisterClass*> RCs = getRegClasses();
1757 const CodeGenRegisterClass *FoundRC = 0;
1758 for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
1759 const CodeGenRegisterClass &RC = *RCs[i];
1760 if (!RC.contains(Reg))
1763 // If this is the first class that contains the register,
1764 // make a note of it and go on to the next class.
1770 // If a register's classes have different types, return null.
1771 if (RC.getValueTypes() != FoundRC->getValueTypes())
1774 // Check to see if the previously found class that contains
1775 // the register is a subclass of the current class. If so,
1776 // prefer the superclass.
1777 if (RC.hasSubClass(FoundRC)) {
1782 // Check to see if the previously found class that contains
1783 // the register is a superclass of the current class. If so,
1784 // prefer the superclass.
1785 if (FoundRC->hasSubClass(&RC))
1788 // Multiple classes, and neither is a superclass of the other.
1795 BitVector CodeGenRegBank::computeCoveredRegisters(ArrayRef<Record*> Regs) {
1796 SetVector<const CodeGenRegister*> Set;
1798 // First add Regs with all sub-registers.
1799 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
1800 CodeGenRegister *Reg = getReg(Regs[i]);
1801 if (Set.insert(Reg))
1802 // Reg is new, add all sub-registers.
1803 // The pre-ordering is not important here.
1804 Reg->addSubRegsPreOrder(Set, *this);
1807 // Second, find all super-registers that are completely covered by the set.
1808 for (unsigned i = 0; i != Set.size(); ++i) {
1809 const CodeGenRegister::SuperRegList &SR = Set[i]->getSuperRegs();
1810 for (unsigned j = 0, e = SR.size(); j != e; ++j) {
1811 const CodeGenRegister *Super = SR[j];
1812 if (!Super->CoveredBySubRegs || Set.count(Super))
1814 // This new super-register is covered by its sub-registers.
1815 bool AllSubsInSet = true;
1816 const CodeGenRegister::SubRegMap &SRM = Super->getSubRegs();
1817 for (CodeGenRegister::SubRegMap::const_iterator I = SRM.begin(),
1818 E = SRM.end(); I != E; ++I)
1819 if (!Set.count(I->second)) {
1820 AllSubsInSet = false;
1823 // All sub-registers in Set, add Super as well.
1824 // We will visit Super later to recheck its super-registers.
1830 // Convert to BitVector.
1831 BitVector BV(Registers.size() + 1);
1832 for (unsigned i = 0, e = Set.size(); i != e; ++i)
1833 BV.set(Set[i]->EnumValue);