1 //===- CodeGenRegisters.cpp - Register and RegisterClass Info -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines structures to encapsulate information gleaned from the
11 // target register and register class definitions.
13 //===----------------------------------------------------------------------===//
15 #include "CodeGenRegisters.h"
16 #include "CodeGenTarget.h"
17 #include "llvm/ADT/IntEqClasses.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/ADT/StringExtras.h"
21 #include "llvm/ADT/Twine.h"
22 #include "llvm/TableGen/Error.h"
26 //===----------------------------------------------------------------------===//
28 //===----------------------------------------------------------------------===//
30 CodeGenSubRegIndex::CodeGenSubRegIndex(Record *R, unsigned Enum)
31 : TheDef(R), EnumValue(Enum), LaneMask(0), AllSuperRegsCovered(true) {
33 if (R->getValue("Namespace"))
34 Namespace = R->getValueAsString("Namespace");
37 CodeGenSubRegIndex::CodeGenSubRegIndex(StringRef N, StringRef Nspace,
39 : TheDef(0), Name(N), Namespace(Nspace), EnumValue(Enum),
40 LaneMask(0), AllSuperRegsCovered(true) {
43 std::string CodeGenSubRegIndex::getQualifiedName() const {
44 std::string N = getNamespace();
51 void CodeGenSubRegIndex::updateComponents(CodeGenRegBank &RegBank) {
55 std::vector<Record*> Comps = TheDef->getValueAsListOfDefs("ComposedOf");
57 if (Comps.size() != 2)
58 PrintFatalError(TheDef->getLoc(),
59 "ComposedOf must have exactly two entries");
60 CodeGenSubRegIndex *A = RegBank.getSubRegIdx(Comps[0]);
61 CodeGenSubRegIndex *B = RegBank.getSubRegIdx(Comps[1]);
62 CodeGenSubRegIndex *X = A->addComposite(B, this);
64 PrintFatalError(TheDef->getLoc(), "Ambiguous ComposedOf entries");
67 std::vector<Record*> Parts =
68 TheDef->getValueAsListOfDefs("CoveringSubRegIndices");
71 PrintFatalError(TheDef->getLoc(),
72 "CoveredBySubRegs must have two or more entries");
73 SmallVector<CodeGenSubRegIndex*, 8> IdxParts;
74 for (unsigned i = 0, e = Parts.size(); i != e; ++i)
75 IdxParts.push_back(RegBank.getSubRegIdx(Parts[i]));
76 RegBank.addConcatSubRegIndex(IdxParts, this);
80 unsigned CodeGenSubRegIndex::computeLaneMask() {
85 // Recursion guard, shouldn't be required.
88 // The lane mask is simply the union of all sub-indices.
90 for (CompMap::iterator I = Composed.begin(), E = Composed.end(); I != E; ++I)
91 M |= I->second->computeLaneMask();
92 assert(M && "Missing lane mask, sub-register cycle?");
97 //===----------------------------------------------------------------------===//
99 //===----------------------------------------------------------------------===//
101 CodeGenRegister::CodeGenRegister(Record *R, unsigned Enum)
104 CostPerUse(R->getValueAsInt("CostPerUse")),
105 CoveredBySubRegs(R->getValueAsBit("CoveredBySubRegs")),
106 NumNativeRegUnits(0),
107 SubRegsComplete(false),
108 SuperRegsComplete(false),
112 void CodeGenRegister::buildObjectGraph(CodeGenRegBank &RegBank) {
113 std::vector<Record*> SRIs = TheDef->getValueAsListOfDefs("SubRegIndices");
114 std::vector<Record*> SRs = TheDef->getValueAsListOfDefs("SubRegs");
116 if (SRIs.size() != SRs.size())
117 PrintFatalError(TheDef->getLoc(),
118 "SubRegs and SubRegIndices must have the same size");
120 for (unsigned i = 0, e = SRIs.size(); i != e; ++i) {
121 ExplicitSubRegIndices.push_back(RegBank.getSubRegIdx(SRIs[i]));
122 ExplicitSubRegs.push_back(RegBank.getReg(SRs[i]));
125 // Also compute leading super-registers. Each register has a list of
126 // covered-by-subregs super-registers where it appears as the first explicit
129 // This is used by computeSecondarySubRegs() to find candidates.
130 if (CoveredBySubRegs && !ExplicitSubRegs.empty())
131 ExplicitSubRegs.front()->LeadingSuperRegs.push_back(this);
133 // Add ad hoc alias links. This is a symmetric relationship between two
134 // registers, so build a symmetric graph by adding links in both ends.
135 std::vector<Record*> Aliases = TheDef->getValueAsListOfDefs("Aliases");
136 for (unsigned i = 0, e = Aliases.size(); i != e; ++i) {
137 CodeGenRegister *Reg = RegBank.getReg(Aliases[i]);
138 ExplicitAliases.push_back(Reg);
139 Reg->ExplicitAliases.push_back(this);
143 const std::string &CodeGenRegister::getName() const {
144 return TheDef->getName();
148 // Iterate over all register units in a set of registers.
149 class RegUnitIterator {
150 CodeGenRegister::Set::const_iterator RegI, RegE;
151 CodeGenRegister::RegUnitList::const_iterator UnitI, UnitE;
154 RegUnitIterator(const CodeGenRegister::Set &Regs):
155 RegI(Regs.begin()), RegE(Regs.end()), UnitI(), UnitE() {
158 UnitI = (*RegI)->getRegUnits().begin();
159 UnitE = (*RegI)->getRegUnits().end();
164 bool isValid() const { return UnitI != UnitE; }
166 unsigned operator* () const { assert(isValid()); return *UnitI; }
168 const CodeGenRegister *getReg() const { assert(isValid()); return *RegI; }
170 /// Preincrement. Move to the next unit.
172 assert(isValid() && "Cannot advance beyond the last operand");
179 while (UnitI == UnitE) {
182 UnitI = (*RegI)->getRegUnits().begin();
183 UnitE = (*RegI)->getRegUnits().end();
189 // Merge two RegUnitLists maintaining the order and removing duplicates.
190 // Overwrites MergedRU in the process.
191 static void mergeRegUnits(CodeGenRegister::RegUnitList &MergedRU,
192 const CodeGenRegister::RegUnitList &RRU) {
193 CodeGenRegister::RegUnitList LRU = MergedRU;
195 std::set_union(LRU.begin(), LRU.end(), RRU.begin(), RRU.end(),
196 std::back_inserter(MergedRU));
199 // Return true of this unit appears in RegUnits.
200 static bool hasRegUnit(CodeGenRegister::RegUnitList &RegUnits, unsigned Unit) {
201 return std::count(RegUnits.begin(), RegUnits.end(), Unit);
204 // Inherit register units from subregisters.
205 // Return true if the RegUnits changed.
206 bool CodeGenRegister::inheritRegUnits(CodeGenRegBank &RegBank) {
207 unsigned OldNumUnits = RegUnits.size();
208 for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
210 CodeGenRegister *SR = I->second;
211 // Merge the subregister's units into this register's RegUnits.
212 mergeRegUnits(RegUnits, SR->RegUnits);
214 return OldNumUnits != RegUnits.size();
217 const CodeGenRegister::SubRegMap &
218 CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) {
219 // Only compute this map once.
222 SubRegsComplete = true;
224 // First insert the explicit subregs and make sure they are fully indexed.
225 for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) {
226 CodeGenRegister *SR = ExplicitSubRegs[i];
227 CodeGenSubRegIndex *Idx = ExplicitSubRegIndices[i];
228 if (!SubRegs.insert(std::make_pair(Idx, SR)).second)
229 PrintFatalError(TheDef->getLoc(), "SubRegIndex " + Idx->getName() +
230 " appears twice in Register " + getName());
231 // Map explicit sub-registers first, so the names take precedence.
232 // The inherited sub-registers are mapped below.
233 SubReg2Idx.insert(std::make_pair(SR, Idx));
236 // Keep track of inherited subregs and how they can be reached.
237 SmallPtrSet<CodeGenRegister*, 8> Orphans;
239 // Clone inherited subregs and place duplicate entries in Orphans.
240 // Here the order is important - earlier subregs take precedence.
241 for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) {
242 CodeGenRegister *SR = ExplicitSubRegs[i];
243 const SubRegMap &Map = SR->computeSubRegs(RegBank);
245 for (SubRegMap::const_iterator SI = Map.begin(), SE = Map.end(); SI != SE;
247 if (!SubRegs.insert(*SI).second)
248 Orphans.insert(SI->second);
252 // Expand any composed subreg indices.
253 // If dsub_2 has ComposedOf = [qsub_1, dsub_0], and this register has a
254 // qsub_1 subreg, add a dsub_2 subreg. Keep growing Indices and process
255 // expanded subreg indices recursively.
256 SmallVector<CodeGenSubRegIndex*, 8> Indices = ExplicitSubRegIndices;
257 for (unsigned i = 0; i != Indices.size(); ++i) {
258 CodeGenSubRegIndex *Idx = Indices[i];
259 const CodeGenSubRegIndex::CompMap &Comps = Idx->getComposites();
260 CodeGenRegister *SR = SubRegs[Idx];
261 const SubRegMap &Map = SR->computeSubRegs(RegBank);
263 // Look at the possible compositions of Idx.
264 // They may not all be supported by SR.
265 for (CodeGenSubRegIndex::CompMap::const_iterator I = Comps.begin(),
266 E = Comps.end(); I != E; ++I) {
267 SubRegMap::const_iterator SRI = Map.find(I->first);
268 if (SRI == Map.end())
269 continue; // Idx + I->first doesn't exist in SR.
270 // Add I->second as a name for the subreg SRI->second, assuming it is
271 // orphaned, and the name isn't already used for something else.
272 if (SubRegs.count(I->second) || !Orphans.erase(SRI->second))
274 // We found a new name for the orphaned sub-register.
275 SubRegs.insert(std::make_pair(I->second, SRI->second));
276 Indices.push_back(I->second);
280 // Now Orphans contains the inherited subregisters without a direct index.
281 // Create inferred indexes for all missing entries.
282 // Work backwards in the Indices vector in order to compose subregs bottom-up.
283 // Consider this subreg sequence:
285 // qsub_1 -> dsub_0 -> ssub_0
287 // The qsub_1 -> dsub_0 composition becomes dsub_2, so the ssub_0 register
288 // can be reached in two different ways:
293 // We pick the latter composition because another register may have [dsub_0,
294 // dsub_1, dsub_2] subregs without necessarily having a qsub_1 subreg. The
295 // dsub_2 -> ssub_0 composition can be shared.
296 while (!Indices.empty() && !Orphans.empty()) {
297 CodeGenSubRegIndex *Idx = Indices.pop_back_val();
298 CodeGenRegister *SR = SubRegs[Idx];
299 const SubRegMap &Map = SR->computeSubRegs(RegBank);
300 for (SubRegMap::const_iterator SI = Map.begin(), SE = Map.end(); SI != SE;
302 if (Orphans.erase(SI->second))
303 SubRegs[RegBank.getCompositeSubRegIndex(Idx, SI->first)] = SI->second;
306 // Compute the inverse SubReg -> Idx map.
307 for (SubRegMap::const_iterator SI = SubRegs.begin(), SE = SubRegs.end();
309 if (SI->second == this) {
312 Loc = TheDef->getLoc();
313 PrintFatalError(Loc, "Register " + getName() +
314 " has itself as a sub-register");
317 // Compute AllSuperRegsCovered.
318 if (!CoveredBySubRegs)
319 SI->first->AllSuperRegsCovered = false;
321 // Ensure that every sub-register has a unique name.
322 DenseMap<const CodeGenRegister*, CodeGenSubRegIndex*>::iterator Ins =
323 SubReg2Idx.insert(std::make_pair(SI->second, SI->first)).first;
324 if (Ins->second == SI->first)
326 // Trouble: Two different names for SI->second.
329 Loc = TheDef->getLoc();
330 PrintFatalError(Loc, "Sub-register can't have two names: " +
331 SI->second->getName() + " available as " +
332 SI->first->getName() + " and " + Ins->second->getName());
335 // Derive possible names for sub-register concatenations from any explicit
336 // sub-registers. By doing this before computeSecondarySubRegs(), we ensure
337 // that getConcatSubRegIndex() won't invent any concatenated indices that the
338 // user already specified.
339 for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) {
340 CodeGenRegister *SR = ExplicitSubRegs[i];
341 if (!SR->CoveredBySubRegs || SR->ExplicitSubRegs.size() <= 1)
344 // SR is composed of multiple sub-regs. Find their names in this register.
345 SmallVector<CodeGenSubRegIndex*, 8> Parts;
346 for (unsigned j = 0, e = SR->ExplicitSubRegs.size(); j != e; ++j)
347 Parts.push_back(getSubRegIndex(SR->ExplicitSubRegs[j]));
349 // Offer this as an existing spelling for the concatenation of Parts.
350 RegBank.addConcatSubRegIndex(Parts, ExplicitSubRegIndices[i]);
353 // Initialize RegUnitList. Because getSubRegs is called recursively, this
354 // processes the register hierarchy in postorder.
356 // Inherit all sub-register units. It is good enough to look at the explicit
357 // sub-registers, the other registers won't contribute any more units.
358 for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) {
359 CodeGenRegister *SR = ExplicitSubRegs[i];
360 // Explicit sub-registers are usually disjoint, so this is a good way of
361 // computing the union. We may pick up a few duplicates that will be
363 unsigned N = RegUnits.size();
364 RegUnits.append(SR->RegUnits.begin(), SR->RegUnits.end());
365 std::inplace_merge(RegUnits.begin(), RegUnits.begin() + N, RegUnits.end());
367 RegUnits.erase(std::unique(RegUnits.begin(), RegUnits.end()), RegUnits.end());
369 // Absent any ad hoc aliasing, we create one register unit per leaf register.
370 // These units correspond to the maximal cliques in the register overlap
371 // graph which is optimal.
373 // When there is ad hoc aliasing, we simply create one unit per edge in the
374 // undirected ad hoc aliasing graph. Technically, we could do better by
375 // identifying maximal cliques in the ad hoc graph, but cliques larger than 2
376 // are extremely rare anyway (I've never seen one), so we don't bother with
377 // the added complexity.
378 for (unsigned i = 0, e = ExplicitAliases.size(); i != e; ++i) {
379 CodeGenRegister *AR = ExplicitAliases[i];
380 // Only visit each edge once.
381 if (AR->SubRegsComplete)
383 // Create a RegUnit representing this alias edge, and add it to both
385 unsigned Unit = RegBank.newRegUnit(this, AR);
386 RegUnits.push_back(Unit);
387 AR->RegUnits.push_back(Unit);
390 // Finally, create units for leaf registers without ad hoc aliases. Note that
391 // a leaf register with ad hoc aliases doesn't get its own unit - it isn't
392 // necessary. This means the aliasing leaf registers can share a single unit.
393 if (RegUnits.empty())
394 RegUnits.push_back(RegBank.newRegUnit(this));
396 // We have now computed the native register units. More may be adopted later
397 // for balancing purposes.
398 NumNativeRegUnits = RegUnits.size();
403 // In a register that is covered by its sub-registers, try to find redundant
404 // sub-registers. For example:
410 // We can infer that D1_D2 is also a sub-register, even if it wasn't named in
411 // the register definition.
413 // The explicitly specified registers form a tree. This function discovers
414 // sub-register relationships that would force a DAG.
416 void CodeGenRegister::computeSecondarySubRegs(CodeGenRegBank &RegBank) {
417 // Collect new sub-registers first, add them later.
418 SmallVector<SubRegMap::value_type, 8> NewSubRegs;
420 // Look at the leading super-registers of each sub-register. Those are the
421 // candidates for new sub-registers, assuming they are fully contained in
423 for (SubRegMap::iterator I = SubRegs.begin(), E = SubRegs.end(); I != E; ++I){
424 const CodeGenRegister *SubReg = I->second;
425 const CodeGenRegister::SuperRegList &Leads = SubReg->LeadingSuperRegs;
426 for (unsigned i = 0, e = Leads.size(); i != e; ++i) {
427 CodeGenRegister *Cand = const_cast<CodeGenRegister*>(Leads[i]);
428 // Already got this sub-register?
429 if (Cand == this || getSubRegIndex(Cand))
431 // Check if each component of Cand is already a sub-register.
432 // We know that the first component is I->second, and is present with the
434 SmallVector<CodeGenSubRegIndex*, 8> Parts(1, I->first);
435 assert(!Cand->ExplicitSubRegs.empty() &&
436 "Super-register has no sub-registers");
437 for (unsigned j = 1, e = Cand->ExplicitSubRegs.size(); j != e; ++j) {
438 if (CodeGenSubRegIndex *Idx = getSubRegIndex(Cand->ExplicitSubRegs[j]))
439 Parts.push_back(Idx);
441 // Sub-register doesn't exist.
446 // If some Cand sub-register is not part of this register, or if Cand only
447 // has one sub-register, there is nothing to do.
448 if (Parts.size() <= 1)
451 // Each part of Cand is a sub-register of this. Make the full Cand also
452 // a sub-register with a concatenated sub-register index.
453 CodeGenSubRegIndex *Concat= RegBank.getConcatSubRegIndex(Parts);
454 NewSubRegs.push_back(std::make_pair(Concat, Cand));
458 // Now add all the new sub-registers.
459 for (unsigned i = 0, e = NewSubRegs.size(); i != e; ++i) {
460 // Don't add Cand if another sub-register is already using the index.
461 if (!SubRegs.insert(NewSubRegs[i]).second)
464 CodeGenSubRegIndex *NewIdx = NewSubRegs[i].first;
465 CodeGenRegister *NewSubReg = NewSubRegs[i].second;
466 SubReg2Idx.insert(std::make_pair(NewSubReg, NewIdx));
469 // Create sub-register index composition maps for the synthesized indices.
470 for (unsigned i = 0, e = NewSubRegs.size(); i != e; ++i) {
471 CodeGenSubRegIndex *NewIdx = NewSubRegs[i].first;
472 CodeGenRegister *NewSubReg = NewSubRegs[i].second;
473 for (SubRegMap::const_iterator SI = NewSubReg->SubRegs.begin(),
474 SE = NewSubReg->SubRegs.end(); SI != SE; ++SI) {
475 CodeGenSubRegIndex *SubIdx = getSubRegIndex(SI->second);
477 PrintFatalError(TheDef->getLoc(), "No SubRegIndex for " +
478 SI->second->getName() + " in " + getName());
479 NewIdx->addComposite(SI->first, SubIdx);
484 void CodeGenRegister::computeSuperRegs(CodeGenRegBank &RegBank) {
485 // Only visit each register once.
486 if (SuperRegsComplete)
488 SuperRegsComplete = true;
490 // Make sure all sub-registers have been visited first, so the super-reg
491 // lists will be topologically ordered.
492 for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
494 I->second->computeSuperRegs(RegBank);
496 // Now add this as a super-register on all sub-registers.
497 // Also compute the TopoSigId in post-order.
499 for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
501 // Topological signature computed from SubIdx, TopoId(SubReg).
502 // Loops and idempotent indices have TopoSig = ~0u.
503 Id.push_back(I->first->EnumValue);
504 Id.push_back(I->second->TopoSig);
506 // Don't add duplicate entries.
507 if (!I->second->SuperRegs.empty() && I->second->SuperRegs.back() == this)
509 I->second->SuperRegs.push_back(this);
511 TopoSig = RegBank.getTopoSig(Id);
515 CodeGenRegister::addSubRegsPreOrder(SetVector<const CodeGenRegister*> &OSet,
516 CodeGenRegBank &RegBank) const {
517 assert(SubRegsComplete && "Must precompute sub-registers");
518 for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) {
519 CodeGenRegister *SR = ExplicitSubRegs[i];
521 SR->addSubRegsPreOrder(OSet, RegBank);
523 // Add any secondary sub-registers that weren't part of the explicit tree.
524 for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
526 OSet.insert(I->second);
529 // Get the sum of this register's unit weights.
530 unsigned CodeGenRegister::getWeight(const CodeGenRegBank &RegBank) const {
532 for (RegUnitList::const_iterator I = RegUnits.begin(), E = RegUnits.end();
534 Weight += RegBank.getRegUnit(*I).Weight;
539 //===----------------------------------------------------------------------===//
541 //===----------------------------------------------------------------------===//
543 // A RegisterTuples def is used to generate pseudo-registers from lists of
544 // sub-registers. We provide a SetTheory expander class that returns the new
547 struct TupleExpander : SetTheory::Expander {
548 void expand(SetTheory &ST, Record *Def, SetTheory::RecSet &Elts) {
549 std::vector<Record*> Indices = Def->getValueAsListOfDefs("SubRegIndices");
550 unsigned Dim = Indices.size();
551 ListInit *SubRegs = Def->getValueAsListInit("SubRegs");
552 if (Dim != SubRegs->getSize())
553 PrintFatalError(Def->getLoc(), "SubRegIndices and SubRegs size mismatch");
555 PrintFatalError(Def->getLoc(),
556 "Tuples must have at least 2 sub-registers");
558 // Evaluate the sub-register lists to be zipped.
559 unsigned Length = ~0u;
560 SmallVector<SetTheory::RecSet, 4> Lists(Dim);
561 for (unsigned i = 0; i != Dim; ++i) {
562 ST.evaluate(SubRegs->getElement(i), Lists[i], Def->getLoc());
563 Length = std::min(Length, unsigned(Lists[i].size()));
569 // Precompute some types.
570 Record *RegisterCl = Def->getRecords().getClass("Register");
571 RecTy *RegisterRecTy = RecordRecTy::get(RegisterCl);
572 StringInit *BlankName = StringInit::get("");
575 for (unsigned n = 0; n != Length; ++n) {
577 Record *Proto = Lists[0][n];
578 std::vector<Init*> Tuple;
579 unsigned CostPerUse = 0;
580 for (unsigned i = 0; i != Dim; ++i) {
581 Record *Reg = Lists[i][n];
583 Name += Reg->getName();
584 Tuple.push_back(DefInit::get(Reg));
585 CostPerUse = std::max(CostPerUse,
586 unsigned(Reg->getValueAsInt("CostPerUse")));
589 // Create a new Record representing the synthesized register. This record
590 // is only for consumption by CodeGenRegister, it is not added to the
592 Record *NewReg = new Record(Name, Def->getLoc(), Def->getRecords());
595 // Copy Proto super-classes.
596 ArrayRef<Record *> Supers = Proto->getSuperClasses();
597 ArrayRef<SMRange> Ranges = Proto->getSuperClassRanges();
598 for (unsigned i = 0, e = Supers.size(); i != e; ++i)
599 NewReg->addSuperClass(Supers[i], Ranges[i]);
601 // Copy Proto fields.
602 for (unsigned i = 0, e = Proto->getValues().size(); i != e; ++i) {
603 RecordVal RV = Proto->getValues()[i];
605 // Skip existing fields, like NAME.
606 if (NewReg->getValue(RV.getNameInit()))
609 StringRef Field = RV.getName();
611 // Replace the sub-register list with Tuple.
612 if (Field == "SubRegs")
613 RV.setValue(ListInit::get(Tuple, RegisterRecTy));
615 // Provide a blank AsmName. MC hacks are required anyway.
616 if (Field == "AsmName")
617 RV.setValue(BlankName);
619 // CostPerUse is aggregated from all Tuple members.
620 if (Field == "CostPerUse")
621 RV.setValue(IntInit::get(CostPerUse));
623 // Composite registers are always covered by sub-registers.
624 if (Field == "CoveredBySubRegs")
625 RV.setValue(BitInit::get(true));
627 // Copy fields from the RegisterTuples def.
628 if (Field == "SubRegIndices" ||
629 Field == "CompositeIndices") {
630 NewReg->addValue(*Def->getValue(Field));
634 // Some fields get their default uninitialized value.
635 if (Field == "DwarfNumbers" ||
636 Field == "DwarfAlias" ||
637 Field == "Aliases") {
638 if (const RecordVal *DefRV = RegisterCl->getValue(Field))
639 NewReg->addValue(*DefRV);
643 // Everything else is copied from Proto.
644 NewReg->addValue(RV);
651 //===----------------------------------------------------------------------===//
652 // CodeGenRegisterClass
653 //===----------------------------------------------------------------------===//
655 CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
658 TopoSigs(RegBank.getNumTopoSigs()),
660 // Rename anonymous register classes.
661 if (R->getName().size() > 9 && R->getName()[9] == '.') {
662 static unsigned AnonCounter = 0;
663 R->setName("AnonRegClass_" + utostr(AnonCounter));
664 // MSVC2012 ICEs if AnonCounter++ is directly passed to utostr.
668 std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes");
669 for (unsigned i = 0, e = TypeList.size(); i != e; ++i) {
670 Record *Type = TypeList[i];
671 if (!Type->isSubClassOf("ValueType"))
672 PrintFatalError("RegTypes list member '" + Type->getName() +
673 "' does not derive from the ValueType class!");
674 VTs.push_back(getValueType(Type));
676 assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!");
678 // Allocation order 0 is the full set. AltOrders provides others.
679 const SetTheory::RecVec *Elements = RegBank.getSets().expand(R);
680 ListInit *AltOrders = R->getValueAsListInit("AltOrders");
681 Orders.resize(1 + AltOrders->size());
683 // Default allocation order always contains all registers.
684 for (unsigned i = 0, e = Elements->size(); i != e; ++i) {
685 Orders[0].push_back((*Elements)[i]);
686 const CodeGenRegister *Reg = RegBank.getReg((*Elements)[i]);
688 TopoSigs.set(Reg->getTopoSig());
691 // Alternative allocation orders may be subsets.
692 SetTheory::RecSet Order;
693 for (unsigned i = 0, e = AltOrders->size(); i != e; ++i) {
694 RegBank.getSets().evaluate(AltOrders->getElement(i), Order, R->getLoc());
695 Orders[1 + i].append(Order.begin(), Order.end());
696 // Verify that all altorder members are regclass members.
697 while (!Order.empty()) {
698 CodeGenRegister *Reg = RegBank.getReg(Order.back());
701 PrintFatalError(R->getLoc(), " AltOrder register " + Reg->getName() +
702 " is not a class member");
706 // Allow targets to override the size in bits of the RegisterClass.
707 unsigned Size = R->getValueAsInt("Size");
709 Namespace = R->getValueAsString("Namespace");
710 SpillSize = Size ? Size : EVT(VTs[0]).getSizeInBits();
711 SpillAlignment = R->getValueAsInt("Alignment");
712 CopyCost = R->getValueAsInt("CopyCost");
713 Allocatable = R->getValueAsBit("isAllocatable");
714 AltOrderSelect = R->getValueAsString("AltOrderSelect");
717 // Create an inferred register class that was missing from the .td files.
718 // Most properties will be inherited from the closest super-class after the
719 // class structure has been computed.
720 CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank,
721 StringRef Name, Key Props)
722 : Members(*Props.Members),
725 TopoSigs(RegBank.getNumTopoSigs()),
727 SpillSize(Props.SpillSize),
728 SpillAlignment(Props.SpillAlignment),
731 for (CodeGenRegister::Set::iterator I = Members.begin(), E = Members.end();
733 TopoSigs.set((*I)->getTopoSig());
736 // Compute inherited propertied for a synthesized register class.
737 void CodeGenRegisterClass::inheritProperties(CodeGenRegBank &RegBank) {
738 assert(!getDef() && "Only synthesized classes can inherit properties");
739 assert(!SuperClasses.empty() && "Synthesized class without super class");
741 // The last super-class is the smallest one.
742 CodeGenRegisterClass &Super = *SuperClasses.back();
744 // Most properties are copied directly.
745 // Exceptions are members, size, and alignment
746 Namespace = Super.Namespace;
748 CopyCost = Super.CopyCost;
749 Allocatable = Super.Allocatable;
750 AltOrderSelect = Super.AltOrderSelect;
752 // Copy all allocation orders, filter out foreign registers from the larger
754 Orders.resize(Super.Orders.size());
755 for (unsigned i = 0, ie = Super.Orders.size(); i != ie; ++i)
756 for (unsigned j = 0, je = Super.Orders[i].size(); j != je; ++j)
757 if (contains(RegBank.getReg(Super.Orders[i][j])))
758 Orders[i].push_back(Super.Orders[i][j]);
761 bool CodeGenRegisterClass::contains(const CodeGenRegister *Reg) const {
762 return Members.count(Reg);
766 raw_ostream &operator<<(raw_ostream &OS, const CodeGenRegisterClass::Key &K) {
767 OS << "{ S=" << K.SpillSize << ", A=" << K.SpillAlignment;
768 for (CodeGenRegister::Set::const_iterator I = K.Members->begin(),
769 E = K.Members->end(); I != E; ++I)
770 OS << ", " << (*I)->getName();
775 // This is a simple lexicographical order that can be used to search for sets.
776 // It is not the same as the topological order provided by TopoOrderRC.
777 bool CodeGenRegisterClass::Key::
778 operator<(const CodeGenRegisterClass::Key &B) const {
779 assert(Members && B.Members);
780 if (*Members != *B.Members)
781 return *Members < *B.Members;
782 if (SpillSize != B.SpillSize)
783 return SpillSize < B.SpillSize;
784 return SpillAlignment < B.SpillAlignment;
787 // Returns true if RC is a strict subclass.
788 // RC is a sub-class of this class if it is a valid replacement for any
789 // instruction operand where a register of this classis required. It must
790 // satisfy these conditions:
792 // 1. All RC registers are also in this.
793 // 2. The RC spill size must not be smaller than our spill size.
794 // 3. RC spill alignment must be compatible with ours.
796 static bool testSubClass(const CodeGenRegisterClass *A,
797 const CodeGenRegisterClass *B) {
798 return A->SpillAlignment && B->SpillAlignment % A->SpillAlignment == 0 &&
799 A->SpillSize <= B->SpillSize &&
800 std::includes(A->getMembers().begin(), A->getMembers().end(),
801 B->getMembers().begin(), B->getMembers().end(),
802 CodeGenRegister::Less());
805 /// Sorting predicate for register classes. This provides a topological
806 /// ordering that arranges all register classes before their sub-classes.
808 /// Register classes with the same registers, spill size, and alignment form a
809 /// clique. They will be ordered alphabetically.
811 static int TopoOrderRC(const void *PA, const void *PB) {
812 const CodeGenRegisterClass *A = *(const CodeGenRegisterClass* const*)PA;
813 const CodeGenRegisterClass *B = *(const CodeGenRegisterClass* const*)PB;
817 // Order by ascending spill size.
818 if (A->SpillSize < B->SpillSize)
820 if (A->SpillSize > B->SpillSize)
823 // Order by ascending spill alignment.
824 if (A->SpillAlignment < B->SpillAlignment)
826 if (A->SpillAlignment > B->SpillAlignment)
829 // Order by descending set size. Note that the classes' allocation order may
830 // not have been computed yet. The Members set is always vaild.
831 if (A->getMembers().size() > B->getMembers().size())
833 if (A->getMembers().size() < B->getMembers().size())
836 // Finally order by name as a tie breaker.
837 return StringRef(A->getName()).compare(B->getName());
840 std::string CodeGenRegisterClass::getQualifiedName() const {
841 if (Namespace.empty())
844 return Namespace + "::" + getName();
847 // Compute sub-classes of all register classes.
848 // Assume the classes are ordered topologically.
849 void CodeGenRegisterClass::computeSubClasses(CodeGenRegBank &RegBank) {
850 ArrayRef<CodeGenRegisterClass*> RegClasses = RegBank.getRegClasses();
852 // Visit backwards so sub-classes are seen first.
853 for (unsigned rci = RegClasses.size(); rci; --rci) {
854 CodeGenRegisterClass &RC = *RegClasses[rci - 1];
855 RC.SubClasses.resize(RegClasses.size());
856 RC.SubClasses.set(RC.EnumValue);
858 // Normally, all subclasses have IDs >= rci, unless RC is part of a clique.
859 for (unsigned s = rci; s != RegClasses.size(); ++s) {
860 if (RC.SubClasses.test(s))
862 CodeGenRegisterClass *SubRC = RegClasses[s];
863 if (!testSubClass(&RC, SubRC))
865 // SubRC is a sub-class. Grap all its sub-classes so we won't have to
867 RC.SubClasses |= SubRC->SubClasses;
870 // Sweep up missed clique members. They will be immediately preceding RC.
871 for (unsigned s = rci - 1; s && testSubClass(&RC, RegClasses[s - 1]); --s)
872 RC.SubClasses.set(s - 1);
875 // Compute the SuperClasses lists from the SubClasses vectors.
876 for (unsigned rci = 0; rci != RegClasses.size(); ++rci) {
877 const BitVector &SC = RegClasses[rci]->getSubClasses();
878 for (int s = SC.find_first(); s >= 0; s = SC.find_next(s)) {
879 if (unsigned(s) == rci)
881 RegClasses[s]->SuperClasses.push_back(RegClasses[rci]);
885 // With the class hierarchy in place, let synthesized register classes inherit
886 // properties from their closest super-class. The iteration order here can
887 // propagate properties down multiple levels.
888 for (unsigned rci = 0; rci != RegClasses.size(); ++rci)
889 if (!RegClasses[rci]->getDef())
890 RegClasses[rci]->inheritProperties(RegBank);
894 CodeGenRegisterClass::getSuperRegClasses(CodeGenSubRegIndex *SubIdx,
895 BitVector &Out) const {
896 DenseMap<CodeGenSubRegIndex*,
897 SmallPtrSet<CodeGenRegisterClass*, 8> >::const_iterator
898 FindI = SuperRegClasses.find(SubIdx);
899 if (FindI == SuperRegClasses.end())
901 for (SmallPtrSet<CodeGenRegisterClass*, 8>::const_iterator I =
902 FindI->second.begin(), E = FindI->second.end(); I != E; ++I)
903 Out.set((*I)->EnumValue);
906 // Populate a unique sorted list of units from a register set.
907 void CodeGenRegisterClass::buildRegUnitSet(
908 std::vector<unsigned> &RegUnits) const {
909 std::vector<unsigned> TmpUnits;
910 for (RegUnitIterator UnitI(Members); UnitI.isValid(); ++UnitI)
911 TmpUnits.push_back(*UnitI);
912 std::sort(TmpUnits.begin(), TmpUnits.end());
913 std::unique_copy(TmpUnits.begin(), TmpUnits.end(),
914 std::back_inserter(RegUnits));
917 //===----------------------------------------------------------------------===//
919 //===----------------------------------------------------------------------===//
921 CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records) {
922 // Configure register Sets to understand register classes and tuples.
923 Sets.addFieldExpander("RegisterClass", "MemberList");
924 Sets.addFieldExpander("CalleeSavedRegs", "SaveList");
925 Sets.addExpander("RegisterTuples", new TupleExpander());
927 // Read in the user-defined (named) sub-register indices.
928 // More indices will be synthesized later.
929 std::vector<Record*> SRIs = Records.getAllDerivedDefinitions("SubRegIndex");
930 std::sort(SRIs.begin(), SRIs.end(), LessRecord());
931 for (unsigned i = 0, e = SRIs.size(); i != e; ++i)
932 getSubRegIdx(SRIs[i]);
933 // Build composite maps from ComposedOf fields.
934 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i)
935 SubRegIndices[i]->updateComponents(*this);
937 // Read in the register definitions.
938 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
939 std::sort(Regs.begin(), Regs.end(), LessRecord());
940 Registers.reserve(Regs.size());
941 // Assign the enumeration values.
942 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
945 // Expand tuples and number the new registers.
946 std::vector<Record*> Tups =
947 Records.getAllDerivedDefinitions("RegisterTuples");
948 for (unsigned i = 0, e = Tups.size(); i != e; ++i) {
949 const std::vector<Record*> *TupRegs = Sets.expand(Tups[i]);
950 for (unsigned j = 0, je = TupRegs->size(); j != je; ++j)
951 getReg((*TupRegs)[j]);
954 // Now all the registers are known. Build the object graph of explicit
955 // register-register references.
956 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
957 Registers[i]->buildObjectGraph(*this);
959 // Compute register name map.
960 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
961 RegistersByName.GetOrCreateValue(
962 Registers[i]->TheDef->getValueAsString("AsmName"),
965 // Precompute all sub-register maps.
966 // This will create Composite entries for all inferred sub-register indices.
967 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
968 Registers[i]->computeSubRegs(*this);
970 // Infer even more sub-registers by combining leading super-registers.
971 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
972 if (Registers[i]->CoveredBySubRegs)
973 Registers[i]->computeSecondarySubRegs(*this);
975 // After the sub-register graph is complete, compute the topologically
976 // ordered SuperRegs list.
977 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
978 Registers[i]->computeSuperRegs(*this);
980 // Native register units are associated with a leaf register. They've all been
982 NumNativeRegUnits = RegUnits.size();
984 // Read in register class definitions.
985 std::vector<Record*> RCs = Records.getAllDerivedDefinitions("RegisterClass");
987 PrintFatalError(std::string("No 'RegisterClass' subclasses defined!"));
989 // Allocate user-defined register classes.
990 RegClasses.reserve(RCs.size());
991 for (unsigned i = 0, e = RCs.size(); i != e; ++i)
992 addToMaps(new CodeGenRegisterClass(*this, RCs[i]));
994 // Infer missing classes to create a full algebra.
995 computeInferredRegisterClasses();
997 // Order register classes topologically and assign enum values.
998 array_pod_sort(RegClasses.begin(), RegClasses.end(), TopoOrderRC);
999 for (unsigned i = 0, e = RegClasses.size(); i != e; ++i)
1000 RegClasses[i]->EnumValue = i;
1001 CodeGenRegisterClass::computeSubClasses(*this);
1004 // Create a synthetic CodeGenSubRegIndex without a corresponding Record.
1006 CodeGenRegBank::createSubRegIndex(StringRef Name, StringRef Namespace) {
1007 CodeGenSubRegIndex *Idx = new CodeGenSubRegIndex(Name, Namespace,
1008 SubRegIndices.size() + 1);
1009 SubRegIndices.push_back(Idx);
1013 CodeGenSubRegIndex *CodeGenRegBank::getSubRegIdx(Record *Def) {
1014 CodeGenSubRegIndex *&Idx = Def2SubRegIdx[Def];
1017 Idx = new CodeGenSubRegIndex(Def, SubRegIndices.size() + 1);
1018 SubRegIndices.push_back(Idx);
1022 CodeGenRegister *CodeGenRegBank::getReg(Record *Def) {
1023 CodeGenRegister *&Reg = Def2Reg[Def];
1026 Reg = new CodeGenRegister(Def, Registers.size() + 1);
1027 Registers.push_back(Reg);
1031 void CodeGenRegBank::addToMaps(CodeGenRegisterClass *RC) {
1032 RegClasses.push_back(RC);
1034 if (Record *Def = RC->getDef())
1035 Def2RC.insert(std::make_pair(Def, RC));
1037 // Duplicate classes are rejected by insert().
1038 // That's OK, we only care about the properties handled by CGRC::Key.
1039 CodeGenRegisterClass::Key K(*RC);
1040 Key2RC.insert(std::make_pair(K, RC));
1043 // Create a synthetic sub-class if it is missing.
1044 CodeGenRegisterClass*
1045 CodeGenRegBank::getOrCreateSubClass(const CodeGenRegisterClass *RC,
1046 const CodeGenRegister::Set *Members,
1048 // Synthetic sub-class has the same size and alignment as RC.
1049 CodeGenRegisterClass::Key K(Members, RC->SpillSize, RC->SpillAlignment);
1050 RCKeyMap::const_iterator FoundI = Key2RC.find(K);
1051 if (FoundI != Key2RC.end())
1052 return FoundI->second;
1054 // Sub-class doesn't exist, create a new one.
1055 CodeGenRegisterClass *NewRC = new CodeGenRegisterClass(*this, Name, K);
1060 CodeGenRegisterClass *CodeGenRegBank::getRegClass(Record *Def) {
1061 if (CodeGenRegisterClass *RC = Def2RC[Def])
1064 PrintFatalError(Def->getLoc(), "Not a known RegisterClass!");
1068 CodeGenRegBank::getCompositeSubRegIndex(CodeGenSubRegIndex *A,
1069 CodeGenSubRegIndex *B) {
1070 // Look for an existing entry.
1071 CodeGenSubRegIndex *Comp = A->compose(B);
1075 // None exists, synthesize one.
1076 std::string Name = A->getName() + "_then_" + B->getName();
1077 Comp = createSubRegIndex(Name, A->getNamespace());
1078 A->addComposite(B, Comp);
1082 CodeGenSubRegIndex *CodeGenRegBank::
1083 getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex*, 8> &Parts) {
1084 assert(Parts.size() > 1 && "Need two parts to concatenate");
1086 // Look for an existing entry.
1087 CodeGenSubRegIndex *&Idx = ConcatIdx[Parts];
1091 // None exists, synthesize one.
1092 std::string Name = Parts.front()->getName();
1093 for (unsigned i = 1, e = Parts.size(); i != e; ++i) {
1095 Name += Parts[i]->getName();
1097 return Idx = createSubRegIndex(Name, Parts.front()->getNamespace());
1100 void CodeGenRegBank::computeComposites() {
1101 // Keep track of TopoSigs visited. We only need to visit each TopoSig once,
1102 // and many registers will share TopoSigs on regular architectures.
1103 BitVector TopoSigs(getNumTopoSigs());
1105 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
1106 CodeGenRegister *Reg1 = Registers[i];
1108 // Skip identical subreg structures already processed.
1109 if (TopoSigs.test(Reg1->getTopoSig()))
1111 TopoSigs.set(Reg1->getTopoSig());
1113 const CodeGenRegister::SubRegMap &SRM1 = Reg1->getSubRegs();
1114 for (CodeGenRegister::SubRegMap::const_iterator i1 = SRM1.begin(),
1115 e1 = SRM1.end(); i1 != e1; ++i1) {
1116 CodeGenSubRegIndex *Idx1 = i1->first;
1117 CodeGenRegister *Reg2 = i1->second;
1118 // Ignore identity compositions.
1121 const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs();
1122 // Try composing Idx1 with another SubRegIndex.
1123 for (CodeGenRegister::SubRegMap::const_iterator i2 = SRM2.begin(),
1124 e2 = SRM2.end(); i2 != e2; ++i2) {
1125 CodeGenSubRegIndex *Idx2 = i2->first;
1126 CodeGenRegister *Reg3 = i2->second;
1127 // Ignore identity compositions.
1130 // OK Reg1:IdxPair == Reg3. Find the index with Reg:Idx == Reg3.
1131 CodeGenSubRegIndex *Idx3 = Reg1->getSubRegIndex(Reg3);
1132 assert(Idx3 && "Sub-register doesn't have an index");
1134 // Conflicting composition? Emit a warning but allow it.
1135 if (CodeGenSubRegIndex *Prev = Idx1->addComposite(Idx2, Idx3))
1136 PrintWarning(Twine("SubRegIndex ") + Idx1->getQualifiedName() +
1137 " and " + Idx2->getQualifiedName() +
1138 " compose ambiguously as " + Prev->getQualifiedName() +
1139 " or " + Idx3->getQualifiedName());
1145 // Compute lane masks. This is similar to register units, but at the
1146 // sub-register index level. Each bit in the lane mask is like a register unit
1147 // class, and two lane masks will have a bit in common if two sub-register
1148 // indices overlap in some register.
1150 // Conservatively share a lane mask bit if two sub-register indices overlap in
1151 // some registers, but not in others. That shouldn't happen a lot.
1152 void CodeGenRegBank::computeSubRegIndexLaneMasks() {
1153 // First assign individual bits to all the leaf indices.
1155 // Determine mask of lanes that cover their registers.
1156 CoveringLanes = ~0u;
1157 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
1158 CodeGenSubRegIndex *Idx = SubRegIndices[i];
1159 if (Idx->getComposites().empty()) {
1160 Idx->LaneMask = 1u << Bit;
1161 // Share bit 31 in the unlikely case there are more than 32 leafs.
1163 // Sharing bits is harmless; it allows graceful degradation in targets
1164 // with more than 32 vector lanes. They simply get a limited resolution
1165 // view of lanes beyond the 32nd.
1167 // See also the comment for getSubRegIndexLaneMask().
1171 // Once bit 31 is shared among multiple leafs, the 'lane' it represents
1172 // is no longer covering its registers.
1173 CoveringLanes &= ~(1u << Bit);
1179 // FIXME: What if ad-hoc aliasing introduces overlaps that aren't represented
1180 // by the sub-register graph? This doesn't occur in any known targets.
1182 // Inherit lanes from composites.
1183 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
1184 unsigned Mask = SubRegIndices[i]->computeLaneMask();
1185 // If some super-registers without CoveredBySubRegs use this index, we can
1186 // no longer assume that the lanes are covering their registers.
1187 if (!SubRegIndices[i]->AllSuperRegsCovered)
1188 CoveringLanes &= ~Mask;
1193 // UberRegSet is a helper class for computeRegUnitWeights. Each UberRegSet is
1194 // the transitive closure of the union of overlapping register
1195 // classes. Together, the UberRegSets form a partition of the registers. If we
1196 // consider overlapping register classes to be connected, then each UberRegSet
1197 // is a set of connected components.
1199 // An UberRegSet will likely be a horizontal slice of register names of
1200 // the same width. Nontrivial subregisters should then be in a separate
1201 // UberRegSet. But this property isn't required for valid computation of
1202 // register unit weights.
1204 // A Weight field caches the max per-register unit weight in each UberRegSet.
1206 // A set of SingularDeterminants flags single units of some register in this set
1207 // for which the unit weight equals the set weight. These units should not have
1208 // their weight increased.
1210 CodeGenRegister::Set Regs;
1212 CodeGenRegister::RegUnitList SingularDeterminants;
1214 UberRegSet(): Weight(0) {}
1218 // Partition registers into UberRegSets, where each set is the transitive
1219 // closure of the union of overlapping register classes.
1221 // UberRegSets[0] is a special non-allocatable set.
1222 static void computeUberSets(std::vector<UberRegSet> &UberSets,
1223 std::vector<UberRegSet*> &RegSets,
1224 CodeGenRegBank &RegBank) {
1226 const std::vector<CodeGenRegister*> &Registers = RegBank.getRegisters();
1228 // The Register EnumValue is one greater than its index into Registers.
1229 assert(Registers.size() == Registers[Registers.size()-1]->EnumValue &&
1230 "register enum value mismatch");
1232 // For simplicitly make the SetID the same as EnumValue.
1233 IntEqClasses UberSetIDs(Registers.size()+1);
1234 std::set<unsigned> AllocatableRegs;
1235 for (unsigned i = 0, e = RegBank.getRegClasses().size(); i != e; ++i) {
1237 CodeGenRegisterClass *RegClass = RegBank.getRegClasses()[i];
1238 if (!RegClass->Allocatable)
1241 const CodeGenRegister::Set &Regs = RegClass->getMembers();
1245 unsigned USetID = UberSetIDs.findLeader((*Regs.begin())->EnumValue);
1246 assert(USetID && "register number 0 is invalid");
1248 AllocatableRegs.insert((*Regs.begin())->EnumValue);
1249 for (CodeGenRegister::Set::const_iterator I = llvm::next(Regs.begin()),
1250 E = Regs.end(); I != E; ++I) {
1251 AllocatableRegs.insert((*I)->EnumValue);
1252 UberSetIDs.join(USetID, (*I)->EnumValue);
1255 // Combine non-allocatable regs.
1256 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
1257 unsigned RegNum = Registers[i]->EnumValue;
1258 if (AllocatableRegs.count(RegNum))
1261 UberSetIDs.join(0, RegNum);
1263 UberSetIDs.compress();
1265 // Make the first UberSet a special unallocatable set.
1266 unsigned ZeroID = UberSetIDs[0];
1268 // Insert Registers into the UberSets formed by union-find.
1269 // Do not resize after this.
1270 UberSets.resize(UberSetIDs.getNumClasses());
1271 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
1272 const CodeGenRegister *Reg = Registers[i];
1273 unsigned USetID = UberSetIDs[Reg->EnumValue];
1276 else if (USetID == ZeroID)
1279 UberRegSet *USet = &UberSets[USetID];
1280 USet->Regs.insert(Reg);
1285 // Recompute each UberSet weight after changing unit weights.
1286 static void computeUberWeights(std::vector<UberRegSet> &UberSets,
1287 CodeGenRegBank &RegBank) {
1288 // Skip the first unallocatable set.
1289 for (std::vector<UberRegSet>::iterator I = llvm::next(UberSets.begin()),
1290 E = UberSets.end(); I != E; ++I) {
1292 // Initialize all unit weights in this set, and remember the max units/reg.
1293 const CodeGenRegister *Reg = 0;
1294 unsigned MaxWeight = 0, Weight = 0;
1295 for (RegUnitIterator UnitI(I->Regs); UnitI.isValid(); ++UnitI) {
1296 if (Reg != UnitI.getReg()) {
1297 if (Weight > MaxWeight)
1299 Reg = UnitI.getReg();
1302 unsigned UWeight = RegBank.getRegUnit(*UnitI).Weight;
1305 RegBank.increaseRegUnitWeight(*UnitI, UWeight);
1309 if (Weight > MaxWeight)
1312 // Update the set weight.
1313 I->Weight = MaxWeight;
1315 // Find singular determinants.
1316 for (CodeGenRegister::Set::iterator RegI = I->Regs.begin(),
1317 RegE = I->Regs.end(); RegI != RegE; ++RegI) {
1318 if ((*RegI)->getRegUnits().size() == 1
1319 && (*RegI)->getWeight(RegBank) == I->Weight)
1320 mergeRegUnits(I->SingularDeterminants, (*RegI)->getRegUnits());
1325 // normalizeWeight is a computeRegUnitWeights helper that adjusts the weight of
1326 // a register and its subregisters so that they have the same weight as their
1327 // UberSet. Self-recursion processes the subregister tree in postorder so
1328 // subregisters are normalized first.
1331 // - creates new adopted register units
1332 // - causes superregisters to inherit adopted units
1333 // - increases the weight of "singular" units
1334 // - induces recomputation of UberWeights.
1335 static bool normalizeWeight(CodeGenRegister *Reg,
1336 std::vector<UberRegSet> &UberSets,
1337 std::vector<UberRegSet*> &RegSets,
1338 std::set<unsigned> &NormalRegs,
1339 CodeGenRegister::RegUnitList &NormalUnits,
1340 CodeGenRegBank &RegBank) {
1341 bool Changed = false;
1342 if (!NormalRegs.insert(Reg->EnumValue).second)
1345 const CodeGenRegister::SubRegMap &SRM = Reg->getSubRegs();
1346 for (CodeGenRegister::SubRegMap::const_iterator SRI = SRM.begin(),
1347 SRE = SRM.end(); SRI != SRE; ++SRI) {
1348 if (SRI->second == Reg)
1349 continue; // self-cycles happen
1351 Changed |= normalizeWeight(SRI->second, UberSets, RegSets,
1352 NormalRegs, NormalUnits, RegBank);
1354 // Postorder register normalization.
1356 // Inherit register units newly adopted by subregisters.
1357 if (Reg->inheritRegUnits(RegBank))
1358 computeUberWeights(UberSets, RegBank);
1360 // Check if this register is too skinny for its UberRegSet.
1361 UberRegSet *UberSet = RegSets[RegBank.getRegIndex(Reg)];
1363 unsigned RegWeight = Reg->getWeight(RegBank);
1364 if (UberSet->Weight > RegWeight) {
1365 // A register unit's weight can be adjusted only if it is the singular unit
1366 // for this register, has not been used to normalize a subregister's set,
1367 // and has not already been used to singularly determine this UberRegSet.
1368 unsigned AdjustUnit = Reg->getRegUnits().front();
1369 if (Reg->getRegUnits().size() != 1
1370 || hasRegUnit(NormalUnits, AdjustUnit)
1371 || hasRegUnit(UberSet->SingularDeterminants, AdjustUnit)) {
1372 // We don't have an adjustable unit, so adopt a new one.
1373 AdjustUnit = RegBank.newRegUnit(UberSet->Weight - RegWeight);
1374 Reg->adoptRegUnit(AdjustUnit);
1375 // Adopting a unit does not immediately require recomputing set weights.
1378 // Adjust the existing single unit.
1379 RegBank.increaseRegUnitWeight(AdjustUnit, UberSet->Weight - RegWeight);
1380 // The unit may be shared among sets and registers within this set.
1381 computeUberWeights(UberSets, RegBank);
1386 // Mark these units normalized so superregisters can't change their weights.
1387 mergeRegUnits(NormalUnits, Reg->getRegUnits());
1392 // Compute a weight for each register unit created during getSubRegs.
1394 // The goal is that two registers in the same class will have the same weight,
1395 // where each register's weight is defined as sum of its units' weights.
1396 void CodeGenRegBank::computeRegUnitWeights() {
1397 std::vector<UberRegSet> UberSets;
1398 std::vector<UberRegSet*> RegSets(Registers.size());
1399 computeUberSets(UberSets, RegSets, *this);
1400 // UberSets and RegSets are now immutable.
1402 computeUberWeights(UberSets, *this);
1404 // Iterate over each Register, normalizing the unit weights until reaching
1406 unsigned NumIters = 0;
1407 for (bool Changed = true; Changed; ++NumIters) {
1408 assert(NumIters <= NumNativeRegUnits && "Runaway register unit weights");
1410 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
1411 CodeGenRegister::RegUnitList NormalUnits;
1412 std::set<unsigned> NormalRegs;
1413 Changed |= normalizeWeight(Registers[i], UberSets, RegSets,
1414 NormalRegs, NormalUnits, *this);
1419 // Find a set in UniqueSets with the same elements as Set.
1420 // Return an iterator into UniqueSets.
1421 static std::vector<RegUnitSet>::const_iterator
1422 findRegUnitSet(const std::vector<RegUnitSet> &UniqueSets,
1423 const RegUnitSet &Set) {
1424 std::vector<RegUnitSet>::const_iterator
1425 I = UniqueSets.begin(), E = UniqueSets.end();
1427 if (I->Units == Set.Units)
1433 // Return true if the RUSubSet is a subset of RUSuperSet.
1434 static bool isRegUnitSubSet(const std::vector<unsigned> &RUSubSet,
1435 const std::vector<unsigned> &RUSuperSet) {
1436 return std::includes(RUSuperSet.begin(), RUSuperSet.end(),
1437 RUSubSet.begin(), RUSubSet.end());
1440 // Iteratively prune unit sets.
1441 void CodeGenRegBank::pruneUnitSets() {
1442 assert(RegClassUnitSets.empty() && "this invalidates RegClassUnitSets");
1444 // Form an equivalence class of UnitSets with no significant difference.
1445 std::vector<unsigned> SuperSetIDs;
1446 for (unsigned SubIdx = 0, EndIdx = RegUnitSets.size();
1447 SubIdx != EndIdx; ++SubIdx) {
1448 const RegUnitSet &SubSet = RegUnitSets[SubIdx];
1449 unsigned SuperIdx = 0;
1450 for (; SuperIdx != EndIdx; ++SuperIdx) {
1451 if (SuperIdx == SubIdx)
1454 const RegUnitSet &SuperSet = RegUnitSets[SuperIdx];
1455 if (isRegUnitSubSet(SubSet.Units, SuperSet.Units)
1456 && (SubSet.Units.size() + 3 > SuperSet.Units.size())) {
1460 if (SuperIdx == EndIdx)
1461 SuperSetIDs.push_back(SubIdx);
1463 // Populate PrunedUnitSets with each equivalence class's superset.
1464 std::vector<RegUnitSet> PrunedUnitSets(SuperSetIDs.size());
1465 for (unsigned i = 0, e = SuperSetIDs.size(); i != e; ++i) {
1466 unsigned SuperIdx = SuperSetIDs[i];
1467 PrunedUnitSets[i].Name = RegUnitSets[SuperIdx].Name;
1468 PrunedUnitSets[i].Units.swap(RegUnitSets[SuperIdx].Units);
1470 RegUnitSets.swap(PrunedUnitSets);
1473 // Create a RegUnitSet for each RegClass that contains all units in the class
1474 // including adopted units that are necessary to model register pressure. Then
1475 // iteratively compute RegUnitSets such that the union of any two overlapping
1476 // RegUnitSets is repreresented.
1478 // RegisterInfoEmitter will map each RegClass to its RegUnitClass and any
1479 // RegUnitSet that is a superset of that RegUnitClass.
1480 void CodeGenRegBank::computeRegUnitSets() {
1482 // Compute a unique RegUnitSet for each RegClass.
1483 const ArrayRef<CodeGenRegisterClass*> &RegClasses = getRegClasses();
1484 unsigned NumRegClasses = RegClasses.size();
1485 for (unsigned RCIdx = 0, RCEnd = NumRegClasses; RCIdx != RCEnd; ++RCIdx) {
1486 if (!RegClasses[RCIdx]->Allocatable)
1489 // Speculatively grow the RegUnitSets to hold the new set.
1490 RegUnitSets.resize(RegUnitSets.size() + 1);
1491 RegUnitSets.back().Name = RegClasses[RCIdx]->getName();
1493 // Compute a sorted list of units in this class.
1494 RegClasses[RCIdx]->buildRegUnitSet(RegUnitSets.back().Units);
1496 // Find an existing RegUnitSet.
1497 std::vector<RegUnitSet>::const_iterator SetI =
1498 findRegUnitSet(RegUnitSets, RegUnitSets.back());
1499 if (SetI != llvm::prior(RegUnitSets.end()))
1500 RegUnitSets.pop_back();
1503 // Iteratively prune unit sets.
1506 // Iterate over all unit sets, including new ones added by this loop.
1507 unsigned NumRegUnitSubSets = RegUnitSets.size();
1508 for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx) {
1509 // In theory, this is combinatorial. In practice, it needs to be bounded
1510 // by a small number of sets for regpressure to be efficient.
1511 // If the assert is hit, we need to implement pruning.
1512 assert(Idx < (2*NumRegUnitSubSets) && "runaway unit set inference");
1514 // Compare new sets with all original classes.
1515 for (unsigned SearchIdx = (Idx >= NumRegUnitSubSets) ? 0 : Idx+1;
1516 SearchIdx != EndIdx; ++SearchIdx) {
1517 std::set<unsigned> Intersection;
1518 std::set_intersection(RegUnitSets[Idx].Units.begin(),
1519 RegUnitSets[Idx].Units.end(),
1520 RegUnitSets[SearchIdx].Units.begin(),
1521 RegUnitSets[SearchIdx].Units.end(),
1522 std::inserter(Intersection, Intersection.begin()));
1523 if (Intersection.empty())
1526 // Speculatively grow the RegUnitSets to hold the new set.
1527 RegUnitSets.resize(RegUnitSets.size() + 1);
1528 RegUnitSets.back().Name =
1529 RegUnitSets[Idx].Name + "+" + RegUnitSets[SearchIdx].Name;
1531 std::set_union(RegUnitSets[Idx].Units.begin(),
1532 RegUnitSets[Idx].Units.end(),
1533 RegUnitSets[SearchIdx].Units.begin(),
1534 RegUnitSets[SearchIdx].Units.end(),
1535 std::inserter(RegUnitSets.back().Units,
1536 RegUnitSets.back().Units.begin()));
1538 // Find an existing RegUnitSet, or add the union to the unique sets.
1539 std::vector<RegUnitSet>::const_iterator SetI =
1540 findRegUnitSet(RegUnitSets, RegUnitSets.back());
1541 if (SetI != llvm::prior(RegUnitSets.end()))
1542 RegUnitSets.pop_back();
1546 // Iteratively prune unit sets after inferring supersets.
1549 // For each register class, list the UnitSets that are supersets.
1550 RegClassUnitSets.resize(NumRegClasses);
1551 for (unsigned RCIdx = 0, RCEnd = NumRegClasses; RCIdx != RCEnd; ++RCIdx) {
1552 if (!RegClasses[RCIdx]->Allocatable)
1555 // Recompute the sorted list of units in this class.
1556 std::vector<unsigned> RegUnits;
1557 RegClasses[RCIdx]->buildRegUnitSet(RegUnits);
1559 // Don't increase pressure for unallocatable regclasses.
1560 if (RegUnits.empty())
1563 // Find all supersets.
1564 for (unsigned USIdx = 0, USEnd = RegUnitSets.size();
1565 USIdx != USEnd; ++USIdx) {
1566 if (isRegUnitSubSet(RegUnits, RegUnitSets[USIdx].Units))
1567 RegClassUnitSets[RCIdx].push_back(USIdx);
1569 assert(!RegClassUnitSets[RCIdx].empty() && "missing unit set for regclass");
1572 // For each register unit, ensure that we have the list of UnitSets that
1573 // contain the unit. Normally, this matches an existing list of UnitSets for a
1574 // register class. If not, we create a new entry in RegClassUnitSets as a
1575 // "fake" register class.
1576 for (unsigned UnitIdx = 0, UnitEnd = NumNativeRegUnits;
1577 UnitIdx < UnitEnd; ++UnitIdx) {
1578 std::vector<unsigned> RUSets;
1579 for (unsigned i = 0, e = RegUnitSets.size(); i != e; ++i) {
1580 RegUnitSet &RUSet = RegUnitSets[i];
1581 if (std::find(RUSet.Units.begin(), RUSet.Units.end(), UnitIdx)
1582 == RUSet.Units.end())
1584 RUSets.push_back(i);
1586 unsigned RCUnitSetsIdx = 0;
1587 for (unsigned e = RegClassUnitSets.size();
1588 RCUnitSetsIdx != e; ++RCUnitSetsIdx) {
1589 if (RegClassUnitSets[RCUnitSetsIdx] == RUSets) {
1593 RegUnits[UnitIdx].RegClassUnitSetsIdx = RCUnitSetsIdx;
1594 if (RCUnitSetsIdx == RegClassUnitSets.size()) {
1595 // Create a new list of UnitSets as a "fake" register class.
1596 RegClassUnitSets.resize(RCUnitSetsIdx + 1);
1597 RegClassUnitSets[RCUnitSetsIdx].swap(RUSets);
1602 void CodeGenRegBank::computeDerivedInfo() {
1603 computeComposites();
1604 computeSubRegIndexLaneMasks();
1606 // Compute a weight for each register unit created during getSubRegs.
1607 // This may create adopted register units (with unit # >= NumNativeRegUnits).
1608 computeRegUnitWeights();
1610 // Compute a unique set of RegUnitSets. One for each RegClass and inferred
1611 // supersets for the union of overlapping sets.
1612 computeRegUnitSets();
1616 // Synthesize missing register class intersections.
1618 // Make sure that sub-classes of RC exists such that getCommonSubClass(RC, X)
1619 // returns a maximal register class for all X.
1621 void CodeGenRegBank::inferCommonSubClass(CodeGenRegisterClass *RC) {
1622 for (unsigned rci = 0, rce = RegClasses.size(); rci != rce; ++rci) {
1623 CodeGenRegisterClass *RC1 = RC;
1624 CodeGenRegisterClass *RC2 = RegClasses[rci];
1628 // Compute the set intersection of RC1 and RC2.
1629 const CodeGenRegister::Set &Memb1 = RC1->getMembers();
1630 const CodeGenRegister::Set &Memb2 = RC2->getMembers();
1631 CodeGenRegister::Set Intersection;
1632 std::set_intersection(Memb1.begin(), Memb1.end(),
1633 Memb2.begin(), Memb2.end(),
1634 std::inserter(Intersection, Intersection.begin()),
1635 CodeGenRegister::Less());
1637 // Skip disjoint class pairs.
1638 if (Intersection.empty())
1641 // If RC1 and RC2 have different spill sizes or alignments, use the
1642 // larger size for sub-classing. If they are equal, prefer RC1.
1643 if (RC2->SpillSize > RC1->SpillSize ||
1644 (RC2->SpillSize == RC1->SpillSize &&
1645 RC2->SpillAlignment > RC1->SpillAlignment))
1646 std::swap(RC1, RC2);
1648 getOrCreateSubClass(RC1, &Intersection,
1649 RC1->getName() + "_and_" + RC2->getName());
1654 // Synthesize missing sub-classes for getSubClassWithSubReg().
1656 // Make sure that the set of registers in RC with a given SubIdx sub-register
1657 // form a register class. Update RC->SubClassWithSubReg.
1659 void CodeGenRegBank::inferSubClassWithSubReg(CodeGenRegisterClass *RC) {
1660 // Map SubRegIndex to set of registers in RC supporting that SubRegIndex.
1661 typedef std::map<CodeGenSubRegIndex*, CodeGenRegister::Set,
1662 CodeGenSubRegIndex::Less> SubReg2SetMap;
1664 // Compute the set of registers supporting each SubRegIndex.
1665 SubReg2SetMap SRSets;
1666 for (CodeGenRegister::Set::const_iterator RI = RC->getMembers().begin(),
1667 RE = RC->getMembers().end(); RI != RE; ++RI) {
1668 const CodeGenRegister::SubRegMap &SRM = (*RI)->getSubRegs();
1669 for (CodeGenRegister::SubRegMap::const_iterator I = SRM.begin(),
1670 E = SRM.end(); I != E; ++I)
1671 SRSets[I->first].insert(*RI);
1674 // Find matching classes for all SRSets entries. Iterate in SubRegIndex
1675 // numerical order to visit synthetic indices last.
1676 for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
1677 CodeGenSubRegIndex *SubIdx = SubRegIndices[sri];
1678 SubReg2SetMap::const_iterator I = SRSets.find(SubIdx);
1679 // Unsupported SubRegIndex. Skip it.
1680 if (I == SRSets.end())
1682 // In most cases, all RC registers support the SubRegIndex.
1683 if (I->second.size() == RC->getMembers().size()) {
1684 RC->setSubClassWithSubReg(SubIdx, RC);
1687 // This is a real subset. See if we have a matching class.
1688 CodeGenRegisterClass *SubRC =
1689 getOrCreateSubClass(RC, &I->second,
1690 RC->getName() + "_with_" + I->first->getName());
1691 RC->setSubClassWithSubReg(SubIdx, SubRC);
1696 // Synthesize missing sub-classes of RC for getMatchingSuperRegClass().
1698 // Create sub-classes of RC such that getMatchingSuperRegClass(RC, SubIdx, X)
1699 // has a maximal result for any SubIdx and any X >= FirstSubRegRC.
1702 void CodeGenRegBank::inferMatchingSuperRegClass(CodeGenRegisterClass *RC,
1703 unsigned FirstSubRegRC) {
1704 SmallVector<std::pair<const CodeGenRegister*,
1705 const CodeGenRegister*>, 16> SSPairs;
1706 BitVector TopoSigs(getNumTopoSigs());
1708 // Iterate in SubRegIndex numerical order to visit synthetic indices last.
1709 for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
1710 CodeGenSubRegIndex *SubIdx = SubRegIndices[sri];
1711 // Skip indexes that aren't fully supported by RC's registers. This was
1712 // computed by inferSubClassWithSubReg() above which should have been
1714 if (RC->getSubClassWithSubReg(SubIdx) != RC)
1717 // Build list of (Super, Sub) pairs for this SubIdx.
1720 for (CodeGenRegister::Set::const_iterator RI = RC->getMembers().begin(),
1721 RE = RC->getMembers().end(); RI != RE; ++RI) {
1722 const CodeGenRegister *Super = *RI;
1723 const CodeGenRegister *Sub = Super->getSubRegs().find(SubIdx)->second;
1724 assert(Sub && "Missing sub-register");
1725 SSPairs.push_back(std::make_pair(Super, Sub));
1726 TopoSigs.set(Sub->getTopoSig());
1729 // Iterate over sub-register class candidates. Ignore classes created by
1730 // this loop. They will never be useful.
1731 for (unsigned rci = FirstSubRegRC, rce = RegClasses.size(); rci != rce;
1733 CodeGenRegisterClass *SubRC = RegClasses[rci];
1734 // Topological shortcut: SubRC members have the wrong shape.
1735 if (!TopoSigs.anyCommon(SubRC->getTopoSigs()))
1737 // Compute the subset of RC that maps into SubRC.
1738 CodeGenRegister::Set SubSet;
1739 for (unsigned i = 0, e = SSPairs.size(); i != e; ++i)
1740 if (SubRC->contains(SSPairs[i].second))
1741 SubSet.insert(SSPairs[i].first);
1744 // RC injects completely into SubRC.
1745 if (SubSet.size() == SSPairs.size()) {
1746 SubRC->addSuperRegClass(SubIdx, RC);
1749 // Only a subset of RC maps into SubRC. Make sure it is represented by a
1751 getOrCreateSubClass(RC, &SubSet, RC->getName() +
1752 "_with_" + SubIdx->getName() +
1753 "_in_" + SubRC->getName());
1760 // Infer missing register classes.
1762 void CodeGenRegBank::computeInferredRegisterClasses() {
1763 // When this function is called, the register classes have not been sorted
1764 // and assigned EnumValues yet. That means getSubClasses(),
1765 // getSuperClasses(), and hasSubClass() functions are defunct.
1766 unsigned FirstNewRC = RegClasses.size();
1768 // Visit all register classes, including the ones being added by the loop.
1769 for (unsigned rci = 0; rci != RegClasses.size(); ++rci) {
1770 CodeGenRegisterClass *RC = RegClasses[rci];
1772 // Synthesize answers for getSubClassWithSubReg().
1773 inferSubClassWithSubReg(RC);
1775 // Synthesize answers for getCommonSubClass().
1776 inferCommonSubClass(RC);
1778 // Synthesize answers for getMatchingSuperRegClass().
1779 inferMatchingSuperRegClass(RC);
1781 // New register classes are created while this loop is running, and we need
1782 // to visit all of them. I particular, inferMatchingSuperRegClass needs
1783 // to match old super-register classes with sub-register classes created
1784 // after inferMatchingSuperRegClass was called. At this point,
1785 // inferMatchingSuperRegClass has checked SuperRC = [0..rci] with SubRC =
1786 // [0..FirstNewRC). We need to cover SubRC = [FirstNewRC..rci].
1787 if (rci + 1 == FirstNewRC) {
1788 unsigned NextNewRC = RegClasses.size();
1789 for (unsigned rci2 = 0; rci2 != FirstNewRC; ++rci2)
1790 inferMatchingSuperRegClass(RegClasses[rci2], FirstNewRC);
1791 FirstNewRC = NextNewRC;
1796 /// getRegisterClassForRegister - Find the register class that contains the
1797 /// specified physical register. If the register is not in a register class,
1798 /// return null. If the register is in multiple classes, and the classes have a
1799 /// superset-subset relationship and the same set of types, return the
1800 /// superclass. Otherwise return null.
1801 const CodeGenRegisterClass*
1802 CodeGenRegBank::getRegClassForRegister(Record *R) {
1803 const CodeGenRegister *Reg = getReg(R);
1804 ArrayRef<CodeGenRegisterClass*> RCs = getRegClasses();
1805 const CodeGenRegisterClass *FoundRC = 0;
1806 for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
1807 const CodeGenRegisterClass &RC = *RCs[i];
1808 if (!RC.contains(Reg))
1811 // If this is the first class that contains the register,
1812 // make a note of it and go on to the next class.
1818 // If a register's classes have different types, return null.
1819 if (RC.getValueTypes() != FoundRC->getValueTypes())
1822 // Check to see if the previously found class that contains
1823 // the register is a subclass of the current class. If so,
1824 // prefer the superclass.
1825 if (RC.hasSubClass(FoundRC)) {
1830 // Check to see if the previously found class that contains
1831 // the register is a superclass of the current class. If so,
1832 // prefer the superclass.
1833 if (FoundRC->hasSubClass(&RC))
1836 // Multiple classes, and neither is a superclass of the other.
1843 BitVector CodeGenRegBank::computeCoveredRegisters(ArrayRef<Record*> Regs) {
1844 SetVector<const CodeGenRegister*> Set;
1846 // First add Regs with all sub-registers.
1847 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
1848 CodeGenRegister *Reg = getReg(Regs[i]);
1849 if (Set.insert(Reg))
1850 // Reg is new, add all sub-registers.
1851 // The pre-ordering is not important here.
1852 Reg->addSubRegsPreOrder(Set, *this);
1855 // Second, find all super-registers that are completely covered by the set.
1856 for (unsigned i = 0; i != Set.size(); ++i) {
1857 const CodeGenRegister::SuperRegList &SR = Set[i]->getSuperRegs();
1858 for (unsigned j = 0, e = SR.size(); j != e; ++j) {
1859 const CodeGenRegister *Super = SR[j];
1860 if (!Super->CoveredBySubRegs || Set.count(Super))
1862 // This new super-register is covered by its sub-registers.
1863 bool AllSubsInSet = true;
1864 const CodeGenRegister::SubRegMap &SRM = Super->getSubRegs();
1865 for (CodeGenRegister::SubRegMap::const_iterator I = SRM.begin(),
1866 E = SRM.end(); I != E; ++I)
1867 if (!Set.count(I->second)) {
1868 AllSubsInSet = false;
1871 // All sub-registers in Set, add Super as well.
1872 // We will visit Super later to recheck its super-registers.
1878 // Convert to BitVector.
1879 BitVector BV(Registers.size() + 1);
1880 for (unsigned i = 0, e = Set.size(); i != e; ++i)
1881 BV.set(Set[i]->EnumValue);