1 //===- CodeGenRegisters.cpp - Register and RegisterClass Info -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines structures to encapsulate information gleaned from the
11 // target register and register class definitions.
13 //===----------------------------------------------------------------------===//
15 #include "CodeGenRegisters.h"
16 #include "CodeGenTarget.h"
17 #include "llvm/TableGen/Error.h"
18 #include "llvm/ADT/IntEqClasses.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/StringExtras.h"
25 //===----------------------------------------------------------------------===//
27 //===----------------------------------------------------------------------===//
29 CodeGenSubRegIndex::CodeGenSubRegIndex(Record *R, unsigned Enum)
34 std::string CodeGenSubRegIndex::getNamespace() const {
35 if (TheDef->getValue("Namespace"))
36 return TheDef->getValueAsString("Namespace");
41 const std::string &CodeGenSubRegIndex::getName() const {
42 return TheDef->getName();
45 std::string CodeGenSubRegIndex::getQualifiedName() const {
46 std::string N = getNamespace();
53 void CodeGenSubRegIndex::updateComponents(CodeGenRegBank &RegBank) {
54 std::vector<Record*> Comps = TheDef->getValueAsListOfDefs("ComposedOf");
57 if (Comps.size() != 2)
58 throw TGError(TheDef->getLoc(), "ComposedOf must have exactly two entries");
59 CodeGenSubRegIndex *A = RegBank.getSubRegIdx(Comps[0]);
60 CodeGenSubRegIndex *B = RegBank.getSubRegIdx(Comps[1]);
61 CodeGenSubRegIndex *X = A->addComposite(B, this);
63 throw TGError(TheDef->getLoc(), "Ambiguous ComposedOf entries");
66 void CodeGenSubRegIndex::cleanComposites() {
67 // Clean out redundant mappings of the form this+X -> X.
68 for (CompMap::iterator i = Composed.begin(), e = Composed.end(); i != e;) {
69 CompMap::iterator j = i;
71 if (j->first == j->second)
76 //===----------------------------------------------------------------------===//
78 //===----------------------------------------------------------------------===//
80 CodeGenRegister::CodeGenRegister(Record *R, unsigned Enum)
83 CostPerUse(R->getValueAsInt("CostPerUse")),
84 CoveredBySubRegs(R->getValueAsBit("CoveredBySubRegs")),
85 SubRegsComplete(false)
88 const std::string &CodeGenRegister::getName() const {
89 return TheDef->getName();
93 // Iterate over all register units in a set of registers.
94 class RegUnitIterator {
95 CodeGenRegister::Set::const_iterator RegI, RegE;
96 CodeGenRegister::RegUnitList::const_iterator UnitI, UnitE;
99 RegUnitIterator(const CodeGenRegister::Set &Regs):
100 RegI(Regs.begin()), RegE(Regs.end()), UnitI(), UnitE() {
103 UnitI = (*RegI)->getRegUnits().begin();
104 UnitE = (*RegI)->getRegUnits().end();
109 bool isValid() const { return UnitI != UnitE; }
111 unsigned operator* () const { assert(isValid()); return *UnitI; };
113 const CodeGenRegister *getReg() const { assert(isValid()); return *RegI; }
115 /// Preincrement. Move to the next unit.
117 assert(isValid() && "Cannot advance beyond the last operand");
124 while (UnitI == UnitE) {
127 UnitI = (*RegI)->getRegUnits().begin();
128 UnitE = (*RegI)->getRegUnits().end();
134 // Merge two RegUnitLists maintaining the order and removing duplicates.
135 // Overwrites MergedRU in the process.
136 static void mergeRegUnits(CodeGenRegister::RegUnitList &MergedRU,
137 const CodeGenRegister::RegUnitList &RRU) {
138 CodeGenRegister::RegUnitList LRU = MergedRU;
140 std::set_union(LRU.begin(), LRU.end(), RRU.begin(), RRU.end(),
141 std::back_inserter(MergedRU));
144 // Return true of this unit appears in RegUnits.
145 static bool hasRegUnit(CodeGenRegister::RegUnitList &RegUnits, unsigned Unit) {
146 return std::count(RegUnits.begin(), RegUnits.end(), Unit);
149 // Inherit register units from subregisters.
150 // Return true if the RegUnits changed.
151 bool CodeGenRegister::inheritRegUnits(CodeGenRegBank &RegBank) {
152 unsigned OldNumUnits = RegUnits.size();
153 for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
155 // Strangely a register may have itself as a subreg (self-cycle) e.g. XMM.
156 // Only create a unit if no other subregs have units.
157 CodeGenRegister *SR = I->second;
159 // RegUnits are only empty during getSubRegs, prior to computing weight.
160 if (RegUnits.empty())
161 RegUnits.push_back(RegBank.newRegUnit(0));
164 // Merge the subregister's units into this register's RegUnits.
165 mergeRegUnits(RegUnits, SR->RegUnits);
167 return OldNumUnits != RegUnits.size();
170 const CodeGenRegister::SubRegMap &
171 CodeGenRegister::getSubRegs(CodeGenRegBank &RegBank) {
172 // Only compute this map once.
175 SubRegsComplete = true;
177 std::vector<Record*> SubList = TheDef->getValueAsListOfDefs("SubRegs");
178 std::vector<Record*> IdxList = TheDef->getValueAsListOfDefs("SubRegIndices");
179 if (SubList.size() != IdxList.size())
180 throw TGError(TheDef->getLoc(), "Register " + getName() +
181 " SubRegIndices doesn't match SubRegs");
183 // First insert the direct subregs and make sure they are fully indexed.
184 SmallVector<CodeGenSubRegIndex*, 8> Indices;
185 for (unsigned i = 0, e = SubList.size(); i != e; ++i) {
186 CodeGenRegister *SR = RegBank.getReg(SubList[i]);
187 CodeGenSubRegIndex *Idx = RegBank.getSubRegIdx(IdxList[i]);
188 Indices.push_back(Idx);
189 if (!SubRegs.insert(std::make_pair(Idx, SR)).second)
190 throw TGError(TheDef->getLoc(), "SubRegIndex " + Idx->getName() +
191 " appears twice in Register " + getName());
194 // Keep track of inherited subregs and how they can be reached.
195 SmallPtrSet<CodeGenRegister*, 8> Orphans;
197 // Clone inherited subregs and place duplicate entries in Orphans.
198 // Here the order is important - earlier subregs take precedence.
199 for (unsigned i = 0, e = SubList.size(); i != e; ++i) {
200 CodeGenRegister *SR = RegBank.getReg(SubList[i]);
201 const SubRegMap &Map = SR->getSubRegs(RegBank);
203 // Add this as a super-register of SR now all sub-registers are in the list.
204 // This creates a topological ordering, the exact order depends on the
205 // order getSubRegs is called on all registers.
206 SR->SuperRegs.push_back(this);
208 for (SubRegMap::const_iterator SI = Map.begin(), SE = Map.end(); SI != SE;
210 if (!SubRegs.insert(*SI).second)
211 Orphans.insert(SI->second);
213 // Noop sub-register indexes are possible, so avoid duplicates.
214 if (SI->second != SR)
215 SI->second->SuperRegs.push_back(this);
219 // Expand any composed subreg indices.
220 // If dsub_2 has ComposedOf = [qsub_1, dsub_0], and this register has a
221 // qsub_1 subreg, add a dsub_2 subreg. Keep growing Indices and process
222 // expanded subreg indices recursively.
223 for (unsigned i = 0; i != Indices.size(); ++i) {
224 CodeGenSubRegIndex *Idx = Indices[i];
225 const CodeGenSubRegIndex::CompMap &Comps = Idx->getComposites();
226 CodeGenRegister *SR = SubRegs[Idx];
227 const SubRegMap &Map = SR->getSubRegs(RegBank);
229 // Look at the possible compositions of Idx.
230 // They may not all be supported by SR.
231 for (CodeGenSubRegIndex::CompMap::const_iterator I = Comps.begin(),
232 E = Comps.end(); I != E; ++I) {
233 SubRegMap::const_iterator SRI = Map.find(I->first);
234 if (SRI == Map.end())
235 continue; // Idx + I->first doesn't exist in SR.
236 // Add I->second as a name for the subreg SRI->second, assuming it is
237 // orphaned, and the name isn't already used for something else.
238 if (SubRegs.count(I->second) || !Orphans.erase(SRI->second))
240 // We found a new name for the orphaned sub-register.
241 SubRegs.insert(std::make_pair(I->second, SRI->second));
242 Indices.push_back(I->second);
246 // Process the composites.
247 ListInit *Comps = TheDef->getValueAsListInit("CompositeIndices");
248 for (unsigned i = 0, e = Comps->size(); i != e; ++i) {
249 DagInit *Pat = dynamic_cast<DagInit*>(Comps->getElement(i));
251 throw TGError(TheDef->getLoc(), "Invalid dag '" +
252 Comps->getElement(i)->getAsString() +
253 "' in CompositeIndices");
254 DefInit *BaseIdxInit = dynamic_cast<DefInit*>(Pat->getOperator());
255 if (!BaseIdxInit || !BaseIdxInit->getDef()->isSubClassOf("SubRegIndex"))
256 throw TGError(TheDef->getLoc(), "Invalid SubClassIndex in " +
258 CodeGenSubRegIndex *BaseIdx = RegBank.getSubRegIdx(BaseIdxInit->getDef());
260 // Resolve list of subreg indices into R2.
261 CodeGenRegister *R2 = this;
262 for (DagInit::const_arg_iterator di = Pat->arg_begin(),
263 de = Pat->arg_end(); di != de; ++di) {
264 DefInit *IdxInit = dynamic_cast<DefInit*>(*di);
265 if (!IdxInit || !IdxInit->getDef()->isSubClassOf("SubRegIndex"))
266 throw TGError(TheDef->getLoc(), "Invalid SubClassIndex in " +
268 CodeGenSubRegIndex *Idx = RegBank.getSubRegIdx(IdxInit->getDef());
269 const SubRegMap &R2Subs = R2->getSubRegs(RegBank);
270 SubRegMap::const_iterator ni = R2Subs.find(Idx);
271 if (ni == R2Subs.end())
272 throw TGError(TheDef->getLoc(), "Composite " + Pat->getAsString() +
273 " refers to bad index in " + R2->getName());
277 // Insert composite index. Allow overriding inherited indices etc.
278 SubRegs[BaseIdx] = R2;
280 // R2 is no longer an orphan.
284 // Now Orphans contains the inherited subregisters without a direct index.
285 // Create inferred indexes for all missing entries.
286 // Work backwards in the Indices vector in order to compose subregs bottom-up.
287 // Consider this subreg sequence:
289 // qsub_1 -> dsub_0 -> ssub_0
291 // The qsub_1 -> dsub_0 composition becomes dsub_2, so the ssub_0 register
292 // can be reached in two different ways:
297 // We pick the latter composition because another register may have [dsub_0,
298 // dsub_1, dsub_2] subregs without neccessarily having a qsub_1 subreg. The
299 // dsub_2 -> ssub_0 composition can be shared.
300 while (!Indices.empty() && !Orphans.empty()) {
301 CodeGenSubRegIndex *Idx = Indices.pop_back_val();
302 CodeGenRegister *SR = SubRegs[Idx];
303 const SubRegMap &Map = SR->getSubRegs(RegBank);
304 for (SubRegMap::const_iterator SI = Map.begin(), SE = Map.end(); SI != SE;
306 if (Orphans.erase(SI->second))
307 SubRegs[RegBank.getCompositeSubRegIndex(Idx, SI->first)] = SI->second;
310 // Initialize RegUnitList. A register with no subregisters creates its own
311 // unit. Otherwise, it inherits all its subregister's units. Because
312 // getSubRegs is called recursively, this processes the register hierarchy in
315 // TODO: We currently assume all register units correspond to a named "leaf"
316 // register. We should also unify register units for ad-hoc register
317 // aliases. This can be done by iteratively merging units for aliasing
318 // registers using a worklist.
319 assert(RegUnits.empty() && "Should only initialize RegUnits once");
321 RegUnits.push_back(RegBank.newRegUnit(0));
323 inheritRegUnits(RegBank);
328 CodeGenRegister::addSubRegsPreOrder(SetVector<const CodeGenRegister*> &OSet,
329 CodeGenRegBank &RegBank) const {
330 assert(SubRegsComplete && "Must precompute sub-registers");
331 std::vector<Record*> Indices = TheDef->getValueAsListOfDefs("SubRegIndices");
332 for (unsigned i = 0, e = Indices.size(); i != e; ++i) {
333 CodeGenSubRegIndex *Idx = RegBank.getSubRegIdx(Indices[i]);
334 CodeGenRegister *SR = SubRegs.find(Idx)->second;
336 SR->addSubRegsPreOrder(OSet, RegBank);
340 // Get the sum of this register's unit weights.
341 unsigned CodeGenRegister::getWeight(const CodeGenRegBank &RegBank) const {
343 for (RegUnitList::const_iterator I = RegUnits.begin(), E = RegUnits.end();
345 Weight += RegBank.getRegUnitWeight(*I);
350 //===----------------------------------------------------------------------===//
352 //===----------------------------------------------------------------------===//
354 // A RegisterTuples def is used to generate pseudo-registers from lists of
355 // sub-registers. We provide a SetTheory expander class that returns the new
358 struct TupleExpander : SetTheory::Expander {
359 void expand(SetTheory &ST, Record *Def, SetTheory::RecSet &Elts) {
360 std::vector<Record*> Indices = Def->getValueAsListOfDefs("SubRegIndices");
361 unsigned Dim = Indices.size();
362 ListInit *SubRegs = Def->getValueAsListInit("SubRegs");
363 if (Dim != SubRegs->getSize())
364 throw TGError(Def->getLoc(), "SubRegIndices and SubRegs size mismatch");
366 throw TGError(Def->getLoc(), "Tuples must have at least 2 sub-registers");
368 // Evaluate the sub-register lists to be zipped.
369 unsigned Length = ~0u;
370 SmallVector<SetTheory::RecSet, 4> Lists(Dim);
371 for (unsigned i = 0; i != Dim; ++i) {
372 ST.evaluate(SubRegs->getElement(i), Lists[i]);
373 Length = std::min(Length, unsigned(Lists[i].size()));
379 // Precompute some types.
380 Record *RegisterCl = Def->getRecords().getClass("Register");
381 RecTy *RegisterRecTy = RecordRecTy::get(RegisterCl);
382 StringInit *BlankName = StringInit::get("");
385 for (unsigned n = 0; n != Length; ++n) {
387 Record *Proto = Lists[0][n];
388 std::vector<Init*> Tuple;
389 unsigned CostPerUse = 0;
390 for (unsigned i = 0; i != Dim; ++i) {
391 Record *Reg = Lists[i][n];
393 Name += Reg->getName();
394 Tuple.push_back(DefInit::get(Reg));
395 CostPerUse = std::max(CostPerUse,
396 unsigned(Reg->getValueAsInt("CostPerUse")));
399 // Create a new Record representing the synthesized register. This record
400 // is only for consumption by CodeGenRegister, it is not added to the
402 Record *NewReg = new Record(Name, Def->getLoc(), Def->getRecords());
405 // Copy Proto super-classes.
406 for (unsigned i = 0, e = Proto->getSuperClasses().size(); i != e; ++i)
407 NewReg->addSuperClass(Proto->getSuperClasses()[i]);
409 // Copy Proto fields.
410 for (unsigned i = 0, e = Proto->getValues().size(); i != e; ++i) {
411 RecordVal RV = Proto->getValues()[i];
413 // Skip existing fields, like NAME.
414 if (NewReg->getValue(RV.getNameInit()))
417 StringRef Field = RV.getName();
419 // Replace the sub-register list with Tuple.
420 if (Field == "SubRegs")
421 RV.setValue(ListInit::get(Tuple, RegisterRecTy));
423 // Provide a blank AsmName. MC hacks are required anyway.
424 if (Field == "AsmName")
425 RV.setValue(BlankName);
427 // CostPerUse is aggregated from all Tuple members.
428 if (Field == "CostPerUse")
429 RV.setValue(IntInit::get(CostPerUse));
431 // Composite registers are always covered by sub-registers.
432 if (Field == "CoveredBySubRegs")
433 RV.setValue(BitInit::get(true));
435 // Copy fields from the RegisterTuples def.
436 if (Field == "SubRegIndices" ||
437 Field == "CompositeIndices") {
438 NewReg->addValue(*Def->getValue(Field));
442 // Some fields get their default uninitialized value.
443 if (Field == "DwarfNumbers" ||
444 Field == "DwarfAlias" ||
445 Field == "Aliases") {
446 if (const RecordVal *DefRV = RegisterCl->getValue(Field))
447 NewReg->addValue(*DefRV);
451 // Everything else is copied from Proto.
452 NewReg->addValue(RV);
459 //===----------------------------------------------------------------------===//
460 // CodeGenRegisterClass
461 //===----------------------------------------------------------------------===//
463 CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
464 : TheDef(R), Name(R->getName()), EnumValue(-1) {
465 // Rename anonymous register classes.
466 if (R->getName().size() > 9 && R->getName()[9] == '.') {
467 static unsigned AnonCounter = 0;
468 R->setName("AnonRegClass_"+utostr(AnonCounter++));
471 std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes");
472 for (unsigned i = 0, e = TypeList.size(); i != e; ++i) {
473 Record *Type = TypeList[i];
474 if (!Type->isSubClassOf("ValueType"))
475 throw "RegTypes list member '" + Type->getName() +
476 "' does not derive from the ValueType class!";
477 VTs.push_back(getValueType(Type));
479 assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!");
481 // Allocation order 0 is the full set. AltOrders provides others.
482 const SetTheory::RecVec *Elements = RegBank.getSets().expand(R);
483 ListInit *AltOrders = R->getValueAsListInit("AltOrders");
484 Orders.resize(1 + AltOrders->size());
486 // Default allocation order always contains all registers.
487 for (unsigned i = 0, e = Elements->size(); i != e; ++i) {
488 Orders[0].push_back((*Elements)[i]);
489 Members.insert(RegBank.getReg((*Elements)[i]));
492 // Alternative allocation orders may be subsets.
493 SetTheory::RecSet Order;
494 for (unsigned i = 0, e = AltOrders->size(); i != e; ++i) {
495 RegBank.getSets().evaluate(AltOrders->getElement(i), Order);
496 Orders[1 + i].append(Order.begin(), Order.end());
497 // Verify that all altorder members are regclass members.
498 while (!Order.empty()) {
499 CodeGenRegister *Reg = RegBank.getReg(Order.back());
502 throw TGError(R->getLoc(), " AltOrder register " + Reg->getName() +
503 " is not a class member");
507 // SubRegClasses is a list<dag> containing (RC, subregindex, ...) dags.
508 ListInit *SRC = R->getValueAsListInit("SubRegClasses");
509 for (ListInit::const_iterator i = SRC->begin(), e = SRC->end(); i != e; ++i) {
510 DagInit *DAG = dynamic_cast<DagInit*>(*i);
511 if (!DAG) throw "SubRegClasses must contain DAGs";
512 DefInit *DAGOp = dynamic_cast<DefInit*>(DAG->getOperator());
514 if (!DAGOp || !(RCRec = DAGOp->getDef())->isSubClassOf("RegisterClass"))
515 throw "Operator '" + DAG->getOperator()->getAsString() +
516 "' in SubRegClasses is not a RegisterClass";
517 // Iterate over args, all SubRegIndex instances.
518 for (DagInit::const_arg_iterator ai = DAG->arg_begin(), ae = DAG->arg_end();
520 DefInit *Idx = dynamic_cast<DefInit*>(*ai);
522 if (!Idx || !(IdxRec = Idx->getDef())->isSubClassOf("SubRegIndex"))
523 throw "Argument '" + (*ai)->getAsString() +
524 "' in SubRegClasses is not a SubRegIndex";
525 if (!SubRegClasses.insert(std::make_pair(IdxRec, RCRec)).second)
526 throw "SubRegIndex '" + IdxRec->getName() + "' mentioned twice";
530 // Allow targets to override the size in bits of the RegisterClass.
531 unsigned Size = R->getValueAsInt("Size");
533 Namespace = R->getValueAsString("Namespace");
534 SpillSize = Size ? Size : EVT(VTs[0]).getSizeInBits();
535 SpillAlignment = R->getValueAsInt("Alignment");
536 CopyCost = R->getValueAsInt("CopyCost");
537 Allocatable = R->getValueAsBit("isAllocatable");
538 AltOrderSelect = R->getValueAsString("AltOrderSelect");
541 // Create an inferred register class that was missing from the .td files.
542 // Most properties will be inherited from the closest super-class after the
543 // class structure has been computed.
544 CodeGenRegisterClass::CodeGenRegisterClass(StringRef Name, Key Props)
545 : Members(*Props.Members),
549 SpillSize(Props.SpillSize),
550 SpillAlignment(Props.SpillAlignment),
555 // Compute inherited propertied for a synthesized register class.
556 void CodeGenRegisterClass::inheritProperties(CodeGenRegBank &RegBank) {
557 assert(!getDef() && "Only synthesized classes can inherit properties");
558 assert(!SuperClasses.empty() && "Synthesized class without super class");
560 // The last super-class is the smallest one.
561 CodeGenRegisterClass &Super = *SuperClasses.back();
563 // Most properties are copied directly.
564 // Exceptions are members, size, and alignment
565 Namespace = Super.Namespace;
567 CopyCost = Super.CopyCost;
568 Allocatable = Super.Allocatable;
569 AltOrderSelect = Super.AltOrderSelect;
571 // Copy all allocation orders, filter out foreign registers from the larger
573 Orders.resize(Super.Orders.size());
574 for (unsigned i = 0, ie = Super.Orders.size(); i != ie; ++i)
575 for (unsigned j = 0, je = Super.Orders[i].size(); j != je; ++j)
576 if (contains(RegBank.getReg(Super.Orders[i][j])))
577 Orders[i].push_back(Super.Orders[i][j]);
580 bool CodeGenRegisterClass::contains(const CodeGenRegister *Reg) const {
581 return Members.count(Reg);
585 raw_ostream &operator<<(raw_ostream &OS, const CodeGenRegisterClass::Key &K) {
586 OS << "{ S=" << K.SpillSize << ", A=" << K.SpillAlignment;
587 for (CodeGenRegister::Set::const_iterator I = K.Members->begin(),
588 E = K.Members->end(); I != E; ++I)
589 OS << ", " << (*I)->getName();
594 // This is a simple lexicographical order that can be used to search for sets.
595 // It is not the same as the topological order provided by TopoOrderRC.
596 bool CodeGenRegisterClass::Key::
597 operator<(const CodeGenRegisterClass::Key &B) const {
598 assert(Members && B.Members);
599 if (*Members != *B.Members)
600 return *Members < *B.Members;
601 if (SpillSize != B.SpillSize)
602 return SpillSize < B.SpillSize;
603 return SpillAlignment < B.SpillAlignment;
606 // Returns true if RC is a strict subclass.
607 // RC is a sub-class of this class if it is a valid replacement for any
608 // instruction operand where a register of this classis required. It must
609 // satisfy these conditions:
611 // 1. All RC registers are also in this.
612 // 2. The RC spill size must not be smaller than our spill size.
613 // 3. RC spill alignment must be compatible with ours.
615 static bool testSubClass(const CodeGenRegisterClass *A,
616 const CodeGenRegisterClass *B) {
617 return A->SpillAlignment && B->SpillAlignment % A->SpillAlignment == 0 &&
618 A->SpillSize <= B->SpillSize &&
619 std::includes(A->getMembers().begin(), A->getMembers().end(),
620 B->getMembers().begin(), B->getMembers().end(),
621 CodeGenRegister::Less());
624 /// Sorting predicate for register classes. This provides a topological
625 /// ordering that arranges all register classes before their sub-classes.
627 /// Register classes with the same registers, spill size, and alignment form a
628 /// clique. They will be ordered alphabetically.
630 static int TopoOrderRC(const void *PA, const void *PB) {
631 const CodeGenRegisterClass *A = *(const CodeGenRegisterClass* const*)PA;
632 const CodeGenRegisterClass *B = *(const CodeGenRegisterClass* const*)PB;
636 // Order by descending set size. Note that the classes' allocation order may
637 // not have been computed yet. The Members set is always vaild.
638 if (A->getMembers().size() > B->getMembers().size())
640 if (A->getMembers().size() < B->getMembers().size())
643 // Order by ascending spill size.
644 if (A->SpillSize < B->SpillSize)
646 if (A->SpillSize > B->SpillSize)
649 // Order by ascending spill alignment.
650 if (A->SpillAlignment < B->SpillAlignment)
652 if (A->SpillAlignment > B->SpillAlignment)
655 // Finally order by name as a tie breaker.
656 return StringRef(A->getName()).compare(B->getName());
659 std::string CodeGenRegisterClass::getQualifiedName() const {
660 if (Namespace.empty())
663 return Namespace + "::" + getName();
666 // Compute sub-classes of all register classes.
667 // Assume the classes are ordered topologically.
668 void CodeGenRegisterClass::computeSubClasses(CodeGenRegBank &RegBank) {
669 ArrayRef<CodeGenRegisterClass*> RegClasses = RegBank.getRegClasses();
671 // Visit backwards so sub-classes are seen first.
672 for (unsigned rci = RegClasses.size(); rci; --rci) {
673 CodeGenRegisterClass &RC = *RegClasses[rci - 1];
674 RC.SubClasses.resize(RegClasses.size());
675 RC.SubClasses.set(RC.EnumValue);
677 // Normally, all subclasses have IDs >= rci, unless RC is part of a clique.
678 for (unsigned s = rci; s != RegClasses.size(); ++s) {
679 if (RC.SubClasses.test(s))
681 CodeGenRegisterClass *SubRC = RegClasses[s];
682 if (!testSubClass(&RC, SubRC))
684 // SubRC is a sub-class. Grap all its sub-classes so we won't have to
686 RC.SubClasses |= SubRC->SubClasses;
689 // Sweep up missed clique members. They will be immediately preceeding RC.
690 for (unsigned s = rci - 1; s && testSubClass(&RC, RegClasses[s - 1]); --s)
691 RC.SubClasses.set(s - 1);
694 // Compute the SuperClasses lists from the SubClasses vectors.
695 for (unsigned rci = 0; rci != RegClasses.size(); ++rci) {
696 const BitVector &SC = RegClasses[rci]->getSubClasses();
697 for (int s = SC.find_first(); s >= 0; s = SC.find_next(s)) {
698 if (unsigned(s) == rci)
700 RegClasses[s]->SuperClasses.push_back(RegClasses[rci]);
704 // With the class hierarchy in place, let synthesized register classes inherit
705 // properties from their closest super-class. The iteration order here can
706 // propagate properties down multiple levels.
707 for (unsigned rci = 0; rci != RegClasses.size(); ++rci)
708 if (!RegClasses[rci]->getDef())
709 RegClasses[rci]->inheritProperties(RegBank);
713 CodeGenRegisterClass::getSuperRegClasses(CodeGenSubRegIndex *SubIdx,
714 BitVector &Out) const {
715 DenseMap<CodeGenSubRegIndex*,
716 SmallPtrSet<CodeGenRegisterClass*, 8> >::const_iterator
717 FindI = SuperRegClasses.find(SubIdx);
718 if (FindI == SuperRegClasses.end())
720 for (SmallPtrSet<CodeGenRegisterClass*, 8>::const_iterator I =
721 FindI->second.begin(), E = FindI->second.end(); I != E; ++I)
722 Out.set((*I)->EnumValue);
726 //===----------------------------------------------------------------------===//
728 //===----------------------------------------------------------------------===//
730 CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records) : Records(Records) {
731 // Configure register Sets to understand register classes and tuples.
732 Sets.addFieldExpander("RegisterClass", "MemberList");
733 Sets.addFieldExpander("CalleeSavedRegs", "SaveList");
734 Sets.addExpander("RegisterTuples", new TupleExpander());
736 // Read in the user-defined (named) sub-register indices.
737 // More indices will be synthesized later.
738 std::vector<Record*> SRIs = Records.getAllDerivedDefinitions("SubRegIndex");
739 std::sort(SRIs.begin(), SRIs.end(), LessRecord());
740 NumNamedIndices = SRIs.size();
741 for (unsigned i = 0, e = SRIs.size(); i != e; ++i)
742 getSubRegIdx(SRIs[i]);
743 // Build composite maps from ComposedOf fields.
744 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i)
745 SubRegIndices[i]->updateComponents(*this);
747 // Read in the register definitions.
748 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
749 std::sort(Regs.begin(), Regs.end(), LessRecord());
750 Registers.reserve(Regs.size());
751 // Assign the enumeration values.
752 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
755 // Expand tuples and number the new registers.
756 std::vector<Record*> Tups =
757 Records.getAllDerivedDefinitions("RegisterTuples");
758 for (unsigned i = 0, e = Tups.size(); i != e; ++i) {
759 const std::vector<Record*> *TupRegs = Sets.expand(Tups[i]);
760 for (unsigned j = 0, je = TupRegs->size(); j != je; ++j)
761 getReg((*TupRegs)[j]);
764 // Precompute all sub-register maps now all the registers are known.
765 // This will create Composite entries for all inferred sub-register indices.
767 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
768 Registers[i]->getSubRegs(*this);
770 // Native register units are associated with a leaf register. They've all been
772 NumNativeRegUnits = NumRegUnits;
774 // Read in register class definitions.
775 std::vector<Record*> RCs = Records.getAllDerivedDefinitions("RegisterClass");
777 throw std::string("No 'RegisterClass' subclasses defined!");
779 // Allocate user-defined register classes.
780 RegClasses.reserve(RCs.size());
781 for (unsigned i = 0, e = RCs.size(); i != e; ++i)
782 addToMaps(new CodeGenRegisterClass(*this, RCs[i]));
784 // Infer missing classes to create a full algebra.
785 computeInferredRegisterClasses();
787 // Order register classes topologically and assign enum values.
788 array_pod_sort(RegClasses.begin(), RegClasses.end(), TopoOrderRC);
789 for (unsigned i = 0, e = RegClasses.size(); i != e; ++i)
790 RegClasses[i]->EnumValue = i;
791 CodeGenRegisterClass::computeSubClasses(*this);
794 CodeGenSubRegIndex *CodeGenRegBank::getSubRegIdx(Record *Def) {
795 CodeGenSubRegIndex *&Idx = Def2SubRegIdx[Def];
798 Idx = new CodeGenSubRegIndex(Def, SubRegIndices.size() + 1);
799 SubRegIndices.push_back(Idx);
803 CodeGenRegister *CodeGenRegBank::getReg(Record *Def) {
804 CodeGenRegister *&Reg = Def2Reg[Def];
807 Reg = new CodeGenRegister(Def, Registers.size() + 1);
808 Registers.push_back(Reg);
812 void CodeGenRegBank::addToMaps(CodeGenRegisterClass *RC) {
813 RegClasses.push_back(RC);
815 if (Record *Def = RC->getDef())
816 Def2RC.insert(std::make_pair(Def, RC));
818 // Duplicate classes are rejected by insert().
819 // That's OK, we only care about the properties handled by CGRC::Key.
820 CodeGenRegisterClass::Key K(*RC);
821 Key2RC.insert(std::make_pair(K, RC));
824 // Create a synthetic sub-class if it is missing.
825 CodeGenRegisterClass*
826 CodeGenRegBank::getOrCreateSubClass(const CodeGenRegisterClass *RC,
827 const CodeGenRegister::Set *Members,
829 // Synthetic sub-class has the same size and alignment as RC.
830 CodeGenRegisterClass::Key K(Members, RC->SpillSize, RC->SpillAlignment);
831 RCKeyMap::const_iterator FoundI = Key2RC.find(K);
832 if (FoundI != Key2RC.end())
833 return FoundI->second;
835 // Sub-class doesn't exist, create a new one.
836 CodeGenRegisterClass *NewRC = new CodeGenRegisterClass(Name, K);
841 CodeGenRegisterClass *CodeGenRegBank::getRegClass(Record *Def) {
842 if (CodeGenRegisterClass *RC = Def2RC[Def])
845 throw TGError(Def->getLoc(), "Not a known RegisterClass!");
849 CodeGenRegBank::getCompositeSubRegIndex(CodeGenSubRegIndex *A,
850 CodeGenSubRegIndex *B) {
851 // Look for an existing entry.
852 CodeGenSubRegIndex *Comp = A->compose(B);
856 // None exists, synthesize one.
857 std::string Name = A->getName() + "_then_" + B->getName();
858 Comp = getSubRegIdx(new Record(Name, SMLoc(), Records));
859 A->addComposite(B, Comp);
863 void CodeGenRegBank::computeComposites() {
864 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
865 CodeGenRegister *Reg1 = Registers[i];
866 const CodeGenRegister::SubRegMap &SRM1 = Reg1->getSubRegs();
867 for (CodeGenRegister::SubRegMap::const_iterator i1 = SRM1.begin(),
868 e1 = SRM1.end(); i1 != e1; ++i1) {
869 CodeGenSubRegIndex *Idx1 = i1->first;
870 CodeGenRegister *Reg2 = i1->second;
871 // Ignore identity compositions.
874 const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs();
875 // Try composing Idx1 with another SubRegIndex.
876 for (CodeGenRegister::SubRegMap::const_iterator i2 = SRM2.begin(),
877 e2 = SRM2.end(); i2 != e2; ++i2) {
878 CodeGenSubRegIndex *Idx2 = i2->first;
879 CodeGenRegister *Reg3 = i2->second;
880 // Ignore identity compositions.
883 // OK Reg1:IdxPair == Reg3. Find the index with Reg:Idx == Reg3.
884 for (CodeGenRegister::SubRegMap::const_iterator i1d = SRM1.begin(),
885 e1d = SRM1.end(); i1d != e1d; ++i1d) {
886 if (i1d->second == Reg3) {
887 // Conflicting composition? Emit a warning but allow it.
888 if (CodeGenSubRegIndex *Prev = Idx1->addComposite(Idx2, i1d->first))
889 errs() << "Warning: SubRegIndex " << Idx1->getQualifiedName()
890 << " and " << Idx2->getQualifiedName()
891 << " compose ambiguously as "
892 << Prev->getQualifiedName() << " or "
893 << i1d->first->getQualifiedName() << "\n";
900 // We don't care about the difference between (Idx1, Idx2) -> Idx2 and invalid
901 // compositions, so remove any mappings of that form.
902 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i)
903 SubRegIndices[i]->cleanComposites();
907 // UberRegSet is a helper class for computeRegUnitWeights. Each UberRegSet is
908 // the transitive closure of the union of overlapping register
909 // classes. Together, the UberRegSets form a partition of the registers. If we
910 // consider overlapping register classes to be connected, then each UberRegSet
911 // is a set of connected components.
913 // An UberRegSet will likely be a horizontal slice of register names of
914 // the same width. Nontrivial subregisters should then be in a separate
915 // UberRegSet. But this property isn't required for valid computation of
916 // register unit weights.
918 // A Weight field caches the max per-register unit weight in each UberRegSet.
920 // A set of SingularDeterminants flags single units of some register in this set
921 // for which the unit weight equals the set weight. These units should not have
922 // their weight increased.
924 CodeGenRegister::Set Regs;
926 CodeGenRegister::RegUnitList SingularDeterminants;
928 UberRegSet(): Weight(0) {}
932 // Partition registers into UberRegSets, where each set is the transitive
933 // closure of the union of overlapping register classes.
935 // UberRegSets[0] is a special non-allocatable set.
936 static void computeUberSets(std::vector<UberRegSet> &UberSets,
937 std::vector<UberRegSet*> &RegSets,
938 CodeGenRegBank &RegBank) {
940 const std::vector<CodeGenRegister*> &Registers = RegBank.getRegisters();
942 // The Register EnumValue is one greater than its index into Registers.
943 assert(Registers.size() == Registers[Registers.size()-1]->EnumValue &&
944 "register enum value mismatch");
946 // For simplicitly make the SetID the same as EnumValue.
947 IntEqClasses UberSetIDs(Registers.size()+1);
948 std::set<unsigned> AllocatableRegs;
949 for (unsigned i = 0, e = RegBank.getRegClasses().size(); i != e; ++i) {
951 CodeGenRegisterClass *RegClass = RegBank.getRegClasses()[i];
952 if (!RegClass->Allocatable)
955 const CodeGenRegister::Set &Regs = RegClass->getMembers();
959 unsigned USetID = UberSetIDs.findLeader((*Regs.begin())->EnumValue);
960 assert(USetID && "register number 0 is invalid");
962 AllocatableRegs.insert((*Regs.begin())->EnumValue);
963 for (CodeGenRegister::Set::const_iterator I = llvm::next(Regs.begin()),
964 E = Regs.end(); I != E; ++I) {
965 AllocatableRegs.insert((*I)->EnumValue);
966 UberSetIDs.join(USetID, (*I)->EnumValue);
969 // Combine non-allocatable regs.
970 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
971 unsigned RegNum = Registers[i]->EnumValue;
972 if (AllocatableRegs.count(RegNum))
975 UberSetIDs.join(0, RegNum);
977 UberSetIDs.compress();
979 // Make the first UberSet a special unallocatable set.
980 unsigned ZeroID = UberSetIDs[0];
982 // Insert Registers into the UberSets formed by union-find.
983 // Do not resize after this.
984 UberSets.resize(UberSetIDs.getNumClasses());
985 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
986 const CodeGenRegister *Reg = Registers[i];
987 unsigned USetID = UberSetIDs[Reg->EnumValue];
990 else if (USetID == ZeroID)
993 UberRegSet *USet = &UberSets[USetID];
994 USet->Regs.insert(Reg);
999 // Recompute each UberSet weight after changing unit weights.
1000 static void computeUberWeights(std::vector<UberRegSet> &UberSets,
1001 CodeGenRegBank &RegBank) {
1002 // Skip the first unallocatable set.
1003 for (std::vector<UberRegSet>::iterator I = llvm::next(UberSets.begin()),
1004 E = UberSets.end(); I != E; ++I) {
1006 // Initialize all unit weights in this set, and remember the max units/reg.
1007 const CodeGenRegister *Reg = 0;
1008 unsigned MaxWeight = 0, Weight = 0;
1009 for (RegUnitIterator UnitI(I->Regs); UnitI.isValid(); ++UnitI) {
1010 if (Reg != UnitI.getReg()) {
1011 if (Weight > MaxWeight)
1013 Reg = UnitI.getReg();
1016 unsigned UWeight = RegBank.getRegUnitWeight(*UnitI);
1019 RegBank.increaseRegUnitWeight(*UnitI, UWeight);
1023 if (Weight > MaxWeight)
1026 // Update the set weight.
1027 I->Weight = MaxWeight;
1029 // Find singular determinants.
1030 for (CodeGenRegister::Set::iterator RegI = I->Regs.begin(),
1031 RegE = I->Regs.end(); RegI != RegE; ++RegI) {
1032 if ((*RegI)->getRegUnits().size() == 1
1033 && (*RegI)->getWeight(RegBank) == I->Weight)
1034 mergeRegUnits(I->SingularDeterminants, (*RegI)->getRegUnits());
1039 // normalizeWeight is a computeRegUnitWeights helper that adjusts the weight of
1040 // a register and its subregisters so that they have the same weight as their
1041 // UberSet. Self-recursion processes the subregister tree in postorder so
1042 // subregisters are normalized first.
1045 // - creates new adopted register units
1046 // - causes superregisters to inherit adopted units
1047 // - increases the weight of "singular" units
1048 // - induces recomputation of UberWeights.
1049 static bool normalizeWeight(CodeGenRegister *Reg,
1050 std::vector<UberRegSet> &UberSets,
1051 std::vector<UberRegSet*> &RegSets,
1052 CodeGenRegister::RegUnitList &NormalUnits,
1053 CodeGenRegBank &RegBank) {
1054 bool Changed = false;
1055 const CodeGenRegister::SubRegMap &SRM = Reg->getSubRegs();
1056 for (CodeGenRegister::SubRegMap::const_iterator SRI = SRM.begin(),
1057 SRE = SRM.end(); SRI != SRE; ++SRI) {
1058 if (SRI->second == Reg)
1059 continue; // self-cycles happen
1062 normalizeWeight(SRI->second, UberSets, RegSets, NormalUnits, RegBank);
1064 // Postorder register normalization.
1066 // Inherit register units newly adopted by subregisters.
1067 if (Reg->inheritRegUnits(RegBank))
1068 computeUberWeights(UberSets, RegBank);
1070 // Check if this register is too skinny for its UberRegSet.
1071 UberRegSet *UberSet = RegSets[RegBank.getRegIndex(Reg)];
1073 unsigned RegWeight = Reg->getWeight(RegBank);
1074 if (UberSet->Weight > RegWeight) {
1075 // A register unit's weight can be adjusted only if it is the singular unit
1076 // for this register, has not been used to normalize a subregister's set,
1077 // and has not already been used to singularly determine this UberRegSet.
1078 unsigned AdjustUnit = Reg->getRegUnits().front();
1079 if (Reg->getRegUnits().size() != 1
1080 || hasRegUnit(NormalUnits, AdjustUnit)
1081 || hasRegUnit(UberSet->SingularDeterminants, AdjustUnit)) {
1082 // We don't have an adjustable unit, so adopt a new one.
1083 AdjustUnit = RegBank.newRegUnit(UberSet->Weight - RegWeight);
1084 Reg->adoptRegUnit(AdjustUnit);
1085 // Adopting a unit does not immediately require recomputing set weights.
1088 // Adjust the existing single unit.
1089 RegBank.increaseRegUnitWeight(AdjustUnit, UberSet->Weight - RegWeight);
1090 // The unit may be shared among sets and registers within this set.
1091 computeUberWeights(UberSets, RegBank);
1096 // Mark these units normalized so superregisters can't change their weights.
1097 mergeRegUnits(NormalUnits, Reg->getRegUnits());
1102 // Compute a weight for each register unit created during getSubRegs.
1104 // The goal is that two registers in the same class will have the same weight,
1105 // where each register's weight is defined as sum of its units' weights.
1106 void CodeGenRegBank::computeRegUnitWeights() {
1107 assert(RegUnitWeights.empty() && "Only initialize RegUnitWeights once");
1109 // Only allocatable units will be initialized to nonzero weight.
1110 RegUnitWeights.resize(NumRegUnits);
1112 std::vector<UberRegSet> UberSets;
1113 std::vector<UberRegSet*> RegSets(Registers.size());
1114 computeUberSets(UberSets, RegSets, *this);
1115 // UberSets and RegSets are now immutable.
1117 computeUberWeights(UberSets, *this);
1119 // Iterate over each Register, normalizing the unit weights until reaching
1121 unsigned NumIters = 0;
1122 for (bool Changed = true; Changed; ++NumIters) {
1123 assert(NumIters <= NumNativeRegUnits && "Runaway register unit weights");
1125 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
1126 CodeGenRegister::RegUnitList NormalUnits;
1128 normalizeWeight(Registers[i], UberSets, RegSets, NormalUnits, *this);
1133 // Populate a unique sorted list of units from a register set.
1134 static void buildRegUnitSet(const CodeGenRegister::Set &Regs,
1135 std::vector<unsigned> &RegUnits) {
1136 std::vector<unsigned> TmpUnits;
1137 for (RegUnitIterator UnitI(Regs); UnitI.isValid(); ++UnitI)
1138 TmpUnits.push_back(*UnitI);
1139 std::sort(TmpUnits.begin(), TmpUnits.end());
1140 std::unique_copy(TmpUnits.begin(), TmpUnits.end(),
1141 std::back_inserter(RegUnits));
1144 // Find a set in UniqueSets with the same elements as Set.
1145 // Return an iterator into UniqueSets.
1146 static std::vector<RegUnitSet>::const_iterator
1147 findRegUnitSet(const std::vector<RegUnitSet> &UniqueSets,
1148 const RegUnitSet &Set) {
1149 std::vector<RegUnitSet>::const_iterator
1150 I = UniqueSets.begin(), E = UniqueSets.end();
1152 if (I->Units == Set.Units)
1158 // Return true if the RUSubSet is a subset of RUSuperSet.
1159 static bool isRegUnitSubSet(const std::vector<unsigned> &RUSubSet,
1160 const std::vector<unsigned> &RUSuperSet) {
1161 return std::includes(RUSuperSet.begin(), RUSuperSet.end(),
1162 RUSubSet.begin(), RUSubSet.end());
1165 // Iteratively prune unit sets.
1166 void CodeGenRegBank::pruneUnitSets() {
1167 assert(RegClassUnitSets.empty() && "this invalidates RegClassUnitSets");
1169 // Form an equivalence class of UnitSets with no significant difference.
1170 std::vector<unsigned> SuperSetIDs;
1171 for (unsigned SubIdx = 0, EndIdx = RegUnitSets.size();
1172 SubIdx != EndIdx; ++SubIdx) {
1173 const RegUnitSet &SubSet = RegUnitSets[SubIdx];
1174 unsigned SuperIdx = 0;
1175 for (; SuperIdx != EndIdx; ++SuperIdx) {
1176 if (SuperIdx == SubIdx)
1179 const RegUnitSet &SuperSet = RegUnitSets[SuperIdx];
1180 if (isRegUnitSubSet(SubSet.Units, SuperSet.Units)
1181 && (SubSet.Units.size() + 3 > SuperSet.Units.size())) {
1185 if (SuperIdx == EndIdx)
1186 SuperSetIDs.push_back(SubIdx);
1188 // Populate PrunedUnitSets with each equivalence class's superset.
1189 std::vector<RegUnitSet> PrunedUnitSets(SuperSetIDs.size());
1190 for (unsigned i = 0, e = SuperSetIDs.size(); i != e; ++i) {
1191 unsigned SuperIdx = SuperSetIDs[i];
1192 PrunedUnitSets[i].Name = RegUnitSets[SuperIdx].Name;
1193 PrunedUnitSets[i].Units.swap(RegUnitSets[SuperIdx].Units);
1195 RegUnitSets.swap(PrunedUnitSets);
1198 // Create a RegUnitSet for each RegClass that contains all units in the class
1199 // including adopted units that are necessary to model register pressure. Then
1200 // iteratively compute RegUnitSets such that the union of any two overlapping
1201 // RegUnitSets is repreresented.
1203 // RegisterInfoEmitter will map each RegClass to its RegUnitClass and any
1204 // RegUnitSet that is a superset of that RegUnitClass.
1205 void CodeGenRegBank::computeRegUnitSets() {
1207 // Compute a unique RegUnitSet for each RegClass.
1208 const ArrayRef<CodeGenRegisterClass*> &RegClasses = getRegClasses();
1209 unsigned NumRegClasses = RegClasses.size();
1210 for (unsigned RCIdx = 0, RCEnd = NumRegClasses; RCIdx != RCEnd; ++RCIdx) {
1211 if (!RegClasses[RCIdx]->Allocatable)
1214 // Speculatively grow the RegUnitSets to hold the new set.
1215 RegUnitSets.resize(RegUnitSets.size() + 1);
1216 RegUnitSets.back().Name = RegClasses[RCIdx]->getName();
1218 // Compute a sorted list of units in this class.
1219 buildRegUnitSet(RegClasses[RCIdx]->getMembers(), RegUnitSets.back().Units);
1221 // Find an existing RegUnitSet.
1222 std::vector<RegUnitSet>::const_iterator SetI =
1223 findRegUnitSet(RegUnitSets, RegUnitSets.back());
1224 if (SetI != llvm::prior(RegUnitSets.end()))
1225 RegUnitSets.pop_back();
1228 // Iteratively prune unit sets.
1231 // Iterate over all unit sets, including new ones added by this loop.
1232 unsigned NumRegUnitSubSets = RegUnitSets.size();
1233 for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx) {
1234 // In theory, this is combinatorial. In practice, it needs to be bounded
1235 // by a small number of sets for regpressure to be efficient.
1236 // If the assert is hit, we need to implement pruning.
1237 assert(Idx < (2*NumRegUnitSubSets) && "runaway unit set inference");
1239 // Compare new sets with all original classes.
1240 for (unsigned SearchIdx = (Idx >= NumRegUnitSubSets) ? 0 : Idx+1;
1241 SearchIdx != EndIdx; ++SearchIdx) {
1242 std::set<unsigned> Intersection;
1243 std::set_intersection(RegUnitSets[Idx].Units.begin(),
1244 RegUnitSets[Idx].Units.end(),
1245 RegUnitSets[SearchIdx].Units.begin(),
1246 RegUnitSets[SearchIdx].Units.end(),
1247 std::inserter(Intersection, Intersection.begin()));
1248 if (Intersection.empty())
1251 // Speculatively grow the RegUnitSets to hold the new set.
1252 RegUnitSets.resize(RegUnitSets.size() + 1);
1253 RegUnitSets.back().Name =
1254 RegUnitSets[Idx].Name + "+" + RegUnitSets[SearchIdx].Name;
1256 std::set_union(RegUnitSets[Idx].Units.begin(),
1257 RegUnitSets[Idx].Units.end(),
1258 RegUnitSets[SearchIdx].Units.begin(),
1259 RegUnitSets[SearchIdx].Units.end(),
1260 std::inserter(RegUnitSets.back().Units,
1261 RegUnitSets.back().Units.begin()));
1263 // Find an existing RegUnitSet, or add the union to the unique sets.
1264 std::vector<RegUnitSet>::const_iterator SetI =
1265 findRegUnitSet(RegUnitSets, RegUnitSets.back());
1266 if (SetI != llvm::prior(RegUnitSets.end()))
1267 RegUnitSets.pop_back();
1271 // Iteratively prune unit sets after inferring supersets.
1274 // For each register class, list the UnitSets that are supersets.
1275 RegClassUnitSets.resize(NumRegClasses);
1276 for (unsigned RCIdx = 0, RCEnd = NumRegClasses; RCIdx != RCEnd; ++RCIdx) {
1277 if (!RegClasses[RCIdx]->Allocatable)
1280 // Recompute the sorted list of units in this class.
1281 std::vector<unsigned> RegUnits;
1282 buildRegUnitSet(RegClasses[RCIdx]->getMembers(), RegUnits);
1284 // Don't increase pressure for unallocatable regclasses.
1285 if (RegUnits.empty())
1288 // Find all supersets.
1289 for (unsigned USIdx = 0, USEnd = RegUnitSets.size();
1290 USIdx != USEnd; ++USIdx) {
1291 if (isRegUnitSubSet(RegUnits, RegUnitSets[USIdx].Units))
1292 RegClassUnitSets[RCIdx].push_back(USIdx);
1294 assert(!RegClassUnitSets[RCIdx].empty() && "missing unit set for regclass");
1298 // Compute sets of overlapping registers.
1300 // The standard set is all super-registers and all sub-registers, but the
1301 // target description can add arbitrary overlapping registers via the 'Aliases'
1302 // field. This complicates things, but we can compute overlapping sets using
1303 // the following rules:
1305 // 1. The relation overlap(A, B) is reflexive and symmetric but not transitive.
1307 // 2. overlap(A, B) implies overlap(A, S) for all S in supers(B).
1311 // overlap(A, B) iff there exists:
1312 // A' in { A, subregs(A) } and B' in { B, subregs(B) } such that:
1313 // A' = B' or A' in aliases(B') or B' in aliases(A').
1315 // Here subregs(A) is the full flattened sub-register set returned by
1316 // A.getSubRegs() while aliases(A) is simply the special 'Aliases' field in the
1317 // description of register A.
1319 // This also implies that registers with a common sub-register are considered
1320 // overlapping. This can happen when forming register pairs:
1326 // In this case, we will infer an overlap between P0 and P1 because of the
1327 // shared sub-register R1. There is no overlap between P0 and P2.
1329 void CodeGenRegBank::
1330 computeOverlaps(std::map<const CodeGenRegister*, CodeGenRegister::Set> &Map) {
1331 assert(Map.empty());
1333 // Collect overlaps that don't follow from rule 2.
1334 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
1335 CodeGenRegister *Reg = Registers[i];
1336 CodeGenRegister::Set &Overlaps = Map[Reg];
1338 // Reg overlaps itself.
1339 Overlaps.insert(Reg);
1341 // All super-registers overlap.
1342 const CodeGenRegister::SuperRegList &Supers = Reg->getSuperRegs();
1343 Overlaps.insert(Supers.begin(), Supers.end());
1345 // Form symmetrical relations from the special Aliases[] lists.
1346 std::vector<Record*> RegList = Reg->TheDef->getValueAsListOfDefs("Aliases");
1347 for (unsigned i2 = 0, e2 = RegList.size(); i2 != e2; ++i2) {
1348 CodeGenRegister *Reg2 = getReg(RegList[i2]);
1349 CodeGenRegister::Set &Overlaps2 = Map[Reg2];
1350 const CodeGenRegister::SuperRegList &Supers2 = Reg2->getSuperRegs();
1351 // Reg overlaps Reg2 which implies it overlaps supers(Reg2).
1352 Overlaps.insert(Reg2);
1353 Overlaps.insert(Supers2.begin(), Supers2.end());
1354 Overlaps2.insert(Reg);
1355 Overlaps2.insert(Supers.begin(), Supers.end());
1359 // Apply rule 2. and inherit all sub-register overlaps.
1360 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
1361 CodeGenRegister *Reg = Registers[i];
1362 CodeGenRegister::Set &Overlaps = Map[Reg];
1363 const CodeGenRegister::SubRegMap &SRM = Reg->getSubRegs();
1364 for (CodeGenRegister::SubRegMap::const_iterator i2 = SRM.begin(),
1365 e2 = SRM.end(); i2 != e2; ++i2) {
1366 CodeGenRegister::Set &Overlaps2 = Map[i2->second];
1367 Overlaps.insert(Overlaps2.begin(), Overlaps2.end());
1372 void CodeGenRegBank::computeDerivedInfo() {
1373 computeComposites();
1375 // Compute a weight for each register unit created during getSubRegs.
1376 // This may create adopted register units (with unit # >= NumNativeRegUnits).
1377 computeRegUnitWeights();
1379 // Compute a unique set of RegUnitSets. One for each RegClass and inferred
1380 // supersets for the union of overlapping sets.
1381 computeRegUnitSets();
1385 // Synthesize missing register class intersections.
1387 // Make sure that sub-classes of RC exists such that getCommonSubClass(RC, X)
1388 // returns a maximal register class for all X.
1390 void CodeGenRegBank::inferCommonSubClass(CodeGenRegisterClass *RC) {
1391 for (unsigned rci = 0, rce = RegClasses.size(); rci != rce; ++rci) {
1392 CodeGenRegisterClass *RC1 = RC;
1393 CodeGenRegisterClass *RC2 = RegClasses[rci];
1397 // Compute the set intersection of RC1 and RC2.
1398 const CodeGenRegister::Set &Memb1 = RC1->getMembers();
1399 const CodeGenRegister::Set &Memb2 = RC2->getMembers();
1400 CodeGenRegister::Set Intersection;
1401 std::set_intersection(Memb1.begin(), Memb1.end(),
1402 Memb2.begin(), Memb2.end(),
1403 std::inserter(Intersection, Intersection.begin()),
1404 CodeGenRegister::Less());
1406 // Skip disjoint class pairs.
1407 if (Intersection.empty())
1410 // If RC1 and RC2 have different spill sizes or alignments, use the
1411 // larger size for sub-classing. If they are equal, prefer RC1.
1412 if (RC2->SpillSize > RC1->SpillSize ||
1413 (RC2->SpillSize == RC1->SpillSize &&
1414 RC2->SpillAlignment > RC1->SpillAlignment))
1415 std::swap(RC1, RC2);
1417 getOrCreateSubClass(RC1, &Intersection,
1418 RC1->getName() + "_and_" + RC2->getName());
1423 // Synthesize missing sub-classes for getSubClassWithSubReg().
1425 // Make sure that the set of registers in RC with a given SubIdx sub-register
1426 // form a register class. Update RC->SubClassWithSubReg.
1428 void CodeGenRegBank::inferSubClassWithSubReg(CodeGenRegisterClass *RC) {
1429 // Map SubRegIndex to set of registers in RC supporting that SubRegIndex.
1430 typedef std::map<CodeGenSubRegIndex*, CodeGenRegister::Set,
1431 CodeGenSubRegIndex::Less> SubReg2SetMap;
1433 // Compute the set of registers supporting each SubRegIndex.
1434 SubReg2SetMap SRSets;
1435 for (CodeGenRegister::Set::const_iterator RI = RC->getMembers().begin(),
1436 RE = RC->getMembers().end(); RI != RE; ++RI) {
1437 const CodeGenRegister::SubRegMap &SRM = (*RI)->getSubRegs();
1438 for (CodeGenRegister::SubRegMap::const_iterator I = SRM.begin(),
1439 E = SRM.end(); I != E; ++I)
1440 SRSets[I->first].insert(*RI);
1443 // Find matching classes for all SRSets entries. Iterate in SubRegIndex
1444 // numerical order to visit synthetic indices last.
1445 for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
1446 CodeGenSubRegIndex *SubIdx = SubRegIndices[sri];
1447 SubReg2SetMap::const_iterator I = SRSets.find(SubIdx);
1448 // Unsupported SubRegIndex. Skip it.
1449 if (I == SRSets.end())
1451 // In most cases, all RC registers support the SubRegIndex.
1452 if (I->second.size() == RC->getMembers().size()) {
1453 RC->setSubClassWithSubReg(SubIdx, RC);
1456 // This is a real subset. See if we have a matching class.
1457 CodeGenRegisterClass *SubRC =
1458 getOrCreateSubClass(RC, &I->second,
1459 RC->getName() + "_with_" + I->first->getName());
1460 RC->setSubClassWithSubReg(SubIdx, SubRC);
1465 // Synthesize missing sub-classes of RC for getMatchingSuperRegClass().
1467 // Create sub-classes of RC such that getMatchingSuperRegClass(RC, SubIdx, X)
1468 // has a maximal result for any SubIdx and any X >= FirstSubRegRC.
1471 void CodeGenRegBank::inferMatchingSuperRegClass(CodeGenRegisterClass *RC,
1472 unsigned FirstSubRegRC) {
1473 SmallVector<std::pair<const CodeGenRegister*,
1474 const CodeGenRegister*>, 16> SSPairs;
1476 // Iterate in SubRegIndex numerical order to visit synthetic indices last.
1477 for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
1478 CodeGenSubRegIndex *SubIdx = SubRegIndices[sri];
1479 // Skip indexes that aren't fully supported by RC's registers. This was
1480 // computed by inferSubClassWithSubReg() above which should have been
1482 if (RC->getSubClassWithSubReg(SubIdx) != RC)
1485 // Build list of (Super, Sub) pairs for this SubIdx.
1487 for (CodeGenRegister::Set::const_iterator RI = RC->getMembers().begin(),
1488 RE = RC->getMembers().end(); RI != RE; ++RI) {
1489 const CodeGenRegister *Super = *RI;
1490 const CodeGenRegister *Sub = Super->getSubRegs().find(SubIdx)->second;
1491 assert(Sub && "Missing sub-register");
1492 SSPairs.push_back(std::make_pair(Super, Sub));
1495 // Iterate over sub-register class candidates. Ignore classes created by
1496 // this loop. They will never be useful.
1497 for (unsigned rci = FirstSubRegRC, rce = RegClasses.size(); rci != rce;
1499 CodeGenRegisterClass *SubRC = RegClasses[rci];
1500 // Compute the subset of RC that maps into SubRC.
1501 CodeGenRegister::Set SubSet;
1502 for (unsigned i = 0, e = SSPairs.size(); i != e; ++i)
1503 if (SubRC->contains(SSPairs[i].second))
1504 SubSet.insert(SSPairs[i].first);
1507 // RC injects completely into SubRC.
1508 if (SubSet.size() == SSPairs.size()) {
1509 SubRC->addSuperRegClass(SubIdx, RC);
1512 // Only a subset of RC maps into SubRC. Make sure it is represented by a
1514 getOrCreateSubClass(RC, &SubSet, RC->getName() +
1515 "_with_" + SubIdx->getName() +
1516 "_in_" + SubRC->getName());
1523 // Infer missing register classes.
1525 void CodeGenRegBank::computeInferredRegisterClasses() {
1526 // When this function is called, the register classes have not been sorted
1527 // and assigned EnumValues yet. That means getSubClasses(),
1528 // getSuperClasses(), and hasSubClass() functions are defunct.
1529 unsigned FirstNewRC = RegClasses.size();
1531 // Visit all register classes, including the ones being added by the loop.
1532 for (unsigned rci = 0; rci != RegClasses.size(); ++rci) {
1533 CodeGenRegisterClass *RC = RegClasses[rci];
1535 // Synthesize answers for getSubClassWithSubReg().
1536 inferSubClassWithSubReg(RC);
1538 // Synthesize answers for getCommonSubClass().
1539 inferCommonSubClass(RC);
1541 // Synthesize answers for getMatchingSuperRegClass().
1542 inferMatchingSuperRegClass(RC);
1544 // New register classes are created while this loop is running, and we need
1545 // to visit all of them. I particular, inferMatchingSuperRegClass needs
1546 // to match old super-register classes with sub-register classes created
1547 // after inferMatchingSuperRegClass was called. At this point,
1548 // inferMatchingSuperRegClass has checked SuperRC = [0..rci] with SubRC =
1549 // [0..FirstNewRC). We need to cover SubRC = [FirstNewRC..rci].
1550 if (rci + 1 == FirstNewRC) {
1551 unsigned NextNewRC = RegClasses.size();
1552 for (unsigned rci2 = 0; rci2 != FirstNewRC; ++rci2)
1553 inferMatchingSuperRegClass(RegClasses[rci2], FirstNewRC);
1554 FirstNewRC = NextNewRC;
1559 /// getRegisterClassForRegister - Find the register class that contains the
1560 /// specified physical register. If the register is not in a register class,
1561 /// return null. If the register is in multiple classes, and the classes have a
1562 /// superset-subset relationship and the same set of types, return the
1563 /// superclass. Otherwise return null.
1564 const CodeGenRegisterClass*
1565 CodeGenRegBank::getRegClassForRegister(Record *R) {
1566 const CodeGenRegister *Reg = getReg(R);
1567 ArrayRef<CodeGenRegisterClass*> RCs = getRegClasses();
1568 const CodeGenRegisterClass *FoundRC = 0;
1569 for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
1570 const CodeGenRegisterClass &RC = *RCs[i];
1571 if (!RC.contains(Reg))
1574 // If this is the first class that contains the register,
1575 // make a note of it and go on to the next class.
1581 // If a register's classes have different types, return null.
1582 if (RC.getValueTypes() != FoundRC->getValueTypes())
1585 // Check to see if the previously found class that contains
1586 // the register is a subclass of the current class. If so,
1587 // prefer the superclass.
1588 if (RC.hasSubClass(FoundRC)) {
1593 // Check to see if the previously found class that contains
1594 // the register is a superclass of the current class. If so,
1595 // prefer the superclass.
1596 if (FoundRC->hasSubClass(&RC))
1599 // Multiple classes, and neither is a superclass of the other.
1606 BitVector CodeGenRegBank::computeCoveredRegisters(ArrayRef<Record*> Regs) {
1607 SetVector<const CodeGenRegister*> Set;
1609 // First add Regs with all sub-registers.
1610 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
1611 CodeGenRegister *Reg = getReg(Regs[i]);
1612 if (Set.insert(Reg))
1613 // Reg is new, add all sub-registers.
1614 // The pre-ordering is not important here.
1615 Reg->addSubRegsPreOrder(Set, *this);
1618 // Second, find all super-registers that are completely covered by the set.
1619 for (unsigned i = 0; i != Set.size(); ++i) {
1620 const CodeGenRegister::SuperRegList &SR = Set[i]->getSuperRegs();
1621 for (unsigned j = 0, e = SR.size(); j != e; ++j) {
1622 const CodeGenRegister *Super = SR[j];
1623 if (!Super->CoveredBySubRegs || Set.count(Super))
1625 // This new super-register is covered by its sub-registers.
1626 bool AllSubsInSet = true;
1627 const CodeGenRegister::SubRegMap &SRM = Super->getSubRegs();
1628 for (CodeGenRegister::SubRegMap::const_iterator I = SRM.begin(),
1629 E = SRM.end(); I != E; ++I)
1630 if (!Set.count(I->second)) {
1631 AllSubsInSet = false;
1634 // All sub-registers in Set, add Super as well.
1635 // We will visit Super later to recheck its super-registers.
1641 // Convert to BitVector.
1642 BitVector BV(Registers.size() + 1);
1643 for (unsigned i = 0, e = Set.size(); i != e; ++i)
1644 BV.set(Set[i]->EnumValue);