1 //===- CodeGenRegisters.cpp - Register and RegisterClass Info -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines structures to encapsulate information gleaned from the
11 // target register and register class definitions.
13 //===----------------------------------------------------------------------===//
15 #include "CodeGenRegisters.h"
16 #include "CodeGenTarget.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/ADT/StringExtras.h"
23 //===----------------------------------------------------------------------===//
25 //===----------------------------------------------------------------------===//
27 CodeGenRegister::CodeGenRegister(Record *R, unsigned Enum)
30 CostPerUse(R->getValueAsInt("CostPerUse")),
31 SubRegsComplete(false)
34 const std::string &CodeGenRegister::getName() const {
35 return TheDef->getName();
40 CodeGenRegister *SubReg;
41 Record *First, *Second;
42 Orphan(CodeGenRegister *r, Record *a, Record *b)
43 : SubReg(r), First(a), Second(b) {}
47 const CodeGenRegister::SubRegMap &
48 CodeGenRegister::getSubRegs(CodeGenRegBank &RegBank) {
49 // Only compute this map once.
52 SubRegsComplete = true;
54 std::vector<Record*> SubList = TheDef->getValueAsListOfDefs("SubRegs");
55 std::vector<Record*> Indices = TheDef->getValueAsListOfDefs("SubRegIndices");
56 if (SubList.size() != Indices.size())
57 throw TGError(TheDef->getLoc(), "Register " + getName() +
58 " SubRegIndices doesn't match SubRegs");
60 // First insert the direct subregs and make sure they are fully indexed.
61 for (unsigned i = 0, e = SubList.size(); i != e; ++i) {
62 CodeGenRegister *SR = RegBank.getReg(SubList[i]);
63 if (!SubRegs.insert(std::make_pair(Indices[i], SR)).second)
64 throw TGError(TheDef->getLoc(), "SubRegIndex " + Indices[i]->getName() +
65 " appears twice in Register " + getName());
68 // Keep track of inherited subregs and how they can be reached.
69 SmallVector<Orphan, 8> Orphans;
71 // Clone inherited subregs and place duplicate entries on Orphans.
72 // Here the order is important - earlier subregs take precedence.
73 for (unsigned i = 0, e = SubList.size(); i != e; ++i) {
74 CodeGenRegister *SR = RegBank.getReg(SubList[i]);
75 const SubRegMap &Map = SR->getSubRegs(RegBank);
77 // Add this as a super-register of SR now all sub-registers are in the list.
78 // This creates a topological ordering, the exact order depends on the
79 // order getSubRegs is called on all registers.
80 SR->SuperRegs.push_back(this);
82 for (SubRegMap::const_iterator SI = Map.begin(), SE = Map.end(); SI != SE;
84 if (!SubRegs.insert(*SI).second)
85 Orphans.push_back(Orphan(SI->second, Indices[i], SI->first));
87 // Noop sub-register indexes are possible, so avoid duplicates.
89 SI->second->SuperRegs.push_back(this);
93 // Process the composites.
94 const ListInit *Comps = TheDef->getValueAsListInit("CompositeIndices");
95 for (unsigned i = 0, e = Comps->size(); i != e; ++i) {
96 const DagInit *Pat = dynamic_cast<const DagInit*>(Comps->getElement(i));
98 throw TGError(TheDef->getLoc(), "Invalid dag '" +
99 Comps->getElement(i)->getAsString() +
100 "' in CompositeIndices");
101 const DefInit *BaseIdxInit =
102 dynamic_cast<const DefInit*>(Pat->getOperator());
103 if (!BaseIdxInit || !BaseIdxInit->getDef()->isSubClassOf("SubRegIndex"))
104 throw TGError(TheDef->getLoc(), "Invalid SubClassIndex in " +
107 // Resolve list of subreg indices into R2.
108 CodeGenRegister *R2 = this;
109 for (DagInit::const_arg_iterator di = Pat->arg_begin(),
110 de = Pat->arg_end(); di != de; ++di) {
111 const DefInit *IdxInit = dynamic_cast<const DefInit*>(*di);
112 if (!IdxInit || !IdxInit->getDef()->isSubClassOf("SubRegIndex"))
113 throw TGError(TheDef->getLoc(), "Invalid SubClassIndex in " +
115 const SubRegMap &R2Subs = R2->getSubRegs(RegBank);
116 SubRegMap::const_iterator ni = R2Subs.find(IdxInit->getDef());
117 if (ni == R2Subs.end())
118 throw TGError(TheDef->getLoc(), "Composite " + Pat->getAsString() +
119 " refers to bad index in " + R2->getName());
123 // Insert composite index. Allow overriding inherited indices etc.
124 SubRegs[BaseIdxInit->getDef()] = R2;
126 // R2 is no longer an orphan.
127 for (unsigned j = 0, je = Orphans.size(); j != je; ++j)
128 if (Orphans[j].SubReg == R2)
129 Orphans[j].SubReg = 0;
132 // Now Orphans contains the inherited subregisters without a direct index.
133 // Create inferred indexes for all missing entries.
134 for (unsigned i = 0, e = Orphans.size(); i != e; ++i) {
135 Orphan &O = Orphans[i];
138 SubRegs[RegBank.getCompositeSubRegIndex(O.First, O.Second, true)] =
145 CodeGenRegister::addSubRegsPreOrder(SetVector<CodeGenRegister*> &OSet) const {
146 assert(SubRegsComplete && "Must precompute sub-registers");
147 std::vector<Record*> Indices = TheDef->getValueAsListOfDefs("SubRegIndices");
148 for (unsigned i = 0, e = Indices.size(); i != e; ++i) {
149 CodeGenRegister *SR = SubRegs.find(Indices[i])->second;
151 SR->addSubRegsPreOrder(OSet);
155 //===----------------------------------------------------------------------===//
157 //===----------------------------------------------------------------------===//
159 // A RegisterTuples def is used to generate pseudo-registers from lists of
160 // sub-registers. We provide a SetTheory expander class that returns the new
163 struct TupleExpander : SetTheory::Expander {
164 void expand(SetTheory &ST, Record *Def, SetTheory::RecSet &Elts) {
165 std::vector<Record*> Indices = Def->getValueAsListOfDefs("SubRegIndices");
166 unsigned Dim = Indices.size();
167 const ListInit *SubRegs = Def->getValueAsListInit("SubRegs");
168 if (Dim != SubRegs->getSize())
169 throw TGError(Def->getLoc(), "SubRegIndices and SubRegs size mismatch");
171 throw TGError(Def->getLoc(), "Tuples must have at least 2 sub-registers");
173 // Evaluate the sub-register lists to be zipped.
174 unsigned Length = ~0u;
175 SmallVector<SetTheory::RecSet, 4> Lists(Dim);
176 for (unsigned i = 0; i != Dim; ++i) {
177 ST.evaluate(SubRegs->getElement(i), Lists[i]);
178 Length = std::min(Length, unsigned(Lists[i].size()));
184 // Precompute some types.
185 Record *RegisterCl = Def->getRecords().getClass("Register");
186 RecTy *RegisterRecTy = new RecordRecTy(RegisterCl);
187 const StringInit *BlankName = StringInit::get("");
190 for (unsigned n = 0; n != Length; ++n) {
192 Record *Proto = Lists[0][n];
193 std::vector<const Init*> Tuple;
194 unsigned CostPerUse = 0;
195 for (unsigned i = 0; i != Dim; ++i) {
196 Record *Reg = Lists[i][n];
198 Name += Reg->getName();
199 Tuple.push_back(DefInit::get(Reg));
200 CostPerUse = std::max(CostPerUse,
201 unsigned(Reg->getValueAsInt("CostPerUse")));
204 // Create a new Record representing the synthesized register. This record
205 // is only for consumption by CodeGenRegister, it is not added to the
207 Record *NewReg = new Record(Name, Def->getLoc(), Def->getRecords());
210 // Copy Proto super-classes.
211 for (unsigned i = 0, e = Proto->getSuperClasses().size(); i != e; ++i)
212 NewReg->addSuperClass(Proto->getSuperClasses()[i]);
214 // Copy Proto fields.
215 for (unsigned i = 0, e = Proto->getValues().size(); i != e; ++i) {
216 RecordVal RV = Proto->getValues()[i];
218 // Replace the sub-register list with Tuple.
219 if (RV.getName() == "SubRegs")
220 RV.setValue(ListInit::get(Tuple, RegisterRecTy));
222 // Provide a blank AsmName. MC hacks are required anyway.
223 if (RV.getName() == "AsmName")
224 RV.setValue(BlankName);
226 // CostPerUse is aggregated from all Tuple members.
227 if (RV.getName() == "CostPerUse")
228 RV.setValue(IntInit::get(CostPerUse));
230 // Copy fields from the RegisterTuples def.
231 if (RV.getName() == "SubRegIndices" ||
232 RV.getName() == "CompositeIndices") {
233 NewReg->addValue(*Def->getValue(RV.getName()));
237 // Some fields get their default uninitialized value.
238 if (RV.getName() == "DwarfNumbers" ||
239 RV.getName() == "DwarfAlias" ||
240 RV.getName() == "Aliases") {
241 if (const RecordVal *DefRV = RegisterCl->getValue(RV.getName()))
242 NewReg->addValue(*DefRV);
246 // Everything else is copied from Proto.
247 NewReg->addValue(RV);
254 //===----------------------------------------------------------------------===//
255 // CodeGenRegisterClass
256 //===----------------------------------------------------------------------===//
258 CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
260 // Rename anonymous register classes.
261 if (R->getName().size() > 9 && R->getName()[9] == '.') {
262 static unsigned AnonCounter = 0;
263 R->setName("AnonRegClass_"+utostr(AnonCounter++));
266 std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes");
267 for (unsigned i = 0, e = TypeList.size(); i != e; ++i) {
268 Record *Type = TypeList[i];
269 if (!Type->isSubClassOf("ValueType"))
270 throw "RegTypes list member '" + Type->getName() +
271 "' does not derive from the ValueType class!";
272 VTs.push_back(getValueType(Type));
274 assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!");
276 // Default allocation order always contains all registers.
277 Elements = RegBank.getSets().expand(R);
278 for (unsigned i = 0, e = Elements->size(); i != e; ++i)
279 Members.insert(RegBank.getReg((*Elements)[i]));
281 // Alternative allocation orders may be subsets.
282 const ListInit *Alts = R->getValueAsListInit("AltOrders");
283 AltOrders.resize(Alts->size());
284 SetTheory::RecSet Order;
285 for (unsigned i = 0, e = Alts->size(); i != e; ++i) {
286 RegBank.getSets().evaluate(Alts->getElement(i), Order);
287 AltOrders[i].append(Order.begin(), Order.end());
288 // Verify that all altorder members are regclass members.
289 while (!Order.empty()) {
290 CodeGenRegister *Reg = RegBank.getReg(Order.back());
293 throw TGError(R->getLoc(), " AltOrder register " + Reg->getName() +
294 " is not a class member");
298 // SubRegClasses is a list<dag> containing (RC, subregindex, ...) dags.
299 const ListInit *SRC = R->getValueAsListInit("SubRegClasses");
300 for (ListInit::const_iterator i = SRC->begin(), e = SRC->end(); i != e; ++i) {
301 const DagInit *DAG = dynamic_cast<const DagInit*>(*i);
302 if (!DAG) throw "SubRegClasses must contain DAGs";
303 const DefInit *DAGOp = dynamic_cast<const DefInit*>(DAG->getOperator());
305 if (!DAGOp || !(RCRec = DAGOp->getDef())->isSubClassOf("RegisterClass"))
306 throw "Operator '" + DAG->getOperator()->getAsString() +
307 "' in SubRegClasses is not a RegisterClass";
308 // Iterate over args, all SubRegIndex instances.
309 for (DagInit::const_arg_iterator ai = DAG->arg_begin(), ae = DAG->arg_end();
311 const DefInit *Idx = dynamic_cast<const DefInit*>(*ai);
313 if (!Idx || !(IdxRec = Idx->getDef())->isSubClassOf("SubRegIndex"))
314 throw "Argument '" + (*ai)->getAsString() +
315 "' in SubRegClasses is not a SubRegIndex";
316 if (!SubRegClasses.insert(std::make_pair(IdxRec, RCRec)).second)
317 throw "SubRegIndex '" + IdxRec->getName() + "' mentioned twice";
321 // Allow targets to override the size in bits of the RegisterClass.
322 unsigned Size = R->getValueAsInt("Size");
324 Namespace = R->getValueAsString("Namespace");
325 SpillSize = Size ? Size : EVT(VTs[0]).getSizeInBits();
326 SpillAlignment = R->getValueAsInt("Alignment");
327 CopyCost = R->getValueAsInt("CopyCost");
328 Allocatable = R->getValueAsBit("isAllocatable");
329 AltOrderSelect = R->getValueAsCode("AltOrderSelect");
332 bool CodeGenRegisterClass::contains(const CodeGenRegister *Reg) const {
333 return Members.count(Reg);
336 // Returns true if RC is a strict subclass.
337 // RC is a sub-class of this class if it is a valid replacement for any
338 // instruction operand where a register of this classis required. It must
339 // satisfy these conditions:
341 // 1. All RC registers are also in this.
342 // 2. The RC spill size must not be smaller than our spill size.
343 // 3. RC spill alignment must be compatible with ours.
345 bool CodeGenRegisterClass::hasSubClass(const CodeGenRegisterClass *RC) const {
346 return SpillAlignment && RC->SpillAlignment % SpillAlignment == 0 &&
347 SpillSize <= RC->SpillSize &&
348 std::includes(Members.begin(), Members.end(),
349 RC->Members.begin(), RC->Members.end(),
350 CodeGenRegister::Less());
353 const std::string &CodeGenRegisterClass::getName() const {
354 return TheDef->getName();
357 //===----------------------------------------------------------------------===//
359 //===----------------------------------------------------------------------===//
361 CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records) : Records(Records) {
362 // Configure register Sets to understand register classes and tuples.
363 Sets.addFieldExpander("RegisterClass", "MemberList");
364 Sets.addExpander("RegisterTuples", new TupleExpander());
366 // Read in the user-defined (named) sub-register indices.
367 // More indices will be synthesized later.
368 SubRegIndices = Records.getAllDerivedDefinitions("SubRegIndex");
369 std::sort(SubRegIndices.begin(), SubRegIndices.end(), LessRecord());
370 NumNamedIndices = SubRegIndices.size();
372 // Read in the register definitions.
373 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
374 std::sort(Regs.begin(), Regs.end(), LessRecord());
375 Registers.reserve(Regs.size());
376 // Assign the enumeration values.
377 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
380 // Expand tuples and number the new registers.
381 std::vector<Record*> Tups =
382 Records.getAllDerivedDefinitions("RegisterTuples");
383 for (unsigned i = 0, e = Tups.size(); i != e; ++i) {
384 const std::vector<Record*> *TupRegs = Sets.expand(Tups[i]);
385 for (unsigned j = 0, je = TupRegs->size(); j != je; ++j)
386 getReg((*TupRegs)[j]);
389 // Read in register class definitions.
390 std::vector<Record*> RCs = Records.getAllDerivedDefinitions("RegisterClass");
392 throw std::string("No 'RegisterClass' subclasses defined!");
394 RegClasses.reserve(RCs.size());
395 for (unsigned i = 0, e = RCs.size(); i != e; ++i)
396 RegClasses.push_back(CodeGenRegisterClass(*this, RCs[i]));
399 CodeGenRegister *CodeGenRegBank::getReg(Record *Def) {
400 CodeGenRegister *&Reg = Def2Reg[Def];
403 Reg = new CodeGenRegister(Def, Registers.size() + 1);
404 Registers.push_back(Reg);
408 CodeGenRegisterClass *CodeGenRegBank::getRegClass(Record *Def) {
410 for (unsigned i = 0, e = RegClasses.size(); i != e; ++i)
411 Def2RC[RegClasses[i].TheDef] = &RegClasses[i];
413 if (CodeGenRegisterClass *RC = Def2RC[Def])
416 throw TGError(Def->getLoc(), "Not a known RegisterClass!");
419 Record *CodeGenRegBank::getCompositeSubRegIndex(Record *A, Record *B,
421 // Look for an existing entry.
422 Record *&Comp = Composite[std::make_pair(A, B)];
426 // None exists, synthesize one.
427 std::string Name = A->getName() + "_then_" + B->getName();
428 Comp = new Record(Name, SMLoc(), Records);
429 Records.addDef(Comp);
430 SubRegIndices.push_back(Comp);
434 unsigned CodeGenRegBank::getSubRegIndexNo(Record *idx) {
435 std::vector<Record*>::const_iterator i =
436 std::find(SubRegIndices.begin(), SubRegIndices.end(), idx);
437 assert(i != SubRegIndices.end() && "Not a SubRegIndex");
438 return (i - SubRegIndices.begin()) + 1;
441 void CodeGenRegBank::computeComposites() {
442 // Precompute all sub-register maps. This will create Composite entries for
443 // all inferred sub-register indices.
444 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
445 Registers[i]->getSubRegs(*this);
447 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
448 CodeGenRegister *Reg1 = Registers[i];
449 const CodeGenRegister::SubRegMap &SRM1 = Reg1->getSubRegs();
450 for (CodeGenRegister::SubRegMap::const_iterator i1 = SRM1.begin(),
451 e1 = SRM1.end(); i1 != e1; ++i1) {
452 Record *Idx1 = i1->first;
453 CodeGenRegister *Reg2 = i1->second;
454 // Ignore identity compositions.
457 const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs();
458 // Try composing Idx1 with another SubRegIndex.
459 for (CodeGenRegister::SubRegMap::const_iterator i2 = SRM2.begin(),
460 e2 = SRM2.end(); i2 != e2; ++i2) {
461 std::pair<Record*, Record*> IdxPair(Idx1, i2->first);
462 CodeGenRegister *Reg3 = i2->second;
463 // Ignore identity compositions.
466 // OK Reg1:IdxPair == Reg3. Find the index with Reg:Idx == Reg3.
467 for (CodeGenRegister::SubRegMap::const_iterator i1d = SRM1.begin(),
468 e1d = SRM1.end(); i1d != e1d; ++i1d) {
469 if (i1d->second == Reg3) {
470 std::pair<CompositeMap::iterator, bool> Ins =
471 Composite.insert(std::make_pair(IdxPair, i1d->first));
472 // Conflicting composition? Emit a warning but allow it.
473 if (!Ins.second && Ins.first->second != i1d->first) {
474 errs() << "Warning: SubRegIndex " << getQualifiedName(Idx1)
475 << " and " << getQualifiedName(IdxPair.second)
476 << " compose ambiguously as "
477 << getQualifiedName(Ins.first->second) << " or "
478 << getQualifiedName(i1d->first) << "\n";
486 // We don't care about the difference between (Idx1, Idx2) -> Idx2 and invalid
487 // compositions, so remove any mappings of that form.
488 for (CompositeMap::iterator i = Composite.begin(), e = Composite.end();
490 CompositeMap::iterator j = i;
492 if (j->first.second == j->second)
497 // Compute sets of overlapping registers.
499 // The standard set is all super-registers and all sub-registers, but the
500 // target description can add arbitrary overlapping registers via the 'Aliases'
501 // field. This complicates things, but we can compute overlapping sets using
502 // the following rules:
504 // 1. The relation overlap(A, B) is reflexive and symmetric but not transitive.
506 // 2. overlap(A, B) implies overlap(A, S) for all S in supers(B).
510 // overlap(A, B) iff there exists:
511 // A' in { A, subregs(A) } and B' in { B, subregs(B) } such that:
512 // A' = B' or A' in aliases(B') or B' in aliases(A').
514 // Here subregs(A) is the full flattened sub-register set returned by
515 // A.getSubRegs() while aliases(A) is simply the special 'Aliases' field in the
516 // description of register A.
518 // This also implies that registers with a common sub-register are considered
519 // overlapping. This can happen when forming register pairs:
525 // In this case, we will infer an overlap between P0 and P1 because of the
526 // shared sub-register R1. There is no overlap between P0 and P2.
528 void CodeGenRegBank::
529 computeOverlaps(std::map<const CodeGenRegister*, CodeGenRegister::Set> &Map) {
532 // Collect overlaps that don't follow from rule 2.
533 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
534 CodeGenRegister *Reg = Registers[i];
535 CodeGenRegister::Set &Overlaps = Map[Reg];
537 // Reg overlaps itself.
538 Overlaps.insert(Reg);
540 // All super-registers overlap.
541 const CodeGenRegister::SuperRegList &Supers = Reg->getSuperRegs();
542 Overlaps.insert(Supers.begin(), Supers.end());
544 // Form symmetrical relations from the special Aliases[] lists.
545 std::vector<Record*> RegList = Reg->TheDef->getValueAsListOfDefs("Aliases");
546 for (unsigned i2 = 0, e2 = RegList.size(); i2 != e2; ++i2) {
547 CodeGenRegister *Reg2 = getReg(RegList[i2]);
548 CodeGenRegister::Set &Overlaps2 = Map[Reg2];
549 const CodeGenRegister::SuperRegList &Supers2 = Reg2->getSuperRegs();
550 // Reg overlaps Reg2 which implies it overlaps supers(Reg2).
551 Overlaps.insert(Reg2);
552 Overlaps.insert(Supers2.begin(), Supers2.end());
553 Overlaps2.insert(Reg);
554 Overlaps2.insert(Supers.begin(), Supers.end());
558 // Apply rule 2. and inherit all sub-register overlaps.
559 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
560 CodeGenRegister *Reg = Registers[i];
561 CodeGenRegister::Set &Overlaps = Map[Reg];
562 const CodeGenRegister::SubRegMap &SRM = Reg->getSubRegs();
563 for (CodeGenRegister::SubRegMap::const_iterator i2 = SRM.begin(),
564 e2 = SRM.end(); i2 != e2; ++i2) {
565 CodeGenRegister::Set &Overlaps2 = Map[i2->second];
566 Overlaps.insert(Overlaps2.begin(), Overlaps2.end());
571 void CodeGenRegBank::computeDerivedInfo() {
575 /// getRegisterClassForRegister - Find the register class that contains the
576 /// specified physical register. If the register is not in a register class,
577 /// return null. If the register is in multiple classes, and the classes have a
578 /// superset-subset relationship and the same set of types, return the
579 /// superclass. Otherwise return null.
580 const CodeGenRegisterClass*
581 CodeGenRegBank::getRegClassForRegister(Record *R) {
582 const CodeGenRegister *Reg = getReg(R);
583 const std::vector<CodeGenRegisterClass> &RCs = getRegClasses();
584 const CodeGenRegisterClass *FoundRC = 0;
585 for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
586 const CodeGenRegisterClass &RC = RCs[i];
587 if (!RC.contains(Reg))
590 // If this is the first class that contains the register,
591 // make a note of it and go on to the next class.
597 // If a register's classes have different types, return null.
598 if (RC.getValueTypes() != FoundRC->getValueTypes())
601 // Check to see if the previously found class that contains
602 // the register is a subclass of the current class. If so,
603 // prefer the superclass.
604 if (RC.hasSubClass(FoundRC)) {
609 // Check to see if the previously found class that contains
610 // the register is a superclass of the current class. If so,
611 // prefer the superclass.
612 if (FoundRC->hasSubClass(&RC))
615 // Multiple classes, and neither is a superclass of the other.