1 //===- CodeGenRegisters.h - Register and RegisterClass Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines structures to encapsulate information gleaned from the
11 // target register and register class definitions.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_UTILS_TABLEGEN_CODEGENREGISTERS_H
16 #define LLVM_UTILS_TABLEGEN_CODEGENREGISTERS_H
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/ADT/DenseMap.h"
21 #include "llvm/ADT/SetVector.h"
22 #include "llvm/CodeGen/MachineValueType.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/TableGen/Record.h"
25 #include "llvm/TableGen/SetTheory.h"
31 #include <forward_list>
36 /// CodeGenSubRegIndex - Represents a sub-register index.
37 class CodeGenSubRegIndex {
40 std::string Namespace;
45 const unsigned EnumValue;
46 mutable unsigned LaneMask;
48 // Are all super-registers containing this SubRegIndex covered by their
50 bool AllSuperRegsCovered;
52 CodeGenSubRegIndex(Record *R, unsigned Enum);
53 CodeGenSubRegIndex(StringRef N, StringRef Nspace, unsigned Enum);
55 const std::string &getName() const { return Name; }
56 const std::string &getNamespace() const { return Namespace; }
57 std::string getQualifiedName() const;
59 // Order CodeGenSubRegIndex pointers by EnumValue.
61 bool operator()(const CodeGenSubRegIndex *A,
62 const CodeGenSubRegIndex *B) const {
64 return A->EnumValue < B->EnumValue;
68 // Map of composite subreg indices.
69 typedef std::map<CodeGenSubRegIndex*, CodeGenSubRegIndex*, Less> CompMap;
71 // Returns the subreg index that results from composing this with Idx.
72 // Returns NULL if this and Idx don't compose.
73 CodeGenSubRegIndex *compose(CodeGenSubRegIndex *Idx) const {
74 CompMap::const_iterator I = Composed.find(Idx);
75 return I == Composed.end() ? nullptr : I->second;
78 // Add a composite subreg index: this+A = B.
79 // Return a conflicting composite, or NULL
80 CodeGenSubRegIndex *addComposite(CodeGenSubRegIndex *A,
81 CodeGenSubRegIndex *B) {
83 std::pair<CompMap::iterator, bool> Ins =
84 Composed.insert(std::make_pair(A, B));
85 // Synthetic subreg indices that aren't contiguous (for instance ARM
86 // register tuples) don't have a bit range, so it's OK to let
87 // B->Offset == -1. For the other cases, accumulate the offset and set
88 // the size here. Only do so if there is no offset yet though.
89 if ((Offset != (uint16_t)-1 && A->Offset != (uint16_t)-1) &&
90 (B->Offset == (uint16_t)-1)) {
91 B->Offset = Offset + A->Offset;
94 return (Ins.second || Ins.first->second == B) ? nullptr
98 // Update the composite maps of components specified in 'ComposedOf'.
99 void updateComponents(CodeGenRegBank&);
101 // Return the map of composites.
102 const CompMap &getComposites() const { return Composed; }
104 // Compute LaneMask from Composed. Return LaneMask.
105 unsigned computeLaneMask() const;
111 /// CodeGenRegister - Represents a register definition.
112 struct CodeGenRegister {
116 bool CoveredBySubRegs;
118 // Map SubRegIndex -> Register.
119 typedef std::map<CodeGenSubRegIndex*, CodeGenRegister*,
120 CodeGenSubRegIndex::Less> SubRegMap;
122 CodeGenRegister(Record *R, unsigned Enum);
124 const std::string &getName() const;
126 // Extract more information from TheDef. This is used to build an object
127 // graph after all CodeGenRegister objects have been created.
128 void buildObjectGraph(CodeGenRegBank&);
130 // Lazily compute a map of all sub-registers.
131 // This includes unique entries for all sub-sub-registers.
132 const SubRegMap &computeSubRegs(CodeGenRegBank&);
134 // Compute extra sub-registers by combining the existing sub-registers.
135 void computeSecondarySubRegs(CodeGenRegBank&);
137 // Add this as a super-register to all sub-registers after the sub-register
138 // graph has been built.
139 void computeSuperRegs(CodeGenRegBank&);
141 const SubRegMap &getSubRegs() const {
142 assert(SubRegsComplete && "Must precompute sub-registers");
146 // Add sub-registers to OSet following a pre-order defined by the .td file.
147 void addSubRegsPreOrder(SetVector<const CodeGenRegister*> &OSet,
148 CodeGenRegBank&) const;
150 // Return the sub-register index naming Reg as a sub-register of this
151 // register. Returns NULL if Reg is not a sub-register.
152 CodeGenSubRegIndex *getSubRegIndex(const CodeGenRegister *Reg) const {
153 return SubReg2Idx.lookup(Reg);
156 typedef std::vector<const CodeGenRegister*> SuperRegList;
158 // Get the list of super-registers in topological order, small to large.
159 // This is valid after computeSubRegs visits all registers during RegBank
161 const SuperRegList &getSuperRegs() const {
162 assert(SubRegsComplete && "Must precompute sub-registers");
166 // Get the list of ad hoc aliases. The graph is symmetric, so the list
167 // contains all registers in 'Aliases', and all registers that mention this
168 // register in 'Aliases'.
169 ArrayRef<CodeGenRegister*> getExplicitAliases() const {
170 return ExplicitAliases;
173 // Get the topological signature of this register. This is a small integer
174 // less than RegBank.getNumTopoSigs(). Registers with the same TopoSig have
175 // identical sub-register structure. That is, they support the same set of
176 // sub-register indices mapping to the same kind of sub-registers
178 unsigned getTopoSig() const {
179 assert(SuperRegsComplete && "TopoSigs haven't been computed yet.");
183 // List of register units in ascending order.
184 typedef SmallVector<unsigned, 16> RegUnitList;
186 // How many entries in RegUnitList are native?
187 unsigned NumNativeRegUnits;
189 // Get the list of register units.
190 // This is only valid after computeSubRegs() completes.
191 const RegUnitList &getRegUnits() const { return RegUnits; }
193 // Get the native register units. This is a prefix of getRegUnits().
194 ArrayRef<unsigned> getNativeRegUnits() const {
195 return makeArrayRef(RegUnits).slice(0, NumNativeRegUnits);
198 // Inherit register units from subregisters.
199 // Return true if the RegUnits changed.
200 bool inheritRegUnits(CodeGenRegBank &RegBank);
202 // Adopt a register unit for pressure tracking.
203 // A unit is adopted iff its unit number is >= NumNativeRegUnits.
204 void adoptRegUnit(unsigned RUID) { RegUnits.push_back(RUID); }
206 // Get the sum of this register's register unit weights.
207 unsigned getWeight(const CodeGenRegBank &RegBank) const;
209 // Order CodeGenRegister pointers by EnumValue.
211 bool operator()(const CodeGenRegister *A,
212 const CodeGenRegister *B) const {
214 return A->EnumValue < B->EnumValue;
218 // Canonically ordered set.
219 typedef std::set<const CodeGenRegister*, Less> Set;
222 bool SubRegsComplete;
223 bool SuperRegsComplete;
226 // The sub-registers explicit in the .td file form a tree.
227 SmallVector<CodeGenSubRegIndex*, 8> ExplicitSubRegIndices;
228 SmallVector<CodeGenRegister*, 8> ExplicitSubRegs;
230 // Explicit ad hoc aliases, symmetrized to form an undirected graph.
231 SmallVector<CodeGenRegister*, 8> ExplicitAliases;
233 // Super-registers where this is the first explicit sub-register.
234 SuperRegList LeadingSuperRegs;
237 SuperRegList SuperRegs;
238 DenseMap<const CodeGenRegister*, CodeGenSubRegIndex*> SubReg2Idx;
239 RegUnitList RegUnits;
243 class CodeGenRegisterClass {
244 CodeGenRegister::Set Members;
245 // Allocation orders. Order[0] always contains all registers in Members.
246 std::vector<SmallVector<Record*, 16> > Orders;
247 // Bit mask of sub-classes including this, indexed by their EnumValue.
248 BitVector SubClasses;
249 // List of super-classes, topologocally ordered to have the larger classes
250 // first. This is the same as sorting by EnumValue.
251 SmallVector<CodeGenRegisterClass*, 4> SuperClasses;
255 // For a synthesized class, inherit missing properties from the nearest
257 void inheritProperties(CodeGenRegBank&);
259 // Map SubRegIndex -> sub-class. This is the largest sub-class where all
260 // registers have a SubRegIndex sub-register.
261 DenseMap<const CodeGenSubRegIndex *, CodeGenRegisterClass *>
264 // Map SubRegIndex -> set of super-reg classes. This is all register
265 // classes SuperRC such that:
267 // R:SubRegIndex in this RC for all R in SuperRC.
269 DenseMap<const CodeGenSubRegIndex *, SmallPtrSet<CodeGenRegisterClass *, 8>>
272 // Bit vector of TopoSigs for the registers in this class. This will be
273 // very sparse on regular architectures.
278 std::string Namespace;
279 SmallVector<MVT::SimpleValueType, 4> VTs;
281 unsigned SpillAlignment;
284 std::string AltOrderSelect;
286 // Return the Record that defined this class, or NULL if the class was
287 // created by TableGen.
288 Record *getDef() const { return TheDef; }
290 const std::string &getName() const { return Name; }
291 std::string getQualifiedName() const;
292 ArrayRef<MVT::SimpleValueType> getValueTypes() const {return VTs;}
293 unsigned getNumValueTypes() const { return VTs.size(); }
295 MVT::SimpleValueType getValueTypeNum(unsigned VTNum) const {
296 if (VTNum < VTs.size())
298 llvm_unreachable("VTNum greater than number of ValueTypes in RegClass!");
301 // Return true if this this class contains the register.
302 bool contains(const CodeGenRegister*) const;
304 // Returns true if RC is a subclass.
305 // RC is a sub-class of this class if it is a valid replacement for any
306 // instruction operand where a register of this classis required. It must
307 // satisfy these conditions:
309 // 1. All RC registers are also in this.
310 // 2. The RC spill size must not be smaller than our spill size.
311 // 3. RC spill alignment must be compatible with ours.
313 bool hasSubClass(const CodeGenRegisterClass *RC) const {
314 return SubClasses.test(RC->EnumValue);
317 // getSubClassWithSubReg - Returns the largest sub-class where all
318 // registers have a SubIdx sub-register.
319 CodeGenRegisterClass *
320 getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const {
321 return SubClassWithSubReg.lookup(SubIdx);
324 void setSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx,
325 CodeGenRegisterClass *SubRC) {
326 SubClassWithSubReg[SubIdx] = SubRC;
329 // getSuperRegClasses - Returns a bit vector of all register classes
330 // containing only SubIdx super-registers of this class.
331 void getSuperRegClasses(const CodeGenSubRegIndex *SubIdx,
332 BitVector &Out) const;
334 // addSuperRegClass - Add a class containing only SudIdx super-registers.
335 void addSuperRegClass(CodeGenSubRegIndex *SubIdx,
336 CodeGenRegisterClass *SuperRC) {
337 SuperRegClasses[SubIdx].insert(SuperRC);
340 // getSubClasses - Returns a constant BitVector of subclasses indexed by
342 // The SubClasses vector includes an entry for this class.
343 const BitVector &getSubClasses() const { return SubClasses; }
345 // getSuperClasses - Returns a list of super classes ordered by EnumValue.
346 // The array does not include an entry for this class.
347 ArrayRef<CodeGenRegisterClass*> getSuperClasses() const {
351 // Returns an ordered list of class members.
352 // The order of registers is the same as in the .td file.
353 // No = 0 is the default allocation order, No = 1 is the first alternative.
354 ArrayRef<Record*> getOrder(unsigned No = 0) const {
358 // Return the total number of allocation orders available.
359 unsigned getNumOrders() const { return Orders.size(); }
361 // Get the set of registers. This set contains the same registers as
363 const CodeGenRegister::Set &getMembers() const { return Members; }
365 // Get a bit vector of TopoSigs present in this register class.
366 const BitVector &getTopoSigs() const { return TopoSigs; }
368 // Populate a unique sorted list of units from a register set.
369 void buildRegUnitSet(std::vector<unsigned> &RegUnits) const;
371 CodeGenRegisterClass(CodeGenRegBank&, Record *R);
373 // A key representing the parts of a register class used for forming
374 // sub-classes. Note the ordering provided by this key is not the same as
375 // the topological order used for the EnumValues.
377 const CodeGenRegister::Set *Members;
379 unsigned SpillAlignment;
381 Key(const CodeGenRegister::Set *M, unsigned S = 0, unsigned A = 0)
382 : Members(M), SpillSize(S), SpillAlignment(A) {}
384 Key(const CodeGenRegisterClass &RC)
385 : Members(&RC.getMembers()),
386 SpillSize(RC.SpillSize),
387 SpillAlignment(RC.SpillAlignment) {}
389 // Lexicographical order of (Members, SpillSize, SpillAlignment).
390 bool operator<(const Key&) const;
393 // Create a non-user defined register class.
394 CodeGenRegisterClass(CodeGenRegBank&, StringRef Name, Key Props);
396 // Called by CodeGenRegBank::CodeGenRegBank().
397 static void computeSubClasses(CodeGenRegBank&);
400 // Register units are used to model interference and register pressure.
401 // Every register is assigned one or more register units such that two
402 // registers overlap if and only if they have a register unit in common.
404 // Normally, one register unit is created per leaf register. Non-leaf
405 // registers inherit the units of their sub-registers.
407 // Weight assigned to this RegUnit for estimating register pressure.
408 // This is useful when equalizing weights in register classes with mixed
409 // register topologies.
412 // Each native RegUnit corresponds to one or two root registers. The full
413 // set of registers containing this unit can be computed as the union of
414 // these two registers and their super-registers.
415 const CodeGenRegister *Roots[2];
417 // Index into RegClassUnitSets where we can find the list of UnitSets that
418 // contain this unit.
419 unsigned RegClassUnitSetsIdx;
421 RegUnit() : Weight(0), RegClassUnitSetsIdx(0) {
422 Roots[0] = Roots[1] = nullptr;
425 ArrayRef<const CodeGenRegister*> getRoots() const {
426 assert(!(Roots[1] && !Roots[0]) && "Invalid roots array");
427 return makeArrayRef(Roots, !!Roots[0] + !!Roots[1]);
431 // Each RegUnitSet is a sorted vector with a name.
433 typedef std::vector<unsigned>::const_iterator iterator;
436 std::vector<unsigned> Units;
437 unsigned Weight; // Cache the sum of all unit weights.
438 unsigned Order; // Cache the sort key.
440 RegUnitSet() : Weight(0), Order(0) {}
443 // Base vector for identifying TopoSigs. The contents uniquely identify a
444 // TopoSig, only computeSuperRegs needs to know how.
445 typedef SmallVector<unsigned, 16> TopoSigId;
447 // CodeGenRegBank - Represent a target's registers and the relations between
449 class CodeGenRegBank {
452 //std::forward_list<CodeGenSubRegIndex> SubRegIndices;
453 std::vector<CodeGenSubRegIndex*> SubRegIndices;
454 DenseMap<Record*, CodeGenSubRegIndex*> Def2SubRegIdx;
456 CodeGenSubRegIndex *createSubRegIndex(StringRef Name, StringRef NameSpace);
458 typedef std::map<SmallVector<CodeGenSubRegIndex*, 8>,
459 CodeGenSubRegIndex*> ConcatIdxMap;
460 ConcatIdxMap ConcatIdx;
463 std::vector<CodeGenRegister*> Registers;
464 StringMap<CodeGenRegister*> RegistersByName;
465 DenseMap<Record*, CodeGenRegister*> Def2Reg;
466 unsigned NumNativeRegUnits;
468 std::map<TopoSigId, unsigned> TopoSigs;
470 // Includes native (0..NumNativeRegUnits-1) and adopted register units.
471 SmallVector<RegUnit, 8> RegUnits;
474 std::vector<CodeGenRegisterClass*> RegClasses;
475 DenseMap<Record*, CodeGenRegisterClass*> Def2RC;
476 typedef std::map<CodeGenRegisterClass::Key, CodeGenRegisterClass*> RCKeyMap;
479 // Remember each unique set of register units. Initially, this contains a
480 // unique set for each register class. Simliar sets are coalesced with
481 // pruneUnitSets and new supersets are inferred during computeRegUnitSets.
482 std::vector<RegUnitSet> RegUnitSets;
484 // Map RegisterClass index to the index of the RegUnitSet that contains the
485 // class's units and any inferred RegUnit supersets.
487 // NOTE: This could grow beyond the number of register classes when we map
488 // register units to lists of unit sets. If the list of unit sets does not
489 // already exist for a register class, we create a new entry in this vector.
490 std::vector<std::vector<unsigned> > RegClassUnitSets;
492 // Give each register unit set an order based on sorting criteria.
493 std::vector<unsigned> RegUnitSetOrder;
495 // Add RC to *2RC maps.
496 void addToMaps(CodeGenRegisterClass*);
498 // Create a synthetic sub-class if it is missing.
499 CodeGenRegisterClass *getOrCreateSubClass(const CodeGenRegisterClass *RC,
500 const CodeGenRegister::Set *Membs,
503 // Infer missing register classes.
504 void computeInferredRegisterClasses();
505 void inferCommonSubClass(CodeGenRegisterClass *RC);
506 void inferSubClassWithSubReg(CodeGenRegisterClass *RC);
507 void inferMatchingSuperRegClass(CodeGenRegisterClass *RC,
508 unsigned FirstSubRegRC = 0);
510 // Iteratively prune unit sets.
511 void pruneUnitSets();
513 // Compute a weight for each register unit created during getSubRegs.
514 void computeRegUnitWeights();
516 // Create a RegUnitSet for each RegClass and infer superclasses.
517 void computeRegUnitSets();
519 // Populate the Composite map from sub-register relationships.
520 void computeComposites();
522 // Compute a lane mask for each sub-register index.
523 void computeSubRegIndexLaneMasks();
526 CodeGenRegBank(RecordKeeper&);
529 SetTheory &getSets() { return Sets; }
531 // Sub-register indices. The first NumNamedIndices are defined by the user
532 // in the .td files. The rest are synthesized such that all sub-registers
533 // have a unique name.
534 std::vector<CodeGenSubRegIndex*> &getSubRegIndices() { return SubRegIndices; }
536 // Find a SubRegIndex form its Record def.
537 CodeGenSubRegIndex *getSubRegIdx(Record*);
539 // Find or create a sub-register index representing the A+B composition.
540 CodeGenSubRegIndex *getCompositeSubRegIndex(CodeGenSubRegIndex *A,
541 CodeGenSubRegIndex *B);
543 // Find or create a sub-register index representing the concatenation of
544 // non-overlapping sibling indices.
546 getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex *, 8>&);
549 addConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex *, 8> &Parts,
550 CodeGenSubRegIndex *Idx) {
551 ConcatIdx.insert(std::make_pair(Parts, Idx));
554 const std::vector<CodeGenRegister*> &getRegisters() { return Registers; }
555 const StringMap<CodeGenRegister*> &getRegistersByName() {
556 return RegistersByName;
559 // Find a register from its Record def.
560 CodeGenRegister *getReg(Record*);
562 // Get a Register's index into the Registers array.
563 unsigned getRegIndex(const CodeGenRegister *Reg) const {
564 return Reg->EnumValue - 1;
567 // Return the number of allocated TopoSigs. The first TopoSig representing
568 // leaf registers is allocated number 0.
569 unsigned getNumTopoSigs() const {
570 return TopoSigs.size();
573 // Find or create a TopoSig for the given TopoSigId.
574 // This function is only for use by CodeGenRegister::computeSuperRegs().
575 // Others should simply use Reg->getTopoSig().
576 unsigned getTopoSig(const TopoSigId &Id) {
577 return TopoSigs.insert(std::make_pair(Id, TopoSigs.size())).first->second;
580 // Create a native register unit that is associated with one or two root
582 unsigned newRegUnit(CodeGenRegister *R0, CodeGenRegister *R1 = nullptr) {
583 RegUnits.resize(RegUnits.size() + 1);
584 RegUnits.back().Roots[0] = R0;
585 RegUnits.back().Roots[1] = R1;
586 return RegUnits.size() - 1;
589 // Create a new non-native register unit that can be adopted by a register
590 // to increase its pressure. Note that NumNativeRegUnits is not increased.
591 unsigned newRegUnit(unsigned Weight) {
592 RegUnits.resize(RegUnits.size() + 1);
593 RegUnits.back().Weight = Weight;
594 return RegUnits.size() - 1;
597 // Native units are the singular unit of a leaf register. Register aliasing
598 // is completely characterized by native units. Adopted units exist to give
599 // register additional weight but don't affect aliasing.
600 bool isNativeUnit(unsigned RUID) {
601 return RUID < NumNativeRegUnits;
604 unsigned getNumNativeRegUnits() const {
605 return NumNativeRegUnits;
608 RegUnit &getRegUnit(unsigned RUID) { return RegUnits[RUID]; }
609 const RegUnit &getRegUnit(unsigned RUID) const { return RegUnits[RUID]; }
611 ArrayRef<CodeGenRegisterClass*> getRegClasses() const {
615 // Find a register class from its def.
616 CodeGenRegisterClass *getRegClass(Record*);
618 /// getRegisterClassForRegister - Find the register class that contains the
619 /// specified physical register. If the register is not in a register
620 /// class, return null. If the register is in multiple classes, and the
621 /// classes have a superset-subset relationship and the same set of types,
622 /// return the superclass. Otherwise return null.
623 const CodeGenRegisterClass* getRegClassForRegister(Record *R);
625 // Get the sum of unit weights.
626 unsigned getRegUnitSetWeight(const std::vector<unsigned> &Units) const {
628 for (std::vector<unsigned>::const_iterator
629 I = Units.begin(), E = Units.end(); I != E; ++I)
630 Weight += getRegUnit(*I).Weight;
634 unsigned getRegSetIDAt(unsigned Order) const {
635 return RegUnitSetOrder[Order];
637 const RegUnitSet &getRegSetAt(unsigned Order) const {
638 return RegUnitSets[RegUnitSetOrder[Order]];
641 // Increase a RegUnitWeight.
642 void increaseRegUnitWeight(unsigned RUID, unsigned Inc) {
643 getRegUnit(RUID).Weight += Inc;
646 // Get the number of register pressure dimensions.
647 unsigned getNumRegPressureSets() const { return RegUnitSets.size(); }
649 // Get a set of register unit IDs for a given dimension of pressure.
650 const RegUnitSet &getRegPressureSet(unsigned Idx) const {
651 return RegUnitSets[Idx];
654 // The number of pressure set lists may be larget than the number of
655 // register classes if some register units appeared in a list of sets that
656 // did not correspond to an existing register class.
657 unsigned getNumRegClassPressureSetLists() const {
658 return RegClassUnitSets.size();
661 // Get a list of pressure set IDs for a register class. Liveness of a
662 // register in this class impacts each pressure set in this list by the
663 // weight of the register. An exact solution requires all registers in a
664 // class to have the same class, but it is not strictly guaranteed.
665 ArrayRef<unsigned> getRCPressureSetIDs(unsigned RCIdx) const {
666 return RegClassUnitSets[RCIdx];
669 // Computed derived records such as missing sub-register indices.
670 void computeDerivedInfo();
672 // Compute the set of registers completely covered by the registers in Regs.
673 // The returned BitVector will have a bit set for each register in Regs,
674 // all sub-registers, and all super-registers that are covered by the
675 // registers in Regs.
677 // This is used to compute the mask of call-preserved registers from a list
679 BitVector computeCoveredRegisters(ArrayRef<Record*> Regs);
681 // Bit mask of lanes that cover their registers. A sub-register index whose
682 // LaneMask is contained in CoveringLanes will be completely covered by
683 // another sub-register with the same or larger lane mask.
684 unsigned CoveringLanes;