1 //===- CodeGenRegisters.h - Register and RegisterClass Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines structures to encapsulate information gleaned from the
11 // target register and register class definitions.
13 //===----------------------------------------------------------------------===//
15 #ifndef CODEGEN_REGISTERS_H
16 #define CODEGEN_REGISTERS_H
19 #include "SetTheory.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/ADT/ArrayRef.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/DenseMap.h"
24 #include "llvm/ADT/SetVector.h"
34 /// CodeGenRegister - Represents a register definition.
35 struct CodeGenRegister {
40 // Map SubRegIndex -> Register.
41 typedef std::map<Record*, CodeGenRegister*, LessRecord> SubRegMap;
43 CodeGenRegister(Record *R, unsigned Enum);
45 const std::string &getName() const;
47 // Get a map of sub-registers computed lazily.
48 // This includes unique entries for all sub-sub-registers.
49 const SubRegMap &getSubRegs(CodeGenRegBank&);
51 const SubRegMap &getSubRegs() const {
52 assert(SubRegsComplete && "Must precompute sub-registers");
56 // Add sub-registers to OSet following a pre-order defined by the .td file.
57 void addSubRegsPreOrder(SetVector<CodeGenRegister*> &OSet) const;
59 // List of super-registers in topological order, small to large.
60 typedef std::vector<CodeGenRegister*> SuperRegList;
62 // Get the list of super-registers.
63 // This is only valid after computeDerivedInfo has visited all registers.
64 const SuperRegList &getSuperRegs() const {
65 assert(SubRegsComplete && "Must precompute sub-registers");
69 // Order CodeGenRegister pointers by EnumValue.
71 bool operator()(const CodeGenRegister *A,
72 const CodeGenRegister *B) const {
73 return A->EnumValue < B->EnumValue;
77 // Canonically ordered set.
78 typedef std::set<const CodeGenRegister*, Less> Set;
83 SuperRegList SuperRegs;
87 class CodeGenRegisterClass {
88 CodeGenRegister::Set Members;
89 const std::vector<Record*> *Elements;
90 std::vector<SmallVector<Record*, 16> > AltOrders;
91 // Bit mask of sub-classes including this, indexed by their EnumValue.
93 // List of super-classes, topologocally ordered to have the larger classes
94 // first. This is the same as sorting by EnumValue.
95 SmallVector<CodeGenRegisterClass*, 4> SuperClasses;
99 std::string Namespace;
100 std::vector<MVT::SimpleValueType> VTs;
102 unsigned SpillAlignment;
105 // Map SubRegIndex -> RegisterClass
106 DenseMap<Record*,Record*> SubRegClasses;
107 std::string AltOrderSelect;
109 const std::string &getName() const;
110 const std::vector<MVT::SimpleValueType> &getValueTypes() const {return VTs;}
111 unsigned getNumValueTypes() const { return VTs.size(); }
113 MVT::SimpleValueType getValueTypeNum(unsigned VTNum) const {
114 if (VTNum < VTs.size())
116 assert(0 && "VTNum greater than number of ValueTypes in RegClass!");
120 // Return true if this this class contains the register.
121 bool contains(const CodeGenRegister*) const;
123 // Returns true if RC is a subclass.
124 // RC is a sub-class of this class if it is a valid replacement for any
125 // instruction operand where a register of this classis required. It must
126 // satisfy these conditions:
128 // 1. All RC registers are also in this.
129 // 2. The RC spill size must not be smaller than our spill size.
130 // 3. RC spill alignment must be compatible with ours.
132 bool hasSubClass(const CodeGenRegisterClass *RC) const;
134 // getSubClasses - Returns a constant BitVector of subclasses indexed by
136 // The SubClasses vector includs an entry for this class.
137 const BitVector &getSubClasses() const { return SubClasses; };
139 // getSuperClasses - Returns a list of super classes ordered by EnumValue.
140 // The array does not include an entry for this class.
141 ArrayRef<CodeGenRegisterClass*> getSuperClasses() const {
145 // Returns an ordered list of class members.
146 // The order of registers is the same as in the .td file.
147 // No = 0 is the default allocation order, No = 1 is the first alternative.
148 ArrayRef<Record*> getOrder(unsigned No = 0) const {
152 return AltOrders[No - 1];
155 // Return the total number of allocation orders available.
156 unsigned getNumOrders() const { return 1 + AltOrders.size(); }
158 CodeGenRegisterClass(CodeGenRegBank&, Record *R);
160 // Called by CodeGenRegBank::CodeGenRegBank().
161 static void computeSubClasses(ArrayRef<CodeGenRegisterClass*>);
164 // CodeGenRegBank - Represent a target's registers and the relations between
166 class CodeGenRegBank {
167 RecordKeeper &Records;
170 std::vector<Record*> SubRegIndices;
171 unsigned NumNamedIndices;
172 std::vector<CodeGenRegister*> Registers;
173 DenseMap<Record*, CodeGenRegister*> Def2Reg;
175 std::vector<CodeGenRegisterClass*> RegClasses;
176 DenseMap<Record*, CodeGenRegisterClass*> Def2RC;
178 // Composite SubRegIndex instances.
179 // Map (SubRegIndex, SubRegIndex) -> SubRegIndex.
180 typedef DenseMap<std::pair<Record*, Record*>, Record*> CompositeMap;
181 CompositeMap Composite;
183 // Populate the Composite map from sub-register relationships.
184 void computeComposites();
187 CodeGenRegBank(RecordKeeper&);
189 SetTheory &getSets() { return Sets; }
191 // Sub-register indices. The first NumNamedIndices are defined by the user
192 // in the .td files. The rest are synthesized such that all sub-registers
193 // have a unique name.
194 const std::vector<Record*> &getSubRegIndices() { return SubRegIndices; }
195 unsigned getNumNamedIndices() { return NumNamedIndices; }
197 // Map a SubRegIndex Record to its enum value.
198 unsigned getSubRegIndexNo(Record *idx);
200 // Find or create a sub-register index representing the A+B composition.
201 Record *getCompositeSubRegIndex(Record *A, Record *B, bool create = false);
203 const std::vector<CodeGenRegister*> &getRegisters() { return Registers; }
205 // Find a register from its Record def.
206 CodeGenRegister *getReg(Record*);
208 ArrayRef<CodeGenRegisterClass*> getRegClasses() const {
212 // Find a register class from its def.
213 CodeGenRegisterClass *getRegClass(Record*);
215 /// getRegisterClassForRegister - Find the register class that contains the
216 /// specified physical register. If the register is not in a register
217 /// class, return null. If the register is in multiple classes, and the
218 /// classes have a superset-subset relationship and the same set of types,
219 /// return the superclass. Otherwise return null.
220 const CodeGenRegisterClass* getRegClassForRegister(Record *R);
222 // Computed derived records such as missing sub-register indices.
223 void computeDerivedInfo();
225 // Compute full overlap sets for every register. These sets include the
226 // rarely used aliases that are neither sub nor super-registers.
228 // Map[R1].count(R2) is reflexive and symmetric, but not transitive.
230 // If R1 is a sub-register of R2, Map[R1] is a subset of Map[R2].
231 void computeOverlaps(std::map<const CodeGenRegister*,
232 CodeGenRegister::Set> &Map);