1 //===- CodeGenRegisters.h - Register and RegisterClass Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines structures to encapsulate information gleaned from the
11 // target register and register class definitions.
13 //===----------------------------------------------------------------------===//
15 #ifndef CODEGEN_REGISTERS_H
16 #define CODEGEN_REGISTERS_H
18 #include "SetTheory.h"
19 #include "llvm/TableGen/Record.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/ADT/ArrayRef.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/DenseMap.h"
24 #include "llvm/ADT/SetVector.h"
34 /// CodeGenSubRegIndex - Represents a sub-register index.
35 class CodeGenSubRegIndex {
37 const unsigned EnumValue;
40 CodeGenSubRegIndex(Record *R, unsigned Enum);
42 const std::string &getName() const;
43 std::string getNamespace() const;
44 std::string getQualifiedName() const;
46 // Order CodeGenSubRegIndex pointers by EnumValue.
48 bool operator()(const CodeGenSubRegIndex *A,
49 const CodeGenSubRegIndex *B) const {
51 return A->EnumValue < B->EnumValue;
56 /// CodeGenRegister - Represents a register definition.
57 struct CodeGenRegister {
61 bool CoveredBySubRegs;
63 // Map SubRegIndex -> Register.
64 typedef std::map<CodeGenSubRegIndex*, CodeGenRegister*,
65 CodeGenSubRegIndex::Less> SubRegMap;
67 CodeGenRegister(Record *R, unsigned Enum);
69 const std::string &getName() const;
71 // Get a map of sub-registers computed lazily.
72 // This includes unique entries for all sub-sub-registers.
73 const SubRegMap &getSubRegs(CodeGenRegBank&);
75 const SubRegMap &getSubRegs() const {
76 assert(SubRegsComplete && "Must precompute sub-registers");
80 // Add sub-registers to OSet following a pre-order defined by the .td file.
81 void addSubRegsPreOrder(SetVector<CodeGenRegister*> &OSet,
82 CodeGenRegBank&) const;
84 // List of super-registers in topological order, small to large.
85 typedef std::vector<CodeGenRegister*> SuperRegList;
87 // Get the list of super-registers.
88 // This is only valid after computeDerivedInfo has visited all registers.
89 const SuperRegList &getSuperRegs() const {
90 assert(SubRegsComplete && "Must precompute sub-registers");
94 // Order CodeGenRegister pointers by EnumValue.
96 bool operator()(const CodeGenRegister *A,
97 const CodeGenRegister *B) const {
99 return A->EnumValue < B->EnumValue;
103 // Canonically ordered set.
104 typedef std::set<const CodeGenRegister*, Less> Set;
107 bool SubRegsComplete;
109 SuperRegList SuperRegs;
113 class CodeGenRegisterClass {
114 CodeGenRegister::Set Members;
115 // Allocation orders. Order[0] always contains all registers in Members.
116 std::vector<SmallVector<Record*, 16> > Orders;
117 // Bit mask of sub-classes including this, indexed by their EnumValue.
118 BitVector SubClasses;
119 // List of super-classes, topologocally ordered to have the larger classes
120 // first. This is the same as sorting by EnumValue.
121 SmallVector<CodeGenRegisterClass*, 4> SuperClasses;
125 // For a synthesized class, inherit missing properties from the nearest
127 void inheritProperties(CodeGenRegBank&);
129 // Map SubRegIndex -> sub-class. This is the largest sub-class where all
130 // registers have a SubRegIndex sub-register.
131 DenseMap<CodeGenSubRegIndex*, CodeGenRegisterClass*> SubClassWithSubReg;
133 // Map SubRegIndex -> set of super-reg classes. This is all register
134 // classes SuperRC such that:
136 // R:SubRegIndex in this RC for all R in SuperRC.
138 DenseMap<CodeGenSubRegIndex*,
139 SmallPtrSet<CodeGenRegisterClass*, 8> > SuperRegClasses;
142 std::string Namespace;
143 std::vector<MVT::SimpleValueType> VTs;
145 unsigned SpillAlignment;
148 // Map SubRegIndex -> RegisterClass
149 DenseMap<Record*,Record*> SubRegClasses;
150 std::string AltOrderSelect;
152 // Return the Record that defined this class, or NULL if the class was
153 // created by TableGen.
154 Record *getDef() const { return TheDef; }
156 const std::string &getName() const { return Name; }
157 std::string getQualifiedName() const;
158 const std::vector<MVT::SimpleValueType> &getValueTypes() const {return VTs;}
159 unsigned getNumValueTypes() const { return VTs.size(); }
161 MVT::SimpleValueType getValueTypeNum(unsigned VTNum) const {
162 if (VTNum < VTs.size())
164 assert(0 && "VTNum greater than number of ValueTypes in RegClass!");
168 // Return true if this this class contains the register.
169 bool contains(const CodeGenRegister*) const;
171 // Returns true if RC is a subclass.
172 // RC is a sub-class of this class if it is a valid replacement for any
173 // instruction operand where a register of this classis required. It must
174 // satisfy these conditions:
176 // 1. All RC registers are also in this.
177 // 2. The RC spill size must not be smaller than our spill size.
178 // 3. RC spill alignment must be compatible with ours.
180 bool hasSubClass(const CodeGenRegisterClass *RC) const {
181 return SubClasses.test(RC->EnumValue);
184 // getSubClassWithSubReg - Returns the largest sub-class where all
185 // registers have a SubIdx sub-register.
186 CodeGenRegisterClass*
187 getSubClassWithSubReg(CodeGenSubRegIndex *SubIdx) const {
188 return SubClassWithSubReg.lookup(SubIdx);
191 void setSubClassWithSubReg(CodeGenSubRegIndex *SubIdx,
192 CodeGenRegisterClass *SubRC) {
193 SubClassWithSubReg[SubIdx] = SubRC;
196 // getSuperRegClasses - Returns a bit vector of all register classes
197 // containing only SubIdx super-registers of this class.
198 void getSuperRegClasses(CodeGenSubRegIndex *SubIdx, BitVector &Out) const;
200 // addSuperRegClass - Add a class containing only SudIdx super-registers.
201 void addSuperRegClass(CodeGenSubRegIndex *SubIdx,
202 CodeGenRegisterClass *SuperRC) {
203 SuperRegClasses[SubIdx].insert(SuperRC);
206 // getSubClasses - Returns a constant BitVector of subclasses indexed by
208 // The SubClasses vector includs an entry for this class.
209 const BitVector &getSubClasses() const { return SubClasses; }
211 // getSuperClasses - Returns a list of super classes ordered by EnumValue.
212 // The array does not include an entry for this class.
213 ArrayRef<CodeGenRegisterClass*> getSuperClasses() const {
217 // Returns an ordered list of class members.
218 // The order of registers is the same as in the .td file.
219 // No = 0 is the default allocation order, No = 1 is the first alternative.
220 ArrayRef<Record*> getOrder(unsigned No = 0) const {
224 // Return the total number of allocation orders available.
225 unsigned getNumOrders() const { return Orders.size(); }
227 // Get the set of registers. This set contains the same registers as
229 const CodeGenRegister::Set &getMembers() const { return Members; }
231 CodeGenRegisterClass(CodeGenRegBank&, Record *R);
233 // A key representing the parts of a register class used for forming
234 // sub-classes. Note the ordering provided by this key is not the same as
235 // the topological order used for the EnumValues.
237 const CodeGenRegister::Set *Members;
239 unsigned SpillAlignment;
242 : Members(O.Members),
243 SpillSize(O.SpillSize),
244 SpillAlignment(O.SpillAlignment) {}
246 Key(const CodeGenRegister::Set *M, unsigned S = 0, unsigned A = 0)
247 : Members(M), SpillSize(S), SpillAlignment(A) {}
249 Key(const CodeGenRegisterClass &RC)
250 : Members(&RC.getMembers()),
251 SpillSize(RC.SpillSize),
252 SpillAlignment(RC.SpillAlignment) {}
254 // Lexicographical order of (Members, SpillSize, SpillAlignment).
255 bool operator<(const Key&) const;
258 // Create a non-user defined register class.
259 CodeGenRegisterClass(StringRef Name, Key Props);
261 // Called by CodeGenRegBank::CodeGenRegBank().
262 static void computeSubClasses(CodeGenRegBank&);
265 // CodeGenRegBank - Represent a target's registers and the relations between
267 class CodeGenRegBank {
268 RecordKeeper &Records;
272 std::vector<CodeGenSubRegIndex*> SubRegIndices;
273 DenseMap<Record*, CodeGenSubRegIndex*> Def2SubRegIdx;
274 unsigned NumNamedIndices;
277 std::vector<CodeGenRegister*> Registers;
278 DenseMap<Record*, CodeGenRegister*> Def2Reg;
281 std::vector<CodeGenRegisterClass*> RegClasses;
282 DenseMap<Record*, CodeGenRegisterClass*> Def2RC;
283 typedef std::map<CodeGenRegisterClass::Key, CodeGenRegisterClass*> RCKeyMap;
286 // Add RC to *2RC maps.
287 void addToMaps(CodeGenRegisterClass*);
289 // Create a synthetic sub-class if it is missing.
290 CodeGenRegisterClass *getOrCreateSubClass(const CodeGenRegisterClass *RC,
291 const CodeGenRegister::Set *Membs,
294 // Infer missing register classes.
295 void computeInferredRegisterClasses();
296 void inferCommonSubClass(CodeGenRegisterClass *RC);
297 void inferSubClassWithSubReg(CodeGenRegisterClass *RC);
298 void inferMatchingSuperRegClass(CodeGenRegisterClass *RC,
299 unsigned FirstSubRegRC = 0);
301 // Composite SubRegIndex instances.
302 // Map (SubRegIndex, SubRegIndex) -> SubRegIndex.
303 typedef DenseMap<std::pair<CodeGenSubRegIndex*, CodeGenSubRegIndex*>,
304 CodeGenSubRegIndex*> CompositeMap;
305 CompositeMap Composite;
307 // Populate the Composite map from sub-register relationships.
308 void computeComposites();
311 CodeGenRegBank(RecordKeeper&);
313 SetTheory &getSets() { return Sets; }
315 // Sub-register indices. The first NumNamedIndices are defined by the user
316 // in the .td files. The rest are synthesized such that all sub-registers
317 // have a unique name.
318 ArrayRef<CodeGenSubRegIndex*> getSubRegIndices() { return SubRegIndices; }
319 unsigned getNumNamedIndices() { return NumNamedIndices; }
321 // Find a SubRegIndex form its Record def.
322 CodeGenSubRegIndex *getSubRegIdx(Record*);
324 // Find or create a sub-register index representing the A+B composition.
325 CodeGenSubRegIndex *getCompositeSubRegIndex(CodeGenSubRegIndex *A,
326 CodeGenSubRegIndex *B,
327 bool create = false);
329 const std::vector<CodeGenRegister*> &getRegisters() { return Registers; }
331 // Find a register from its Record def.
332 CodeGenRegister *getReg(Record*);
334 ArrayRef<CodeGenRegisterClass*> getRegClasses() const {
338 // Find a register class from its def.
339 CodeGenRegisterClass *getRegClass(Record*);
341 /// getRegisterClassForRegister - Find the register class that contains the
342 /// specified physical register. If the register is not in a register
343 /// class, return null. If the register is in multiple classes, and the
344 /// classes have a superset-subset relationship and the same set of types,
345 /// return the superclass. Otherwise return null.
346 const CodeGenRegisterClass* getRegClassForRegister(Record *R);
348 // Computed derived records such as missing sub-register indices.
349 void computeDerivedInfo();
351 // Compute full overlap sets for every register. These sets include the
352 // rarely used aliases that are neither sub nor super-registers.
354 // Map[R1].count(R2) is reflexive and symmetric, but not transitive.
356 // If R1 is a sub-register of R2, Map[R1] is a subset of Map[R2].
357 void computeOverlaps(std::map<const CodeGenRegister*,
358 CodeGenRegister::Set> &Map);
360 // Compute the set of registers completely covered by the registers in Regs.
361 // The returned BitVector will have a bit set for each register in Regs,
362 // all sub-registers, and all super-registers that are covered by the
363 // registers in Regs.
365 // This is used to compute the mask of call-preserved registers from a list
367 BitVector computeCoveredRegisters(ArrayRef<Record*> Regs);