1 //===- CodeGenRegisters.h - Register and RegisterClass Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines structures to encapsulate information gleaned from the
11 // target register and register class definitions.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_UTILS_TABLEGEN_CODEGENREGISTERS_H
16 #define LLVM_UTILS_TABLEGEN_CODEGENREGISTERS_H
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/ADT/DenseMap.h"
21 #include "llvm/ADT/SetVector.h"
22 #include "llvm/CodeGen/MachineValueType.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/TableGen/Record.h"
25 #include "llvm/TableGen/SetTheory.h"
37 /// Used to encode a step in a register lane mask transformation.
38 /// Mask the bits specified in Mask, then rotate them Rol bits to the left
39 /// assuming a wraparound at 32bits.
43 bool operator==(const MaskRolPair Other) {
44 return Mask == Other.Mask && RotateLeft == Other.RotateLeft;
46 bool operator!=(const MaskRolPair Other) {
47 return Mask != Other.Mask || RotateLeft != Other.RotateLeft;
51 /// CodeGenSubRegIndex - Represents a sub-register index.
52 class CodeGenSubRegIndex {
55 std::string Namespace;
60 const unsigned EnumValue;
61 mutable unsigned LaneMask;
62 mutable SmallVector<MaskRolPair,1> CompositionLaneMaskTransform;
64 // Are all super-registers containing this SubRegIndex covered by their
66 bool AllSuperRegsCovered;
68 CodeGenSubRegIndex(Record *R, unsigned Enum);
69 CodeGenSubRegIndex(StringRef N, StringRef Nspace, unsigned Enum);
71 const std::string &getName() const { return Name; }
72 const std::string &getNamespace() const { return Namespace; }
73 std::string getQualifiedName() const;
75 // Order CodeGenSubRegIndex pointers by EnumValue.
77 bool operator()(const CodeGenSubRegIndex *A,
78 const CodeGenSubRegIndex *B) const {
80 return A->EnumValue < B->EnumValue;
84 // Map of composite subreg indices.
85 typedef std::map<CodeGenSubRegIndex*, CodeGenSubRegIndex*, Less> CompMap;
87 // Returns the subreg index that results from composing this with Idx.
88 // Returns NULL if this and Idx don't compose.
89 CodeGenSubRegIndex *compose(CodeGenSubRegIndex *Idx) const {
90 CompMap::const_iterator I = Composed.find(Idx);
91 return I == Composed.end() ? nullptr : I->second;
94 // Add a composite subreg index: this+A = B.
95 // Return a conflicting composite, or NULL
96 CodeGenSubRegIndex *addComposite(CodeGenSubRegIndex *A,
97 CodeGenSubRegIndex *B) {
99 std::pair<CompMap::iterator, bool> Ins =
100 Composed.insert(std::make_pair(A, B));
101 // Synthetic subreg indices that aren't contiguous (for instance ARM
102 // register tuples) don't have a bit range, so it's OK to let
103 // B->Offset == -1. For the other cases, accumulate the offset and set
104 // the size here. Only do so if there is no offset yet though.
105 if ((Offset != (uint16_t)-1 && A->Offset != (uint16_t)-1) &&
106 (B->Offset == (uint16_t)-1)) {
107 B->Offset = Offset + A->Offset;
110 return (Ins.second || Ins.first->second == B) ? nullptr
114 // Update the composite maps of components specified in 'ComposedOf'.
115 void updateComponents(CodeGenRegBank&);
117 // Return the map of composites.
118 const CompMap &getComposites() const { return Composed; }
120 // Compute LaneMask from Composed. Return LaneMask.
121 unsigned computeLaneMask() const;
127 /// CodeGenRegister - Represents a register definition.
128 struct CodeGenRegister {
132 bool CoveredBySubRegs;
134 // Map SubRegIndex -> Register.
135 typedef std::map<CodeGenSubRegIndex*, CodeGenRegister*,
136 CodeGenSubRegIndex::Less> SubRegMap;
138 CodeGenRegister(Record *R, unsigned Enum);
140 const std::string &getName() const;
142 // Extract more information from TheDef. This is used to build an object
143 // graph after all CodeGenRegister objects have been created.
144 void buildObjectGraph(CodeGenRegBank&);
146 // Lazily compute a map of all sub-registers.
147 // This includes unique entries for all sub-sub-registers.
148 const SubRegMap &computeSubRegs(CodeGenRegBank&);
150 // Compute extra sub-registers by combining the existing sub-registers.
151 void computeSecondarySubRegs(CodeGenRegBank&);
153 // Add this as a super-register to all sub-registers after the sub-register
154 // graph has been built.
155 void computeSuperRegs(CodeGenRegBank&);
157 const SubRegMap &getSubRegs() const {
158 assert(SubRegsComplete && "Must precompute sub-registers");
162 // Add sub-registers to OSet following a pre-order defined by the .td file.
163 void addSubRegsPreOrder(SetVector<const CodeGenRegister*> &OSet,
164 CodeGenRegBank&) const;
166 // Return the sub-register index naming Reg as a sub-register of this
167 // register. Returns NULL if Reg is not a sub-register.
168 CodeGenSubRegIndex *getSubRegIndex(const CodeGenRegister *Reg) const {
169 return SubReg2Idx.lookup(Reg);
172 typedef std::vector<const CodeGenRegister*> SuperRegList;
174 // Get the list of super-registers in topological order, small to large.
175 // This is valid after computeSubRegs visits all registers during RegBank
177 const SuperRegList &getSuperRegs() const {
178 assert(SubRegsComplete && "Must precompute sub-registers");
182 // Get the list of ad hoc aliases. The graph is symmetric, so the list
183 // contains all registers in 'Aliases', and all registers that mention this
184 // register in 'Aliases'.
185 ArrayRef<CodeGenRegister*> getExplicitAliases() const {
186 return ExplicitAliases;
189 // Get the topological signature of this register. This is a small integer
190 // less than RegBank.getNumTopoSigs(). Registers with the same TopoSig have
191 // identical sub-register structure. That is, they support the same set of
192 // sub-register indices mapping to the same kind of sub-registers
194 unsigned getTopoSig() const {
195 assert(SuperRegsComplete && "TopoSigs haven't been computed yet.");
199 // List of register units in ascending order.
200 typedef SmallVector<unsigned, 16> RegUnitList;
201 typedef SmallVector<unsigned, 16> RegUnitLaneMaskList;
203 // How many entries in RegUnitList are native?
204 unsigned NumNativeRegUnits;
206 // Get the list of register units.
207 // This is only valid after computeSubRegs() completes.
208 const RegUnitList &getRegUnits() const { return RegUnits; }
210 ArrayRef<unsigned> getRegUnitLaneMasks() const {
211 return makeArrayRef(RegUnitLaneMasks).slice(0, NumNativeRegUnits);
214 // Get the native register units. This is a prefix of getRegUnits().
215 ArrayRef<unsigned> getNativeRegUnits() const {
216 return makeArrayRef(RegUnits).slice(0, NumNativeRegUnits);
219 void setRegUnitLaneMasks(const RegUnitLaneMaskList &LaneMasks) {
220 RegUnitLaneMasks = LaneMasks;
223 // Inherit register units from subregisters.
224 // Return true if the RegUnits changed.
225 bool inheritRegUnits(CodeGenRegBank &RegBank);
227 // Adopt a register unit for pressure tracking.
228 // A unit is adopted iff its unit number is >= NumNativeRegUnits.
229 void adoptRegUnit(unsigned RUID) { RegUnits.push_back(RUID); }
231 // Get the sum of this register's register unit weights.
232 unsigned getWeight(const CodeGenRegBank &RegBank) const;
234 // Order CodeGenRegister pointers by EnumValue.
236 bool operator()(const CodeGenRegister *A,
237 const CodeGenRegister *B) const {
239 return A->EnumValue < B->EnumValue;
243 // Canonically ordered set.
244 typedef std::set<const CodeGenRegister*, Less> Set;
247 bool SubRegsComplete;
248 bool SuperRegsComplete;
251 // The sub-registers explicit in the .td file form a tree.
252 SmallVector<CodeGenSubRegIndex*, 8> ExplicitSubRegIndices;
253 SmallVector<CodeGenRegister*, 8> ExplicitSubRegs;
255 // Explicit ad hoc aliases, symmetrized to form an undirected graph.
256 SmallVector<CodeGenRegister*, 8> ExplicitAliases;
258 // Super-registers where this is the first explicit sub-register.
259 SuperRegList LeadingSuperRegs;
262 SuperRegList SuperRegs;
263 DenseMap<const CodeGenRegister*, CodeGenSubRegIndex*> SubReg2Idx;
264 RegUnitList RegUnits;
265 RegUnitLaneMaskList RegUnitLaneMasks;
269 class CodeGenRegisterClass {
270 CodeGenRegister::Set Members;
271 // Allocation orders. Order[0] always contains all registers in Members.
272 std::vector<SmallVector<Record*, 16> > Orders;
273 // Bit mask of sub-classes including this, indexed by their EnumValue.
274 BitVector SubClasses;
275 // List of super-classes, topologocally ordered to have the larger classes
276 // first. This is the same as sorting by EnumValue.
277 SmallVector<CodeGenRegisterClass*, 4> SuperClasses;
281 // For a synthesized class, inherit missing properties from the nearest
283 void inheritProperties(CodeGenRegBank&);
285 // Map SubRegIndex -> sub-class. This is the largest sub-class where all
286 // registers have a SubRegIndex sub-register.
287 DenseMap<const CodeGenSubRegIndex *, CodeGenRegisterClass *>
290 // Map SubRegIndex -> set of super-reg classes. This is all register
291 // classes SuperRC such that:
293 // R:SubRegIndex in this RC for all R in SuperRC.
295 DenseMap<const CodeGenSubRegIndex *, SmallPtrSet<CodeGenRegisterClass *, 8>>
298 // Bit vector of TopoSigs for the registers in this class. This will be
299 // very sparse on regular architectures.
304 std::string Namespace;
305 SmallVector<MVT::SimpleValueType, 4> VTs;
307 unsigned SpillAlignment;
310 std::string AltOrderSelect;
311 /// Contains the combination of the lane masks of all subregisters.
314 // Return the Record that defined this class, or NULL if the class was
315 // created by TableGen.
316 Record *getDef() const { return TheDef; }
318 const std::string &getName() const { return Name; }
319 std::string getQualifiedName() const;
320 ArrayRef<MVT::SimpleValueType> getValueTypes() const {return VTs;}
321 unsigned getNumValueTypes() const { return VTs.size(); }
323 MVT::SimpleValueType getValueTypeNum(unsigned VTNum) const {
324 if (VTNum < VTs.size())
326 llvm_unreachable("VTNum greater than number of ValueTypes in RegClass!");
329 // Return true if this this class contains the register.
330 bool contains(const CodeGenRegister*) const;
332 // Returns true if RC is a subclass.
333 // RC is a sub-class of this class if it is a valid replacement for any
334 // instruction operand where a register of this classis required. It must
335 // satisfy these conditions:
337 // 1. All RC registers are also in this.
338 // 2. The RC spill size must not be smaller than our spill size.
339 // 3. RC spill alignment must be compatible with ours.
341 bool hasSubClass(const CodeGenRegisterClass *RC) const {
342 return SubClasses.test(RC->EnumValue);
345 // getSubClassWithSubReg - Returns the largest sub-class where all
346 // registers have a SubIdx sub-register.
347 CodeGenRegisterClass *
348 getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const {
349 return SubClassWithSubReg.lookup(SubIdx);
352 void setSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx,
353 CodeGenRegisterClass *SubRC) {
354 SubClassWithSubReg[SubIdx] = SubRC;
357 // getSuperRegClasses - Returns a bit vector of all register classes
358 // containing only SubIdx super-registers of this class.
359 void getSuperRegClasses(const CodeGenSubRegIndex *SubIdx,
360 BitVector &Out) const;
362 // addSuperRegClass - Add a class containing only SudIdx super-registers.
363 void addSuperRegClass(CodeGenSubRegIndex *SubIdx,
364 CodeGenRegisterClass *SuperRC) {
365 SuperRegClasses[SubIdx].insert(SuperRC);
368 // getSubClasses - Returns a constant BitVector of subclasses indexed by
370 // The SubClasses vector includes an entry for this class.
371 const BitVector &getSubClasses() const { return SubClasses; }
373 // getSuperClasses - Returns a list of super classes ordered by EnumValue.
374 // The array does not include an entry for this class.
375 ArrayRef<CodeGenRegisterClass*> getSuperClasses() const {
379 // Returns an ordered list of class members.
380 // The order of registers is the same as in the .td file.
381 // No = 0 is the default allocation order, No = 1 is the first alternative.
382 ArrayRef<Record*> getOrder(unsigned No = 0) const {
386 // Return the total number of allocation orders available.
387 unsigned getNumOrders() const { return Orders.size(); }
389 // Get the set of registers. This set contains the same registers as
391 const CodeGenRegister::Set &getMembers() const { return Members; }
393 // Get a bit vector of TopoSigs present in this register class.
394 const BitVector &getTopoSigs() const { return TopoSigs; }
396 // Populate a unique sorted list of units from a register set.
397 void buildRegUnitSet(std::vector<unsigned> &RegUnits) const;
399 CodeGenRegisterClass(CodeGenRegBank&, Record *R);
401 // A key representing the parts of a register class used for forming
402 // sub-classes. Note the ordering provided by this key is not the same as
403 // the topological order used for the EnumValues.
405 const CodeGenRegister::Set *Members;
407 unsigned SpillAlignment;
409 Key(const CodeGenRegister::Set *M, unsigned S = 0, unsigned A = 0)
410 : Members(M), SpillSize(S), SpillAlignment(A) {}
412 Key(const CodeGenRegisterClass &RC)
413 : Members(&RC.getMembers()),
414 SpillSize(RC.SpillSize),
415 SpillAlignment(RC.SpillAlignment) {}
417 // Lexicographical order of (Members, SpillSize, SpillAlignment).
418 bool operator<(const Key&) const;
421 // Create a non-user defined register class.
422 CodeGenRegisterClass(CodeGenRegBank&, StringRef Name, Key Props);
424 // Called by CodeGenRegBank::CodeGenRegBank().
425 static void computeSubClasses(CodeGenRegBank&);
428 // Register units are used to model interference and register pressure.
429 // Every register is assigned one or more register units such that two
430 // registers overlap if and only if they have a register unit in common.
432 // Normally, one register unit is created per leaf register. Non-leaf
433 // registers inherit the units of their sub-registers.
435 // Weight assigned to this RegUnit for estimating register pressure.
436 // This is useful when equalizing weights in register classes with mixed
437 // register topologies.
440 // Each native RegUnit corresponds to one or two root registers. The full
441 // set of registers containing this unit can be computed as the union of
442 // these two registers and their super-registers.
443 const CodeGenRegister *Roots[2];
445 // Index into RegClassUnitSets where we can find the list of UnitSets that
446 // contain this unit.
447 unsigned RegClassUnitSetsIdx;
449 RegUnit() : Weight(0), RegClassUnitSetsIdx(0) {
450 Roots[0] = Roots[1] = nullptr;
453 ArrayRef<const CodeGenRegister*> getRoots() const {
454 assert(!(Roots[1] && !Roots[0]) && "Invalid roots array");
455 return makeArrayRef(Roots, !!Roots[0] + !!Roots[1]);
459 // Each RegUnitSet is a sorted vector with a name.
461 typedef std::vector<unsigned>::const_iterator iterator;
464 std::vector<unsigned> Units;
465 unsigned Weight; // Cache the sum of all unit weights.
466 unsigned Order; // Cache the sort key.
468 RegUnitSet() : Weight(0), Order(0) {}
471 // Base vector for identifying TopoSigs. The contents uniquely identify a
472 // TopoSig, only computeSuperRegs needs to know how.
473 typedef SmallVector<unsigned, 16> TopoSigId;
475 // CodeGenRegBank - Represent a target's registers and the relations between
477 class CodeGenRegBank {
480 std::deque<CodeGenSubRegIndex> SubRegIndices;
481 DenseMap<Record*, CodeGenSubRegIndex*> Def2SubRegIdx;
483 CodeGenSubRegIndex *createSubRegIndex(StringRef Name, StringRef NameSpace);
485 typedef std::map<SmallVector<CodeGenSubRegIndex*, 8>,
486 CodeGenSubRegIndex*> ConcatIdxMap;
487 ConcatIdxMap ConcatIdx;
490 std::deque<CodeGenRegister> Registers;
491 StringMap<CodeGenRegister*> RegistersByName;
492 DenseMap<Record*, CodeGenRegister*> Def2Reg;
493 unsigned NumNativeRegUnits;
495 std::map<TopoSigId, unsigned> TopoSigs;
497 // Includes native (0..NumNativeRegUnits-1) and adopted register units.
498 SmallVector<RegUnit, 8> RegUnits;
501 std::list<CodeGenRegisterClass> RegClasses;
502 DenseMap<Record*, CodeGenRegisterClass*> Def2RC;
503 typedef std::map<CodeGenRegisterClass::Key, CodeGenRegisterClass*> RCKeyMap;
506 // Remember each unique set of register units. Initially, this contains a
507 // unique set for each register class. Simliar sets are coalesced with
508 // pruneUnitSets and new supersets are inferred during computeRegUnitSets.
509 std::vector<RegUnitSet> RegUnitSets;
511 // Map RegisterClass index to the index of the RegUnitSet that contains the
512 // class's units and any inferred RegUnit supersets.
514 // NOTE: This could grow beyond the number of register classes when we map
515 // register units to lists of unit sets. If the list of unit sets does not
516 // already exist for a register class, we create a new entry in this vector.
517 std::vector<std::vector<unsigned> > RegClassUnitSets;
519 // Give each register unit set an order based on sorting criteria.
520 std::vector<unsigned> RegUnitSetOrder;
522 // Add RC to *2RC maps.
523 void addToMaps(CodeGenRegisterClass*);
525 // Create a synthetic sub-class if it is missing.
526 CodeGenRegisterClass *getOrCreateSubClass(const CodeGenRegisterClass *RC,
527 const CodeGenRegister::Set *Membs,
530 // Infer missing register classes.
531 void computeInferredRegisterClasses();
532 void inferCommonSubClass(CodeGenRegisterClass *RC);
533 void inferSubClassWithSubReg(CodeGenRegisterClass *RC);
534 void inferMatchingSuperRegClass(CodeGenRegisterClass *RC) {
535 inferMatchingSuperRegClass(RC, RegClasses.begin());
538 void inferMatchingSuperRegClass(
539 CodeGenRegisterClass *RC,
540 std::list<CodeGenRegisterClass>::iterator FirstSubRegRC);
542 // Iteratively prune unit sets.
543 void pruneUnitSets();
545 // Compute a weight for each register unit created during getSubRegs.
546 void computeRegUnitWeights();
548 // Create a RegUnitSet for each RegClass and infer superclasses.
549 void computeRegUnitSets();
551 // Populate the Composite map from sub-register relationships.
552 void computeComposites();
554 // Compute a lane mask for each sub-register index.
555 void computeSubRegLaneMasks();
557 /// Computes a lane mask for each register unit enumerated by a physical
559 void computeRegUnitLaneMasks();
562 CodeGenRegBank(RecordKeeper&);
564 SetTheory &getSets() { return Sets; }
566 // Sub-register indices. The first NumNamedIndices are defined by the user
567 // in the .td files. The rest are synthesized such that all sub-registers
568 // have a unique name.
569 const std::deque<CodeGenSubRegIndex> &getSubRegIndices() const {
570 return SubRegIndices;
573 // Find a SubRegIndex form its Record def.
574 CodeGenSubRegIndex *getSubRegIdx(Record*);
576 // Find or create a sub-register index representing the A+B composition.
577 CodeGenSubRegIndex *getCompositeSubRegIndex(CodeGenSubRegIndex *A,
578 CodeGenSubRegIndex *B);
580 // Find or create a sub-register index representing the concatenation of
581 // non-overlapping sibling indices.
583 getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex *, 8>&);
586 addConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex *, 8> &Parts,
587 CodeGenSubRegIndex *Idx) {
588 ConcatIdx.insert(std::make_pair(Parts, Idx));
591 const std::deque<CodeGenRegister> &getRegisters() { return Registers; }
592 const StringMap<CodeGenRegister*> &getRegistersByName() {
593 return RegistersByName;
596 // Find a register from its Record def.
597 CodeGenRegister *getReg(Record*);
599 // Get a Register's index into the Registers array.
600 unsigned getRegIndex(const CodeGenRegister *Reg) const {
601 return Reg->EnumValue - 1;
604 // Return the number of allocated TopoSigs. The first TopoSig representing
605 // leaf registers is allocated number 0.
606 unsigned getNumTopoSigs() const {
607 return TopoSigs.size();
610 // Find or create a TopoSig for the given TopoSigId.
611 // This function is only for use by CodeGenRegister::computeSuperRegs().
612 // Others should simply use Reg->getTopoSig().
613 unsigned getTopoSig(const TopoSigId &Id) {
614 return TopoSigs.insert(std::make_pair(Id, TopoSigs.size())).first->second;
617 // Create a native register unit that is associated with one or two root
619 unsigned newRegUnit(CodeGenRegister *R0, CodeGenRegister *R1 = nullptr) {
620 RegUnits.resize(RegUnits.size() + 1);
621 RegUnits.back().Roots[0] = R0;
622 RegUnits.back().Roots[1] = R1;
623 return RegUnits.size() - 1;
626 // Create a new non-native register unit that can be adopted by a register
627 // to increase its pressure. Note that NumNativeRegUnits is not increased.
628 unsigned newRegUnit(unsigned Weight) {
629 RegUnits.resize(RegUnits.size() + 1);
630 RegUnits.back().Weight = Weight;
631 return RegUnits.size() - 1;
634 // Native units are the singular unit of a leaf register. Register aliasing
635 // is completely characterized by native units. Adopted units exist to give
636 // register additional weight but don't affect aliasing.
637 bool isNativeUnit(unsigned RUID) {
638 return RUID < NumNativeRegUnits;
641 unsigned getNumNativeRegUnits() const {
642 return NumNativeRegUnits;
645 RegUnit &getRegUnit(unsigned RUID) { return RegUnits[RUID]; }
646 const RegUnit &getRegUnit(unsigned RUID) const { return RegUnits[RUID]; }
648 std::list<CodeGenRegisterClass> &getRegClasses() { return RegClasses; }
650 const std::list<CodeGenRegisterClass> &getRegClasses() const {
654 // Find a register class from its def.
655 CodeGenRegisterClass *getRegClass(Record*);
657 /// getRegisterClassForRegister - Find the register class that contains the
658 /// specified physical register. If the register is not in a register
659 /// class, return null. If the register is in multiple classes, and the
660 /// classes have a superset-subset relationship and the same set of types,
661 /// return the superclass. Otherwise return null.
662 const CodeGenRegisterClass* getRegClassForRegister(Record *R);
664 // Get the sum of unit weights.
665 unsigned getRegUnitSetWeight(const std::vector<unsigned> &Units) const {
667 for (std::vector<unsigned>::const_iterator
668 I = Units.begin(), E = Units.end(); I != E; ++I)
669 Weight += getRegUnit(*I).Weight;
673 unsigned getRegSetIDAt(unsigned Order) const {
674 return RegUnitSetOrder[Order];
676 const RegUnitSet &getRegSetAt(unsigned Order) const {
677 return RegUnitSets[RegUnitSetOrder[Order]];
680 // Increase a RegUnitWeight.
681 void increaseRegUnitWeight(unsigned RUID, unsigned Inc) {
682 getRegUnit(RUID).Weight += Inc;
685 // Get the number of register pressure dimensions.
686 unsigned getNumRegPressureSets() const { return RegUnitSets.size(); }
688 // Get a set of register unit IDs for a given dimension of pressure.
689 const RegUnitSet &getRegPressureSet(unsigned Idx) const {
690 return RegUnitSets[Idx];
693 // The number of pressure set lists may be larget than the number of
694 // register classes if some register units appeared in a list of sets that
695 // did not correspond to an existing register class.
696 unsigned getNumRegClassPressureSetLists() const {
697 return RegClassUnitSets.size();
700 // Get a list of pressure set IDs for a register class. Liveness of a
701 // register in this class impacts each pressure set in this list by the
702 // weight of the register. An exact solution requires all registers in a
703 // class to have the same class, but it is not strictly guaranteed.
704 ArrayRef<unsigned> getRCPressureSetIDs(unsigned RCIdx) const {
705 return RegClassUnitSets[RCIdx];
708 // Computed derived records such as missing sub-register indices.
709 void computeDerivedInfo();
711 // Compute the set of registers completely covered by the registers in Regs.
712 // The returned BitVector will have a bit set for each register in Regs,
713 // all sub-registers, and all super-registers that are covered by the
714 // registers in Regs.
716 // This is used to compute the mask of call-preserved registers from a list
718 BitVector computeCoveredRegisters(ArrayRef<Record*> Regs);
720 // Bit mask of lanes that cover their registers. A sub-register index whose
721 // LaneMask is contained in CoveringLanes will be completely covered by
722 // another sub-register with the same or larger lane mask.
723 unsigned CoveringLanes;