1 //===- CodeGenRegisters.h - Register and RegisterClass Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines structures to encapsulate information gleaned from the
11 // target register and register class definitions.
13 //===----------------------------------------------------------------------===//
15 #ifndef CODEGEN_REGISTERS_H
16 #define CODEGEN_REGISTERS_H
19 #include "SetTheory.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/ADT/ArrayRef.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/DenseMap.h"
24 #include "llvm/ADT/SetVector.h"
34 /// CodeGenRegister - Represents a register definition.
35 struct CodeGenRegister {
40 // Map SubRegIndex -> Register.
41 typedef std::map<Record*, CodeGenRegister*, LessRecord> SubRegMap;
43 CodeGenRegister(Record *R, unsigned Enum);
45 const std::string &getName() const;
47 // Get a map of sub-registers computed lazily.
48 // This includes unique entries for all sub-sub-registers.
49 const SubRegMap &getSubRegs(CodeGenRegBank&);
51 const SubRegMap &getSubRegs() const {
52 assert(SubRegsComplete && "Must precompute sub-registers");
56 // Add sub-registers to OSet following a pre-order defined by the .td file.
57 void addSubRegsPreOrder(SetVector<CodeGenRegister*> &OSet) const;
59 // List of super-registers in topological order, small to large.
60 typedef std::vector<CodeGenRegister*> SuperRegList;
62 // Get the list of super-registers.
63 // This is only valid after computeDerivedInfo has visited all registers.
64 const SuperRegList &getSuperRegs() const {
65 assert(SubRegsComplete && "Must precompute sub-registers");
69 // Order CodeGenRegister pointers by EnumValue.
71 bool operator()(const CodeGenRegister *A,
72 const CodeGenRegister *B) const {
73 return A->EnumValue < B->EnumValue;
77 // Canonically ordered set.
78 typedef std::set<const CodeGenRegister*, Less> Set;
83 SuperRegList SuperRegs;
87 class CodeGenRegisterClass {
88 CodeGenRegister::Set Members;
89 const std::vector<Record*> *Elements;
90 std::vector<SmallVector<Record*, 16> > AltOrders;
91 // Bit mask of sub-classes including this, indexed by their EnumValue.
96 std::string Namespace;
97 std::vector<MVT::SimpleValueType> VTs;
99 unsigned SpillAlignment;
102 // Map SubRegIndex -> RegisterClass
103 DenseMap<Record*,Record*> SubRegClasses;
104 std::string AltOrderSelect;
106 const std::string &getName() const;
107 const std::vector<MVT::SimpleValueType> &getValueTypes() const {return VTs;}
108 unsigned getNumValueTypes() const { return VTs.size(); }
110 MVT::SimpleValueType getValueTypeNum(unsigned VTNum) const {
111 if (VTNum < VTs.size())
113 assert(0 && "VTNum greater than number of ValueTypes in RegClass!");
117 // Return true if this this class contains the register.
118 bool contains(const CodeGenRegister*) const;
120 // Returns true if RC is a subclass.
121 // RC is a sub-class of this class if it is a valid replacement for any
122 // instruction operand where a register of this classis required. It must
123 // satisfy these conditions:
125 // 1. All RC registers are also in this.
126 // 2. The RC spill size must not be smaller than our spill size.
127 // 3. RC spill alignment must be compatible with ours.
129 bool hasSubClass(const CodeGenRegisterClass *RC) const;
131 // Returns an ordered list of class members.
132 // The order of registers is the same as in the .td file.
133 // No = 0 is the default allocation order, No = 1 is the first alternative.
134 ArrayRef<Record*> getOrder(unsigned No = 0) const {
138 return AltOrders[No - 1];
141 // Return the total number of allocation orders available.
142 unsigned getNumOrders() const { return 1 + AltOrders.size(); }
144 CodeGenRegisterClass(CodeGenRegBank&, Record *R);
146 // Called by CodeGenRegBank::CodeGenRegBank().
147 static void computeSubClasses(ArrayRef<CodeGenRegisterClass*>);
150 // CodeGenRegBank - Represent a target's registers and the relations between
152 class CodeGenRegBank {
153 RecordKeeper &Records;
156 std::vector<Record*> SubRegIndices;
157 unsigned NumNamedIndices;
158 std::vector<CodeGenRegister*> Registers;
159 DenseMap<Record*, CodeGenRegister*> Def2Reg;
161 std::vector<CodeGenRegisterClass*> RegClasses;
162 DenseMap<Record*, CodeGenRegisterClass*> Def2RC;
164 // Composite SubRegIndex instances.
165 // Map (SubRegIndex, SubRegIndex) -> SubRegIndex.
166 typedef DenseMap<std::pair<Record*, Record*>, Record*> CompositeMap;
167 CompositeMap Composite;
169 // Populate the Composite map from sub-register relationships.
170 void computeComposites();
173 CodeGenRegBank(RecordKeeper&);
175 SetTheory &getSets() { return Sets; }
177 // Sub-register indices. The first NumNamedIndices are defined by the user
178 // in the .td files. The rest are synthesized such that all sub-registers
179 // have a unique name.
180 const std::vector<Record*> &getSubRegIndices() { return SubRegIndices; }
181 unsigned getNumNamedIndices() { return NumNamedIndices; }
183 // Map a SubRegIndex Record to its enum value.
184 unsigned getSubRegIndexNo(Record *idx);
186 // Find or create a sub-register index representing the A+B composition.
187 Record *getCompositeSubRegIndex(Record *A, Record *B, bool create = false);
189 const std::vector<CodeGenRegister*> &getRegisters() { return Registers; }
191 // Find a register from its Record def.
192 CodeGenRegister *getReg(Record*);
194 ArrayRef<CodeGenRegisterClass*> getRegClasses() const {
198 // Find a register class from its def.
199 CodeGenRegisterClass *getRegClass(Record*);
201 /// getRegisterClassForRegister - Find the register class that contains the
202 /// specified physical register. If the register is not in a register
203 /// class, return null. If the register is in multiple classes, and the
204 /// classes have a superset-subset relationship and the same set of types,
205 /// return the superclass. Otherwise return null.
206 const CodeGenRegisterClass* getRegClassForRegister(Record *R);
208 // Computed derived records such as missing sub-register indices.
209 void computeDerivedInfo();
211 // Compute full overlap sets for every register. These sets include the
212 // rarely used aliases that are neither sub nor super-registers.
214 // Map[R1].count(R2) is reflexive and symmetric, but not transitive.
216 // If R1 is a sub-register of R2, Map[R1] is a subset of Map[R2].
217 void computeOverlaps(std::map<const CodeGenRegister*,
218 CodeGenRegister::Set> &Map);