1 //===- CodeGenRegisters.h - Register and RegisterClass Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines structures to encapsulate information gleaned from the
11 // target register and register class definitions.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_UTILS_TABLEGEN_CODEGENREGISTERS_H
16 #define LLVM_UTILS_TABLEGEN_CODEGENREGISTERS_H
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/ADT/DenseMap.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/SetVector.h"
23 #include "llvm/ADT/SparseBitVector.h"
24 #include "llvm/CodeGen/MachineValueType.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/TableGen/Record.h"
27 #include "llvm/TableGen/SetTheory.h"
39 /// Used to encode a step in a register lane mask transformation.
40 /// Mask the bits specified in Mask, then rotate them Rol bits to the left
41 /// assuming a wraparound at 32bits.
45 bool operator==(const MaskRolPair Other) const {
46 return Mask == Other.Mask && RotateLeft == Other.RotateLeft;
48 bool operator!=(const MaskRolPair Other) const {
49 return Mask != Other.Mask || RotateLeft != Other.RotateLeft;
53 /// CodeGenSubRegIndex - Represents a sub-register index.
54 class CodeGenSubRegIndex {
57 std::string Namespace;
62 const unsigned EnumValue;
63 mutable unsigned LaneMask;
64 mutable SmallVector<MaskRolPair,1> CompositionLaneMaskTransform;
66 // Are all super-registers containing this SubRegIndex covered by their
68 bool AllSuperRegsCovered;
70 CodeGenSubRegIndex(Record *R, unsigned Enum);
71 CodeGenSubRegIndex(StringRef N, StringRef Nspace, unsigned Enum);
73 const std::string &getName() const { return Name; }
74 const std::string &getNamespace() const { return Namespace; }
75 std::string getQualifiedName() const;
77 // Map of composite subreg indices.
78 typedef std::map<CodeGenSubRegIndex *, CodeGenSubRegIndex *,
79 deref<llvm::less>> CompMap;
81 // Returns the subreg index that results from composing this with Idx.
82 // Returns NULL if this and Idx don't compose.
83 CodeGenSubRegIndex *compose(CodeGenSubRegIndex *Idx) const {
84 CompMap::const_iterator I = Composed.find(Idx);
85 return I == Composed.end() ? nullptr : I->second;
88 // Add a composite subreg index: this+A = B.
89 // Return a conflicting composite, or NULL
90 CodeGenSubRegIndex *addComposite(CodeGenSubRegIndex *A,
91 CodeGenSubRegIndex *B) {
93 std::pair<CompMap::iterator, bool> Ins =
94 Composed.insert(std::make_pair(A, B));
95 // Synthetic subreg indices that aren't contiguous (for instance ARM
96 // register tuples) don't have a bit range, so it's OK to let
97 // B->Offset == -1. For the other cases, accumulate the offset and set
98 // the size here. Only do so if there is no offset yet though.
99 if ((Offset != (uint16_t)-1 && A->Offset != (uint16_t)-1) &&
100 (B->Offset == (uint16_t)-1)) {
101 B->Offset = Offset + A->Offset;
104 return (Ins.second || Ins.first->second == B) ? nullptr
108 // Update the composite maps of components specified in 'ComposedOf'.
109 void updateComponents(CodeGenRegBank&);
111 // Return the map of composites.
112 const CompMap &getComposites() const { return Composed; }
114 // Compute LaneMask from Composed. Return LaneMask.
115 unsigned computeLaneMask() const;
121 inline bool operator<(const CodeGenSubRegIndex &A,
122 const CodeGenSubRegIndex &B) {
123 return A.EnumValue < B.EnumValue;
126 /// CodeGenRegister - Represents a register definition.
127 struct CodeGenRegister {
131 bool CoveredBySubRegs;
133 // Map SubRegIndex -> Register.
134 typedef std::map<CodeGenSubRegIndex *, CodeGenRegister *, deref<llvm::less>>
137 CodeGenRegister(Record *R, unsigned Enum);
139 const std::string &getName() const;
141 // Extract more information from TheDef. This is used to build an object
142 // graph after all CodeGenRegister objects have been created.
143 void buildObjectGraph(CodeGenRegBank&);
145 // Lazily compute a map of all sub-registers.
146 // This includes unique entries for all sub-sub-registers.
147 const SubRegMap &computeSubRegs(CodeGenRegBank&);
149 // Compute extra sub-registers by combining the existing sub-registers.
150 void computeSecondarySubRegs(CodeGenRegBank&);
152 // Add this as a super-register to all sub-registers after the sub-register
153 // graph has been built.
154 void computeSuperRegs(CodeGenRegBank&);
156 const SubRegMap &getSubRegs() const {
157 assert(SubRegsComplete && "Must precompute sub-registers");
161 // Add sub-registers to OSet following a pre-order defined by the .td file.
162 void addSubRegsPreOrder(SetVector<const CodeGenRegister*> &OSet,
163 CodeGenRegBank&) const;
165 // Return the sub-register index naming Reg as a sub-register of this
166 // register. Returns NULL if Reg is not a sub-register.
167 CodeGenSubRegIndex *getSubRegIndex(const CodeGenRegister *Reg) const {
168 return SubReg2Idx.lookup(Reg);
171 typedef std::vector<const CodeGenRegister*> SuperRegList;
173 // Get the list of super-registers in topological order, small to large.
174 // This is valid after computeSubRegs visits all registers during RegBank
176 const SuperRegList &getSuperRegs() const {
177 assert(SubRegsComplete && "Must precompute sub-registers");
181 // Get the list of ad hoc aliases. The graph is symmetric, so the list
182 // contains all registers in 'Aliases', and all registers that mention this
183 // register in 'Aliases'.
184 ArrayRef<CodeGenRegister*> getExplicitAliases() const {
185 return ExplicitAliases;
188 // Get the topological signature of this register. This is a small integer
189 // less than RegBank.getNumTopoSigs(). Registers with the same TopoSig have
190 // identical sub-register structure. That is, they support the same set of
191 // sub-register indices mapping to the same kind of sub-registers
193 unsigned getTopoSig() const {
194 assert(SuperRegsComplete && "TopoSigs haven't been computed yet.");
198 // List of register units in ascending order.
199 typedef SparseBitVector<> RegUnitList;
200 typedef SmallVector<unsigned, 16> RegUnitLaneMaskList;
202 // How many entries in RegUnitList are native?
203 RegUnitList NativeRegUnits;
205 // Get the list of register units.
206 // This is only valid after computeSubRegs() completes.
207 const RegUnitList &getRegUnits() const { return RegUnits; }
209 ArrayRef<unsigned> getRegUnitLaneMasks() const {
210 return makeArrayRef(RegUnitLaneMasks).slice(0, NativeRegUnits.count());
213 // Get the native register units. This is a prefix of getRegUnits().
214 RegUnitList getNativeRegUnits() const {
215 return NativeRegUnits;
218 void setRegUnitLaneMasks(const RegUnitLaneMaskList &LaneMasks) {
219 RegUnitLaneMasks = LaneMasks;
222 // Inherit register units from subregisters.
223 // Return true if the RegUnits changed.
224 bool inheritRegUnits(CodeGenRegBank &RegBank);
226 // Adopt a register unit for pressure tracking.
227 // A unit is adopted iff its unit number is >= NativeRegUnits.count().
228 void adoptRegUnit(unsigned RUID) { RegUnits.set(RUID); }
230 // Get the sum of this register's register unit weights.
231 unsigned getWeight(const CodeGenRegBank &RegBank) const;
233 // Canonically ordered set.
234 typedef std::vector<const CodeGenRegister*> Vec;
237 bool SubRegsComplete;
238 bool SuperRegsComplete;
241 // The sub-registers explicit in the .td file form a tree.
242 SmallVector<CodeGenSubRegIndex*, 8> ExplicitSubRegIndices;
243 SmallVector<CodeGenRegister*, 8> ExplicitSubRegs;
245 // Explicit ad hoc aliases, symmetrized to form an undirected graph.
246 SmallVector<CodeGenRegister*, 8> ExplicitAliases;
248 // Super-registers where this is the first explicit sub-register.
249 SuperRegList LeadingSuperRegs;
252 SuperRegList SuperRegs;
253 DenseMap<const CodeGenRegister*, CodeGenSubRegIndex*> SubReg2Idx;
254 RegUnitList RegUnits;
255 RegUnitLaneMaskList RegUnitLaneMasks;
258 inline bool operator<(const CodeGenRegister &A, const CodeGenRegister &B) {
259 return A.EnumValue < B.EnumValue;
262 inline bool operator==(const CodeGenRegister &A, const CodeGenRegister &B) {
263 return A.EnumValue == B.EnumValue;
266 class CodeGenRegisterClass {
267 CodeGenRegister::Vec Members;
268 // Allocation orders. Order[0] always contains all registers in Members.
269 std::vector<SmallVector<Record*, 16> > Orders;
270 // Bit mask of sub-classes including this, indexed by their EnumValue.
271 BitVector SubClasses;
272 // List of super-classes, topologocally ordered to have the larger classes
273 // first. This is the same as sorting by EnumValue.
274 SmallVector<CodeGenRegisterClass*, 4> SuperClasses;
278 // For a synthesized class, inherit missing properties from the nearest
280 void inheritProperties(CodeGenRegBank&);
282 // Map SubRegIndex -> sub-class. This is the largest sub-class where all
283 // registers have a SubRegIndex sub-register.
284 DenseMap<const CodeGenSubRegIndex *, CodeGenRegisterClass *>
287 // Map SubRegIndex -> set of super-reg classes. This is all register
288 // classes SuperRC such that:
290 // R:SubRegIndex in this RC for all R in SuperRC.
292 DenseMap<const CodeGenSubRegIndex *, SmallPtrSet<CodeGenRegisterClass *, 8>>
295 // Bit vector of TopoSigs for the registers in this class. This will be
296 // very sparse on regular architectures.
301 std::string Namespace;
302 SmallVector<MVT::SimpleValueType, 4> VTs;
304 unsigned SpillAlignment;
307 std::string AltOrderSelect;
308 /// Contains the combination of the lane masks of all subregisters.
311 // Return the Record that defined this class, or NULL if the class was
312 // created by TableGen.
313 Record *getDef() const { return TheDef; }
315 const std::string &getName() const { return Name; }
316 std::string getQualifiedName() const;
317 ArrayRef<MVT::SimpleValueType> getValueTypes() const {return VTs;}
318 unsigned getNumValueTypes() const { return VTs.size(); }
320 MVT::SimpleValueType getValueTypeNum(unsigned VTNum) const {
321 if (VTNum < VTs.size())
323 llvm_unreachable("VTNum greater than number of ValueTypes in RegClass!");
326 // Return true if this this class contains the register.
327 bool contains(const CodeGenRegister*) const;
329 // Returns true if RC is a subclass.
330 // RC is a sub-class of this class if it is a valid replacement for any
331 // instruction operand where a register of this classis required. It must
332 // satisfy these conditions:
334 // 1. All RC registers are also in this.
335 // 2. The RC spill size must not be smaller than our spill size.
336 // 3. RC spill alignment must be compatible with ours.
338 bool hasSubClass(const CodeGenRegisterClass *RC) const {
339 return SubClasses.test(RC->EnumValue);
342 // getSubClassWithSubReg - Returns the largest sub-class where all
343 // registers have a SubIdx sub-register.
344 CodeGenRegisterClass *
345 getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const {
346 return SubClassWithSubReg.lookup(SubIdx);
349 void setSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx,
350 CodeGenRegisterClass *SubRC) {
351 SubClassWithSubReg[SubIdx] = SubRC;
354 // getSuperRegClasses - Returns a bit vector of all register classes
355 // containing only SubIdx super-registers of this class.
356 void getSuperRegClasses(const CodeGenSubRegIndex *SubIdx,
357 BitVector &Out) const;
359 // addSuperRegClass - Add a class containing only SudIdx super-registers.
360 void addSuperRegClass(CodeGenSubRegIndex *SubIdx,
361 CodeGenRegisterClass *SuperRC) {
362 SuperRegClasses[SubIdx].insert(SuperRC);
365 // getSubClasses - Returns a constant BitVector of subclasses indexed by
367 // The SubClasses vector includes an entry for this class.
368 const BitVector &getSubClasses() const { return SubClasses; }
370 // getSuperClasses - Returns a list of super classes ordered by EnumValue.
371 // The array does not include an entry for this class.
372 ArrayRef<CodeGenRegisterClass*> getSuperClasses() const {
376 // Returns an ordered list of class members.
377 // The order of registers is the same as in the .td file.
378 // No = 0 is the default allocation order, No = 1 is the first alternative.
379 ArrayRef<Record*> getOrder(unsigned No = 0) const {
383 // Return the total number of allocation orders available.
384 unsigned getNumOrders() const { return Orders.size(); }
386 // Get the set of registers. This set contains the same registers as
388 const CodeGenRegister::Vec &getMembers() const { return Members; }
390 // Get a bit vector of TopoSigs present in this register class.
391 const BitVector &getTopoSigs() const { return TopoSigs; }
393 // Populate a unique sorted list of units from a register set.
394 void buildRegUnitSet(std::vector<unsigned> &RegUnits) const;
396 CodeGenRegisterClass(CodeGenRegBank&, Record *R);
398 // A key representing the parts of a register class used for forming
399 // sub-classes. Note the ordering provided by this key is not the same as
400 // the topological order used for the EnumValues.
402 const CodeGenRegister::Vec *Members;
404 unsigned SpillAlignment;
406 Key(const CodeGenRegister::Vec *M, unsigned S = 0, unsigned A = 0)
407 : Members(M), SpillSize(S), SpillAlignment(A) {}
409 Key(const CodeGenRegisterClass &RC)
410 : Members(&RC.getMembers()),
411 SpillSize(RC.SpillSize),
412 SpillAlignment(RC.SpillAlignment) {}
414 // Lexicographical order of (Members, SpillSize, SpillAlignment).
415 bool operator<(const Key&) const;
418 // Create a non-user defined register class.
419 CodeGenRegisterClass(CodeGenRegBank&, StringRef Name, Key Props);
421 // Called by CodeGenRegBank::CodeGenRegBank().
422 static void computeSubClasses(CodeGenRegBank&);
425 // Register units are used to model interference and register pressure.
426 // Every register is assigned one or more register units such that two
427 // registers overlap if and only if they have a register unit in common.
429 // Normally, one register unit is created per leaf register. Non-leaf
430 // registers inherit the units of their sub-registers.
432 // Weight assigned to this RegUnit for estimating register pressure.
433 // This is useful when equalizing weights in register classes with mixed
434 // register topologies.
437 // Each native RegUnit corresponds to one or two root registers. The full
438 // set of registers containing this unit can be computed as the union of
439 // these two registers and their super-registers.
440 const CodeGenRegister *Roots[2];
442 // Index into RegClassUnitSets where we can find the list of UnitSets that
443 // contain this unit.
444 unsigned RegClassUnitSetsIdx;
446 RegUnit() : Weight(0), RegClassUnitSetsIdx(0) {
447 Roots[0] = Roots[1] = nullptr;
450 ArrayRef<const CodeGenRegister*> getRoots() const {
451 assert(!(Roots[1] && !Roots[0]) && "Invalid roots array");
452 return makeArrayRef(Roots, !!Roots[0] + !!Roots[1]);
456 // Each RegUnitSet is a sorted vector with a name.
458 typedef std::vector<unsigned>::const_iterator iterator;
461 std::vector<unsigned> Units;
462 unsigned Weight; // Cache the sum of all unit weights.
463 unsigned Order; // Cache the sort key.
465 RegUnitSet() : Weight(0), Order(0) {}
468 // Base vector for identifying TopoSigs. The contents uniquely identify a
469 // TopoSig, only computeSuperRegs needs to know how.
470 typedef SmallVector<unsigned, 16> TopoSigId;
472 // CodeGenRegBank - Represent a target's registers and the relations between
474 class CodeGenRegBank {
477 std::deque<CodeGenSubRegIndex> SubRegIndices;
478 DenseMap<Record*, CodeGenSubRegIndex*> Def2SubRegIdx;
480 CodeGenSubRegIndex *createSubRegIndex(StringRef Name, StringRef NameSpace);
482 typedef std::map<SmallVector<CodeGenSubRegIndex*, 8>,
483 CodeGenSubRegIndex*> ConcatIdxMap;
484 ConcatIdxMap ConcatIdx;
487 std::deque<CodeGenRegister> Registers;
488 StringMap<CodeGenRegister*> RegistersByName;
489 DenseMap<Record*, CodeGenRegister*> Def2Reg;
490 unsigned NumNativeRegUnits;
492 std::map<TopoSigId, unsigned> TopoSigs;
494 // Includes native (0..NumNativeRegUnits-1) and adopted register units.
495 SmallVector<RegUnit, 8> RegUnits;
498 std::list<CodeGenRegisterClass> RegClasses;
499 DenseMap<Record*, CodeGenRegisterClass*> Def2RC;
500 typedef std::map<CodeGenRegisterClass::Key, CodeGenRegisterClass*> RCKeyMap;
503 // Remember each unique set of register units. Initially, this contains a
504 // unique set for each register class. Simliar sets are coalesced with
505 // pruneUnitSets and new supersets are inferred during computeRegUnitSets.
506 std::vector<RegUnitSet> RegUnitSets;
508 // Map RegisterClass index to the index of the RegUnitSet that contains the
509 // class's units and any inferred RegUnit supersets.
511 // NOTE: This could grow beyond the number of register classes when we map
512 // register units to lists of unit sets. If the list of unit sets does not
513 // already exist for a register class, we create a new entry in this vector.
514 std::vector<std::vector<unsigned> > RegClassUnitSets;
516 // Give each register unit set an order based on sorting criteria.
517 std::vector<unsigned> RegUnitSetOrder;
519 // Add RC to *2RC maps.
520 void addToMaps(CodeGenRegisterClass*);
522 // Create a synthetic sub-class if it is missing.
523 CodeGenRegisterClass *getOrCreateSubClass(const CodeGenRegisterClass *RC,
524 const CodeGenRegister::Vec *Membs,
527 // Infer missing register classes.
528 void computeInferredRegisterClasses();
529 void inferCommonSubClass(CodeGenRegisterClass *RC);
530 void inferSubClassWithSubReg(CodeGenRegisterClass *RC);
531 void inferMatchingSuperRegClass(CodeGenRegisterClass *RC) {
532 inferMatchingSuperRegClass(RC, RegClasses.begin());
535 void inferMatchingSuperRegClass(
536 CodeGenRegisterClass *RC,
537 std::list<CodeGenRegisterClass>::iterator FirstSubRegRC);
539 // Iteratively prune unit sets.
540 void pruneUnitSets();
542 // Compute a weight for each register unit created during getSubRegs.
543 void computeRegUnitWeights();
545 // Create a RegUnitSet for each RegClass and infer superclasses.
546 void computeRegUnitSets();
548 // Populate the Composite map from sub-register relationships.
549 void computeComposites();
551 // Compute a lane mask for each sub-register index.
552 void computeSubRegLaneMasks();
554 /// Computes a lane mask for each register unit enumerated by a physical
556 void computeRegUnitLaneMasks();
559 CodeGenRegBank(RecordKeeper&);
561 SetTheory &getSets() { return Sets; }
563 // Sub-register indices. The first NumNamedIndices are defined by the user
564 // in the .td files. The rest are synthesized such that all sub-registers
565 // have a unique name.
566 const std::deque<CodeGenSubRegIndex> &getSubRegIndices() const {
567 return SubRegIndices;
570 // Find a SubRegIndex form its Record def.
571 CodeGenSubRegIndex *getSubRegIdx(Record*);
573 // Find or create a sub-register index representing the A+B composition.
574 CodeGenSubRegIndex *getCompositeSubRegIndex(CodeGenSubRegIndex *A,
575 CodeGenSubRegIndex *B);
577 // Find or create a sub-register index representing the concatenation of
578 // non-overlapping sibling indices.
580 getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex *, 8>&);
583 addConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex *, 8> &Parts,
584 CodeGenSubRegIndex *Idx) {
585 ConcatIdx.insert(std::make_pair(Parts, Idx));
588 const std::deque<CodeGenRegister> &getRegisters() { return Registers; }
589 const StringMap<CodeGenRegister*> &getRegistersByName() {
590 return RegistersByName;
593 // Find a register from its Record def.
594 CodeGenRegister *getReg(Record*);
596 // Get a Register's index into the Registers array.
597 unsigned getRegIndex(const CodeGenRegister *Reg) const {
598 return Reg->EnumValue - 1;
601 // Return the number of allocated TopoSigs. The first TopoSig representing
602 // leaf registers is allocated number 0.
603 unsigned getNumTopoSigs() const {
604 return TopoSigs.size();
607 // Find or create a TopoSig for the given TopoSigId.
608 // This function is only for use by CodeGenRegister::computeSuperRegs().
609 // Others should simply use Reg->getTopoSig().
610 unsigned getTopoSig(const TopoSigId &Id) {
611 return TopoSigs.insert(std::make_pair(Id, TopoSigs.size())).first->second;
614 // Create a native register unit that is associated with one or two root
616 unsigned newRegUnit(CodeGenRegister *R0, CodeGenRegister *R1 = nullptr) {
617 RegUnits.resize(RegUnits.size() + 1);
618 RegUnits.back().Roots[0] = R0;
619 RegUnits.back().Roots[1] = R1;
620 return RegUnits.size() - 1;
623 // Create a new non-native register unit that can be adopted by a register
624 // to increase its pressure. Note that NumNativeRegUnits is not increased.
625 unsigned newRegUnit(unsigned Weight) {
626 RegUnits.resize(RegUnits.size() + 1);
627 RegUnits.back().Weight = Weight;
628 return RegUnits.size() - 1;
631 // Native units are the singular unit of a leaf register. Register aliasing
632 // is completely characterized by native units. Adopted units exist to give
633 // register additional weight but don't affect aliasing.
634 bool isNativeUnit(unsigned RUID) {
635 return RUID < NumNativeRegUnits;
638 unsigned getNumNativeRegUnits() const {
639 return NumNativeRegUnits;
642 RegUnit &getRegUnit(unsigned RUID) { return RegUnits[RUID]; }
643 const RegUnit &getRegUnit(unsigned RUID) const { return RegUnits[RUID]; }
645 std::list<CodeGenRegisterClass> &getRegClasses() { return RegClasses; }
647 const std::list<CodeGenRegisterClass> &getRegClasses() const {
651 // Find a register class from its def.
652 CodeGenRegisterClass *getRegClass(Record*);
654 /// getRegisterClassForRegister - Find the register class that contains the
655 /// specified physical register. If the register is not in a register
656 /// class, return null. If the register is in multiple classes, and the
657 /// classes have a superset-subset relationship and the same set of types,
658 /// return the superclass. Otherwise return null.
659 const CodeGenRegisterClass* getRegClassForRegister(Record *R);
661 // Get the sum of unit weights.
662 unsigned getRegUnitSetWeight(const std::vector<unsigned> &Units) const {
664 for (std::vector<unsigned>::const_iterator
665 I = Units.begin(), E = Units.end(); I != E; ++I)
666 Weight += getRegUnit(*I).Weight;
670 unsigned getRegSetIDAt(unsigned Order) const {
671 return RegUnitSetOrder[Order];
673 const RegUnitSet &getRegSetAt(unsigned Order) const {
674 return RegUnitSets[RegUnitSetOrder[Order]];
677 // Increase a RegUnitWeight.
678 void increaseRegUnitWeight(unsigned RUID, unsigned Inc) {
679 getRegUnit(RUID).Weight += Inc;
682 // Get the number of register pressure dimensions.
683 unsigned getNumRegPressureSets() const { return RegUnitSets.size(); }
685 // Get a set of register unit IDs for a given dimension of pressure.
686 const RegUnitSet &getRegPressureSet(unsigned Idx) const {
687 return RegUnitSets[Idx];
690 // The number of pressure set lists may be larget than the number of
691 // register classes if some register units appeared in a list of sets that
692 // did not correspond to an existing register class.
693 unsigned getNumRegClassPressureSetLists() const {
694 return RegClassUnitSets.size();
697 // Get a list of pressure set IDs for a register class. Liveness of a
698 // register in this class impacts each pressure set in this list by the
699 // weight of the register. An exact solution requires all registers in a
700 // class to have the same class, but it is not strictly guaranteed.
701 ArrayRef<unsigned> getRCPressureSetIDs(unsigned RCIdx) const {
702 return RegClassUnitSets[RCIdx];
705 // Computed derived records such as missing sub-register indices.
706 void computeDerivedInfo();
708 // Compute the set of registers completely covered by the registers in Regs.
709 // The returned BitVector will have a bit set for each register in Regs,
710 // all sub-registers, and all super-registers that are covered by the
711 // registers in Regs.
713 // This is used to compute the mask of call-preserved registers from a list
715 BitVector computeCoveredRegisters(ArrayRef<Record*> Regs);
717 // Bit mask of lanes that cover their registers. A sub-register index whose
718 // LaneMask is contained in CoveringLanes will be completely covered by
719 // another sub-register with the same or larger lane mask.
720 unsigned CoveringLanes;