1 //===- CodeGenRegisters.h - Register and RegisterClass Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines structures to encapsulate information gleaned from the
11 // target register and register class definitions.
13 //===----------------------------------------------------------------------===//
15 #ifndef CODEGEN_REGISTERS_H
16 #define CODEGEN_REGISTERS_H
18 #include "SetTheory.h"
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/DenseMap.h"
22 #include "llvm/ADT/SetVector.h"
23 #include "llvm/CodeGen/ValueTypes.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/TableGen/Record.h"
35 /// CodeGenSubRegIndex - Represents a sub-register index.
36 class CodeGenSubRegIndex {
39 std::string Namespace;
44 const unsigned EnumValue;
47 // Are all super-registers containing this SubRegIndex covered by their
49 bool AllSuperRegsCovered;
51 CodeGenSubRegIndex(Record *R, unsigned Enum);
52 CodeGenSubRegIndex(StringRef N, StringRef Nspace, unsigned Enum);
54 const std::string &getName() const { return Name; }
55 const std::string &getNamespace() const { return Namespace; }
56 std::string getQualifiedName() const;
58 // Order CodeGenSubRegIndex pointers by EnumValue.
60 bool operator()(const CodeGenSubRegIndex *A,
61 const CodeGenSubRegIndex *B) const {
63 return A->EnumValue < B->EnumValue;
67 // Map of composite subreg indices.
68 typedef std::map<CodeGenSubRegIndex*, CodeGenSubRegIndex*, Less> CompMap;
70 // Returns the subreg index that results from composing this with Idx.
71 // Returns NULL if this and Idx don't compose.
72 CodeGenSubRegIndex *compose(CodeGenSubRegIndex *Idx) const {
73 CompMap::const_iterator I = Composed.find(Idx);
74 return I == Composed.end() ? 0 : I->second;
77 // Add a composite subreg index: this+A = B.
78 // Return a conflicting composite, or NULL
79 CodeGenSubRegIndex *addComposite(CodeGenSubRegIndex *A,
80 CodeGenSubRegIndex *B) {
82 std::pair<CompMap::iterator, bool> Ins =
83 Composed.insert(std::make_pair(A, B));
84 // Synthetic subreg indices that aren't contiguous (for instance ARM
85 // register tuples) don't have a bit range, so it's OK to let
86 // B->Offset == -1. For the other cases, accumulate the offset and set
87 // the size here. Only do so if there is no offset yet though.
88 if ((Offset != (uint16_t)-1 && A->Offset != (uint16_t)-1) &&
89 (B->Offset == (uint16_t)-1)) {
90 B->Offset = Offset + A->Offset;
93 return (Ins.second || Ins.first->second == B) ? 0 : Ins.first->second;
96 // Update the composite maps of components specified in 'ComposedOf'.
97 void updateComponents(CodeGenRegBank&);
99 // Return the map of composites.
100 const CompMap &getComposites() const { return Composed; }
102 // Compute LaneMask from Composed. Return LaneMask.
103 unsigned computeLaneMask();
109 /// CodeGenRegister - Represents a register definition.
110 struct CodeGenRegister {
114 bool CoveredBySubRegs;
116 // Map SubRegIndex -> Register.
117 typedef std::map<CodeGenSubRegIndex*, CodeGenRegister*,
118 CodeGenSubRegIndex::Less> SubRegMap;
120 CodeGenRegister(Record *R, unsigned Enum);
122 const std::string &getName() const;
124 // Extract more information from TheDef. This is used to build an object
125 // graph after all CodeGenRegister objects have been created.
126 void buildObjectGraph(CodeGenRegBank&);
128 // Lazily compute a map of all sub-registers.
129 // This includes unique entries for all sub-sub-registers.
130 const SubRegMap &computeSubRegs(CodeGenRegBank&);
132 // Compute extra sub-registers by combining the existing sub-registers.
133 void computeSecondarySubRegs(CodeGenRegBank&);
135 // Add this as a super-register to all sub-registers after the sub-register
136 // graph has been built.
137 void computeSuperRegs(CodeGenRegBank&);
139 const SubRegMap &getSubRegs() const {
140 assert(SubRegsComplete && "Must precompute sub-registers");
144 // Add sub-registers to OSet following a pre-order defined by the .td file.
145 void addSubRegsPreOrder(SetVector<const CodeGenRegister*> &OSet,
146 CodeGenRegBank&) const;
148 // Return the sub-register index naming Reg as a sub-register of this
149 // register. Returns NULL if Reg is not a sub-register.
150 CodeGenSubRegIndex *getSubRegIndex(const CodeGenRegister *Reg) const {
151 return SubReg2Idx.lookup(Reg);
154 typedef std::vector<const CodeGenRegister*> SuperRegList;
156 // Get the list of super-registers in topological order, small to large.
157 // This is valid after computeSubRegs visits all registers during RegBank
159 const SuperRegList &getSuperRegs() const {
160 assert(SubRegsComplete && "Must precompute sub-registers");
164 // Get the list of ad hoc aliases. The graph is symmetric, so the list
165 // contains all registers in 'Aliases', and all registers that mention this
166 // register in 'Aliases'.
167 ArrayRef<CodeGenRegister*> getExplicitAliases() const {
168 return ExplicitAliases;
171 // Get the topological signature of this register. This is a small integer
172 // less than RegBank.getNumTopoSigs(). Registers with the same TopoSig have
173 // identical sub-register structure. That is, they support the same set of
174 // sub-register indices mapping to the same kind of sub-registers
176 unsigned getTopoSig() const {
177 assert(SuperRegsComplete && "TopoSigs haven't been computed yet.");
181 // List of register units in ascending order.
182 typedef SmallVector<unsigned, 16> RegUnitList;
184 // How many entries in RegUnitList are native?
185 unsigned NumNativeRegUnits;
187 // Get the list of register units.
188 // This is only valid after computeSubRegs() completes.
189 const RegUnitList &getRegUnits() const { return RegUnits; }
191 // Get the native register units. This is a prefix of getRegUnits().
192 ArrayRef<unsigned> getNativeRegUnits() const {
193 return makeArrayRef(RegUnits).slice(0, NumNativeRegUnits);
196 // Inherit register units from subregisters.
197 // Return true if the RegUnits changed.
198 bool inheritRegUnits(CodeGenRegBank &RegBank);
200 // Adopt a register unit for pressure tracking.
201 // A unit is adopted iff its unit number is >= NumNativeRegUnits.
202 void adoptRegUnit(unsigned RUID) { RegUnits.push_back(RUID); }
204 // Get the sum of this register's register unit weights.
205 unsigned getWeight(const CodeGenRegBank &RegBank) const;
207 // Order CodeGenRegister pointers by EnumValue.
209 bool operator()(const CodeGenRegister *A,
210 const CodeGenRegister *B) const {
212 return A->EnumValue < B->EnumValue;
216 // Canonically ordered set.
217 typedef std::set<const CodeGenRegister*, Less> Set;
220 bool SubRegsComplete;
221 bool SuperRegsComplete;
224 // The sub-registers explicit in the .td file form a tree.
225 SmallVector<CodeGenSubRegIndex*, 8> ExplicitSubRegIndices;
226 SmallVector<CodeGenRegister*, 8> ExplicitSubRegs;
228 // Explicit ad hoc aliases, symmetrized to form an undirected graph.
229 SmallVector<CodeGenRegister*, 8> ExplicitAliases;
231 // Super-registers where this is the first explicit sub-register.
232 SuperRegList LeadingSuperRegs;
235 SuperRegList SuperRegs;
236 DenseMap<const CodeGenRegister*, CodeGenSubRegIndex*> SubReg2Idx;
237 RegUnitList RegUnits;
241 class CodeGenRegisterClass {
242 CodeGenRegister::Set Members;
243 // Allocation orders. Order[0] always contains all registers in Members.
244 std::vector<SmallVector<Record*, 16> > Orders;
245 // Bit mask of sub-classes including this, indexed by their EnumValue.
246 BitVector SubClasses;
247 // List of super-classes, topologocally ordered to have the larger classes
248 // first. This is the same as sorting by EnumValue.
249 SmallVector<CodeGenRegisterClass*, 4> SuperClasses;
253 // For a synthesized class, inherit missing properties from the nearest
255 void inheritProperties(CodeGenRegBank&);
257 // Map SubRegIndex -> sub-class. This is the largest sub-class where all
258 // registers have a SubRegIndex sub-register.
259 DenseMap<CodeGenSubRegIndex*, CodeGenRegisterClass*> SubClassWithSubReg;
261 // Map SubRegIndex -> set of super-reg classes. This is all register
262 // classes SuperRC such that:
264 // R:SubRegIndex in this RC for all R in SuperRC.
266 DenseMap<CodeGenSubRegIndex*,
267 SmallPtrSet<CodeGenRegisterClass*, 8> > SuperRegClasses;
269 // Bit vector of TopoSigs for the registers in this class. This will be
270 // very sparse on regular architectures.
275 std::string Namespace;
276 SmallVector<MVT::SimpleValueType, 4> VTs;
278 unsigned SpillAlignment;
281 std::string AltOrderSelect;
283 // Return the Record that defined this class, or NULL if the class was
284 // created by TableGen.
285 Record *getDef() const { return TheDef; }
287 const std::string &getName() const { return Name; }
288 std::string getQualifiedName() const;
289 ArrayRef<MVT::SimpleValueType> getValueTypes() const {return VTs;}
290 unsigned getNumValueTypes() const { return VTs.size(); }
292 MVT::SimpleValueType getValueTypeNum(unsigned VTNum) const {
293 if (VTNum < VTs.size())
295 llvm_unreachable("VTNum greater than number of ValueTypes in RegClass!");
298 // Return true if this this class contains the register.
299 bool contains(const CodeGenRegister*) const;
301 // Returns true if RC is a subclass.
302 // RC is a sub-class of this class if it is a valid replacement for any
303 // instruction operand where a register of this classis required. It must
304 // satisfy these conditions:
306 // 1. All RC registers are also in this.
307 // 2. The RC spill size must not be smaller than our spill size.
308 // 3. RC spill alignment must be compatible with ours.
310 bool hasSubClass(const CodeGenRegisterClass *RC) const {
311 return SubClasses.test(RC->EnumValue);
314 // getSubClassWithSubReg - Returns the largest sub-class where all
315 // registers have a SubIdx sub-register.
316 CodeGenRegisterClass*
317 getSubClassWithSubReg(CodeGenSubRegIndex *SubIdx) const {
318 return SubClassWithSubReg.lookup(SubIdx);
321 void setSubClassWithSubReg(CodeGenSubRegIndex *SubIdx,
322 CodeGenRegisterClass *SubRC) {
323 SubClassWithSubReg[SubIdx] = SubRC;
326 // getSuperRegClasses - Returns a bit vector of all register classes
327 // containing only SubIdx super-registers of this class.
328 void getSuperRegClasses(CodeGenSubRegIndex *SubIdx, BitVector &Out) const;
330 // addSuperRegClass - Add a class containing only SudIdx super-registers.
331 void addSuperRegClass(CodeGenSubRegIndex *SubIdx,
332 CodeGenRegisterClass *SuperRC) {
333 SuperRegClasses[SubIdx].insert(SuperRC);
336 // getSubClasses - Returns a constant BitVector of subclasses indexed by
338 // The SubClasses vector includs an entry for this class.
339 const BitVector &getSubClasses() const { return SubClasses; }
341 // getSuperClasses - Returns a list of super classes ordered by EnumValue.
342 // The array does not include an entry for this class.
343 ArrayRef<CodeGenRegisterClass*> getSuperClasses() const {
347 // Returns an ordered list of class members.
348 // The order of registers is the same as in the .td file.
349 // No = 0 is the default allocation order, No = 1 is the first alternative.
350 ArrayRef<Record*> getOrder(unsigned No = 0) const {
354 // Return the total number of allocation orders available.
355 unsigned getNumOrders() const { return Orders.size(); }
357 // Get the set of registers. This set contains the same registers as
359 const CodeGenRegister::Set &getMembers() const { return Members; }
361 // Get a bit vector of TopoSigs present in this register class.
362 const BitVector &getTopoSigs() const { return TopoSigs; }
364 // Populate a unique sorted list of units from a register set.
365 void buildRegUnitSet(std::vector<unsigned> &RegUnits) const;
367 CodeGenRegisterClass(CodeGenRegBank&, Record *R);
369 // A key representing the parts of a register class used for forming
370 // sub-classes. Note the ordering provided by this key is not the same as
371 // the topological order used for the EnumValues.
373 const CodeGenRegister::Set *Members;
375 unsigned SpillAlignment;
378 : Members(O.Members),
379 SpillSize(O.SpillSize),
380 SpillAlignment(O.SpillAlignment) {}
382 Key(const CodeGenRegister::Set *M, unsigned S = 0, unsigned A = 0)
383 : Members(M), SpillSize(S), SpillAlignment(A) {}
385 Key(const CodeGenRegisterClass &RC)
386 : Members(&RC.getMembers()),
387 SpillSize(RC.SpillSize),
388 SpillAlignment(RC.SpillAlignment) {}
390 // Lexicographical order of (Members, SpillSize, SpillAlignment).
391 bool operator<(const Key&) const;
394 // Create a non-user defined register class.
395 CodeGenRegisterClass(CodeGenRegBank&, StringRef Name, Key Props);
397 // Called by CodeGenRegBank::CodeGenRegBank().
398 static void computeSubClasses(CodeGenRegBank&);
401 // Register units are used to model interference and register pressure.
402 // Every register is assigned one or more register units such that two
403 // registers overlap if and only if they have a register unit in common.
405 // Normally, one register unit is created per leaf register. Non-leaf
406 // registers inherit the units of their sub-registers.
408 // Weight assigned to this RegUnit for estimating register pressure.
409 // This is useful when equalizing weights in register classes with mixed
410 // register topologies.
413 // Each native RegUnit corresponds to one or two root registers. The full
414 // set of registers containing this unit can be computed as the union of
415 // these two registers and their super-registers.
416 const CodeGenRegister *Roots[2];
418 // Index into RegClassUnitSets where we can find the list of UnitSets that
419 // contain this unit.
420 unsigned RegClassUnitSetsIdx;
422 RegUnit() : Weight(0), RegClassUnitSetsIdx(0) { Roots[0] = Roots[1] = 0; }
424 ArrayRef<const CodeGenRegister*> getRoots() const {
425 assert(!(Roots[1] && !Roots[0]) && "Invalid roots array");
426 return makeArrayRef(Roots, !!Roots[0] + !!Roots[1]);
430 // Each RegUnitSet is a sorted vector with a name.
432 typedef std::vector<unsigned>::const_iterator iterator;
435 std::vector<unsigned> Units;
438 // Base vector for identifying TopoSigs. The contents uniquely identify a
439 // TopoSig, only computeSuperRegs needs to know how.
440 typedef SmallVector<unsigned, 16> TopoSigId;
442 // CodeGenRegBank - Represent a target's registers and the relations between
444 class CodeGenRegBank {
448 std::vector<CodeGenSubRegIndex*> SubRegIndices;
449 DenseMap<Record*, CodeGenSubRegIndex*> Def2SubRegIdx;
451 CodeGenSubRegIndex *createSubRegIndex(StringRef Name, StringRef NameSpace);
453 typedef std::map<SmallVector<CodeGenSubRegIndex*, 8>,
454 CodeGenSubRegIndex*> ConcatIdxMap;
455 ConcatIdxMap ConcatIdx;
458 std::vector<CodeGenRegister*> Registers;
459 StringMap<CodeGenRegister*> RegistersByName;
460 DenseMap<Record*, CodeGenRegister*> Def2Reg;
461 unsigned NumNativeRegUnits;
463 std::map<TopoSigId, unsigned> TopoSigs;
465 // Includes native (0..NumNativeRegUnits-1) and adopted register units.
466 SmallVector<RegUnit, 8> RegUnits;
469 std::vector<CodeGenRegisterClass*> RegClasses;
470 DenseMap<Record*, CodeGenRegisterClass*> Def2RC;
471 typedef std::map<CodeGenRegisterClass::Key, CodeGenRegisterClass*> RCKeyMap;
474 // Remember each unique set of register units. Initially, this contains a
475 // unique set for each register class. Simliar sets are coalesced with
476 // pruneUnitSets and new supersets are inferred during computeRegUnitSets.
477 std::vector<RegUnitSet> RegUnitSets;
479 // Map RegisterClass index to the index of the RegUnitSet that contains the
480 // class's units and any inferred RegUnit supersets.
482 // NOTE: This could grow beyond the number of register classes when we map
483 // register units to lists of unit sets. If the list of unit sets does not
484 // already exist for a register class, we create a new entry in this vector.
485 std::vector<std::vector<unsigned> > RegClassUnitSets;
487 // Add RC to *2RC maps.
488 void addToMaps(CodeGenRegisterClass*);
490 // Create a synthetic sub-class if it is missing.
491 CodeGenRegisterClass *getOrCreateSubClass(const CodeGenRegisterClass *RC,
492 const CodeGenRegister::Set *Membs,
495 // Infer missing register classes.
496 void computeInferredRegisterClasses();
497 void inferCommonSubClass(CodeGenRegisterClass *RC);
498 void inferSubClassWithSubReg(CodeGenRegisterClass *RC);
499 void inferMatchingSuperRegClass(CodeGenRegisterClass *RC,
500 unsigned FirstSubRegRC = 0);
502 // Iteratively prune unit sets.
503 void pruneUnitSets();
505 // Compute a weight for each register unit created during getSubRegs.
506 void computeRegUnitWeights();
508 // Create a RegUnitSet for each RegClass and infer superclasses.
509 void computeRegUnitSets();
511 // Populate the Composite map from sub-register relationships.
512 void computeComposites();
514 // Compute a lane mask for each sub-register index.
515 void computeSubRegIndexLaneMasks();
518 CodeGenRegBank(RecordKeeper&);
520 SetTheory &getSets() { return Sets; }
522 // Sub-register indices. The first NumNamedIndices are defined by the user
523 // in the .td files. The rest are synthesized such that all sub-registers
524 // have a unique name.
525 ArrayRef<CodeGenSubRegIndex*> getSubRegIndices() { return SubRegIndices; }
527 // Find a SubRegIndex form its Record def.
528 CodeGenSubRegIndex *getSubRegIdx(Record*);
530 // Find or create a sub-register index representing the A+B composition.
531 CodeGenSubRegIndex *getCompositeSubRegIndex(CodeGenSubRegIndex *A,
532 CodeGenSubRegIndex *B);
534 // Find or create a sub-register index representing the concatenation of
535 // non-overlapping sibling indices.
537 getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex*, 8>&);
540 addConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex*, 8> &Parts,
541 CodeGenSubRegIndex *Idx) {
542 ConcatIdx.insert(std::make_pair(Parts, Idx));
545 const std::vector<CodeGenRegister*> &getRegisters() { return Registers; }
546 const StringMap<CodeGenRegister*> &getRegistersByName() {
547 return RegistersByName;
550 // Find a register from its Record def.
551 CodeGenRegister *getReg(Record*);
553 // Get a Register's index into the Registers array.
554 unsigned getRegIndex(const CodeGenRegister *Reg) const {
555 return Reg->EnumValue - 1;
558 // Return the number of allocated TopoSigs. The first TopoSig representing
559 // leaf registers is allocated number 0.
560 unsigned getNumTopoSigs() const {
561 return TopoSigs.size();
564 // Find or create a TopoSig for the given TopoSigId.
565 // This function is only for use by CodeGenRegister::computeSuperRegs().
566 // Others should simply use Reg->getTopoSig().
567 unsigned getTopoSig(const TopoSigId &Id) {
568 return TopoSigs.insert(std::make_pair(Id, TopoSigs.size())).first->second;
571 // Create a native register unit that is associated with one or two root
573 unsigned newRegUnit(CodeGenRegister *R0, CodeGenRegister *R1 = 0) {
574 RegUnits.resize(RegUnits.size() + 1);
575 RegUnits.back().Roots[0] = R0;
576 RegUnits.back().Roots[1] = R1;
577 return RegUnits.size() - 1;
580 // Create a new non-native register unit that can be adopted by a register
581 // to increase its pressure. Note that NumNativeRegUnits is not increased.
582 unsigned newRegUnit(unsigned Weight) {
583 RegUnits.resize(RegUnits.size() + 1);
584 RegUnits.back().Weight = Weight;
585 return RegUnits.size() - 1;
588 // Native units are the singular unit of a leaf register. Register aliasing
589 // is completely characterized by native units. Adopted units exist to give
590 // register additional weight but don't affect aliasing.
591 bool isNativeUnit(unsigned RUID) {
592 return RUID < NumNativeRegUnits;
595 unsigned getNumNativeRegUnits() const {
596 return NumNativeRegUnits;
599 RegUnit &getRegUnit(unsigned RUID) { return RegUnits[RUID]; }
600 const RegUnit &getRegUnit(unsigned RUID) const { return RegUnits[RUID]; }
602 ArrayRef<CodeGenRegisterClass*> getRegClasses() const {
606 // Find a register class from its def.
607 CodeGenRegisterClass *getRegClass(Record*);
609 /// getRegisterClassForRegister - Find the register class that contains the
610 /// specified physical register. If the register is not in a register
611 /// class, return null. If the register is in multiple classes, and the
612 /// classes have a superset-subset relationship and the same set of types,
613 /// return the superclass. Otherwise return null.
614 const CodeGenRegisterClass* getRegClassForRegister(Record *R);
616 // Get the sum of unit weights.
617 unsigned getRegUnitSetWeight(const std::vector<unsigned> &Units) const {
619 for (std::vector<unsigned>::const_iterator
620 I = Units.begin(), E = Units.end(); I != E; ++I)
621 Weight += getRegUnit(*I).Weight;
625 // Increase a RegUnitWeight.
626 void increaseRegUnitWeight(unsigned RUID, unsigned Inc) {
627 getRegUnit(RUID).Weight += Inc;
630 // Get the number of register pressure dimensions.
631 unsigned getNumRegPressureSets() const { return RegUnitSets.size(); }
633 // Get a set of register unit IDs for a given dimension of pressure.
634 RegUnitSet getRegPressureSet(unsigned Idx) const {
635 return RegUnitSets[Idx];
638 // The number of pressure set lists may be larget than the number of
639 // register classes if some register units appeared in a list of sets that
640 // did not correspond to an existing register class.
641 unsigned getNumRegClassPressureSetLists() const {
642 return RegClassUnitSets.size();
645 // Get a list of pressure set IDs for a register class. Liveness of a
646 // register in this class impacts each pressure set in this list by the
647 // weight of the register. An exact solution requires all registers in a
648 // class to have the same class, but it is not strictly guaranteed.
649 ArrayRef<unsigned> getRCPressureSetIDs(unsigned RCIdx) const {
650 return RegClassUnitSets[RCIdx];
653 // Computed derived records such as missing sub-register indices.
654 void computeDerivedInfo();
656 // Compute the set of registers completely covered by the registers in Regs.
657 // The returned BitVector will have a bit set for each register in Regs,
658 // all sub-registers, and all super-registers that are covered by the
659 // registers in Regs.
661 // This is used to compute the mask of call-preserved registers from a list
663 BitVector computeCoveredRegisters(ArrayRef<Record*> Regs);
665 // Bit mask of lanes that cover their registers. A sub-register index whose
666 // LaneMask is contained in CoveringLanes will be completely covered by
667 // another sub-register with the same or larger lane mask.
668 unsigned CoveringLanes;