1 //===- CodeGenRegisters.h - Register and RegisterClass Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines structures to encapsulate information gleaned from the
11 // target register and register class definitions.
13 //===----------------------------------------------------------------------===//
15 #ifndef CODEGEN_REGISTERS_H
16 #define CODEGEN_REGISTERS_H
18 #include "SetTheory.h"
19 #include "llvm/TableGen/Record.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/ADT/ArrayRef.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/DenseMap.h"
24 #include "llvm/ADT/SetVector.h"
25 #include "llvm/Support/ErrorHandling.h"
35 /// CodeGenSubRegIndex - Represents a sub-register index.
36 class CodeGenSubRegIndex {
38 const unsigned EnumValue;
41 CodeGenSubRegIndex(Record *R, unsigned Enum);
43 const std::string &getName() const;
44 std::string getNamespace() const;
45 std::string getQualifiedName() const;
47 // Order CodeGenSubRegIndex pointers by EnumValue.
49 bool operator()(const CodeGenSubRegIndex *A,
50 const CodeGenSubRegIndex *B) const {
52 return A->EnumValue < B->EnumValue;
56 // Map of composite subreg indices.
57 typedef std::map<CodeGenSubRegIndex*, CodeGenSubRegIndex*, Less> CompMap;
59 // Returns the subreg index that results from composing this with Idx.
60 // Returns NULL if this and Idx don't compose.
61 CodeGenSubRegIndex *compose(CodeGenSubRegIndex *Idx) const {
62 CompMap::const_iterator I = Composed.find(Idx);
63 return I == Composed.end() ? 0 : I->second;
66 // Add a composite subreg index: this+A = B.
67 // Return a conflicting composite, or NULL
68 CodeGenSubRegIndex *addComposite(CodeGenSubRegIndex *A,
69 CodeGenSubRegIndex *B) {
70 std::pair<CompMap::iterator, bool> Ins =
71 Composed.insert(std::make_pair(A, B));
72 return (Ins.second || Ins.first->second == B) ? 0 : Ins.first->second;
75 // Update the composite maps of components specified in 'ComposedOf'.
76 void updateComponents(CodeGenRegBank&);
78 // Clean out redundant composite mappings.
79 void cleanComposites();
81 // Return the map of composites.
82 const CompMap &getComposites() const { return Composed; }
88 /// CodeGenRegister - Represents a register definition.
89 struct CodeGenRegister {
93 bool CoveredBySubRegs;
95 // Map SubRegIndex -> Register.
96 typedef std::map<CodeGenSubRegIndex*, CodeGenRegister*,
97 CodeGenSubRegIndex::Less> SubRegMap;
99 CodeGenRegister(Record *R, unsigned Enum);
101 const std::string &getName() const;
103 // Get a map of sub-registers computed lazily.
104 // This includes unique entries for all sub-sub-registers.
105 const SubRegMap &getSubRegs(CodeGenRegBank&);
107 const SubRegMap &getSubRegs() const {
108 assert(SubRegsComplete && "Must precompute sub-registers");
112 // Add sub-registers to OSet following a pre-order defined by the .td file.
113 void addSubRegsPreOrder(SetVector<const CodeGenRegister*> &OSet,
114 CodeGenRegBank&) const;
116 // List of super-registers in topological order, small to large.
117 typedef std::vector<const CodeGenRegister*> SuperRegList;
119 // Get the list of super-registers.
120 // This is only valid after computeDerivedInfo has visited all registers.
121 const SuperRegList &getSuperRegs() const {
122 assert(SubRegsComplete && "Must precompute sub-registers");
126 // List of register units in ascending order.
127 typedef SmallVector<unsigned, 16> RegUnitList;
129 // Get the list of register units.
130 // This is only valid after getSubRegs() completes.
131 const RegUnitList &getRegUnits() const { return RegUnits; }
133 // Order CodeGenRegister pointers by EnumValue.
135 bool operator()(const CodeGenRegister *A,
136 const CodeGenRegister *B) const {
138 return A->EnumValue < B->EnumValue;
142 // Canonically ordered set.
143 typedef std::set<const CodeGenRegister*, Less> Set;
146 bool SubRegsComplete;
148 SuperRegList SuperRegs;
149 RegUnitList RegUnits;
153 class CodeGenRegisterClass {
154 CodeGenRegister::Set Members;
155 // Allocation orders. Order[0] always contains all registers in Members.
156 std::vector<SmallVector<Record*, 16> > Orders;
157 // Bit mask of sub-classes including this, indexed by their EnumValue.
158 BitVector SubClasses;
159 // List of super-classes, topologocally ordered to have the larger classes
160 // first. This is the same as sorting by EnumValue.
161 SmallVector<CodeGenRegisterClass*, 4> SuperClasses;
165 // For a synthesized class, inherit missing properties from the nearest
167 void inheritProperties(CodeGenRegBank&);
169 // Map SubRegIndex -> sub-class. This is the largest sub-class where all
170 // registers have a SubRegIndex sub-register.
171 DenseMap<CodeGenSubRegIndex*, CodeGenRegisterClass*> SubClassWithSubReg;
173 // Map SubRegIndex -> set of super-reg classes. This is all register
174 // classes SuperRC such that:
176 // R:SubRegIndex in this RC for all R in SuperRC.
178 DenseMap<CodeGenSubRegIndex*,
179 SmallPtrSet<CodeGenRegisterClass*, 8> > SuperRegClasses;
182 std::string Namespace;
183 std::vector<MVT::SimpleValueType> VTs;
185 unsigned SpillAlignment;
188 // Map SubRegIndex -> RegisterClass
189 DenseMap<Record*,Record*> SubRegClasses;
190 std::string AltOrderSelect;
192 // Return the Record that defined this class, or NULL if the class was
193 // created by TableGen.
194 Record *getDef() const { return TheDef; }
196 const std::string &getName() const { return Name; }
197 std::string getQualifiedName() const;
198 const std::vector<MVT::SimpleValueType> &getValueTypes() const {return VTs;}
199 unsigned getNumValueTypes() const { return VTs.size(); }
201 MVT::SimpleValueType getValueTypeNum(unsigned VTNum) const {
202 if (VTNum < VTs.size())
204 llvm_unreachable("VTNum greater than number of ValueTypes in RegClass!");
207 // Return true if this this class contains the register.
208 bool contains(const CodeGenRegister*) const;
210 // Returns true if RC is a subclass.
211 // RC is a sub-class of this class if it is a valid replacement for any
212 // instruction operand where a register of this classis required. It must
213 // satisfy these conditions:
215 // 1. All RC registers are also in this.
216 // 2. The RC spill size must not be smaller than our spill size.
217 // 3. RC spill alignment must be compatible with ours.
219 bool hasSubClass(const CodeGenRegisterClass *RC) const {
220 return SubClasses.test(RC->EnumValue);
223 // getSubClassWithSubReg - Returns the largest sub-class where all
224 // registers have a SubIdx sub-register.
225 CodeGenRegisterClass*
226 getSubClassWithSubReg(CodeGenSubRegIndex *SubIdx) const {
227 return SubClassWithSubReg.lookup(SubIdx);
230 void setSubClassWithSubReg(CodeGenSubRegIndex *SubIdx,
231 CodeGenRegisterClass *SubRC) {
232 SubClassWithSubReg[SubIdx] = SubRC;
235 // getSuperRegClasses - Returns a bit vector of all register classes
236 // containing only SubIdx super-registers of this class.
237 void getSuperRegClasses(CodeGenSubRegIndex *SubIdx, BitVector &Out) const;
239 // addSuperRegClass - Add a class containing only SudIdx super-registers.
240 void addSuperRegClass(CodeGenSubRegIndex *SubIdx,
241 CodeGenRegisterClass *SuperRC) {
242 SuperRegClasses[SubIdx].insert(SuperRC);
245 // getSubClasses - Returns a constant BitVector of subclasses indexed by
247 // The SubClasses vector includs an entry for this class.
248 const BitVector &getSubClasses() const { return SubClasses; }
250 // getSuperClasses - Returns a list of super classes ordered by EnumValue.
251 // The array does not include an entry for this class.
252 ArrayRef<CodeGenRegisterClass*> getSuperClasses() const {
256 // Returns an ordered list of class members.
257 // The order of registers is the same as in the .td file.
258 // No = 0 is the default allocation order, No = 1 is the first alternative.
259 ArrayRef<Record*> getOrder(unsigned No = 0) const {
263 // Return the total number of allocation orders available.
264 unsigned getNumOrders() const { return Orders.size(); }
266 // Get the set of registers. This set contains the same registers as
268 const CodeGenRegister::Set &getMembers() const { return Members; }
270 CodeGenRegisterClass(CodeGenRegBank&, Record *R);
272 // A key representing the parts of a register class used for forming
273 // sub-classes. Note the ordering provided by this key is not the same as
274 // the topological order used for the EnumValues.
276 const CodeGenRegister::Set *Members;
278 unsigned SpillAlignment;
281 : Members(O.Members),
282 SpillSize(O.SpillSize),
283 SpillAlignment(O.SpillAlignment) {}
285 Key(const CodeGenRegister::Set *M, unsigned S = 0, unsigned A = 0)
286 : Members(M), SpillSize(S), SpillAlignment(A) {}
288 Key(const CodeGenRegisterClass &RC)
289 : Members(&RC.getMembers()),
290 SpillSize(RC.SpillSize),
291 SpillAlignment(RC.SpillAlignment) {}
293 // Lexicographical order of (Members, SpillSize, SpillAlignment).
294 bool operator<(const Key&) const;
297 // Create a non-user defined register class.
298 CodeGenRegisterClass(StringRef Name, Key Props);
300 // Called by CodeGenRegBank::CodeGenRegBank().
301 static void computeSubClasses(CodeGenRegBank&);
304 // CodeGenRegBank - Represent a target's registers and the relations between
306 class CodeGenRegBank {
307 RecordKeeper &Records;
311 std::vector<CodeGenSubRegIndex*> SubRegIndices;
312 DenseMap<Record*, CodeGenSubRegIndex*> Def2SubRegIdx;
313 unsigned NumNamedIndices;
316 std::vector<CodeGenRegister*> Registers;
317 DenseMap<Record*, CodeGenRegister*> Def2Reg;
318 unsigned NumRegUnits;
321 std::vector<CodeGenRegisterClass*> RegClasses;
322 DenseMap<Record*, CodeGenRegisterClass*> Def2RC;
323 typedef std::map<CodeGenRegisterClass::Key, CodeGenRegisterClass*> RCKeyMap;
326 // Add RC to *2RC maps.
327 void addToMaps(CodeGenRegisterClass*);
329 // Create a synthetic sub-class if it is missing.
330 CodeGenRegisterClass *getOrCreateSubClass(const CodeGenRegisterClass *RC,
331 const CodeGenRegister::Set *Membs,
334 // Infer missing register classes.
335 void computeInferredRegisterClasses();
336 void inferCommonSubClass(CodeGenRegisterClass *RC);
337 void inferSubClassWithSubReg(CodeGenRegisterClass *RC);
338 void inferMatchingSuperRegClass(CodeGenRegisterClass *RC,
339 unsigned FirstSubRegRC = 0);
341 // Populate the Composite map from sub-register relationships.
342 void computeComposites();
345 CodeGenRegBank(RecordKeeper&);
347 SetTheory &getSets() { return Sets; }
349 // Sub-register indices. The first NumNamedIndices are defined by the user
350 // in the .td files. The rest are synthesized such that all sub-registers
351 // have a unique name.
352 ArrayRef<CodeGenSubRegIndex*> getSubRegIndices() { return SubRegIndices; }
353 unsigned getNumNamedIndices() { return NumNamedIndices; }
355 // Find a SubRegIndex form its Record def.
356 CodeGenSubRegIndex *getSubRegIdx(Record*);
358 // Find or create a sub-register index representing the A+B composition.
359 CodeGenSubRegIndex *getCompositeSubRegIndex(CodeGenSubRegIndex *A,
360 CodeGenSubRegIndex *B);
362 const std::vector<CodeGenRegister*> &getRegisters() { return Registers; }
364 // Find a register from its Record def.
365 CodeGenRegister *getReg(Record*);
367 unsigned newRegUnit() { return NumRegUnits++; }
369 ArrayRef<CodeGenRegisterClass*> getRegClasses() const {
373 // Find a register class from its def.
374 CodeGenRegisterClass *getRegClass(Record*);
376 /// getRegisterClassForRegister - Find the register class that contains the
377 /// specified physical register. If the register is not in a register
378 /// class, return null. If the register is in multiple classes, and the
379 /// classes have a superset-subset relationship and the same set of types,
380 /// return the superclass. Otherwise return null.
381 const CodeGenRegisterClass* getRegClassForRegister(Record *R);
383 // Computed derived records such as missing sub-register indices.
384 void computeDerivedInfo();
386 // Compute full overlap sets for every register. These sets include the
387 // rarely used aliases that are neither sub nor super-registers.
389 // Map[R1].count(R2) is reflexive and symmetric, but not transitive.
391 // If R1 is a sub-register of R2, Map[R1] is a subset of Map[R2].
392 void computeOverlaps(std::map<const CodeGenRegister*,
393 CodeGenRegister::Set> &Map);
395 // Compute the set of registers completely covered by the registers in Regs.
396 // The returned BitVector will have a bit set for each register in Regs,
397 // all sub-registers, and all super-registers that are covered by the
398 // registers in Regs.
400 // This is used to compute the mask of call-preserved registers from a list
402 BitVector computeCoveredRegisters(ArrayRef<Record*> Regs);