1 //===- CodeGenSchedule.h - Scheduling Machine Models ------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines structures to encapsulate the machine model as decribed in
11 // the target description.
13 //===----------------------------------------------------------------------===//
15 #ifndef CODEGEN_SCHEDULE_H
16 #define CODEGEN_SCHEDULE_H
18 #include "SetTheory.h"
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/ADT/StringMap.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/TableGen/Record.h"
27 class CodeGenSchedModels;
28 class CodeGenInstruction;
30 typedef std::vector<Record*> RecVec;
31 typedef std::vector<Record*>::const_iterator RecIter;
33 typedef std::vector<unsigned> IdxVec;
34 typedef std::vector<unsigned>::const_iterator IdxIter;
36 void splitSchedReadWrites(const RecVec &RWDefs,
37 RecVec &WriteDefs, RecVec &ReadDefs);
39 /// We have two kinds of SchedReadWrites. Explicitly defined and inferred
40 /// sequences. TheDef is nonnull for explicit SchedWrites, but Sequence may or
41 /// may not be empty. TheDef is null for inferred sequences, and Sequence must
44 /// IsVariadic controls whether the variants are expanded into multiple operands
45 /// or a sequence of writes on one operand.
46 struct CodeGenSchedRW {
59 : Index(0), TheDef(0), IsRead(false), IsAlias(false),
60 HasVariants(false), IsVariadic(false), IsSequence(false) {}
61 CodeGenSchedRW(unsigned Idx, Record *Def)
62 : Index(Idx), TheDef(Def), IsAlias(false), IsVariadic(false) {
63 Name = Def->getName();
64 IsRead = Def->isSubClassOf("SchedRead");
65 HasVariants = Def->isSubClassOf("SchedVariant");
67 IsVariadic = Def->getValueAsBit("Variadic");
69 // Read records don't currently have sequences, but it can be easily
70 // added. Note that implicit Reads (from ReadVariant) may have a Sequence
72 IsSequence = Def->isSubClassOf("WriteSequence");
75 CodeGenSchedRW(unsigned Idx, bool Read, const IdxVec &Seq,
76 const std::string &Name)
77 : Index(Idx), Name(Name), TheDef(0), IsRead(Read), IsAlias(false),
78 HasVariants(false), IsVariadic(false), IsSequence(true), Sequence(Seq) {
79 assert(Sequence.size() > 1 && "implied sequence needs >1 RWs");
82 bool isValid() const {
83 assert((!HasVariants || TheDef) && "Variant write needs record def");
84 assert((!IsVariadic || HasVariants) && "Variadic write needs variants");
85 assert((!IsSequence || !HasVariants) && "Sequence can't have variant");
86 assert((!IsSequence || !Sequence.empty()) && "Sequence should be nonempty");
87 assert((!IsAlias || Aliases.empty()) && "Alias cannot have aliases");
88 return TheDef || !Sequence.empty();
96 /// Represent a transition between SchedClasses induced by SchedVariant.
97 struct CodeGenSchedTransition {
103 /// Scheduling class.
105 /// Each instruction description will be mapped to a scheduling class. There are
106 /// four types of classes:
108 /// 1) An explicitly defined itinerary class with ItinClassDef set.
109 /// Writes and ReadDefs are empty. ProcIndices contains 0 for any processor.
111 /// 2) An implied class with a list of SchedWrites and SchedReads that are
112 /// defined in an instruction definition and which are common across all
113 /// subtargets. ProcIndices contains 0 for any processor.
115 /// 3) An implied class with a list of InstRW records that map instructions to
116 /// SchedWrites and SchedReads per-processor. InstrClassMap should map the same
117 /// instructions to this class. ProcIndices contains all the processors that
118 /// provided InstrRW records for this class. ItinClassDef or Writes/Reads may
119 /// still be defined for processors with no InstRW entry.
121 /// 4) An inferred class represents a variant of another class that may be
122 /// resolved at runtime. ProcIndices contains the set of processors that may
123 /// require the class. ProcIndices are propagated through SchedClasses as
124 /// variants are expanded. Multiple SchedClasses may be inferred from an
125 /// itinerary class. Each inherits the processor index from the ItinRW record
126 /// that mapped the itinerary class to the variant Writes or Reads.
127 struct CodeGenSchedClass {
129 Record *ItinClassDef;
133 // Sorted list of ProcIdx, where ProcIdx==0 implies any processor.
136 std::vector<CodeGenSchedTransition> Transitions;
138 // InstRW records associated with this class. These records may refer to an
139 // Instruction no longer mapped to this class by InstrClassMap. These
140 // Instructions should be ignored by this class because they have been split
141 // off to join another inferred class.
144 CodeGenSchedClass(): ItinClassDef(0) {}
145 CodeGenSchedClass(Record *rec): ItinClassDef(rec) {
146 Name = rec->getName();
147 ProcIndices.push_back(0);
151 void dump(const CodeGenSchedModels *SchedModels) const;
157 // ModelName is a unique name used to name an instantiation of MCSchedModel.
159 // ModelDef is NULL for inferred Models. This happens when a processor defines
160 // an itinerary but no machine model. If the processer defines neither a machine
161 // model nor itinerary, then ModelDef remains pointing to NoModel. NoModel has
162 // the special "NoModel" field set to true.
164 // ItinsDef always points to a valid record definition, but may point to the
165 // default NoItineraries. NoItineraries has an empty list of InstrItinData
168 // ItinDefList orders this processor's InstrItinData records by SchedClass idx.
169 struct CodeGenProcModel {
171 std::string ModelName;
175 // Derived members...
177 // Array of InstrItinData records indexed by a CodeGenSchedClass index.
178 // This list is empty if the Processor has no value for Itineraries.
179 // Initialized by collectProcItins().
182 // Map itinerary classes to per-operand resources.
183 // This list is empty if no ItinRW refers to this Processor.
186 // All read/write resources associated with this processor.
188 RecVec ReadAdvanceDefs;
190 // Per-operand machine model resources associated with this processor.
191 RecVec ProcResourceDefs;
193 CodeGenProcModel(unsigned Idx, const std::string &Name, Record *MDef,
195 Index(Idx), ModelName(Name), ModelDef(MDef), ItinsDef(IDef) {}
197 bool hasInstrSchedModel() const {
198 return !WriteResDefs.empty() || !ItinRWDefs.empty();
201 unsigned getProcResourceIdx(Record *PRDef) const;
208 /// Top level container for machine model data.
209 class CodeGenSchedModels {
210 RecordKeeper &Records;
211 const CodeGenTarget &Target;
213 // Map dag expressions to Instruction lists.
216 // List of unique processor models.
217 std::vector<CodeGenProcModel> ProcModels;
219 // Map Processor's MachineModel or ProcItin to a CodeGenProcModel index.
220 typedef DenseMap<Record*, unsigned> ProcModelMapTy;
221 ProcModelMapTy ProcModelMap;
223 // Per-operand SchedReadWrite types.
224 std::vector<CodeGenSchedRW> SchedWrites;
225 std::vector<CodeGenSchedRW> SchedReads;
227 // List of unique SchedClasses.
228 std::vector<CodeGenSchedClass> SchedClasses;
230 // Map SchedClass name to itinerary index.
231 // These are either explicit itinerary classes or classes implied by
232 // instruction definitions with SchedReadWrite lists.
233 StringMap<unsigned> SchedClassIdxMap;
235 // SchedClass indices 1 up to and including NumItineraryClasses identify
236 // itinerary classes that are explicitly used for this target's instruction
237 // definitions. NoItinerary always has index 0 regardless of whether it is
238 // explicitly referenced.
240 // Any implied SchedClass has an index greater than NumItineraryClasses.
241 unsigned NumItineraryClasses;
243 // Any inferred SchedClass has an index greater than NumInstrSchedClassses.
244 unsigned NumInstrSchedClasses;
246 // Map Instruction to SchedClass index. Only for Instructions mentioned in
248 typedef DenseMap<Record*, unsigned> InstClassMapTy;
249 InstClassMapTy InstrClassMap;
252 CodeGenSchedModels(RecordKeeper& RK, const CodeGenTarget &TGT);
254 Record *getModelOrItinDef(Record *ProcDef) const {
255 Record *ModelDef = ProcDef->getValueAsDef("SchedModel");
256 Record *ItinsDef = ProcDef->getValueAsDef("ProcItin");
257 if (!ItinsDef->getValueAsListOfDefs("IID").empty()) {
258 assert(ModelDef->getValueAsBit("NoModel")
259 && "Itineraries must be defined within SchedMachineModel");
265 const CodeGenProcModel &getModelForProc(Record *ProcDef) const {
266 Record *ModelDef = getModelOrItinDef(ProcDef);
267 ProcModelMapTy::const_iterator I = ProcModelMap.find(ModelDef);
268 assert(I != ProcModelMap.end() && "missing machine model");
269 return ProcModels[I->second];
272 const CodeGenProcModel &getProcModel(Record *ModelDef) const {
273 ProcModelMapTy::const_iterator I = ProcModelMap.find(ModelDef);
274 assert(I != ProcModelMap.end() && "missing machine model");
275 return ProcModels[I->second];
278 // Iterate over the unique processor models.
279 typedef std::vector<CodeGenProcModel>::const_iterator ProcIter;
280 ProcIter procModelBegin() const { return ProcModels.begin(); }
281 ProcIter procModelEnd() const { return ProcModels.end(); }
283 // Get a SchedWrite from its index.
284 const CodeGenSchedRW &getSchedWrite(unsigned Idx) const {
285 assert(Idx < SchedWrites.size() && "bad SchedWrite index");
286 assert(SchedWrites[Idx].isValid() && "invalid SchedWrite");
287 return SchedWrites[Idx];
289 // Get a SchedWrite from its index.
290 const CodeGenSchedRW &getSchedRead(unsigned Idx) const {
291 assert(Idx < SchedReads.size() && "bad SchedRead index");
292 assert(SchedReads[Idx].isValid() && "invalid SchedRead");
293 return SchedReads[Idx];
296 const CodeGenSchedRW &getSchedRW(unsigned Idx, bool IsRead) const {
297 return IsRead ? getSchedRead(Idx) : getSchedWrite(Idx);
299 CodeGenSchedRW &getSchedRW(Record *Def) {
300 bool IsRead = Def->isSubClassOf("SchedRead");
301 unsigned Idx = getSchedRWIdx(Def, IsRead);
302 return const_cast<CodeGenSchedRW&>(
303 IsRead ? getSchedRead(Idx) : getSchedWrite(Idx));
305 const CodeGenSchedRW &getSchedRW(Record*Def) const {
306 return const_cast<CodeGenSchedModels&>(*this).getSchedRW(Def);
309 unsigned getSchedRWIdx(Record *Def, bool IsRead, unsigned After = 0) const;
311 // Return true if the given write record is referenced by a ReadAdvance.
312 bool hasReadOfWrite(Record *WriteDef) const;
314 // Check if any instructions are assigned to an explicit itinerary class other
316 bool hasItineraryClasses() const { return NumItineraryClasses > 0; }
318 // Return the number of itinerary classes in use by this target's instruction
319 // descriptions, not including "NoItinerary".
320 unsigned numItineraryClasses() const {
321 return NumItineraryClasses;
324 // Get a SchedClass from its index.
325 CodeGenSchedClass &getSchedClass(unsigned Idx) {
326 assert(Idx < SchedClasses.size() && "bad SchedClass index");
327 return SchedClasses[Idx];
329 const CodeGenSchedClass &getSchedClass(unsigned Idx) const {
330 assert(Idx < SchedClasses.size() && "bad SchedClass index");
331 return SchedClasses[Idx];
334 // Get the SchedClass index for an instruction. Instructions with no
335 // itinerary, no SchedReadWrites, and no InstrReadWrites references return 0
337 unsigned getSchedClassIdx(const CodeGenInstruction &Inst) const;
339 unsigned getSchedClassIdx(const RecVec &RWDefs) const;
341 unsigned getSchedClassIdxForItin(const Record *ItinDef) {
342 return SchedClassIdxMap[ItinDef->getName()];
345 typedef std::vector<CodeGenSchedClass>::const_iterator SchedClassIter;
346 SchedClassIter schedClassBegin() const { return SchedClasses.begin(); }
347 SchedClassIter schedClassEnd() const { return SchedClasses.end(); }
349 void findRWs(const RecVec &RWDefs, IdxVec &Writes, IdxVec &Reads) const;
350 void findRWs(const RecVec &RWDefs, IdxVec &RWs, bool IsRead) const;
351 void expandRWSequence(unsigned RWIdx, IdxVec &RWSeq, bool IsRead) const;
352 void expandRWSeqForProc(unsigned RWIdx, IdxVec &RWSeq, bool IsRead,
353 const CodeGenProcModel &ProcModel) const;
355 unsigned addSchedClass(const IdxVec &OperWrites, const IdxVec &OperReads,
356 const IdxVec &ProcIndices);
358 unsigned findOrInsertRW(ArrayRef<unsigned> Seq, bool IsRead);
360 unsigned findSchedClassIdx(const IdxVec &Writes, const IdxVec &Reads) const;
362 Record *findProcResUnits(Record *ProcResKind,
363 const CodeGenProcModel &PM) const;
366 void collectProcModels();
368 // Initialize a new processor model if it is unique.
369 void addProcModel(Record *ProcDef);
371 void collectSchedRW();
373 std::string genRWName(const IdxVec& Seq, bool IsRead);
374 unsigned findRWForSequence(const IdxVec &Seq, bool IsRead);
376 void collectSchedClasses();
378 std::string createSchedClassName(const IdxVec &OperWrites,
379 const IdxVec &OperReads);
380 std::string createSchedClassName(const RecVec &InstDefs);
381 void createInstRWClass(Record *InstRWDef);
383 void collectProcItins();
385 void collectProcItinRW();
387 void inferSchedClasses();
389 void inferFromRW(const IdxVec &OperWrites, const IdxVec &OperReads,
390 unsigned FromClassIdx, const IdxVec &ProcIndices);
391 void inferFromItinClass(Record *ItinClassDef, unsigned FromClassIdx);
392 void inferFromInstRWs(unsigned SCIdx);
394 void collectProcResources();
396 void collectItinProcResources(Record *ItinClassDef);
398 void collectRWResources(unsigned RWIdx, bool IsRead,
399 const IdxVec &ProcIndices);
401 void collectRWResources(const IdxVec &Writes, const IdxVec &Reads,
402 const IdxVec &ProcIndices);
404 void addProcResource(Record *ProcResourceKind, CodeGenProcModel &PM);
406 void addWriteRes(Record *ProcWriteResDef, unsigned PIdx);
408 void addReadAdvance(Record *ProcReadAdvanceDef, unsigned PIdx);