1 //===- CodeGenSchedule.h - Scheduling Machine Models ------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines structures to encapsulate the machine model as described in
11 // the target description.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_UTILS_TABLEGEN_CODEGENSCHEDULE_H
16 #define LLVM_UTILS_TABLEGEN_CODEGENSCHEDULE_H
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/StringMap.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/TableGen/Record.h"
22 #include "llvm/TableGen/SetTheory.h"
27 class CodeGenSchedModels;
28 class CodeGenInstruction;
30 typedef std::vector<Record*> RecVec;
31 typedef std::vector<Record*>::const_iterator RecIter;
33 typedef std::vector<unsigned> IdxVec;
34 typedef std::vector<unsigned>::const_iterator IdxIter;
36 void splitSchedReadWrites(const RecVec &RWDefs,
37 RecVec &WriteDefs, RecVec &ReadDefs);
39 /// We have two kinds of SchedReadWrites. Explicitly defined and inferred
40 /// sequences. TheDef is nonnull for explicit SchedWrites, but Sequence may or
41 /// may not be empty. TheDef is null for inferred sequences, and Sequence must
44 /// IsVariadic controls whether the variants are expanded into multiple operands
45 /// or a sequence of writes on one operand.
46 struct CodeGenSchedRW {
59 : Index(0), TheDef(nullptr), IsRead(false), IsAlias(false),
60 HasVariants(false), IsVariadic(false), IsSequence(false) {}
61 CodeGenSchedRW(unsigned Idx, Record *Def)
62 : Index(Idx), TheDef(Def), IsAlias(false), IsVariadic(false) {
63 Name = Def->getName();
64 IsRead = Def->isSubClassOf("SchedRead");
65 HasVariants = Def->isSubClassOf("SchedVariant");
67 IsVariadic = Def->getValueAsBit("Variadic");
69 // Read records don't currently have sequences, but it can be easily
70 // added. Note that implicit Reads (from ReadVariant) may have a Sequence
72 IsSequence = Def->isSubClassOf("WriteSequence");
75 CodeGenSchedRW(unsigned Idx, bool Read, ArrayRef<unsigned> Seq,
76 const std::string &Name)
77 : Index(Idx), Name(Name), TheDef(nullptr), IsRead(Read), IsAlias(false),
78 HasVariants(false), IsVariadic(false), IsSequence(true), Sequence(Seq) {
79 assert(Sequence.size() > 1 && "implied sequence needs >1 RWs");
82 bool isValid() const {
83 assert((!HasVariants || TheDef) && "Variant write needs record def");
84 assert((!IsVariadic || HasVariants) && "Variadic write needs variants");
85 assert((!IsSequence || !HasVariants) && "Sequence can't have variant");
86 assert((!IsSequence || !Sequence.empty()) && "Sequence should be nonempty");
87 assert((!IsAlias || Aliases.empty()) && "Alias cannot have aliases");
88 return TheDef || !Sequence.empty();
96 /// Represent a transition between SchedClasses induced by SchedVariant.
97 struct CodeGenSchedTransition {
103 /// Scheduling class.
105 /// Each instruction description will be mapped to a scheduling class. There are
106 /// four types of classes:
108 /// 1) An explicitly defined itinerary class with ItinClassDef set.
109 /// Writes and ReadDefs are empty. ProcIndices contains 0 for any processor.
111 /// 2) An implied class with a list of SchedWrites and SchedReads that are
112 /// defined in an instruction definition and which are common across all
113 /// subtargets. ProcIndices contains 0 for any processor.
115 /// 3) An implied class with a list of InstRW records that map instructions to
116 /// SchedWrites and SchedReads per-processor. InstrClassMap should map the same
117 /// instructions to this class. ProcIndices contains all the processors that
118 /// provided InstrRW records for this class. ItinClassDef or Writes/Reads may
119 /// still be defined for processors with no InstRW entry.
121 /// 4) An inferred class represents a variant of another class that may be
122 /// resolved at runtime. ProcIndices contains the set of processors that may
123 /// require the class. ProcIndices are propagated through SchedClasses as
124 /// variants are expanded. Multiple SchedClasses may be inferred from an
125 /// itinerary class. Each inherits the processor index from the ItinRW record
126 /// that mapped the itinerary class to the variant Writes or Reads.
127 struct CodeGenSchedClass {
130 Record *ItinClassDef;
134 // Sorted list of ProcIdx, where ProcIdx==0 implies any processor.
137 std::vector<CodeGenSchedTransition> Transitions;
139 // InstRW records associated with this class. These records may refer to an
140 // Instruction no longer mapped to this class by InstrClassMap. These
141 // Instructions should be ignored by this class because they have been split
142 // off to join another inferred class.
145 CodeGenSchedClass(): Index(0), ItinClassDef(nullptr) {}
147 bool isKeyEqual(Record *IC, ArrayRef<unsigned> W, ArrayRef<unsigned> R) {
148 return ItinClassDef == IC && makeArrayRef(Writes) == W &&
149 makeArrayRef(Reads) == R;
152 // Is this class generated from a variants if existing classes? Instructions
153 // are never mapped directly to inferred scheduling classes.
154 bool isInferred() const { return !ItinClassDef; }
157 void dump(const CodeGenSchedModels *SchedModels) const;
163 // ModelName is a unique name used to name an instantiation of MCSchedModel.
165 // ModelDef is NULL for inferred Models. This happens when a processor defines
166 // an itinerary but no machine model. If the processor defines neither a machine
167 // model nor itinerary, then ModelDef remains pointing to NoModel. NoModel has
168 // the special "NoModel" field set to true.
170 // ItinsDef always points to a valid record definition, but may point to the
171 // default NoItineraries. NoItineraries has an empty list of InstrItinData
174 // ItinDefList orders this processor's InstrItinData records by SchedClass idx.
175 struct CodeGenProcModel {
177 std::string ModelName;
181 // Derived members...
183 // Array of InstrItinData records indexed by a CodeGenSchedClass index.
184 // This list is empty if the Processor has no value for Itineraries.
185 // Initialized by collectProcItins().
188 // Map itinerary classes to per-operand resources.
189 // This list is empty if no ItinRW refers to this Processor.
192 // All read/write resources associated with this processor.
194 RecVec ReadAdvanceDefs;
196 // Per-operand machine model resources associated with this processor.
197 RecVec ProcResourceDefs;
198 RecVec ProcResGroupDefs;
200 CodeGenProcModel(unsigned Idx, const std::string &Name, Record *MDef,
202 Index(Idx), ModelName(Name), ModelDef(MDef), ItinsDef(IDef) {}
204 bool hasItineraries() const {
205 return !ItinsDef->getValueAsListOfDefs("IID").empty();
208 bool hasInstrSchedModel() const {
209 return !WriteResDefs.empty() || !ItinRWDefs.empty();
212 unsigned getProcResourceIdx(Record *PRDef) const;
219 /// Top level container for machine model data.
220 class CodeGenSchedModels {
221 RecordKeeper &Records;
222 const CodeGenTarget &Target;
224 // Map dag expressions to Instruction lists.
227 // List of unique processor models.
228 std::vector<CodeGenProcModel> ProcModels;
230 // Map Processor's MachineModel or ProcItin to a CodeGenProcModel index.
231 typedef DenseMap<Record*, unsigned> ProcModelMapTy;
232 ProcModelMapTy ProcModelMap;
234 // Per-operand SchedReadWrite types.
235 std::vector<CodeGenSchedRW> SchedWrites;
236 std::vector<CodeGenSchedRW> SchedReads;
238 // List of unique SchedClasses.
239 std::vector<CodeGenSchedClass> SchedClasses;
241 // Any inferred SchedClass has an index greater than NumInstrSchedClassses.
242 unsigned NumInstrSchedClasses;
244 // Map each instruction to its unique SchedClass index considering the
245 // combination of it's itinerary class, SchedRW list, and InstRW records.
246 typedef DenseMap<Record*, unsigned> InstClassMapTy;
247 InstClassMapTy InstrClassMap;
250 CodeGenSchedModels(RecordKeeper& RK, const CodeGenTarget &TGT);
252 // iterator access to the scheduling classes.
253 typedef std::vector<CodeGenSchedClass>::iterator class_iterator;
254 typedef std::vector<CodeGenSchedClass>::const_iterator const_class_iterator;
255 class_iterator classes_begin() { return SchedClasses.begin(); }
256 const_class_iterator classes_begin() const { return SchedClasses.begin(); }
257 class_iterator classes_end() { return SchedClasses.end(); }
258 const_class_iterator classes_end() const { return SchedClasses.end(); }
259 iterator_range<class_iterator> classes() {
260 return make_range(classes_begin(), classes_end());
262 iterator_range<const_class_iterator> classes() const {
263 return make_range(classes_begin(), classes_end());
265 iterator_range<class_iterator> explicit_classes() {
266 return make_range(classes_begin(), classes_begin() + NumInstrSchedClasses);
268 iterator_range<const_class_iterator> explicit_classes() const {
269 return make_range(classes_begin(), classes_begin() + NumInstrSchedClasses);
272 Record *getModelOrItinDef(Record *ProcDef) const {
273 Record *ModelDef = ProcDef->getValueAsDef("SchedModel");
274 Record *ItinsDef = ProcDef->getValueAsDef("ProcItin");
275 if (!ItinsDef->getValueAsListOfDefs("IID").empty()) {
276 assert(ModelDef->getValueAsBit("NoModel")
277 && "Itineraries must be defined within SchedMachineModel");
283 const CodeGenProcModel &getModelForProc(Record *ProcDef) const {
284 Record *ModelDef = getModelOrItinDef(ProcDef);
285 ProcModelMapTy::const_iterator I = ProcModelMap.find(ModelDef);
286 assert(I != ProcModelMap.end() && "missing machine model");
287 return ProcModels[I->second];
290 CodeGenProcModel &getProcModel(Record *ModelDef) {
291 ProcModelMapTy::const_iterator I = ProcModelMap.find(ModelDef);
292 assert(I != ProcModelMap.end() && "missing machine model");
293 return ProcModels[I->second];
295 const CodeGenProcModel &getProcModel(Record *ModelDef) const {
296 return const_cast<CodeGenSchedModels*>(this)->getProcModel(ModelDef);
299 // Iterate over the unique processor models.
300 typedef std::vector<CodeGenProcModel>::const_iterator ProcIter;
301 ProcIter procModelBegin() const { return ProcModels.begin(); }
302 ProcIter procModelEnd() const { return ProcModels.end(); }
304 // Return true if any processors have itineraries.
305 bool hasItineraries() const;
307 // Get a SchedWrite from its index.
308 const CodeGenSchedRW &getSchedWrite(unsigned Idx) const {
309 assert(Idx < SchedWrites.size() && "bad SchedWrite index");
310 assert(SchedWrites[Idx].isValid() && "invalid SchedWrite");
311 return SchedWrites[Idx];
313 // Get a SchedWrite from its index.
314 const CodeGenSchedRW &getSchedRead(unsigned Idx) const {
315 assert(Idx < SchedReads.size() && "bad SchedRead index");
316 assert(SchedReads[Idx].isValid() && "invalid SchedRead");
317 return SchedReads[Idx];
320 const CodeGenSchedRW &getSchedRW(unsigned Idx, bool IsRead) const {
321 return IsRead ? getSchedRead(Idx) : getSchedWrite(Idx);
323 CodeGenSchedRW &getSchedRW(Record *Def) {
324 bool IsRead = Def->isSubClassOf("SchedRead");
325 unsigned Idx = getSchedRWIdx(Def, IsRead);
326 return const_cast<CodeGenSchedRW&>(
327 IsRead ? getSchedRead(Idx) : getSchedWrite(Idx));
329 const CodeGenSchedRW &getSchedRW(Record*Def) const {
330 return const_cast<CodeGenSchedModels&>(*this).getSchedRW(Def);
333 unsigned getSchedRWIdx(Record *Def, bool IsRead, unsigned After = 0) const;
335 // Return true if the given write record is referenced by a ReadAdvance.
336 bool hasReadOfWrite(Record *WriteDef) const;
338 // Get a SchedClass from its index.
339 CodeGenSchedClass &getSchedClass(unsigned Idx) {
340 assert(Idx < SchedClasses.size() && "bad SchedClass index");
341 return SchedClasses[Idx];
343 const CodeGenSchedClass &getSchedClass(unsigned Idx) const {
344 assert(Idx < SchedClasses.size() && "bad SchedClass index");
345 return SchedClasses[Idx];
348 // Get the SchedClass index for an instruction. Instructions with no
349 // itinerary, no SchedReadWrites, and no InstrReadWrites references return 0
351 unsigned getSchedClassIdx(const CodeGenInstruction &Inst) const;
353 typedef std::vector<CodeGenSchedClass>::const_iterator SchedClassIter;
354 SchedClassIter schedClassBegin() const { return SchedClasses.begin(); }
355 SchedClassIter schedClassEnd() const { return SchedClasses.end(); }
357 unsigned numInstrSchedClasses() const { return NumInstrSchedClasses; }
359 void findRWs(const RecVec &RWDefs, IdxVec &Writes, IdxVec &Reads) const;
360 void findRWs(const RecVec &RWDefs, IdxVec &RWs, bool IsRead) const;
361 void expandRWSequence(unsigned RWIdx, IdxVec &RWSeq, bool IsRead) const;
362 void expandRWSeqForProc(unsigned RWIdx, IdxVec &RWSeq, bool IsRead,
363 const CodeGenProcModel &ProcModel) const;
365 unsigned addSchedClass(Record *ItinDef, ArrayRef<unsigned> OperWrites,
366 ArrayRef<unsigned> OperReads,
367 ArrayRef<unsigned> ProcIndices);
369 unsigned findOrInsertRW(ArrayRef<unsigned> Seq, bool IsRead);
371 unsigned findSchedClassIdx(Record *ItinClassDef, ArrayRef<unsigned> Writes,
372 ArrayRef<unsigned> Reads) const;
374 Record *findProcResUnits(Record *ProcResKind,
375 const CodeGenProcModel &PM) const;
378 void collectProcModels();
380 // Initialize a new processor model if it is unique.
381 void addProcModel(Record *ProcDef);
383 void collectSchedRW();
385 std::string genRWName(ArrayRef<unsigned> Seq, bool IsRead);
386 unsigned findRWForSequence(ArrayRef<unsigned> Seq, bool IsRead);
388 void collectSchedClasses();
390 std::string createSchedClassName(Record *ItinClassDef,
391 ArrayRef<unsigned> OperWrites,
392 ArrayRef<unsigned> OperReads);
393 std::string createSchedClassName(const RecVec &InstDefs);
394 void createInstRWClass(Record *InstRWDef);
396 void collectProcItins();
398 void collectProcItinRW();
400 void inferSchedClasses();
402 void inferFromRW(ArrayRef<unsigned> OperWrites, ArrayRef<unsigned> OperReads,
403 unsigned FromClassIdx, ArrayRef<unsigned> ProcIndices);
404 void inferFromItinClass(Record *ItinClassDef, unsigned FromClassIdx);
405 void inferFromInstRWs(unsigned SCIdx);
407 bool hasSuperGroup(RecVec &SubUnits, CodeGenProcModel &PM);
408 void verifyProcResourceGroups(CodeGenProcModel &PM);
410 void collectProcResources();
412 void collectItinProcResources(Record *ItinClassDef);
414 void collectRWResources(unsigned RWIdx, bool IsRead,
415 ArrayRef<unsigned> ProcIndices);
417 void collectRWResources(ArrayRef<unsigned> Writes, ArrayRef<unsigned> Reads,
418 ArrayRef<unsigned> ProcIndices);
420 void addProcResource(Record *ProcResourceKind, CodeGenProcModel &PM);
422 void addWriteRes(Record *ProcWriteResDef, unsigned PIdx);
424 void addReadAdvance(Record *ProcReadAdvanceDef, unsigned PIdx);