1 //===- CodeGenSchedule.h - Scheduling Machine Models ------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines structures to encapsulate the machine model as decribed in
11 // the target description.
13 //===----------------------------------------------------------------------===//
15 #ifndef CODEGEN_SCHEDULE_H
16 #define CODEGEN_SCHEDULE_H
18 #include "SetTheory.h"
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/ADT/StringMap.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/TableGen/Record.h"
27 class CodeGenSchedModels;
28 class CodeGenInstruction;
30 typedef std::vector<Record*> RecVec;
31 typedef std::vector<Record*>::const_iterator RecIter;
33 typedef std::vector<unsigned> IdxVec;
34 typedef std::vector<unsigned>::const_iterator IdxIter;
36 void splitSchedReadWrites(const RecVec &RWDefs,
37 RecVec &WriteDefs, RecVec &ReadDefs);
39 /// We have two kinds of SchedReadWrites. Explicitly defined and inferred
40 /// sequences. TheDef is nonnull for explicit SchedWrites, but Sequence may or
41 /// may not be empty. TheDef is null for inferred sequences, and Sequence must
44 /// IsVariadic controls whether the variants are expanded into multiple operands
45 /// or a sequence of writes on one operand.
46 struct CodeGenSchedRW {
59 : Index(0), TheDef(0), IsRead(false), IsAlias(false),
60 HasVariants(false), IsVariadic(false), IsSequence(false) {}
61 CodeGenSchedRW(unsigned Idx, Record *Def)
62 : Index(Idx), TheDef(Def), IsAlias(false), IsVariadic(false) {
63 Name = Def->getName();
64 IsRead = Def->isSubClassOf("SchedRead");
65 HasVariants = Def->isSubClassOf("SchedVariant");
67 IsVariadic = Def->getValueAsBit("Variadic");
69 // Read records don't currently have sequences, but it can be easily
70 // added. Note that implicit Reads (from ReadVariant) may have a Sequence
72 IsSequence = Def->isSubClassOf("WriteSequence");
75 CodeGenSchedRW(unsigned Idx, bool Read, const IdxVec &Seq,
76 const std::string &Name)
77 : Index(Idx), Name(Name), TheDef(0), IsRead(Read), IsAlias(false),
78 HasVariants(false), IsVariadic(false), IsSequence(true), Sequence(Seq) {
79 assert(Sequence.size() > 1 && "implied sequence needs >1 RWs");
82 bool isValid() const {
83 assert((!HasVariants || TheDef) && "Variant write needs record def");
84 assert((!IsVariadic || HasVariants) && "Variadic write needs variants");
85 assert((!IsSequence || !HasVariants) && "Sequence can't have variant");
86 assert((!IsSequence || !Sequence.empty()) && "Sequence should be nonempty");
87 assert((!IsAlias || Aliases.empty()) && "Alias cannot have aliases");
88 return TheDef || !Sequence.empty();
96 /// Represent a transition between SchedClasses induced by SchedVariant.
97 struct CodeGenSchedTransition {
103 /// Scheduling class.
105 /// Each instruction description will be mapped to a scheduling class. There are
106 /// four types of classes:
108 /// 1) An explicitly defined itinerary class with ItinClassDef set.
109 /// Writes and ReadDefs are empty. ProcIndices contains 0 for any processor.
111 /// 2) An implied class with a list of SchedWrites and SchedReads that are
112 /// defined in an instruction definition and which are common across all
113 /// subtargets. ProcIndices contains 0 for any processor.
115 /// 3) An implied class with a list of InstRW records that map instructions to
116 /// SchedWrites and SchedReads per-processor. InstrClassMap should map the same
117 /// instructions to this class. ProcIndices contains all the processors that
118 /// provided InstrRW records for this class. ItinClassDef or Writes/Reads may
119 /// still be defined for processors with no InstRW entry.
121 /// 4) An inferred class represents a variant of another class that may be
122 /// resolved at runtime. ProcIndices contains the set of processors that may
123 /// require the class. ProcIndices are propagated through SchedClasses as
124 /// variants are expanded. Multiple SchedClasses may be inferred from an
125 /// itinerary class. Each inherits the processor index from the ItinRW record
126 /// that mapped the itinerary class to the variant Writes or Reads.
127 struct CodeGenSchedClass {
130 Record *ItinClassDef;
134 // Sorted list of ProcIdx, where ProcIdx==0 implies any processor.
137 std::vector<CodeGenSchedTransition> Transitions;
139 // InstRW records associated with this class. These records may refer to an
140 // Instruction no longer mapped to this class by InstrClassMap. These
141 // Instructions should be ignored by this class because they have been split
142 // off to join another inferred class.
145 CodeGenSchedClass(): Index(0), ItinClassDef(0) {}
147 bool isKeyEqual(Record *IC, const IdxVec &W, const IdxVec &R) {
148 return ItinClassDef == IC && Writes == W && Reads == R;
151 // Is this class generated from a variants if existing classes? Instructions
152 // are never mapped directly to inferred scheduling classes.
153 bool isInferred() const { return !ItinClassDef; }
156 void dump(const CodeGenSchedModels *SchedModels) const;
162 // ModelName is a unique name used to name an instantiation of MCSchedModel.
164 // ModelDef is NULL for inferred Models. This happens when a processor defines
165 // an itinerary but no machine model. If the processer defines neither a machine
166 // model nor itinerary, then ModelDef remains pointing to NoModel. NoModel has
167 // the special "NoModel" field set to true.
169 // ItinsDef always points to a valid record definition, but may point to the
170 // default NoItineraries. NoItineraries has an empty list of InstrItinData
173 // ItinDefList orders this processor's InstrItinData records by SchedClass idx.
174 struct CodeGenProcModel {
176 std::string ModelName;
180 // Derived members...
182 // Array of InstrItinData records indexed by a CodeGenSchedClass index.
183 // This list is empty if the Processor has no value for Itineraries.
184 // Initialized by collectProcItins().
187 // Map itinerary classes to per-operand resources.
188 // This list is empty if no ItinRW refers to this Processor.
191 // All read/write resources associated with this processor.
193 RecVec ReadAdvanceDefs;
195 // Per-operand machine model resources associated with this processor.
196 RecVec ProcResourceDefs;
197 RecVec ProcResGroupDefs;
199 CodeGenProcModel(unsigned Idx, const std::string &Name, Record *MDef,
201 Index(Idx), ModelName(Name), ModelDef(MDef), ItinsDef(IDef) {}
203 bool hasItineraries() const {
204 return !ItinsDef->getValueAsListOfDefs("IID").empty();
207 bool hasInstrSchedModel() const {
208 return !WriteResDefs.empty() || !ItinRWDefs.empty();
211 unsigned getProcResourceIdx(Record *PRDef) const;
218 /// Top level container for machine model data.
219 class CodeGenSchedModels {
220 RecordKeeper &Records;
221 const CodeGenTarget &Target;
223 // Map dag expressions to Instruction lists.
226 // List of unique processor models.
227 std::vector<CodeGenProcModel> ProcModels;
229 // Map Processor's MachineModel or ProcItin to a CodeGenProcModel index.
230 typedef DenseMap<Record*, unsigned> ProcModelMapTy;
231 ProcModelMapTy ProcModelMap;
233 // Per-operand SchedReadWrite types.
234 std::vector<CodeGenSchedRW> SchedWrites;
235 std::vector<CodeGenSchedRW> SchedReads;
237 // List of unique SchedClasses.
238 std::vector<CodeGenSchedClass> SchedClasses;
240 // Any inferred SchedClass has an index greater than NumInstrSchedClassses.
241 unsigned NumInstrSchedClasses;
243 // Map each instruction to its unique SchedClass index considering the
244 // combination of it's itinerary class, SchedRW list, and InstRW records.
245 typedef DenseMap<Record*, unsigned> InstClassMapTy;
246 InstClassMapTy InstrClassMap;
249 CodeGenSchedModels(RecordKeeper& RK, const CodeGenTarget &TGT);
251 Record *getModelOrItinDef(Record *ProcDef) const {
252 Record *ModelDef = ProcDef->getValueAsDef("SchedModel");
253 Record *ItinsDef = ProcDef->getValueAsDef("ProcItin");
254 if (!ItinsDef->getValueAsListOfDefs("IID").empty()) {
255 assert(ModelDef->getValueAsBit("NoModel")
256 && "Itineraries must be defined within SchedMachineModel");
262 const CodeGenProcModel &getModelForProc(Record *ProcDef) const {
263 Record *ModelDef = getModelOrItinDef(ProcDef);
264 ProcModelMapTy::const_iterator I = ProcModelMap.find(ModelDef);
265 assert(I != ProcModelMap.end() && "missing machine model");
266 return ProcModels[I->second];
269 CodeGenProcModel &getProcModel(Record *ModelDef) {
270 ProcModelMapTy::const_iterator I = ProcModelMap.find(ModelDef);
271 assert(I != ProcModelMap.end() && "missing machine model");
272 return ProcModels[I->second];
274 const CodeGenProcModel &getProcModel(Record *ModelDef) const {
275 return const_cast<CodeGenSchedModels*>(this)->getProcModel(ModelDef);
278 // Iterate over the unique processor models.
279 typedef std::vector<CodeGenProcModel>::const_iterator ProcIter;
280 ProcIter procModelBegin() const { return ProcModels.begin(); }
281 ProcIter procModelEnd() const { return ProcModels.end(); }
283 // Return true if any processors have itineraries.
284 bool hasItineraries() const;
286 // Get a SchedWrite from its index.
287 const CodeGenSchedRW &getSchedWrite(unsigned Idx) const {
288 assert(Idx < SchedWrites.size() && "bad SchedWrite index");
289 assert(SchedWrites[Idx].isValid() && "invalid SchedWrite");
290 return SchedWrites[Idx];
292 // Get a SchedWrite from its index.
293 const CodeGenSchedRW &getSchedRead(unsigned Idx) const {
294 assert(Idx < SchedReads.size() && "bad SchedRead index");
295 assert(SchedReads[Idx].isValid() && "invalid SchedRead");
296 return SchedReads[Idx];
299 const CodeGenSchedRW &getSchedRW(unsigned Idx, bool IsRead) const {
300 return IsRead ? getSchedRead(Idx) : getSchedWrite(Idx);
302 CodeGenSchedRW &getSchedRW(Record *Def) {
303 bool IsRead = Def->isSubClassOf("SchedRead");
304 unsigned Idx = getSchedRWIdx(Def, IsRead);
305 return const_cast<CodeGenSchedRW&>(
306 IsRead ? getSchedRead(Idx) : getSchedWrite(Idx));
308 const CodeGenSchedRW &getSchedRW(Record*Def) const {
309 return const_cast<CodeGenSchedModels&>(*this).getSchedRW(Def);
312 unsigned getSchedRWIdx(Record *Def, bool IsRead, unsigned After = 0) const;
314 // Return true if the given write record is referenced by a ReadAdvance.
315 bool hasReadOfWrite(Record *WriteDef) const;
317 // Get a SchedClass from its index.
318 CodeGenSchedClass &getSchedClass(unsigned Idx) {
319 assert(Idx < SchedClasses.size() && "bad SchedClass index");
320 return SchedClasses[Idx];
322 const CodeGenSchedClass &getSchedClass(unsigned Idx) const {
323 assert(Idx < SchedClasses.size() && "bad SchedClass index");
324 return SchedClasses[Idx];
327 // Get the SchedClass index for an instruction. Instructions with no
328 // itinerary, no SchedReadWrites, and no InstrReadWrites references return 0
330 unsigned getSchedClassIdx(const CodeGenInstruction &Inst) const;
332 typedef std::vector<CodeGenSchedClass>::const_iterator SchedClassIter;
333 SchedClassIter schedClassBegin() const { return SchedClasses.begin(); }
334 SchedClassIter schedClassEnd() const { return SchedClasses.end(); }
336 unsigned numInstrSchedClasses() const { return NumInstrSchedClasses; }
338 void findRWs(const RecVec &RWDefs, IdxVec &Writes, IdxVec &Reads) const;
339 void findRWs(const RecVec &RWDefs, IdxVec &RWs, bool IsRead) const;
340 void expandRWSequence(unsigned RWIdx, IdxVec &RWSeq, bool IsRead) const;
341 void expandRWSeqForProc(unsigned RWIdx, IdxVec &RWSeq, bool IsRead,
342 const CodeGenProcModel &ProcModel) const;
344 unsigned addSchedClass(Record *ItinDef, const IdxVec &OperWrites,
345 const IdxVec &OperReads, const IdxVec &ProcIndices);
347 unsigned findOrInsertRW(ArrayRef<unsigned> Seq, bool IsRead);
349 unsigned findSchedClassIdx(Record *ItinClassDef,
350 const IdxVec &Writes,
351 const IdxVec &Reads) const;
353 Record *findProcResUnits(Record *ProcResKind,
354 const CodeGenProcModel &PM) const;
357 void collectProcModels();
359 // Initialize a new processor model if it is unique.
360 void addProcModel(Record *ProcDef);
362 void collectSchedRW();
364 std::string genRWName(const IdxVec& Seq, bool IsRead);
365 unsigned findRWForSequence(const IdxVec &Seq, bool IsRead);
367 void collectSchedClasses();
369 std::string createSchedClassName(Record *ItinClassDef,
370 const IdxVec &OperWrites,
371 const IdxVec &OperReads);
372 std::string createSchedClassName(const RecVec &InstDefs);
373 void createInstRWClass(Record *InstRWDef);
375 void collectProcItins();
377 void collectProcItinRW();
379 void inferSchedClasses();
381 void inferFromRW(const IdxVec &OperWrites, const IdxVec &OperReads,
382 unsigned FromClassIdx, const IdxVec &ProcIndices);
383 void inferFromItinClass(Record *ItinClassDef, unsigned FromClassIdx);
384 void inferFromInstRWs(unsigned SCIdx);
386 bool hasSuperGroup(RecVec &SubUnits, CodeGenProcModel &PM);
387 void verifyProcResourceGroups(CodeGenProcModel &PM);
389 void collectProcResources();
391 void collectItinProcResources(Record *ItinClassDef);
393 void collectRWResources(unsigned RWIdx, bool IsRead,
394 const IdxVec &ProcIndices);
396 void collectRWResources(const IdxVec &Writes, const IdxVec &Reads,
397 const IdxVec &ProcIndices);
399 void addProcResource(Record *ProcResourceKind, CodeGenProcModel &PM);
401 void addWriteRes(Record *ProcWriteResDef, unsigned PIdx);
403 void addReadAdvance(Record *ProcReadAdvanceDef, unsigned PIdx);