1 //===- CodeGenTarget.cpp - CodeGen Target Class Wrapper -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class wraps target description classes used by the various code
11 // generation TableGen backends. This makes it easier to access the data and
12 // provides a single place that needs to check it for validity. All of these
13 // classes throw exceptions on error conditions.
15 //===----------------------------------------------------------------------===//
17 #include "CodeGenTarget.h"
18 #include "CodeGenIntrinsics.h"
20 #include "llvm/ADT/StringExtras.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/Support/CommandLine.h"
26 static cl::opt<unsigned>
27 AsmParserNum("asmparsernum", cl::init(0),
28 cl::desc("Make -gen-asm-parser emit assembly parser #N"));
30 static cl::opt<unsigned>
31 AsmWriterNum("asmwriternum", cl::init(0),
32 cl::desc("Make -gen-asm-writer emit assembly writer #N"));
34 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen
35 /// record corresponds to.
36 MVT::SimpleValueType llvm::getValueType(Record *Rec) {
37 return (MVT::SimpleValueType)Rec->getValueAsInt("Value");
40 std::string llvm::getName(MVT::SimpleValueType T) {
42 case MVT::Other: return "UNKNOWN";
43 case MVT::iPTR: return "TLI.getPointerTy()";
44 case MVT::iPTRAny: return "TLI.getPointerTy()";
45 default: return getEnumName(T);
49 std::string llvm::getEnumName(MVT::SimpleValueType T) {
51 case MVT::Other: return "MVT::Other";
52 case MVT::i1: return "MVT::i1";
53 case MVT::i8: return "MVT::i8";
54 case MVT::i16: return "MVT::i16";
55 case MVT::i32: return "MVT::i32";
56 case MVT::i64: return "MVT::i64";
57 case MVT::i128: return "MVT::i128";
58 case MVT::iAny: return "MVT::iAny";
59 case MVT::fAny: return "MVT::fAny";
60 case MVT::vAny: return "MVT::vAny";
61 case MVT::f32: return "MVT::f32";
62 case MVT::f64: return "MVT::f64";
63 case MVT::f80: return "MVT::f80";
64 case MVT::f128: return "MVT::f128";
65 case MVT::ppcf128: return "MVT::ppcf128";
66 case MVT::Flag: return "MVT::Flag";
67 case MVT::isVoid:return "MVT::isVoid";
68 case MVT::v2i8: return "MVT::v2i8";
69 case MVT::v4i8: return "MVT::v4i8";
70 case MVT::v8i8: return "MVT::v8i8";
71 case MVT::v16i8: return "MVT::v16i8";
72 case MVT::v32i8: return "MVT::v32i8";
73 case MVT::v2i16: return "MVT::v2i16";
74 case MVT::v4i16: return "MVT::v4i16";
75 case MVT::v8i16: return "MVT::v8i16";
76 case MVT::v16i16: return "MVT::v16i16";
77 case MVT::v2i32: return "MVT::v2i32";
78 case MVT::v4i32: return "MVT::v4i32";
79 case MVT::v8i32: return "MVT::v8i32";
80 case MVT::v1i64: return "MVT::v1i64";
81 case MVT::v2i64: return "MVT::v2i64";
82 case MVT::v4i64: return "MVT::v4i64";
83 case MVT::v2f32: return "MVT::v2f32";
84 case MVT::v4f32: return "MVT::v4f32";
85 case MVT::v8f32: return "MVT::v8f32";
86 case MVT::v2f64: return "MVT::v2f64";
87 case MVT::v4f64: return "MVT::v4f64";
88 case MVT::Metadata: return "MVT::Metadata";
89 case MVT::iPTR: return "MVT::iPTR";
90 case MVT::iPTRAny: return "MVT::iPTRAny";
91 default: assert(0 && "ILLEGAL VALUE TYPE!"); return "";
95 /// getQualifiedName - Return the name of the specified record, with a
96 /// namespace qualifier if the record contains one.
98 std::string llvm::getQualifiedName(const Record *R) {
99 std::string Namespace = R->getValueAsString("Namespace");
100 if (Namespace.empty()) return R->getName();
101 return Namespace + "::" + R->getName();
107 /// getTarget - Return the current instance of the Target class.
109 CodeGenTarget::CodeGenTarget() {
110 std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target");
111 if (Targets.size() == 0)
112 throw std::string("ERROR: No 'Target' subclasses defined!");
113 if (Targets.size() != 1)
114 throw std::string("ERROR: Multiple subclasses of Target defined!");
115 TargetRec = Targets[0];
119 const std::string &CodeGenTarget::getName() const {
120 return TargetRec->getName();
123 std::string CodeGenTarget::getInstNamespace() const {
124 for (inst_iterator i = inst_begin(), e = inst_end(); i != e; ++i) {
125 // Make sure not to pick up "TargetOpcode" by accidentally getting
126 // the namespace off the PHI instruction or something.
127 if ((*i)->Namespace != "TargetOpcode")
128 return (*i)->Namespace;
134 Record *CodeGenTarget::getInstructionSet() const {
135 return TargetRec->getValueAsDef("InstructionSet");
139 /// getAsmParser - Return the AssemblyParser definition for this target.
141 Record *CodeGenTarget::getAsmParser() const {
142 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyParsers");
143 if (AsmParserNum >= LI.size())
144 throw "Target does not have an AsmParser #" + utostr(AsmParserNum) + "!";
145 return LI[AsmParserNum];
148 /// getAsmWriter - Return the AssemblyWriter definition for this target.
150 Record *CodeGenTarget::getAsmWriter() const {
151 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters");
152 if (AsmWriterNum >= LI.size())
153 throw "Target does not have an AsmWriter #" + utostr(AsmWriterNum) + "!";
154 return LI[AsmWriterNum];
157 void CodeGenTarget::ReadRegisters() const {
158 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
160 throw std::string("No 'Register' subclasses defined!");
162 Registers.reserve(Regs.size());
163 Registers.assign(Regs.begin(), Regs.end());
166 CodeGenRegister::CodeGenRegister(Record *R) : TheDef(R) {
167 DeclaredSpillSize = R->getValueAsInt("SpillSize");
168 DeclaredSpillAlignment = R->getValueAsInt("SpillAlignment");
171 const std::string &CodeGenRegister::getName() const {
172 return TheDef->getName();
175 void CodeGenTarget::ReadRegisterClasses() const {
176 std::vector<Record*> RegClasses =
177 Records.getAllDerivedDefinitions("RegisterClass");
178 if (RegClasses.empty())
179 throw std::string("No 'RegisterClass' subclasses defined!");
181 RegisterClasses.reserve(RegClasses.size());
182 RegisterClasses.assign(RegClasses.begin(), RegClasses.end());
185 std::vector<MVT::SimpleValueType> CodeGenTarget::
186 getRegisterVTs(Record *R) const {
187 std::vector<MVT::SimpleValueType> Result;
188 const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses();
189 for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
190 const CodeGenRegisterClass &RC = RegisterClasses[i];
191 for (unsigned ei = 0, ee = RC.Elements.size(); ei != ee; ++ei) {
192 if (R == RC.Elements[ei]) {
193 const std::vector<MVT::SimpleValueType> &InVTs = RC.getValueTypes();
194 Result.insert(Result.end(), InVTs.begin(), InVTs.end());
199 // Remove duplicates.
200 array_pod_sort(Result.begin(), Result.end());
201 Result.erase(std::unique(Result.begin(), Result.end()), Result.end());
206 CodeGenRegisterClass::CodeGenRegisterClass(Record *R) : TheDef(R) {
207 // Rename anonymous register classes.
208 if (R->getName().size() > 9 && R->getName()[9] == '.') {
209 static unsigned AnonCounter = 0;
210 R->setName("AnonRegClass_"+utostr(AnonCounter++));
213 std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes");
214 for (unsigned i = 0, e = TypeList.size(); i != e; ++i) {
215 Record *Type = TypeList[i];
216 if (!Type->isSubClassOf("ValueType"))
217 throw "RegTypes list member '" + Type->getName() +
218 "' does not derive from the ValueType class!";
219 VTs.push_back(getValueType(Type));
221 assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!");
223 std::vector<Record*> RegList = R->getValueAsListOfDefs("MemberList");
224 for (unsigned i = 0, e = RegList.size(); i != e; ++i) {
225 Record *Reg = RegList[i];
226 if (!Reg->isSubClassOf("Register"))
227 throw "Register Class member '" + Reg->getName() +
228 "' does not derive from the Register class!";
229 Elements.push_back(Reg);
232 std::vector<Record*> SubRegClassList =
233 R->getValueAsListOfDefs("SubRegClassList");
234 for (unsigned i = 0, e = SubRegClassList.size(); i != e; ++i) {
235 Record *SubRegClass = SubRegClassList[i];
236 if (!SubRegClass->isSubClassOf("RegisterClass"))
237 throw "Register Class member '" + SubRegClass->getName() +
238 "' does not derive from the RegisterClass class!";
239 SubRegClasses.push_back(SubRegClass);
242 // Allow targets to override the size in bits of the RegisterClass.
243 unsigned Size = R->getValueAsInt("Size");
245 Namespace = R->getValueAsString("Namespace");
246 SpillSize = Size ? Size : EVT(VTs[0]).getSizeInBits();
247 SpillAlignment = R->getValueAsInt("Alignment");
248 CopyCost = R->getValueAsInt("CopyCost");
249 MethodBodies = R->getValueAsCode("MethodBodies");
250 MethodProtos = R->getValueAsCode("MethodProtos");
253 const std::string &CodeGenRegisterClass::getName() const {
254 return TheDef->getName();
257 void CodeGenTarget::ReadLegalValueTypes() const {
258 const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses();
259 for (unsigned i = 0, e = RCs.size(); i != e; ++i)
260 for (unsigned ri = 0, re = RCs[i].VTs.size(); ri != re; ++ri)
261 LegalValueTypes.push_back(RCs[i].VTs[ri]);
263 // Remove duplicates.
264 std::sort(LegalValueTypes.begin(), LegalValueTypes.end());
265 LegalValueTypes.erase(std::unique(LegalValueTypes.begin(),
266 LegalValueTypes.end()),
267 LegalValueTypes.end());
271 void CodeGenTarget::ReadInstructions() const {
272 std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
273 if (Insts.size() <= 2)
274 throw std::string("No 'Instruction' subclasses defined!");
276 // Parse the instructions defined in the .td file.
277 std::string InstFormatName =
278 getAsmWriter()->getValueAsString("InstFormatName");
280 for (unsigned i = 0, e = Insts.size(); i != e; ++i) {
281 std::string AsmStr = Insts[i]->getValueAsString(InstFormatName);
282 Instructions[Insts[i]] = new CodeGenInstruction(Insts[i], AsmStr);
286 static const CodeGenInstruction *
287 GetInstByName(const char *Name,
288 const DenseMap<const Record*, CodeGenInstruction*> &Insts) {
289 const Record *Rec = Records.getDef(Name);
291 DenseMap<const Record*, CodeGenInstruction*>::const_iterator
293 if (Rec == 0 || I == Insts.end())
294 throw std::string("Could not find '") + Name + "' instruction!";
299 /// SortInstByName - Sorting predicate to sort instructions by name.
301 struct SortInstByName {
302 bool operator()(const CodeGenInstruction *Rec1,
303 const CodeGenInstruction *Rec2) const {
304 return Rec1->TheDef->getName() < Rec2->TheDef->getName();
309 /// getInstructionsByEnumValue - Return all of the instructions defined by the
310 /// target, ordered by their enum value.
311 void CodeGenTarget::ComputeInstrsByEnum() const {
312 const DenseMap<const Record*, CodeGenInstruction*> &Insts = getInstructions();
313 const CodeGenInstruction *PHI = GetInstByName("PHI", Insts);
314 const CodeGenInstruction *INLINEASM = GetInstByName("INLINEASM", Insts);
315 const CodeGenInstruction *DBG_LABEL = GetInstByName("DBG_LABEL", Insts);
316 const CodeGenInstruction *EH_LABEL = GetInstByName("EH_LABEL", Insts);
317 const CodeGenInstruction *GC_LABEL = GetInstByName("GC_LABEL", Insts);
318 const CodeGenInstruction *KILL = GetInstByName("KILL", Insts);
319 const CodeGenInstruction *EXTRACT_SUBREG =
320 GetInstByName("EXTRACT_SUBREG", Insts);
321 const CodeGenInstruction *INSERT_SUBREG =
322 GetInstByName("INSERT_SUBREG", Insts);
323 const CodeGenInstruction *IMPLICIT_DEF = GetInstByName("IMPLICIT_DEF", Insts);
324 const CodeGenInstruction *SUBREG_TO_REG =
325 GetInstByName("SUBREG_TO_REG", Insts);
326 const CodeGenInstruction *COPY_TO_REGCLASS =
327 GetInstByName("COPY_TO_REGCLASS", Insts);
328 const CodeGenInstruction *DBG_VALUE = GetInstByName("DBG_VALUE", Insts);
329 const CodeGenInstruction *REG_SEQUENCE = GetInstByName("REG_SEQUENCE", Insts);
331 // Print out the rest of the instructions now.
332 InstrsByEnum.push_back(PHI);
333 InstrsByEnum.push_back(INLINEASM);
334 InstrsByEnum.push_back(DBG_LABEL);
335 InstrsByEnum.push_back(EH_LABEL);
336 InstrsByEnum.push_back(GC_LABEL);
337 InstrsByEnum.push_back(KILL);
338 InstrsByEnum.push_back(EXTRACT_SUBREG);
339 InstrsByEnum.push_back(INSERT_SUBREG);
340 InstrsByEnum.push_back(IMPLICIT_DEF);
341 InstrsByEnum.push_back(SUBREG_TO_REG);
342 InstrsByEnum.push_back(COPY_TO_REGCLASS);
343 InstrsByEnum.push_back(DBG_VALUE);
344 InstrsByEnum.push_back(REG_SEQUENCE);
346 unsigned EndOfPredefines = InstrsByEnum.size();
348 for (DenseMap<const Record*, CodeGenInstruction*>::const_iterator
349 I = Insts.begin(), E = Insts.end(); I != E; ++I) {
350 const CodeGenInstruction *CGI = I->second;
357 CGI != EXTRACT_SUBREG &&
358 CGI != INSERT_SUBREG &&
359 CGI != IMPLICIT_DEF &&
360 CGI != SUBREG_TO_REG &&
361 CGI != COPY_TO_REGCLASS &&
364 InstrsByEnum.push_back(CGI);
367 // All of the instructions are now in random order based on the map iteration.
368 // Sort them by name.
369 std::sort(InstrsByEnum.begin()+EndOfPredefines, InstrsByEnum.end(),
374 /// isLittleEndianEncoding - Return whether this target encodes its instruction
375 /// in little-endian format, i.e. bits laid out in the order [0..n]
377 bool CodeGenTarget::isLittleEndianEncoding() const {
378 return getInstructionSet()->getValueAsBit("isLittleEndianEncoding");
381 //===----------------------------------------------------------------------===//
382 // ComplexPattern implementation
384 ComplexPattern::ComplexPattern(Record *R) {
385 Ty = ::getValueType(R->getValueAsDef("Ty"));
386 NumOperands = R->getValueAsInt("NumOperands");
387 SelectFunc = R->getValueAsString("SelectFunc");
388 RootNodes = R->getValueAsListOfDefs("RootNodes");
390 // Parse the properties.
392 std::vector<Record*> PropList = R->getValueAsListOfDefs("Properties");
393 for (unsigned i = 0, e = PropList.size(); i != e; ++i)
394 if (PropList[i]->getName() == "SDNPHasChain") {
395 Properties |= 1 << SDNPHasChain;
396 } else if (PropList[i]->getName() == "SDNPOptInFlag") {
397 Properties |= 1 << SDNPOptInFlag;
398 } else if (PropList[i]->getName() == "SDNPMayStore") {
399 Properties |= 1 << SDNPMayStore;
400 } else if (PropList[i]->getName() == "SDNPMayLoad") {
401 Properties |= 1 << SDNPMayLoad;
402 } else if (PropList[i]->getName() == "SDNPSideEffect") {
403 Properties |= 1 << SDNPSideEffect;
404 } else if (PropList[i]->getName() == "SDNPMemOperand") {
405 Properties |= 1 << SDNPMemOperand;
406 } else if (PropList[i]->getName() == "SDNPVariadic") {
407 Properties |= 1 << SDNPVariadic;
409 errs() << "Unsupported SD Node property '" << PropList[i]->getName()
410 << "' on ComplexPattern '" << R->getName() << "'!\n";
415 //===----------------------------------------------------------------------===//
416 // CodeGenIntrinsic Implementation
417 //===----------------------------------------------------------------------===//
419 std::vector<CodeGenIntrinsic> llvm::LoadIntrinsics(const RecordKeeper &RC,
421 std::vector<Record*> I = RC.getAllDerivedDefinitions("Intrinsic");
423 std::vector<CodeGenIntrinsic> Result;
425 for (unsigned i = 0, e = I.size(); i != e; ++i) {
426 bool isTarget = I[i]->getValueAsBit("isTarget");
427 if (isTarget == TargetOnly)
428 Result.push_back(CodeGenIntrinsic(I[i]));
433 CodeGenIntrinsic::CodeGenIntrinsic(Record *R) {
435 std::string DefName = R->getName();
437 isOverloaded = false;
438 isCommutative = false;
440 if (DefName.size() <= 4 ||
441 std::string(DefName.begin(), DefName.begin() + 4) != "int_")
442 throw "Intrinsic '" + DefName + "' does not start with 'int_'!";
444 EnumName = std::string(DefName.begin()+4, DefName.end());
446 if (R->getValue("GCCBuiltinName")) // Ignore a missing GCCBuiltinName field.
447 GCCBuiltinName = R->getValueAsString("GCCBuiltinName");
449 TargetPrefix = R->getValueAsString("TargetPrefix");
450 Name = R->getValueAsString("LLVMName");
453 // If an explicit name isn't specified, derive one from the DefName.
456 for (unsigned i = 0, e = EnumName.size(); i != e; ++i)
457 Name += (EnumName[i] == '_') ? '.' : EnumName[i];
459 // Verify it starts with "llvm.".
460 if (Name.size() <= 5 ||
461 std::string(Name.begin(), Name.begin() + 5) != "llvm.")
462 throw "Intrinsic '" + DefName + "'s name does not start with 'llvm.'!";
465 // If TargetPrefix is specified, make sure that Name starts with
466 // "llvm.<targetprefix>.".
467 if (!TargetPrefix.empty()) {
468 if (Name.size() < 6+TargetPrefix.size() ||
469 std::string(Name.begin() + 5, Name.begin() + 6 + TargetPrefix.size())
470 != (TargetPrefix + "."))
471 throw "Intrinsic '" + DefName + "' does not start with 'llvm." +
472 TargetPrefix + ".'!";
475 // Parse the list of return types.
476 std::vector<MVT::SimpleValueType> OverloadedVTs;
477 ListInit *TypeList = R->getValueAsListInit("RetTypes");
478 for (unsigned i = 0, e = TypeList->getSize(); i != e; ++i) {
479 Record *TyEl = TypeList->getElementAsRecord(i);
480 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
481 MVT::SimpleValueType VT;
482 if (TyEl->isSubClassOf("LLVMMatchType")) {
483 unsigned MatchTy = TyEl->getValueAsInt("Number");
484 assert(MatchTy < OverloadedVTs.size() &&
485 "Invalid matching number!");
486 VT = OverloadedVTs[MatchTy];
487 // It only makes sense to use the extended and truncated vector element
488 // variants with iAny types; otherwise, if the intrinsic is not
489 // overloaded, all the types can be specified directly.
490 assert(((!TyEl->isSubClassOf("LLVMExtendedElementVectorType") &&
491 !TyEl->isSubClassOf("LLVMTruncatedElementVectorType")) ||
492 VT == MVT::iAny || VT == MVT::vAny) &&
493 "Expected iAny or vAny type");
495 VT = getValueType(TyEl->getValueAsDef("VT"));
497 if (EVT(VT).isOverloaded()) {
498 OverloadedVTs.push_back(VT);
502 // Reject invalid types.
503 if (VT == MVT::isVoid)
504 throw "Intrinsic '" + DefName + " has void in result type list!";
506 IS.RetVTs.push_back(VT);
507 IS.RetTypeDefs.push_back(TyEl);
510 // Parse the list of parameter types.
511 TypeList = R->getValueAsListInit("ParamTypes");
512 for (unsigned i = 0, e = TypeList->getSize(); i != e; ++i) {
513 Record *TyEl = TypeList->getElementAsRecord(i);
514 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
515 MVT::SimpleValueType VT;
516 if (TyEl->isSubClassOf("LLVMMatchType")) {
517 unsigned MatchTy = TyEl->getValueAsInt("Number");
518 assert(MatchTy < OverloadedVTs.size() &&
519 "Invalid matching number!");
520 VT = OverloadedVTs[MatchTy];
521 // It only makes sense to use the extended and truncated vector element
522 // variants with iAny types; otherwise, if the intrinsic is not
523 // overloaded, all the types can be specified directly.
524 assert(((!TyEl->isSubClassOf("LLVMExtendedElementVectorType") &&
525 !TyEl->isSubClassOf("LLVMTruncatedElementVectorType")) ||
526 VT == MVT::iAny || VT == MVT::vAny) &&
527 "Expected iAny or vAny type");
529 VT = getValueType(TyEl->getValueAsDef("VT"));
531 if (EVT(VT).isOverloaded()) {
532 OverloadedVTs.push_back(VT);
536 // Reject invalid types.
537 if (VT == MVT::isVoid && i != e-1 /*void at end means varargs*/)
538 throw "Intrinsic '" + DefName + " has void in result type list!";
540 IS.ParamVTs.push_back(VT);
541 IS.ParamTypeDefs.push_back(TyEl);
544 // Parse the intrinsic properties.
545 ListInit *PropList = R->getValueAsListInit("Properties");
546 for (unsigned i = 0, e = PropList->getSize(); i != e; ++i) {
547 Record *Property = PropList->getElementAsRecord(i);
548 assert(Property->isSubClassOf("IntrinsicProperty") &&
549 "Expected a property!");
551 if (Property->getName() == "IntrNoMem")
553 else if (Property->getName() == "IntrReadArgMem")
555 else if (Property->getName() == "IntrReadMem")
557 else if (Property->getName() == "IntrWriteArgMem")
558 ModRef = WriteArgMem;
559 else if (Property->getName() == "IntrWriteMem")
561 else if (Property->getName() == "Commutative")
562 isCommutative = true;
563 else if (Property->isSubClassOf("NoCapture")) {
564 unsigned ArgNo = Property->getValueAsInt("ArgNo");
565 ArgumentAttributes.push_back(std::make_pair(ArgNo, NoCapture));
567 assert(0 && "Unknown property!");