1 //===- CodeGenTarget.cpp - CodeGen Target Class Wrapper ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class wrap target description classes used by the various code
11 // generation TableGen backends. This makes it easier to access the data and
12 // provides a single place that needs to check it for validity. All of these
13 // classes throw exceptions on error conditions.
15 //===----------------------------------------------------------------------===//
17 #include "CodeGenTarget.h"
18 #include "CodeGenIntrinsics.h"
20 #include "llvm/ADT/StringExtras.h"
21 #include "llvm/Support/CommandLine.h"
26 static cl::opt<unsigned>
27 AsmWriterNum("asmwriternum", cl::init(0),
28 cl::desc("Make -gen-asm-writer emit assembly writer #N"));
30 /// getValueType - Return the MCV::ValueType that the specified TableGen record
32 MVT::ValueType llvm::getValueType(Record *Rec, const CodeGenTarget *CGT) {
33 return (MVT::ValueType)Rec->getValueAsInt("Value");
36 std::string llvm::getName(MVT::ValueType T) {
38 case MVT::Other: return "UNKNOWN";
39 case MVT::i1: return "MVT::i1";
40 case MVT::i8: return "MVT::i8";
41 case MVT::i16: return "MVT::i16";
42 case MVT::i32: return "MVT::i32";
43 case MVT::i64: return "MVT::i64";
44 case MVT::i128: return "MVT::i128";
45 case MVT::f32: return "MVT::f32";
46 case MVT::f64: return "MVT::f64";
47 case MVT::f80: return "MVT::f80";
48 case MVT::f128: return "MVT::f128";
49 case MVT::Flag: return "MVT::Flag";
50 case MVT::isVoid:return "MVT::void";
51 case MVT::v8i8: return "MVT::v8i8";
52 case MVT::v4i16: return "MVT::v4i16";
53 case MVT::v2i32: return "MVT::v2i32";
54 case MVT::v16i8: return "MVT::v16i8";
55 case MVT::v8i16: return "MVT::v8i16";
56 case MVT::v4i32: return "MVT::v4i32";
57 case MVT::v2i64: return "MVT::v2i64";
58 case MVT::v2f32: return "MVT::v2f32";
59 case MVT::v4f32: return "MVT::v4f32";
60 case MVT::v2f64: return "MVT::v2f64";
61 case MVT::iPTR: return "TLI.getPointerTy()";
62 default: assert(0 && "ILLEGAL VALUE TYPE!"); return "";
66 std::string llvm::getEnumName(MVT::ValueType T) {
68 case MVT::Other: return "MVT::Other";
69 case MVT::i1: return "MVT::i1";
70 case MVT::i8: return "MVT::i8";
71 case MVT::i16: return "MVT::i16";
72 case MVT::i32: return "MVT::i32";
73 case MVT::i64: return "MVT::i64";
74 case MVT::i128: return "MVT::i128";
75 case MVT::f32: return "MVT::f32";
76 case MVT::f64: return "MVT::f64";
77 case MVT::f80: return "MVT::f80";
78 case MVT::f128: return "MVT::f128";
79 case MVT::Flag: return "MVT::Flag";
80 case MVT::isVoid:return "MVT::isVoid";
81 case MVT::v8i8: return "MVT::v8i8";
82 case MVT::v4i16: return "MVT::v4i16";
83 case MVT::v2i32: return "MVT::v2i32";
84 case MVT::v16i8: return "MVT::v16i8";
85 case MVT::v8i16: return "MVT::v8i16";
86 case MVT::v4i32: return "MVT::v4i32";
87 case MVT::v2i64: return "MVT::v2i64";
88 case MVT::v2f32: return "MVT::v2f32";
89 case MVT::v4f32: return "MVT::v4f32";
90 case MVT::v2f64: return "MVT::v2f64";
91 case MVT::iPTR: return "TLI.getPointerTy()";
92 default: assert(0 && "ILLEGAL VALUE TYPE!"); return "";
97 std::ostream &llvm::operator<<(std::ostream &OS, MVT::ValueType T) {
98 return OS << getName(T);
102 /// getTarget - Return the current instance of the Target class.
104 CodeGenTarget::CodeGenTarget() {
105 std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target");
106 if (Targets.size() == 0)
107 throw std::string("ERROR: No 'Target' subclasses defined!");
108 if (Targets.size() != 1)
109 throw std::string("ERROR: Multiple subclasses of Target defined!");
110 TargetRec = Targets[0];
114 const std::string &CodeGenTarget::getName() const {
115 return TargetRec->getName();
118 Record *CodeGenTarget::getInstructionSet() const {
119 return TargetRec->getValueAsDef("InstructionSet");
122 /// getAsmWriter - Return the AssemblyWriter definition for this target.
124 Record *CodeGenTarget::getAsmWriter() const {
125 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters");
126 if (AsmWriterNum >= LI.size())
127 throw "Target does not have an AsmWriter #" + utostr(AsmWriterNum) + "!";
128 return LI[AsmWriterNum];
131 void CodeGenTarget::ReadRegisters() const {
132 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
134 throw std::string("No 'Register' subclasses defined!");
136 Registers.reserve(Regs.size());
137 Registers.assign(Regs.begin(), Regs.end());
140 CodeGenRegister::CodeGenRegister(Record *R) : TheDef(R) {
141 DeclaredSpillSize = R->getValueAsInt("SpillSize");
142 DeclaredSpillAlignment = R->getValueAsInt("SpillAlignment");
145 const std::string &CodeGenRegister::getName() const {
146 return TheDef->getName();
149 void CodeGenTarget::ReadRegisterClasses() const {
150 std::vector<Record*> RegClasses =
151 Records.getAllDerivedDefinitions("RegisterClass");
152 if (RegClasses.empty())
153 throw std::string("No 'RegisterClass' subclasses defined!");
155 RegisterClasses.reserve(RegClasses.size());
156 RegisterClasses.assign(RegClasses.begin(), RegClasses.end());
159 std::vector<unsigned char> CodeGenTarget::getRegisterVTs(Record *R) const {
160 std::vector<unsigned char> Result;
161 const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses();
162 for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
163 const CodeGenRegisterClass &RC = RegisterClasses[i];
164 for (unsigned ei = 0, ee = RC.Elements.size(); ei != ee; ++ei) {
165 if (R == RC.Elements[ei]) {
166 const std::vector<MVT::ValueType> &InVTs = RC.getValueTypes();
167 for (unsigned i = 0, e = InVTs.size(); i != e; ++i)
168 Result.push_back(InVTs[i]);
176 CodeGenRegisterClass::CodeGenRegisterClass(Record *R) : TheDef(R) {
177 // Rename anonymous register classes.
178 if (R->getName().size() > 9 && R->getName()[9] == '.') {
179 static unsigned AnonCounter = 0;
180 R->setName("AnonRegClass_"+utostr(AnonCounter++));
183 std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes");
184 for (unsigned i = 0, e = TypeList.size(); i != e; ++i) {
185 Record *Type = TypeList[i];
186 if (!Type->isSubClassOf("ValueType"))
187 throw "RegTypes list member '" + Type->getName() +
188 "' does not derive from the ValueType class!";
189 VTs.push_back(getValueType(Type));
191 assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!");
193 std::vector<Record*> RegList = R->getValueAsListOfDefs("MemberList");
194 for (unsigned i = 0, e = RegList.size(); i != e; ++i) {
195 Record *Reg = RegList[i];
196 if (!Reg->isSubClassOf("Register"))
197 throw "Register Class member '" + Reg->getName() +
198 "' does not derive from the Register class!";
199 Elements.push_back(Reg);
202 // Allow targets to override the size in bits of the RegisterClass.
203 unsigned Size = R->getValueAsInt("Size");
205 Namespace = R->getValueAsString("Namespace");
206 SpillSize = Size ? Size : MVT::getSizeInBits(VTs[0]);
207 SpillAlignment = R->getValueAsInt("Alignment");
208 MethodBodies = R->getValueAsCode("MethodBodies");
209 MethodProtos = R->getValueAsCode("MethodProtos");
212 const std::string &CodeGenRegisterClass::getName() const {
213 return TheDef->getName();
216 void CodeGenTarget::ReadLegalValueTypes() const {
217 const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses();
218 for (unsigned i = 0, e = RCs.size(); i != e; ++i)
219 for (unsigned ri = 0, re = RCs[i].VTs.size(); ri != re; ++ri)
220 LegalValueTypes.push_back(RCs[i].VTs[ri]);
222 // Remove duplicates.
223 std::sort(LegalValueTypes.begin(), LegalValueTypes.end());
224 LegalValueTypes.erase(std::unique(LegalValueTypes.begin(),
225 LegalValueTypes.end()),
226 LegalValueTypes.end());
230 void CodeGenTarget::ReadInstructions() const {
231 std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
232 if (Insts.size() <= 2)
233 throw std::string("No 'Instruction' subclasses defined!");
235 // Parse the instructions defined in the .td file.
236 std::string InstFormatName =
237 getAsmWriter()->getValueAsString("InstFormatName");
239 for (unsigned i = 0, e = Insts.size(); i != e; ++i) {
240 std::string AsmStr = Insts[i]->getValueAsString(InstFormatName);
241 Instructions.insert(std::make_pair(Insts[i]->getName(),
242 CodeGenInstruction(Insts[i], AsmStr)));
246 /// getInstructionsByEnumValue - Return all of the instructions defined by the
247 /// target, ordered by their enum value.
249 getInstructionsByEnumValue(std::vector<const CodeGenInstruction*>
250 &NumberedInstructions) {
251 std::map<std::string, CodeGenInstruction>::const_iterator I;
252 I = getInstructions().find("PHI");
253 if (I == Instructions.end()) throw "Could not find 'PHI' instruction!";
254 const CodeGenInstruction *PHI = &I->second;
256 I = getInstructions().find("INLINEASM");
257 if (I == Instructions.end()) throw "Could not find 'INLINEASM' instruction!";
258 const CodeGenInstruction *INLINEASM = &I->second;
260 // Print out the rest of the instructions now.
261 NumberedInstructions.push_back(PHI);
262 NumberedInstructions.push_back(INLINEASM);
263 for (inst_iterator II = inst_begin(), E = inst_end(); II != E; ++II)
264 if (&II->second != PHI &&&II->second != INLINEASM)
265 NumberedInstructions.push_back(&II->second);
269 /// isLittleEndianEncoding - Return whether this target encodes its instruction
270 /// in little-endian format, i.e. bits laid out in the order [0..n]
272 bool CodeGenTarget::isLittleEndianEncoding() const {
273 return getInstructionSet()->getValueAsBit("isLittleEndianEncoding");
276 static std::string ParseConstraint(const std::string &CStr,
277 CodeGenInstruction *I, unsigned &DestOp) {
278 const std::string ops("="); // FIXME: Only supports TIED_TO for now.
279 std::string::size_type pos = CStr.find_first_of(ops);
280 assert(pos != std::string::npos && "Unrecognized constraint");
281 std::string Name = CStr.substr(1, pos); // Skip '$'
283 // TIED_TO: $src1 = $dst
284 const std::string delims(" \t");
285 std::string::size_type wpos = Name.find_first_of(delims);
286 if (wpos != std::string::npos)
287 Name = Name.substr(0, wpos);
288 DestOp = I->getOperandNamed(Name);
290 Name = CStr.substr(pos+1);
291 wpos = Name.find_first_not_of(delims);
292 if (wpos != std::string::npos)
293 Name = Name.substr(wpos+1);
295 unsigned TIdx = I->getOperandNamed(Name);
297 throw "Illegal tied-to operand constraint '" + CStr + "'";
300 return "((" + utostr(TIdx) + " << 16) | (1 << TargetInstrInfo::TIED_TO))";
303 static void ParseConstraints(const std::string &CStr, CodeGenInstruction *I) {
304 if (CStr.empty()) return;
306 const std::string delims(",");
307 std::string::size_type bidx, eidx;
309 bidx = CStr.find_first_not_of(delims);
310 while (bidx != std::string::npos) {
311 eidx = CStr.find_first_of(delims, bidx);
312 if (eidx == std::string::npos)
313 eidx = CStr.length();
316 std::string Constr = ParseConstraint(CStr.substr(bidx, eidx), I, OpNo);
317 assert(OpNo < I->OperandList.size() && "Invalid operand no?");
319 if (!I->OperandList[OpNo].Constraint.empty())
320 throw "Operand #" + utostr(OpNo) + " cannot have multiple constraints!";
321 I->OperandList[OpNo].Constraint = Constr;
322 bidx = CStr.find_first_not_of(delims, eidx);
326 CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
327 : TheDef(R), AsmString(AsmStr) {
328 Name = R->getValueAsString("Name");
329 Namespace = R->getValueAsString("Namespace");
331 isReturn = R->getValueAsBit("isReturn");
332 isBranch = R->getValueAsBit("isBranch");
333 isBarrier = R->getValueAsBit("isBarrier");
334 isCall = R->getValueAsBit("isCall");
335 isLoad = R->getValueAsBit("isLoad");
336 isStore = R->getValueAsBit("isStore");
337 isTwoAddress = R->getValueAsBit("isTwoAddress");
338 isPredicated = false; // set below.
339 isConvertibleToThreeAddress = R->getValueAsBit("isConvertibleToThreeAddress");
340 isCommutable = R->getValueAsBit("isCommutable");
341 isTerminator = R->getValueAsBit("isTerminator");
342 hasDelaySlot = R->getValueAsBit("hasDelaySlot");
343 usesCustomDAGSchedInserter = R->getValueAsBit("usesCustomDAGSchedInserter");
344 hasCtrlDep = R->getValueAsBit("hasCtrlDep");
345 noResults = R->getValueAsBit("noResults");
346 hasVariableNumberOfOperands = false;
350 DI = R->getValueAsDag("OperandList");
352 // Error getting operand list, just ignore it (sparcv9).
358 unsigned MIOperandNo = 0;
359 std::set<std::string> OperandNames;
360 for (unsigned i = 0, e = DI->getNumArgs(); i != e; ++i) {
361 DefInit *Arg = dynamic_cast<DefInit*>(DI->getArg(i));
363 throw "Illegal operand for the '" + R->getName() + "' instruction!";
365 Record *Rec = Arg->getDef();
366 std::string PrintMethod = "printOperand";
368 DagInit *MIOpInfo = 0;
369 if (Rec->isSubClassOf("Operand")) {
370 PrintMethod = Rec->getValueAsString("PrintMethod");
371 MIOpInfo = Rec->getValueAsDag("MIOperandInfo");
373 // Verify that MIOpInfo has an 'ops' root value.
374 if (!dynamic_cast<DefInit*>(MIOpInfo->getOperator()) ||
375 dynamic_cast<DefInit*>(MIOpInfo->getOperator())
376 ->getDef()->getName() != "ops")
377 throw "Bad value for MIOperandInfo in operand '" + Rec->getName() +
380 // If we have MIOpInfo, then we have #operands equal to number of entries
382 if (unsigned NumArgs = MIOpInfo->getNumArgs())
385 isPredicated |= Rec->isSubClassOf("PredicateOperand");
386 } else if (Rec->getName() == "variable_ops") {
387 hasVariableNumberOfOperands = true;
389 } else if (!Rec->isSubClassOf("RegisterClass"))
390 throw "Unknown operand class '" + Rec->getName() +
391 "' in instruction '" + R->getName() + "' instruction!";
393 // Check that the operand has a name and that it's unique.
394 if (DI->getArgName(i).empty())
395 throw "In instruction '" + R->getName() + "', operand #" + utostr(i) +
397 if (!OperandNames.insert(DI->getArgName(i)).second)
398 throw "In instruction '" + R->getName() + "', operand #" + utostr(i) +
399 " has the same name as a previous operand!";
401 OperandList.push_back(OperandInfo(Rec, DI->getArgName(i), PrintMethod,
402 MIOperandNo, NumOps, MIOpInfo));
403 MIOperandNo += NumOps;
406 ParseConstraints(R->getValueAsString("Constraints"), this);
408 // For backward compatibility: isTwoAddress means operand 1 is tied to
410 if (isTwoAddress && OperandList[1].Constraint.empty())
411 OperandList[1].Constraint = "((0 << 16) | (1 << TargetInstrInfo::TIED_TO))";
413 // Any operands with unset constraints get 0 as their constraint.
414 for (unsigned op = 0, e = OperandList.size(); op != e; ++op)
415 if (OperandList[op].Constraint.empty())
416 OperandList[op].Constraint = "0";
421 /// getOperandNamed - Return the index of the operand with the specified
422 /// non-empty name. If the instruction does not have an operand with the
423 /// specified name, throw an exception.
425 unsigned CodeGenInstruction::getOperandNamed(const std::string &Name) const {
426 assert(!Name.empty() && "Cannot search for operand with no name!");
427 for (unsigned i = 0, e = OperandList.size(); i != e; ++i)
428 if (OperandList[i].Name == Name) return i;
429 throw "Instruction '" + TheDef->getName() +
430 "' does not have an operand named '$" + Name + "'!";
433 //===----------------------------------------------------------------------===//
434 // ComplexPattern implementation
436 ComplexPattern::ComplexPattern(Record *R) {
437 Ty = ::getValueType(R->getValueAsDef("Ty"));
438 NumOperands = R->getValueAsInt("NumOperands");
439 SelectFunc = R->getValueAsString("SelectFunc");
440 RootNodes = R->getValueAsListOfDefs("RootNodes");
442 // Parse the properties.
444 std::vector<Record*> PropList = R->getValueAsListOfDefs("Properties");
445 for (unsigned i = 0, e = PropList.size(); i != e; ++i)
446 if (PropList[i]->getName() == "SDNPHasChain") {
447 Properties |= 1 << SDNPHasChain;
448 } else if (PropList[i]->getName() == "SDNPOptInFlag") {
449 Properties |= 1 << SDNPOptInFlag;
451 std::cerr << "Unsupported SD Node property '" << PropList[i]->getName()
452 << "' on ComplexPattern '" << R->getName() << "'!\n";
457 //===----------------------------------------------------------------------===//
458 // CodeGenIntrinsic Implementation
459 //===----------------------------------------------------------------------===//
461 std::vector<CodeGenIntrinsic> llvm::LoadIntrinsics(const RecordKeeper &RC) {
462 std::vector<Record*> I = RC.getAllDerivedDefinitions("Intrinsic");
464 std::vector<CodeGenIntrinsic> Result;
466 // If we are in the context of a target .td file, get the target info so that
467 // we can decode the current intptr_t.
468 CodeGenTarget *CGT = 0;
469 if (Records.getClass("Target") &&
470 Records.getAllDerivedDefinitions("Target").size() == 1)
471 CGT = new CodeGenTarget();
473 for (unsigned i = 0, e = I.size(); i != e; ++i)
474 Result.push_back(CodeGenIntrinsic(I[i], CGT));
479 CodeGenIntrinsic::CodeGenIntrinsic(Record *R, CodeGenTarget *CGT) {
481 std::string DefName = R->getName();
484 if (DefName.size() <= 4 ||
485 std::string(DefName.begin(), DefName.begin()+4) != "int_")
486 throw "Intrinsic '" + DefName + "' does not start with 'int_'!";
487 EnumName = std::string(DefName.begin()+4, DefName.end());
488 if (R->getValue("GCCBuiltinName")) // Ignore a missing GCCBuiltinName field.
489 GCCBuiltinName = R->getValueAsString("GCCBuiltinName");
490 TargetPrefix = R->getValueAsString("TargetPrefix");
491 Name = R->getValueAsString("LLVMName");
493 // If an explicit name isn't specified, derive one from the DefName.
495 for (unsigned i = 0, e = EnumName.size(); i != e; ++i)
496 if (EnumName[i] == '_')
501 // Verify it starts with "llvm.".
502 if (Name.size() <= 5 ||
503 std::string(Name.begin(), Name.begin()+5) != "llvm.")
504 throw "Intrinsic '" + DefName + "'s name does not start with 'llvm.'!";
507 // If TargetPrefix is specified, make sure that Name starts with
508 // "llvm.<targetprefix>.".
509 if (!TargetPrefix.empty()) {
510 if (Name.size() < 6+TargetPrefix.size() ||
511 std::string(Name.begin()+5, Name.begin()+6+TargetPrefix.size())
512 != (TargetPrefix+"."))
513 throw "Intrinsic '" + DefName + "' does not start with 'llvm." +
514 TargetPrefix + ".'!";
517 // Parse the list of argument types.
518 ListInit *TypeList = R->getValueAsListInit("Types");
519 for (unsigned i = 0, e = TypeList->getSize(); i != e; ++i) {
520 DefInit *DI = dynamic_cast<DefInit*>(TypeList->getElement(i));
521 assert(DI && "Invalid list type!");
522 Record *TyEl = DI->getDef();
523 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
524 ArgTypes.push_back(TyEl->getValueAsString("TypeVal"));
527 ArgVTs.push_back(getValueType(TyEl->getValueAsDef("VT"), CGT));
528 ArgTypeDefs.push_back(TyEl);
530 if (ArgTypes.size() == 0)
531 throw "Intrinsic '"+DefName+"' needs at least a type for the ret value!";
533 // Parse the intrinsic properties.
534 ListInit *PropList = R->getValueAsListInit("Properties");
535 for (unsigned i = 0, e = PropList->getSize(); i != e; ++i) {
536 DefInit *DI = dynamic_cast<DefInit*>(PropList->getElement(i));
537 assert(DI && "Invalid list type!");
538 Record *Property = DI->getDef();
539 assert(Property->isSubClassOf("IntrinsicProperty") &&
540 "Expected a property!");
542 if (Property->getName() == "IntrNoMem")
544 else if (Property->getName() == "IntrReadArgMem")
546 else if (Property->getName() == "IntrReadMem")
548 else if (Property->getName() == "IntrWriteArgMem")
549 ModRef = WriteArgMem;
550 else if (Property->getName() == "IntrWriteMem")
553 assert(0 && "Unknown property!");