1 //===- CodeGenTarget.cpp - CodeGen Target Class Wrapper -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class wraps target description classes used by the various code
11 // generation TableGen backends. This makes it easier to access the data and
12 // provides a single place that needs to check it for validity. All of these
13 // classes throw exceptions on error conditions.
15 //===----------------------------------------------------------------------===//
17 #include "CodeGenTarget.h"
18 #include "CodeGenIntrinsics.h"
20 #include "llvm/ADT/StringExtras.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/Streams.h"
26 static cl::opt<unsigned>
27 AsmWriterNum("asmwriternum", cl::init(0),
28 cl::desc("Make -gen-asm-writer emit assembly writer #N"));
30 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen
31 /// record corresponds to.
32 MVT::SimpleValueType llvm::getValueType(Record *Rec) {
33 return (MVT::SimpleValueType)Rec->getValueAsInt("Value");
36 std::string llvm::getName(MVT::SimpleValueType T) {
38 case MVT::Other: return "UNKNOWN";
39 case MVT::i1: return "MVT::i1";
40 case MVT::i8: return "MVT::i8";
41 case MVT::i16: return "MVT::i16";
42 case MVT::i32: return "MVT::i32";
43 case MVT::i64: return "MVT::i64";
44 case MVT::i128: return "MVT::i128";
45 case MVT::iAny: return "MVT::iAny";
46 case MVT::fAny: return "MVT::fAny";
47 case MVT::f32: return "MVT::f32";
48 case MVT::f64: return "MVT::f64";
49 case MVT::f80: return "MVT::f80";
50 case MVT::f128: return "MVT::f128";
51 case MVT::ppcf128: return "MVT::ppcf128";
52 case MVT::Flag: return "MVT::Flag";
53 case MVT::isVoid:return "MVT::void";
54 case MVT::v8i8: return "MVT::v8i8";
55 case MVT::v4i16: return "MVT::v4i16";
56 case MVT::v2i32: return "MVT::v2i32";
57 case MVT::v1i64: return "MVT::v1i64";
58 case MVT::v16i8: return "MVT::v16i8";
59 case MVT::v8i16: return "MVT::v8i16";
60 case MVT::v4i32: return "MVT::v4i32";
61 case MVT::v2i64: return "MVT::v2i64";
62 case MVT::v2f32: return "MVT::v2f32";
63 case MVT::v4f32: return "MVT::v4f32";
64 case MVT::v2f64: return "MVT::v2f64";
65 case MVT::v3i32: return "MVT::v3i32";
66 case MVT::v3f32: return "MVT::v3f32";
67 case MVT::iPTR: return "TLI.getPointerTy()";
68 case MVT::iPTRAny: return "TLI.getPointerTy()";
69 default: assert(0 && "ILLEGAL VALUE TYPE!"); return "";
73 std::string llvm::getEnumName(MVT::SimpleValueType T) {
75 case MVT::Other: return "MVT::Other";
76 case MVT::i1: return "MVT::i1";
77 case MVT::i8: return "MVT::i8";
78 case MVT::i16: return "MVT::i16";
79 case MVT::i32: return "MVT::i32";
80 case MVT::i64: return "MVT::i64";
81 case MVT::i128: return "MVT::i128";
82 case MVT::iAny: return "MVT::iAny";
83 case MVT::fAny: return "MVT::fAny";
84 case MVT::f32: return "MVT::f32";
85 case MVT::f64: return "MVT::f64";
86 case MVT::f80: return "MVT::f80";
87 case MVT::f128: return "MVT::f128";
88 case MVT::ppcf128: return "MVT::ppcf128";
89 case MVT::Flag: return "MVT::Flag";
90 case MVT::isVoid:return "MVT::isVoid";
91 case MVT::v8i8: return "MVT::v8i8";
92 case MVT::v4i16: return "MVT::v4i16";
93 case MVT::v2i32: return "MVT::v2i32";
94 case MVT::v1i64: return "MVT::v1i64";
95 case MVT::v16i8: return "MVT::v16i8";
96 case MVT::v8i16: return "MVT::v8i16";
97 case MVT::v4i32: return "MVT::v4i32";
98 case MVT::v2i64: return "MVT::v2i64";
99 case MVT::v2f32: return "MVT::v2f32";
100 case MVT::v4f32: return "MVT::v4f32";
101 case MVT::v2f64: return "MVT::v2f64";
102 case MVT::v3i32: return "MVT::v3i32";
103 case MVT::v3f32: return "MVT::v3f32";
104 case MVT::iPTR: return "MVT::iPTR";
105 case MVT::iPTRAny: return "MVT::iPTRAny";
106 default: assert(0 && "ILLEGAL VALUE TYPE!"); return "";
110 /// getQualifiedName - Return the name of the specified record, with a
111 /// namespace qualifier if the record contains one.
113 std::string llvm::getQualifiedName(const Record *R) {
114 std::string Namespace = R->getValueAsString("Namespace");
115 if (Namespace.empty()) return R->getName();
116 return Namespace + "::" + R->getName();
122 /// getTarget - Return the current instance of the Target class.
124 CodeGenTarget::CodeGenTarget() {
125 std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target");
126 if (Targets.size() == 0)
127 throw std::string("ERROR: No 'Target' subclasses defined!");
128 if (Targets.size() != 1)
129 throw std::string("ERROR: Multiple subclasses of Target defined!");
130 TargetRec = Targets[0];
134 const std::string &CodeGenTarget::getName() const {
135 return TargetRec->getName();
138 Record *CodeGenTarget::getInstructionSet() const {
139 return TargetRec->getValueAsDef("InstructionSet");
142 /// getAsmWriter - Return the AssemblyWriter definition for this target.
144 Record *CodeGenTarget::getAsmWriter() const {
145 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters");
146 if (AsmWriterNum >= LI.size())
147 throw "Target does not have an AsmWriter #" + utostr(AsmWriterNum) + "!";
148 return LI[AsmWriterNum];
151 void CodeGenTarget::ReadRegisters() const {
152 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
154 throw std::string("No 'Register' subclasses defined!");
156 Registers.reserve(Regs.size());
157 Registers.assign(Regs.begin(), Regs.end());
160 CodeGenRegister::CodeGenRegister(Record *R) : TheDef(R) {
161 DeclaredSpillSize = R->getValueAsInt("SpillSize");
162 DeclaredSpillAlignment = R->getValueAsInt("SpillAlignment");
165 const std::string &CodeGenRegister::getName() const {
166 return TheDef->getName();
169 void CodeGenTarget::ReadRegisterClasses() const {
170 std::vector<Record*> RegClasses =
171 Records.getAllDerivedDefinitions("RegisterClass");
172 if (RegClasses.empty())
173 throw std::string("No 'RegisterClass' subclasses defined!");
175 RegisterClasses.reserve(RegClasses.size());
176 RegisterClasses.assign(RegClasses.begin(), RegClasses.end());
179 std::vector<unsigned char> CodeGenTarget::getRegisterVTs(Record *R) const {
180 std::vector<unsigned char> Result;
181 const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses();
182 for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
183 const CodeGenRegisterClass &RC = RegisterClasses[i];
184 for (unsigned ei = 0, ee = RC.Elements.size(); ei != ee; ++ei) {
185 if (R == RC.Elements[ei]) {
186 const std::vector<MVT::SimpleValueType> &InVTs = RC.getValueTypes();
187 for (unsigned i = 0, e = InVTs.size(); i != e; ++i)
188 Result.push_back(InVTs[i]);
196 CodeGenRegisterClass::CodeGenRegisterClass(Record *R) : TheDef(R) {
197 // Rename anonymous register classes.
198 if (R->getName().size() > 9 && R->getName()[9] == '.') {
199 static unsigned AnonCounter = 0;
200 R->setName("AnonRegClass_"+utostr(AnonCounter++));
203 std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes");
204 for (unsigned i = 0, e = TypeList.size(); i != e; ++i) {
205 Record *Type = TypeList[i];
206 if (!Type->isSubClassOf("ValueType"))
207 throw "RegTypes list member '" + Type->getName() +
208 "' does not derive from the ValueType class!";
209 VTs.push_back(getValueType(Type));
211 assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!");
213 std::vector<Record*> RegList = R->getValueAsListOfDefs("MemberList");
214 for (unsigned i = 0, e = RegList.size(); i != e; ++i) {
215 Record *Reg = RegList[i];
216 if (!Reg->isSubClassOf("Register"))
217 throw "Register Class member '" + Reg->getName() +
218 "' does not derive from the Register class!";
219 Elements.push_back(Reg);
222 std::vector<Record*> SubRegClassList =
223 R->getValueAsListOfDefs("SubRegClassList");
224 for (unsigned i = 0, e = SubRegClassList.size(); i != e; ++i) {
225 Record *SubRegClass = SubRegClassList[i];
226 if (!SubRegClass->isSubClassOf("RegisterClass"))
227 throw "Register Class member '" + SubRegClass->getName() +
228 "' does not derive from the RegisterClass class!";
229 SubRegClasses.push_back(SubRegClass);
232 // Allow targets to override the size in bits of the RegisterClass.
233 unsigned Size = R->getValueAsInt("Size");
235 Namespace = R->getValueAsString("Namespace");
236 SpillSize = Size ? Size : MVT(VTs[0]).getSizeInBits();
237 SpillAlignment = R->getValueAsInt("Alignment");
238 CopyCost = R->getValueAsInt("CopyCost");
239 MethodBodies = R->getValueAsCode("MethodBodies");
240 MethodProtos = R->getValueAsCode("MethodProtos");
243 const std::string &CodeGenRegisterClass::getName() const {
244 return TheDef->getName();
247 void CodeGenTarget::ReadLegalValueTypes() const {
248 const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses();
249 for (unsigned i = 0, e = RCs.size(); i != e; ++i)
250 for (unsigned ri = 0, re = RCs[i].VTs.size(); ri != re; ++ri)
251 LegalValueTypes.push_back(RCs[i].VTs[ri]);
253 // Remove duplicates.
254 std::sort(LegalValueTypes.begin(), LegalValueTypes.end());
255 LegalValueTypes.erase(std::unique(LegalValueTypes.begin(),
256 LegalValueTypes.end()),
257 LegalValueTypes.end());
261 void CodeGenTarget::ReadInstructions() const {
262 std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
263 if (Insts.size() <= 2)
264 throw std::string("No 'Instruction' subclasses defined!");
266 // Parse the instructions defined in the .td file.
267 std::string InstFormatName =
268 getAsmWriter()->getValueAsString("InstFormatName");
270 for (unsigned i = 0, e = Insts.size(); i != e; ++i) {
271 std::string AsmStr = Insts[i]->getValueAsString(InstFormatName);
272 Instructions.insert(std::make_pair(Insts[i]->getName(),
273 CodeGenInstruction(Insts[i], AsmStr)));
277 /// getInstructionsByEnumValue - Return all of the instructions defined by the
278 /// target, ordered by their enum value.
280 getInstructionsByEnumValue(std::vector<const CodeGenInstruction*>
281 &NumberedInstructions) {
282 std::map<std::string, CodeGenInstruction>::const_iterator I;
283 I = getInstructions().find("PHI");
284 if (I == Instructions.end()) throw "Could not find 'PHI' instruction!";
285 const CodeGenInstruction *PHI = &I->second;
287 I = getInstructions().find("INLINEASM");
288 if (I == Instructions.end()) throw "Could not find 'INLINEASM' instruction!";
289 const CodeGenInstruction *INLINEASM = &I->second;
291 I = getInstructions().find("DBG_LABEL");
292 if (I == Instructions.end()) throw "Could not find 'DBG_LABEL' instruction!";
293 const CodeGenInstruction *DBG_LABEL = &I->second;
295 I = getInstructions().find("EH_LABEL");
296 if (I == Instructions.end()) throw "Could not find 'EH_LABEL' instruction!";
297 const CodeGenInstruction *EH_LABEL = &I->second;
299 I = getInstructions().find("GC_LABEL");
300 if (I == Instructions.end()) throw "Could not find 'GC_LABEL' instruction!";
301 const CodeGenInstruction *GC_LABEL = &I->second;
303 I = getInstructions().find("DECLARE");
304 if (I == Instructions.end()) throw "Could not find 'DECLARE' instruction!";
305 const CodeGenInstruction *DECLARE = &I->second;
307 I = getInstructions().find("EXTRACT_SUBREG");
308 if (I == Instructions.end())
309 throw "Could not find 'EXTRACT_SUBREG' instruction!";
310 const CodeGenInstruction *EXTRACT_SUBREG = &I->second;
312 I = getInstructions().find("INSERT_SUBREG");
313 if (I == Instructions.end())
314 throw "Could not find 'INSERT_SUBREG' instruction!";
315 const CodeGenInstruction *INSERT_SUBREG = &I->second;
317 I = getInstructions().find("IMPLICIT_DEF");
318 if (I == Instructions.end())
319 throw "Could not find 'IMPLICIT_DEF' instruction!";
320 const CodeGenInstruction *IMPLICIT_DEF = &I->second;
322 I = getInstructions().find("SUBREG_TO_REG");
323 if (I == Instructions.end())
324 throw "Could not find 'SUBREG_TO_REG' instruction!";
325 const CodeGenInstruction *SUBREG_TO_REG = &I->second;
327 // Print out the rest of the instructions now.
328 NumberedInstructions.push_back(PHI);
329 NumberedInstructions.push_back(INLINEASM);
330 NumberedInstructions.push_back(DBG_LABEL);
331 NumberedInstructions.push_back(EH_LABEL);
332 NumberedInstructions.push_back(GC_LABEL);
333 NumberedInstructions.push_back(DECLARE);
334 NumberedInstructions.push_back(EXTRACT_SUBREG);
335 NumberedInstructions.push_back(INSERT_SUBREG);
336 NumberedInstructions.push_back(IMPLICIT_DEF);
337 NumberedInstructions.push_back(SUBREG_TO_REG);
338 for (inst_iterator II = inst_begin(), E = inst_end(); II != E; ++II)
339 if (&II->second != PHI &&
340 &II->second != INLINEASM &&
341 &II->second != DBG_LABEL &&
342 &II->second != EH_LABEL &&
343 &II->second != GC_LABEL &&
344 &II->second != DECLARE &&
345 &II->second != EXTRACT_SUBREG &&
346 &II->second != INSERT_SUBREG &&
347 &II->second != IMPLICIT_DEF &&
348 &II->second != SUBREG_TO_REG)
349 NumberedInstructions.push_back(&II->second);
353 /// isLittleEndianEncoding - Return whether this target encodes its instruction
354 /// in little-endian format, i.e. bits laid out in the order [0..n]
356 bool CodeGenTarget::isLittleEndianEncoding() const {
357 return getInstructionSet()->getValueAsBit("isLittleEndianEncoding");
360 //===----------------------------------------------------------------------===//
361 // ComplexPattern implementation
363 ComplexPattern::ComplexPattern(Record *R) {
364 Ty = ::getValueType(R->getValueAsDef("Ty"));
365 NumOperands = R->getValueAsInt("NumOperands");
366 SelectFunc = R->getValueAsString("SelectFunc");
367 RootNodes = R->getValueAsListOfDefs("RootNodes");
369 // Parse the properties.
371 std::vector<Record*> PropList = R->getValueAsListOfDefs("Properties");
372 for (unsigned i = 0, e = PropList.size(); i != e; ++i)
373 if (PropList[i]->getName() == "SDNPHasChain") {
374 Properties |= 1 << SDNPHasChain;
375 } else if (PropList[i]->getName() == "SDNPOptInFlag") {
376 Properties |= 1 << SDNPOptInFlag;
377 } else if (PropList[i]->getName() == "SDNPMayStore") {
378 Properties |= 1 << SDNPMayStore;
379 } else if (PropList[i]->getName() == "SDNPMayLoad") {
380 Properties |= 1 << SDNPMayLoad;
381 } else if (PropList[i]->getName() == "SDNPSideEffect") {
382 Properties |= 1 << SDNPSideEffect;
383 } else if (PropList[i]->getName() == "SDNPMemOperand") {
384 Properties |= 1 << SDNPMemOperand;
386 cerr << "Unsupported SD Node property '" << PropList[i]->getName()
387 << "' on ComplexPattern '" << R->getName() << "'!\n";
391 // Parse the attributes.
393 PropList = R->getValueAsListOfDefs("Attributes");
394 for (unsigned i = 0, e = PropList.size(); i != e; ++i)
395 if (PropList[i]->getName() == "CPAttrParentAsRoot") {
396 Attributes |= 1 << CPAttrParentAsRoot;
398 cerr << "Unsupported pattern attribute '" << PropList[i]->getName()
399 << "' on ComplexPattern '" << R->getName() << "'!\n";
404 //===----------------------------------------------------------------------===//
405 // CodeGenIntrinsic Implementation
406 //===----------------------------------------------------------------------===//
408 std::vector<CodeGenIntrinsic> llvm::LoadIntrinsics(const RecordKeeper &RC) {
409 std::vector<Record*> I = RC.getAllDerivedDefinitions("Intrinsic");
411 std::vector<CodeGenIntrinsic> Result;
413 for (unsigned i = 0, e = I.size(); i != e; ++i)
414 Result.push_back(CodeGenIntrinsic(I[i]));
418 CodeGenIntrinsic::CodeGenIntrinsic(Record *R) {
420 std::string DefName = R->getName();
422 isOverloaded = false;
423 isCommutative = false;
425 if (DefName.size() <= 4 ||
426 std::string(DefName.begin(), DefName.begin()+4) != "int_")
427 throw "Intrinsic '" + DefName + "' does not start with 'int_'!";
428 EnumName = std::string(DefName.begin()+4, DefName.end());
429 if (R->getValue("GCCBuiltinName")) // Ignore a missing GCCBuiltinName field.
430 GCCBuiltinName = R->getValueAsString("GCCBuiltinName");
431 TargetPrefix = R->getValueAsString("TargetPrefix");
432 Name = R->getValueAsString("LLVMName");
434 // If an explicit name isn't specified, derive one from the DefName.
436 for (unsigned i = 0, e = EnumName.size(); i != e; ++i)
437 if (EnumName[i] == '_')
442 // Verify it starts with "llvm.".
443 if (Name.size() <= 5 ||
444 std::string(Name.begin(), Name.begin()+5) != "llvm.")
445 throw "Intrinsic '" + DefName + "'s name does not start with 'llvm.'!";
448 // If TargetPrefix is specified, make sure that Name starts with
449 // "llvm.<targetprefix>.".
450 if (!TargetPrefix.empty()) {
451 if (Name.size() < 6+TargetPrefix.size() ||
452 std::string(Name.begin()+5, Name.begin()+6+TargetPrefix.size())
453 != (TargetPrefix+"."))
454 throw "Intrinsic '" + DefName + "' does not start with 'llvm." +
455 TargetPrefix + ".'!";
458 // Parse the list of argument types.
459 ListInit *TypeList = R->getValueAsListInit("Types");
460 for (unsigned i = 0, e = TypeList->getSize(); i != e; ++i) {
461 Record *TyEl = TypeList->getElementAsRecord(i);
462 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
463 MVT::SimpleValueType VT = getValueType(TyEl->getValueAsDef("VT"));
464 isOverloaded |= VT == MVT::iAny || VT == MVT::fAny || VT == MVT::iPTRAny;
465 ArgVTs.push_back(VT);
466 ArgTypeDefs.push_back(TyEl);
468 if (ArgVTs.size() == 0)
469 throw "Intrinsic '"+DefName+"' needs at least a type for the ret value!";
472 // Parse the intrinsic properties.
473 ListInit *PropList = R->getValueAsListInit("Properties");
474 for (unsigned i = 0, e = PropList->getSize(); i != e; ++i) {
475 Record *Property = PropList->getElementAsRecord(i);
476 assert(Property->isSubClassOf("IntrinsicProperty") &&
477 "Expected a property!");
479 if (Property->getName() == "IntrNoMem")
481 else if (Property->getName() == "IntrReadArgMem")
483 else if (Property->getName() == "IntrReadMem")
485 else if (Property->getName() == "IntrWriteArgMem")
486 ModRef = WriteArgMem;
487 else if (Property->getName() == "IntrWriteMem")
489 else if (Property->getName() == "Commutative")
490 isCommutative = true;
492 assert(0 && "Unknown property!");