1 //===- CodeGenTarget.h - Target Class Wrapper -------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines wrappers for the Target class and related global
11 // functionality. This makes it easier to access the data and provides a single
12 // place that needs to check it for validity. All of these classes throw
13 // exceptions on error conditions.
15 //===----------------------------------------------------------------------===//
17 #ifndef CODEGEN_TARGET_H
18 #define CODEGEN_TARGET_H
20 #include "CodeGenRegisters.h"
21 #include "CodeGenInstruction.h"
23 #include "llvm/Support/raw_ostream.h"
28 struct CodeGenRegister;
31 // SelectionDAG node properties.
32 // SDNPMemOperand: indicates that a node touches memory and therefore must
33 // have an associated memory operand that describes the access.
48 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen
49 /// record corresponds to.
50 MVT::SimpleValueType getValueType(Record *Rec);
52 std::string getName(MVT::SimpleValueType T);
53 std::string getEnumName(MVT::SimpleValueType T);
55 /// getQualifiedName - Return the name of the specified record, with a
56 /// namespace qualifier if the record contains one.
57 std::string getQualifiedName(const Record *R);
59 /// CodeGenTarget - This class corresponds to the Target class in the .td files.
64 mutable DenseMap<const Record*, CodeGenInstruction*> Instructions;
65 mutable std::vector<CodeGenRegister> Registers;
66 mutable std::vector<Record*> SubRegIndices;
67 mutable std::vector<CodeGenRegisterClass> RegisterClasses;
68 mutable std::vector<MVT::SimpleValueType> LegalValueTypes;
69 void ReadRegisters() const;
70 void ReadSubRegIndices() const;
71 void ReadRegisterClasses() const;
72 void ReadInstructions() const;
73 void ReadLegalValueTypes() const;
75 mutable std::vector<const CodeGenInstruction*> InstrsByEnum;
79 Record *getTargetRecord() const { return TargetRec; }
80 const std::string &getName() const;
82 /// getInstNamespace - Return the target-specific instruction namespace.
84 std::string getInstNamespace() const;
86 /// getInstructionSet - Return the InstructionSet object.
88 Record *getInstructionSet() const;
90 /// getAsmParser - Return the AssemblyParser definition for this target.
92 Record *getAsmParser() const;
94 /// getAsmWriter - Return the AssemblyWriter definition for this target.
96 Record *getAsmWriter() const;
98 const std::vector<CodeGenRegister> &getRegisters() const {
99 if (Registers.empty()) ReadRegisters();
103 const std::vector<Record*> &getSubRegIndices() const {
104 if (SubRegIndices.empty()) ReadSubRegIndices();
105 return SubRegIndices;
108 // Map a SubRegIndex Record to its number.
109 unsigned getSubRegIndexNo(Record *idx) const {
110 if (SubRegIndices.empty()) ReadSubRegIndices();
111 std::vector<Record*>::const_iterator i =
112 std::find(SubRegIndices.begin(), SubRegIndices.end(), idx);
113 assert(i != SubRegIndices.end() && "Not a SubRegIndex");
114 return (i - SubRegIndices.begin()) + 1;
117 const std::vector<CodeGenRegisterClass> &getRegisterClasses() const {
118 if (RegisterClasses.empty()) ReadRegisterClasses();
119 return RegisterClasses;
122 const CodeGenRegisterClass &getRegisterClass(Record *R) const {
123 const std::vector<CodeGenRegisterClass> &RC = getRegisterClasses();
124 for (unsigned i = 0, e = RC.size(); i != e; ++i)
125 if (RC[i].TheDef == R)
127 assert(0 && "Didn't find the register class");
131 /// getRegisterClassForRegister - Find the register class that contains the
132 /// specified physical register. If the register is not in a register
133 /// class, return null. If the register is in multiple classes, and the
134 /// classes have a superset-subset relationship and the same set of
135 /// types, return the superclass. Otherwise return null.
136 const CodeGenRegisterClass *getRegisterClassForRegister(Record *R) const {
137 const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses();
138 const CodeGenRegisterClass *FoundRC = 0;
139 for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
140 const CodeGenRegisterClass &RC = RegisterClasses[i];
141 for (unsigned ei = 0, ee = RC.Elements.size(); ei != ee; ++ei) {
142 if (R != RC.Elements[ei])
145 // If a register's classes have different types, return null.
146 if (FoundRC && RC.getValueTypes() != FoundRC->getValueTypes())
149 // If this is the first class that contains the register,
150 // make a note of it and go on to the next class.
156 std::vector<Record *> Elements(RC.Elements);
157 std::vector<Record *> FoundElements(FoundRC->Elements);
158 std::sort(Elements.begin(), Elements.end());
159 std::sort(FoundElements.begin(), FoundElements.end());
161 // Check to see if the previously found class that contains
162 // the register is a subclass of the current class. If so,
163 // prefer the superclass.
164 if (std::includes(Elements.begin(), Elements.end(),
165 FoundElements.begin(), FoundElements.end())) {
170 // Check to see if the previously found class that contains
171 // the register is a superclass of the current class. If so,
172 // prefer the superclass.
173 if (std::includes(FoundElements.begin(), FoundElements.end(),
174 Elements.begin(), Elements.end()))
177 // Multiple classes, and neither is a superclass of the other.
185 /// getRegisterVTs - Find the union of all possible SimpleValueTypes for the
186 /// specified physical register.
187 std::vector<MVT::SimpleValueType> getRegisterVTs(Record *R) const;
189 const std::vector<MVT::SimpleValueType> &getLegalValueTypes() const {
190 if (LegalValueTypes.empty()) ReadLegalValueTypes();
191 return LegalValueTypes;
194 /// isLegalValueType - Return true if the specified value type is natively
195 /// supported by the target (i.e. there are registers that directly hold it).
196 bool isLegalValueType(MVT::SimpleValueType VT) const {
197 const std::vector<MVT::SimpleValueType> &LegalVTs = getLegalValueTypes();
198 for (unsigned i = 0, e = LegalVTs.size(); i != e; ++i)
199 if (LegalVTs[i] == VT) return true;
204 DenseMap<const Record*, CodeGenInstruction*> &getInstructions() const {
205 if (Instructions.empty()) ReadInstructions();
210 CodeGenInstruction &getInstruction(const Record *InstRec) const {
211 if (Instructions.empty()) ReadInstructions();
212 DenseMap<const Record*, CodeGenInstruction*>::iterator I =
213 Instructions.find(InstRec);
214 assert(I != Instructions.end() && "Not an instruction");
218 /// getInstructionsByEnumValue - Return all of the instructions defined by the
219 /// target, ordered by their enum value.
220 const std::vector<const CodeGenInstruction*> &
221 getInstructionsByEnumValue() const {
222 if (InstrsByEnum.empty()) ComputeInstrsByEnum();
226 typedef std::vector<const CodeGenInstruction*>::const_iterator inst_iterator;
227 inst_iterator inst_begin() const{return getInstructionsByEnumValue().begin();}
228 inst_iterator inst_end() const { return getInstructionsByEnumValue().end(); }
231 /// isLittleEndianEncoding - are instruction bit patterns defined as [0..n]?
233 bool isLittleEndianEncoding() const;
236 void ComputeInstrsByEnum() const;
239 /// ComplexPattern - ComplexPattern info, corresponding to the ComplexPattern
240 /// tablegen class in TargetSelectionDAG.td
241 class ComplexPattern {
242 MVT::SimpleValueType Ty;
243 unsigned NumOperands;
244 std::string SelectFunc;
245 std::vector<Record*> RootNodes;
246 unsigned Properties; // Node properties
248 ComplexPattern() : NumOperands(0) {}
249 ComplexPattern(Record *R);
251 MVT::SimpleValueType getValueType() const { return Ty; }
252 unsigned getNumOperands() const { return NumOperands; }
253 const std::string &getSelectFunc() const { return SelectFunc; }
254 const std::vector<Record*> &getRootNodes() const {
257 bool hasProperty(enum SDNP Prop) const { return Properties & (1 << Prop); }
260 } // End llvm namespace