1 //===- CodeGenTarget.h - Target Class Wrapper -------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines wrappers for the Target class and related global
11 // functionality. This makes it easier to access the data and provides a single
12 // place that needs to check it for validity. All of these classes throw
13 // exceptions on error conditions.
15 //===----------------------------------------------------------------------===//
17 #ifndef CODEGEN_TARGET_H
18 #define CODEGEN_TARGET_H
20 #include "CodeGenRegisters.h"
21 #include "CodeGenInstruction.h"
29 struct CodeGenRegister;
32 // SelectionDAG node properties.
33 enum SDNP { SDNPCommutative, SDNPAssociative, SDNPHasChain,
34 SDNPOutFlag, SDNPInFlag, SDNPOptInFlag };
36 /// getValueType - Return the MVT::ValueType that the specified TableGen record
38 MVT::ValueType getValueType(Record *Rec);
40 std::string getName(MVT::ValueType T);
41 std::string getEnumName(MVT::ValueType T);
44 /// CodeGenTarget - This class corresponds to the Target class in the .td files.
49 mutable std::map<std::string, CodeGenInstruction> Instructions;
50 mutable std::vector<CodeGenRegister> Registers;
51 mutable std::vector<CodeGenRegisterClass> RegisterClasses;
52 mutable std::vector<MVT::ValueType> LegalValueTypes;
53 void ReadRegisters() const;
54 void ReadRegisterClasses() const;
55 void ReadInstructions() const;
56 void ReadLegalValueTypes() const;
60 Record *getTargetRecord() const { return TargetRec; }
61 const std::string &getName() const;
63 /// getInstructionSet - Return the InstructionSet object.
65 Record *getInstructionSet() const;
67 /// getAsmWriter - Return the AssemblyWriter definition for this target.
69 Record *getAsmWriter() const;
71 const std::vector<CodeGenRegister> &getRegisters() const {
72 if (Registers.empty()) ReadRegisters();
76 const std::vector<CodeGenRegisterClass> &getRegisterClasses() const {
77 if (RegisterClasses.empty()) ReadRegisterClasses();
78 return RegisterClasses;
81 const CodeGenRegisterClass &getRegisterClass(Record *R) const {
82 const std::vector<CodeGenRegisterClass> &RC = getRegisterClasses();
83 for (unsigned i = 0, e = RC.size(); i != e; ++i)
84 if (RC[i].TheDef == R)
86 assert(0 && "Didn't find the register class");
90 /// getRegisterClassForRegister - Find the register class that contains the
91 /// specified physical register. If there register exists in multiple
92 /// register classes or is not in a register class, return null.
93 const CodeGenRegisterClass *getRegisterClassForRegister(Record *R) const {
94 const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses();
95 const CodeGenRegisterClass *FoundRC = 0;
96 for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
97 const CodeGenRegisterClass &RC = RegisterClasses[i];
98 for (unsigned ei = 0, ee = RC.Elements.size(); ei != ee; ++ei) {
99 if (R == RC.Elements[ei]) {
100 if (FoundRC) return 0; // In multiple RC's
109 /// getRegisterVTs - Find the union of all possible ValueTypes for the
110 /// specified physical register.
111 std::vector<unsigned char> getRegisterVTs(Record *R) const;
113 const std::vector<MVT::ValueType> &getLegalValueTypes() const {
114 if (LegalValueTypes.empty()) ReadLegalValueTypes();
115 return LegalValueTypes;
118 /// isLegalValueType - Return true if the specified value type is natively
119 /// supported by the target (i.e. there are registers that directly hold it).
120 bool isLegalValueType(MVT::ValueType VT) const {
121 const std::vector<MVT::ValueType> &LegalVTs = getLegalValueTypes();
122 for (unsigned i = 0, e = LegalVTs.size(); i != e; ++i)
123 if (LegalVTs[i] == VT) return true;
127 /// getInstructions - Return all of the instructions defined for this target.
129 const std::map<std::string, CodeGenInstruction> &getInstructions() const {
130 if (Instructions.empty()) ReadInstructions();
134 CodeGenInstruction &getInstruction(const std::string &Name) const {
135 const std::map<std::string, CodeGenInstruction> &Insts = getInstructions();
136 assert(Insts.count(Name) && "Not an instruction!");
137 return const_cast<CodeGenInstruction&>(Insts.find(Name)->second);
140 typedef std::map<std::string,
141 CodeGenInstruction>::const_iterator inst_iterator;
142 inst_iterator inst_begin() const { return getInstructions().begin(); }
143 inst_iterator inst_end() const { return Instructions.end(); }
145 /// getInstructionsByEnumValue - Return all of the instructions defined by the
146 /// target, ordered by their enum value.
147 void getInstructionsByEnumValue(std::vector<const CodeGenInstruction*>
148 &NumberedInstructions);
151 /// isLittleEndianEncoding - are instruction bit patterns defined as [0..n]?
153 bool isLittleEndianEncoding() const;
156 /// ComplexPattern - ComplexPattern info, corresponding to the ComplexPattern
157 /// tablegen class in TargetSelectionDAG.td
158 class ComplexPattern {
160 unsigned NumOperands;
161 std::string SelectFunc;
162 std::vector<Record*> RootNodes;
165 ComplexPattern() : NumOperands(0) {};
166 ComplexPattern(Record *R);
168 MVT::ValueType getValueType() const { return Ty; }
169 unsigned getNumOperands() const { return NumOperands; }
170 const std::string &getSelectFunc() const { return SelectFunc; }
171 const std::vector<Record*> &getRootNodes() const {
174 bool hasProperty(enum SDNP Prop) const { return Properties & (1 << Prop); }
178 } // End llvm namespace